Semiconductor device and method for fabricating the same

Abstract

This invention discloses a method for manufacturing a semiconductor device, which mainly involves first bonding a first wafer to a second wafer to form a first stacked structure and a first hybrid bond between the first wafer and the second wafer, then bonding a third wafer to a fourth wafer to form a second stacked structure and a second hybrid bond between the third wafer and the fourth wafer, and finally bonding the first stacked structure to the second stacked structure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that it comprises: bonding a first wafer to a second wafer to form a first stacked structure and a first hybrid bond between the first wafer and the second wafer; bonding a third wafer to a fourth wafer to form a second stacked structure and a second hybrid bond between the third wafer and the fourth wafer; and bonding the first stacked structure to the second stacked structure.

2. The method as described in claim 1, further comprising: providing the first wafer, comprising: a first substrate; a first intermetallic dielectric layer disposed on the first substrate; and a first metal interconnect disposed within the first intermetallic dielectric layer; providing the second wafer, comprising: a second substrate; a second intermetallic dielectric layer disposed on the second substrate; and a second metal interconnect disposed within the second intermetallic dielectric layer; bonding the first metal interconnect and the second metal interconnect to form the first hybrid bond; providing the third wafer, comprising: a third substrate; a third intermetallic dielectric layer disposed on the third substrate; and a third metal interconnect disposed within the third intermetallic dielectric layer; providing the fourth wafer, comprising: a fourth substrate; a fourth intermetallic dielectric layer disposed on the fourth substrate; and a fourth metal interconnect disposed within the fourth intermetallic dielectric layer; The third metal interconnect and the fourth metal interconnect are joined to form the second hybrid bond.

3. The method as described in claim 2, wherein the thickness near the edge of the second substrate is different from the thickness near the center of the second substrate.

4. The method as described in claim 2 further comprises: trimming the edge of the first stacked structure; planarizing the bottom surface of the second substrate; forming a first silicon through-hole in the second substrate; and forming a fifth metal interconnect on the first silicon through-hole.

5. The method as described in claim 4 further comprises: trimming the edge of the second stacked structure; planarizing the bottom surface of the fourth substrate; forming a second silicon through-hole in the fourth substrate; and forming a sixth metal interconnect on the second silicon through-hole.

6. The method as described in claim 5 further comprises: joining the fifth metal interconnect and the sixth metal interconnect to form a third hybrid bond.

7. The method as described in claim 1 further comprises: forming a first edge structure at the edge of the first stacked structure; and forming a second edge structure at the edge of the second stacked structure.

8. The method as described in claim 7, wherein the first edge structure and the second edge structure are asymmetrical.

9. The method as described in claim 7, wherein the first edge structure comprises: a first protective layer disposed on the edge of the first stacked structure; a first redistribution layer (RDL) disposed on the first protective layer; and a second protective layer disposed on the first redistribution layer.

10. The method as described in claim 7, wherein the second edge structure comprises: a third protective layer disposed on the edge of the second stacked structure; a second redistribution layer disposed on the third protective layer; and a fourth protective layer disposed on the second redistribution layer.

11. A semiconductor device, characterized in that it comprises: a first stacked structure, comprising: a first wafer bonded to a second wafer; a first hybrid bond disposed between the first wafer and the second wafer; a first edge structure disposed at the edge of the first stacked structure; and a second stacked structure, comprising: a third wafer bonded to a fourth wafer; a second hybrid bond disposed between the third wafer and the fourth wafer; and a second edge structure disposed at the edge of the second stacked structure, wherein the first edge structure and the second edge structure are asymmetrical.

12. The semiconductor device as described in claim 11 further comprises: the first wafer comprising: a first substrate; a first intermetallic dielectric layer disposed on the first substrate; and a first metal interconnect disposed within the first intermetallic dielectric layer; the second wafer comprising: a second substrate; a second intermetallic dielectric layer disposed on the second substrate; and a second metal interconnect disposed within the second intermetallic dielectric layer; the third wafer comprising: a third substrate; a third intermetallic dielectric layer disposed on the third substrate; and a third metal interconnect disposed within the third intermetallic dielectric layer; the fourth wafer comprising: a fourth substrate; a fourth intermetallic dielectric layer disposed on the fourth substrate; and a fourth metal interconnect disposed within the fourth intermetallic dielectric layer.

13. The semiconductor device as described in claim 12, wherein the first metal interconnect and the second metal interconnect include the first hybrid bond.

14. The semiconductor device as described in claim 12, wherein the third metal interconnect and the fourth metal interconnect include the second hybrid bond.

15. The semiconductor device as described in claim 12 further comprises: a first silicon through-hole disposed in the second substrate; a fifth metal interconnect disposed on the first silicon through-hole; a second silicon through-hole disposed in the fourth substrate; and a sixth metal interconnect disposed on the second silicon through-hole.

16. The semiconductor device as described in claim 15, wherein the fifth metal interconnect and the sixth metal interconnect comprise a third hybrid bond.

17. The semiconductor element as described in claim 12, wherein the thickness near the edge of the second substrate is different from the thickness near the center of the second substrate.

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