Vertical power semiconductor device

Abstract

A vertical power semiconductor device includes a semiconductor substrate containing N-type carriers, a semiconductor layer and sources, wells containing P-type carriers disposed within the semiconductor layer, gate components, and a source contact layer. The semiconductor layer is located on the semiconductor substrate and has a top surface. Each well has a doped region extending from the interior of the semiconductor layer to the top surface and a heavily doped region extending from the interior of the doped region to the top surface. Each source is disposed within its respective doped region, extends to the top surface, and surrounds its respective heavily doped region. Gate components are disposed on the top surface and each has a dielectric layer, a gate layer, and an insulating layer covering the dielectric layer and the gate layer. The source contact layer covers the source, the heavily doped region, and the insulating layer. The gate layer, projected orthographically above the source contact layer, is annular, with partial contact between two adjacent gate layers and four adjacent gate layers defining vias filled with the insulating layer.

Claims

1. A vertical power semiconductor device, comprising: a semiconductor substrate containing first conductivity type carriers; a semiconductor layer formed on the semiconductor substrate and containing the first conductivity type carriers, the semiconductor layer having a top surface remote from the semiconductor substrate; a plurality of wells disposed at intervals within the semiconductor layer and containing second conductivity type carriers opposite to the first conductivity type carriers, each well including a doped region extending from an interior of the semiconductor layer to the top surface and a heavily doped region extending from an interior of the doped region to the top surface with a doping concentration higher than that of the doped region; a plurality of sources, each disposed within its corresponding doped region and containing the first conductivity type carriers, each source extending from the interior of its corresponding doped region to the top surface and surrounding its corresponding heavily doped region; Multiple gate components are disposed at intervals on the top surface of the semiconductor layer. Each gate component includes a dielectric layer disposed on the top surface, a gate layer disposed on the dielectric layer, and an insulating layer covering the dielectric layer and the gate layer; and a source contact layer covering and contacting the sources, the heavily doped regions, and the insulating layer; wherein... The gate layers obtained by projecting a downward orthographic projection from above the source contact layer are in a ring shape. The gate layers of two adjacent gate components are partially in contact, and the gate layers of every four adjacent gate components define a through hole for filling the insulating layer of every four adjacent gate components. Each gate layer covers its corresponding source and doped region and surrounds its corresponding heavily doped region.

2. The vertical power semiconductor device as claimed in claim 1, wherein, The ring shape is selected from either a ring-shaped regular hexagon or a ring-shaped parallelogram.

3. The vertical power semiconductor device as claimed in claim 2, wherein, The ring is a regular hexagon, and each gate layer in the ring hexagon has a pair of first parallel sides, a pair of second parallel sides, and a pair of third parallel sides. The first parallel sides of each pair of adjacent gate layers are in complete contact, the second parallel sides of each pair of adjacent gate layers are in partial contact, the third parallel sides of each pair of adjacent gate layers are not in contact, and the second and third parallel sides of each pair of four adjacent gate layers together define their respective through holes for filling the insulating layers of each pair of four adjacent gate components.

4. The vertical power semiconductor device as claimed in claim 2, wherein, The ring is a parallelogram, and each gate layer in the parallelogram has a pair of first parallel sides and a pair of second parallel sides. The first parallel sides of each pair of adjacent gate layers are in partial contact, and the second parallel sides of each pair of adjacent gate layers are not in contact. The first parallel sides and second parallel sides of each pair of four adjacent gate layers together define their respective through holes for filling the insulating layers of each pair of four adjacent gate components.

5. The vertical power semiconductor device as claimed in claim 1, wherein, Each through-hole, obtained by projecting the orthographic projection downwards from above the source contact layer, is a parallelogram and has a predetermined area, which is between 0.04 μm² and 32 μm².

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