Photonic interposer and computing system thereof

Abstract

This invention describes a photonic intermediary layer for achieving low-power, high-bandwidth inter-chip (e.g., board-level and / or rack-level) and intra-chip communication. Techniques, architectures, and procedures for improving the performance of conventional computers are described herein. Some embodiments provide a photonic intermediary layer using photonic tiles, wherein each tile includes programmable photonic circuitry programmable based on the needs of a specific computer architecture. Some tiles are exemplified as a shared template tile spliced ​​together in a 1D or 2D configuration. Some embodiments described herein provide a programmable physical network designed to connect tile pairs together using photonic links.

Description

[Previous Technology]

[0001] A computer system includes random access memory (RAM) for storing data and machine code. RAM is typically volatile memory, meaning that the information stored is lost when power is off. In modern implementations, the memory is in the form of integrated circuits. Each integrated circuit contains several memory cells. To enable access to the stored data and machine code, the memory is positioned in electrical communication with the processor. Typically, this electrical communication is implemented as metal traces formed on a substrate on which the memory and processor are mounted. [Summary of the Invention]

[0002] Certain embodiments relate to a photonic interposer comprising a plurality of photonic tiles, the plurality of photonic tiles being an example of a template photonic tile, each of the plurality of photonic tiles comprising: a transceiver including a transmitter and a receiver; electrical connections coupled to the transceiver, the electrical connections being configured to allow electrical communication between the transceiver and the electronic chip when an electronic chip is attached to the photonic interposer corresponding to the photonic tile; an optically distributed network comprising a first set of bus waveguides, a second set of bus waveguides optically coupled to the transceiver, and a plurality of programmable interconnects, each programmable interconnect being configured to selectively place one of the first set of bus waveguides for optical communication with one of the second set of bus waveguides, wherein each programmable interconnect includes a waveguide crossover and an active coupler.

[0003] In some embodiments, the transceiver includes: a plurality of modulators coupled to a first bus waveguide in the first group of bus waveguides, the plurality of modulators being tuned relative to each other at different wavelengths; and a plurality of offload filters coupled to a second bus waveguide in the first group of bus waveguides, the plurality of offload filters being tuned relative to each other at different wavelengths.

[0004] In some embodiments, the plurality of modulators are resonant modulators, and the plurality of take-off filters are resonant take-off filters.

[0005] In some embodiments, the transmitter is configured to transmit data along one of the first bus waveguides in the first set of bus waveguides in a first direction or in a second direction.

[0006] In some embodiments, each of the plurality of photonic tiles further includes a 2×2 coupler that couples the transceiver to one of the first bus waveguides in the first set of bus waveguides.

[0007] In some embodiments, the 2×2 coupler includes a first terminal, a second terminal, a third terminal and a fourth terminal, wherein: the first terminal is coupled to one output of the transmitter, the second terminal is coupled to one input of the receiver, and the third terminal and the fourth terminal are coupled to the first bus waveguide in the first group of bus waveguides.

[0008] In some embodiments, each of the plurality of photonic tiles further includes an interferometer having an input and a first output and a second output, and a resonant filter, wherein:

[0009] The transmitter is coupled to the input of the interferometer, and the first output and the second output of the interferometer are coupled to the resonant filter, and the resonant filter is coupled to the first bus waveguide in the first group of bus waveguides.

[0010] In some embodiments, each of the plurality of photonic tiles further includes an interferometer having an output and a first input and a second input, and a resonant filter, wherein the resonant filter is coupled to the first bus waveguide in the first set of bus waveguides, the first input and the second input of the interferometer are coupled to the resonant filter, and the receiver is coupled to the output of the interferometer.

[0011] In some embodiments, the waveguide cross includes a first waveguide patterned in a first waveguide layer, a second waveguide patterned in a second waveguide layer, and a third waveguide patterned in a third waveguide layer, wherein the second waveguide layer is located between the first waveguide layer and the third waveguide layer, and the first waveguide is evanescently coupled to the second waveguide, and the second waveguide is evanescently coupled to the third waveguide.

[0012] In some embodiments, the first waveguide layer is made of silicon, and both the second and third waveguide layers are made of silicon nitride.

[0013] In some embodiments, the action coupler includes a first terminal coupled to one of a first additional action couplers, a second terminal coupled to one of the first additional action couplers, and a third terminal coupled to one of the waveguide crossovers.

[0014] In some embodiments, the action coupler includes a first Mach-Zehnder interferometer and a second Mach-Zehnder interferometer (MZI), wherein the first terminal corresponds to a first output of the first MZI, the second terminal corresponds to a second output of the first MZI, and the third terminal corresponds to an output of the second MZI.

[0015] In some embodiments, the bus waveguides in the second group of bus waveguides traverse multiple photonic tiles.

[0016] Certain embodiments relate to a photonic interposer comprising a plurality of photonic tiles, the plurality of photonic tiles being an example of a template photonic tile, the plurality of photonic tiles including a first photonic tile, a second photonic tile, a third photonic tile, and a fourth photonic tile, each of the plurality of photonic tiles including: a first transceiver; and electrical connections coupled to the first transceiver, the electrical connections being configured to allow electrical communication between the first transceiver and the electronic chip when an electronic chip is attached to the photonic interposer corresponding to the photonic tile; a first bus waveguide and a second bus. Waveguides, each traversing the first photonic tile and the second photonic tile; a third bus waveguide and a fourth bus waveguide, each traversing the third photonic tile and the fourth photonic tile; and a first optical fiber and a second optical fiber, wherein: the first optical fiber, the first bus waveguide, and the fourth bus waveguide place the first transceiver of the first photonic tile in optical communication with the first transceiver of the fourth photonic tile, and the second optical fiber, the second bus waveguide, and the third bus waveguide place the first transceiver of the second photonic tile in optical communication with the first transceiver of the third photonic tile.

[0017] In some embodiments, each of the plurality of photonic tiles further includes a second transceiver, wherein the second transceiver of the first photonic tile is in optical communication with the second transceiver of the second photonic tile.

[0018] In some embodiments, the second transceiver of the third photonic tile is in optical communication with the second transceiver of the fourth photonic tile.

[0019] In some embodiments, the photonic interposer further includes a third optical fiber, wherein the third optical fiber, the first bus waveguide, and the fourth bus waveguide place the first transceiver of the first photonic tile in further optical communication with the first transceiver of the fourth photonic tile.

[0020] In some embodiments, the first optical fiber, the third optical fiber, the first bus waveguide, the fourth bus waveguide, the first transceiver of the first photonic tile, and the first transceiver of the fourth photonic tile form a closed loop.

[0021] In some embodiments, the photonic interposer further includes a fourth optical fiber, wherein the fourth optical fiber, the second bus waveguide, and the third bus waveguide place the first transceiver of the second photonic tile in further optical communication with the first transceiver of the third photonic tile.

[0022] In some embodiments, the second optical fiber, the fourth optical fiber, the second bus waveguide, the third bus waveguide, the first transceiver of the second photonic tile, and the first transceiver of the third photonic tile form a closed loop.

[0023] Some embodiments relate to a computing system comprising: a photonic interposer layer including a plurality of photonic tiles, exemplified as a template photonic tile; a first application-specific integrated circuit (ASIC) and a second application-specific integrated circuit (ASIC) disposed on the photonic interposer layer, wherein the first ASIC is coupled to one of the plurality of photonic tiles, and the second ASIC is coupled to one of the plurality of photonic tiles, the second ASIC being coupled to one of the plurality of photonic tiles; a data path arranging the first ASIC to communicate with the second ASIC, the data path including: a first die-to-die... A first die-to-die (D2D) interface, in which the first ASIC is embedded, the first die-to-die interface being composed of a plurality of wires; a first plurality of SerDes coupled to the plurality of wires; a plurality of optical modulators coupled to the plurality of SerDes, the plurality of optical modulators being formed in the first photonic tile; a plurality of optical detectors coupled to the plurality of optical modulators, the plurality of optical detectors being formed in the second photonic tile; a second plurality of SerDes coupled to the plurality of optical detectors; and a second D2D interface, in which the second ASIC is embedded.

[0024] In some embodiments, the plurality of optical detectors are coupled to the plurality of optical modulators via waveguides formed on the photonic intermediary layer.

[0025] In some embodiments, the plurality of optical detectors are coupled to the plurality of optical modulators via optical fibers.

[0026] In some embodiments, the first D2D interface and the second D2D interface include an Advanced Interface Bus (AIB) interface.

[0027] In some embodiments, the first D2D interface and the second D2D interface include a Universal High Speed ​​Wafer Interconnect (UCIe) interface.

[0028] In some embodiments, the data path extends from the first D2D interface across a length greater than 2.5 cm to the second D2D interface.

[0029] Some embodiments relate to a method for fabricating a photonic package, comprising: obtaining a photonic interposer having a grating coupler formed on a first surface of the photonic interposer; attaching an electronic chip to the first surface of the photonic interposer; encapsulating the electronic chip with an encapsulating material; placing a protective material on the first surface of the photonic interposer to cover the grating coupler; after placing the protective material, forming electronic connections on a second surface of the photonic interposer opposite to the first surface; and after forming the electronic connections, removing the protective material from the first surface of the photonic interposer to expose the grating coupler to air.

[0030] In some embodiments, the method further includes cleaning the first surface of the photonic intermediary layer after removing the protective material from the first surface of the photonic intermediary layer.

[0031] In some embodiments, the method further includes: attaching an optical fiber to the first surface of the photonic interposer after removing the protective material, such that the optical fiber is optically coupled to the grating coupler during attachment.

[0032] In some embodiments, when the fiber is optically coupled to the grating coupler, the fiber forms a non-zero angle with respect to the first surface of the photonic intermediary layer.

[0033] In some embodiments, attaching the electronic chip to the first surface of the photonic interposer is performed after the protective material is placed on the first surface of the photonic interposer.

[0034] In some embodiments, the protective material includes a photoimageable dielectric.

[0035] In some embodiments, the placement of the protective material on the first surface of the photonic interposer is performed after the electronic chip is attached to the first surface of the photonic interposer.

[0036] In some embodiments, placing the protective material on the first surface of the photonic interposer is performed after encapsulating the electronic chip with the encapsulation material.

[0037] In some embodiments, the protective material includes a glass cover having a releasable adhesive.

[0038] Some embodiments relate to a method for fabricating a photonic package, comprising: obtaining a photonic interposer having a grating coupler formed on a first surface of the photonic interposer; attaching an electronic chip to the first surface of the photonic interposer; encapsulating the electronic chip with an encapsulating material such that the encapsulating material exposes the grating coupler to air; placing the photonic interposer on a carrier device to cover the grating coupler; after placing the photonic interposer on the carrier device, forming electronic connections on a second surface of the photonic interposer opposite to the first surface; and after forming the electronic connections, removing the carrier device.

[0039] In some embodiments, encapsulating the electronic chip is performed after attaching the electronic chip to the first surface of the photonic interposer.

[0040] In some embodiments, the method further includes: after removing the carrier device, separating the photonic intermediary layer into a plurality of systems, each including an electronic chip and a grating coupler.

[0041] In some embodiments, the method further includes: after removing the protective material, attaching an optical fiber to the first surface of the photonic interposer such that the optical fiber is optically coupled to the grating coupler during attachment.

[0042] In some embodiments, when the fiber is optically coupled to the grating coupler, the fiber forms a non-zero angle with respect to the first surface of the photonic interposer.

[0043] Some embodiments relate to a photonic package comprising: a photonic interposer; a first electronic chip disposed on the photonic interposer; a circuit board having a first surface and a second surface opposite to the first surface, wherein the photonic interposer is coupled to the first surface of the circuit board; a voltage regulator module (VRM) coupled to the second surface of the circuit board; and a connector configured to provide an output voltage of the VRM to the first electronic chip, wherein the connector traverses the circuit board and the photonic interposer.

[0044] In some embodiments, the photonic package further includes a substrate and a socket, wherein the photonic interposer is disposed on the substrate and the substrate is disposed on the socket.

[0045] In some embodiments, the connector further extends across the substrate and the socket.

[0046] In some embodiments, the photonic package further includes a power bus configured to provide an input voltage to one of the voltage regulator modules.

[0047] In some embodiments, the voltage regulator module receives the input voltage from the power bus and regulates the output voltage to the first electronic chip.

[0048] In some embodiments, the first electronic chip is in contact with the photonic intermediary layer.

[0049] In some embodiments, the photonic package further includes a cover covering the photonic interposer and a cold plate covering the cover, wherein the cover is in thermal contact with the first electronic chip.

[0050] Some embodiments relate to a photonic device comprising: a photonic circuit; a plurality of optical channels having a plurality of wafer-to-fiber couplers and a plurality of waveguides coupled to individual wafer-to-fiber couplers; an optical switch coupled between the plurality of optical channels and the optical circuit; and a controller configured to: determine information indicating a performance associated with each of the plurality of optical channels; use the information indicating the performance associated with each of the plurality of optical channels to identify a subgroup of the plurality of optical channels; and control the optical switch to selectively couple the subgroup of the plurality of optical channels to the photonic circuit.

[0051] In some embodiments, the plurality of optical channels further includes a plurality of photodetectors coupled to individual waveguides, and wherein the information determining the performance associated with each of the plurality of optical channels includes determining one of the outputs of each of the plurality of photodetectors.

[0052] In some embodiments, the plurality of photodetectors are coupled to the individual waveguides via tap couplers.

[0053] In some embodiments, determining the information indicating the performance associated with each of the plurality of optical channels includes determining a bit error rate (BER) associated with each of the plurality of optical channels.

[0054] In some embodiments, the photonic circuit includes a plurality of tiles patterned according to a template tile, wherein each tile includes: a transmitter; a receiver; a programmable optical interconnect network; and electrical connectors configured for vertical die-to-die connections to an electronic chip, the electrical connectors being coupled to the transmitter, the receiver and the programmable optical interconnect network.

[0055] In some embodiments, using the information to identify the subgroup of the plurality of optical channels includes identifying the subgroup of the plurality of optical channels that exhibits the best performance.

[0056] In some embodiments, the wafer-to-fiber couplers include edge couplers or grating couplers.

[0057] In some embodiments, the controller is further configured to control the photonic circuit to transmit data outside the photonic device using the subgroup of the plurality of optical channels selected by the optical switch.

[0058] Certain embodiments relate to a method for transmitting data using a photonic device, the photonic device including an optical switch and a plurality of optical channels having a plurality of chip-to-fiber couplers and a plurality of waveguides coupled to individual chip-to-fiber couplers, the method comprising: determining information indicating a performance associated with each of the plurality of optical channels; using the information indicating the performance associated with each of the plurality of optical channels to identify a subgroup of the plurality of optical channels; controlling the optical switch to select the subgroup of the plurality of optical channels; and using the subgroup of the plurality of optical channels selected by the optical switch to transmit the data outside the photonic device.

[0059] In some embodiments, the plurality of optical channels further includes a plurality of photodetectors coupled to individual waveguides, and wherein the information determining the performance associated with each of the plurality of optical channels includes determining one of the outputs of each of the plurality of photodetectors.

[0060] In some embodiments, determining the information indicating the performance associated with each of the plurality of optical channels includes determining a bit error rate (BER) associated with each of the plurality of optical channels.

[0061] In some embodiments, using the information to identify the subgroup of the plurality of optical channels includes identifying the subgroup of the plurality of optical channels that exhibits the best performance.

[0062] Some embodiments relate to a photonic interposer layer comprising: a plurality of photonic tiles, including a redundant tile, each photonic tile including: a transmitter; a receiver; a programmable optical interconnect; electrical connectors configured for vertical die-to-die connections to an electronic chip, the electrical connectors being coupled to the transmitter, the receiver, and the programmable optical interconnect; a monitoring photodetector; and a controller configured to: use the output of one of the respective monitoring photodetectors to determine information indicating the performance of each of the plurality of photonic tiles; use the information indicating the performance of each of the plurality of photonic tiles to identify a defective tile among the plurality of tiles; and functionally exchange the defective tile with the redundant tile.

[0063] In some embodiments, functionally exchanging the defective tile with the redundant tile includes redirecting data directed to the defective tile to the redundant tile.

[0064] In some embodiments, rebooting the data includes programming a programmable photonic network.

[0065] Some embodiments relate to a photonic interposer layer comprising: a bus waveguide; a plurality of photonic transmitters coupled to the bus waveguide; a plurality of photonic receivers coupled to the bus waveguide; and a controller configured to lock one of the plurality of photonic transmitters to one of the plurality of photonic receivers by: jittering a photonic component of the first photonic transmitter at a first frequency; and jittering a photonic component of the first photonic receiver at the first frequency.

[0066] In some embodiments, each of the plurality of photonic transmitters includes a resonant modulator, and each of the plurality of photonic receivers includes a resonant de-extraction filter coupled to the bus waveguide, wherein: jittering the photonic component of the first photonic transmitter includes jittering the resonant modulator of the first photonic transmitter, and jittering the photonic component of the first photonic receiver includes jittering the resonant de-extraction filter of the first photonic receiver.

[0067] In some embodiments, each of the plurality of photonic transmitters includes a resonant addition filter coupled to the bus waveguide, and each of the plurality of photonic receivers includes a resonant removal filter coupled to the bus waveguide, wherein: jittering the photonic component of the first photonic transmitter includes jittering the resonant addition filter of the first photonic transmitter, and jittering the photonic component of the first photonic receiver includes jittering the resonant removal filter of the first photonic receiver.

[0068] In some embodiments, the first frequency is between 1 kHz and 1000 kHz.

[0069] In some embodiments, the photonic intermediary layer further includes a plurality of photonic tiles, exemplified as a template photonic tile, each of the plurality of photonic tiles including one of the plurality of photonic transmitters and one of the plurality of photonic receivers, wherein the bus waveguide traverses more than one photonic tile.

[0070] Some embodiments relate to a photonic transmitter comprising: a resonant modulator configured to modulate light received from a laser using input data; a Mach-Rendt interferometer (MZI) coupled to the resonant modulator, the MZI having a first output and a second output; a resonant addition filter coupled to a bus waveguide; and a controller configured to selectively couple the first or second output of the MZI to the resonant addition filter to transmit the modulated light along the bus waveguide in a first direction or a second direction.

[0071] In some embodiments, the photonic transmitter further includes a heater thermally coupled to the resonant modulator and a first monitoring detector coupled to the first output of the MZI, wherein the controller is further configured to lock the resonant modulator to the laser by applying a first ramp signal to the heater and maximizing an output generated by the first monitoring detector.

[0072] In some embodiments, selectively coupling the first output or the second output of the MZI to the resonant addition filter includes: applying a second ramp signal to the MZI; and minimizing the output generated by the first monitoring detector.

[0073] In some embodiments, selectively coupling the first output or the second output of the MZI to the resonant addition filter further includes: applying a third ramp signal to the resonant addition filter; and minimizing the output generated by the second monitoring detector coupled to the second output of the MZI.

[0074] In some embodiments, the resonant addition filter includes a second-order filter.

[0075] Some embodiments relate to a photonic interposer layer comprising: a first photonic tile and a second photonic tile, exemplified by a template photonic tile, each of the first photonic tile and the second photonic tile including a transceiver and a receiver; an optical channel coupling the transmitter of the first photonic tile to the receiver of the second photonic tile; an encoder coupled to the transmitter of the first photonic tile, the encoder being configured to perform an Xb / Yb encoding scheme; a decoder coupled to the receiver of the second photonic tile, the decoder being configured to perform an Xb / Yb decoding scheme; and a clock recovery circuit system configured to time the receiver of the second photonic tile using one output of the decoder.

[0076] In some embodiments, the photonic intermediary layer further includes a first local oscillator coupled to one of the encoders and a second local oscillator coupled to one of the decoders.

[0077] In some embodiments, the photonic intermediary layer further includes an equalizer coupled to the receiver of the second photonic tile, wherein the equalizer is configured to perform a linear combination of the outputs of the receiver of the second photonic tile.

[0078] In some embodiments, the equalizer is further configured to determine a characteristic of the optical channel during operation, and is configured to adjust the number of taps associated with the equalizer based on the characteristic of the optical channel determined by the equalizer.

[0079] In some embodiments, the equalizer is further configured to determine a characteristic of the optical channel during operation and to adjust the coefficients associated with the equalizer based on the characteristic of the optical channel determined by the equalizer.

Implementation Method

[0153] Cross-reference to related applications This application claims the following rights: U.S. Provisional Application No. 63 / 324,598, filed on March 28, 2022, with agent file number L0858.70053US00 and titled "PACKAGE ASSEMBLY FLOW AND MATERIALS"; U.S. Provisional Application No. 63 / 325,113, filed on March 29, 2022, with agent file number L0858.70053US01 and titled "PACKAGE ASSEMBLY FLOW AND MATERIALS"; and U.S. Provisional Application No. 63 / 332,518, filed on April 19, 2022, with agent file number L0858.70053US02 and titled "PACKAGE ASSEMBLY FLOW AND MATERIALS". The following are U.S. provisional application serial numbers: 63 / 327,717, filed on April 5, 2022, with agent file number L0858.70054US00, entitled "METHOD FOR OPTICAL FIBER ATTACH ON 3D STACKED WAFER"; 63 / 355,275, filed on June 24, 2022, with agent file number L0858,70057US00, entitled "WAFER-SCALE HETEROGENEOUS COMPUTING SYSTEMS"; and 63 / 355,275, filed on August 12, 2022, with agent file number L0858,70059US00, entitled "INCREASING THE YIELD OF FIBER ATTACH BY". The following U.S. provisional application serial number 63 / 397,609, entitled "REDUNDANCY"; and the following U.S. provisional application serial number 63,428,003, filed on November 25, 2022, with agent file number L0858,70061US00, entitled "PHOTONIC PROGRAMMABLE INTERCONNECT CONFIGURATIONS", are hereby incorporated in their entirety hereof. I. Overview

[0154] The inventors have recognized and understood several challenges limiting the scalability of modern digital computing. First, current designs are power-constrained. The trends in modern computing have led to ever-increasing power consumption, which limits scalability. In addition, the high-power nature of modern chips results in hot spots, typically exceeding 100°C. High temperatures severely limit computer performance. Second, modern computing architectures are bandwidth-constrained. These architectures rely on multiple memory chips to provide the hundreds of gigabits or hundreds of megabits of capacity required by modern applications. Unfortunately, providing connectivity among several memory chips is challenging. The physical space available to accommodate interconnects on a board or rack is limited, thus limiting overall bandwidth. Furthermore, maintaining consistency and coherence across several memory chips (e.g., memory-to-memory and processor-to-memory) is difficult to achieve. Some architectures rely on peripheral component interconnects (PCI), compute links (CXL), or Ethernet for chip-to-chip communication. However, such interfaces involve board-level or rack-level communication, which increases power consumption and reduces bandwidth. Wafer-level electrical communication has also been explored, but this approach is plagued by reliability issues and power inefficiency.

[0155] The inventors have developed a photonic intermediary layer for achieving low-power, high-bandwidth inter-chip (e.g., board-level and / or rack-level) and intra-chip communication. Techniques, architectures, and procedures for improving the performance of conventional multi-chip computers are described herein. Some embodiments provide a photonic intermediary layer using "photonic modules" (also referred to herein as "photonic tiles" or simply "tiles"). Each tile contains programmable photonic circuitry that can be programmed based on the needs of a specific computer architecture. Some photonic intermediary layers are configured according to a one-dimensional scheme, such as in a 3×1 tile block, in a 5×1 tile block, in a 10×1 module, or in a 20×1 tile block. Some photonic intermediary layers are configured according to a two-dimensional scheme, such as in a 3×3 tile block, in a 5×3 tile block, in a 5×5 tile block, or in a 10×10 tile block. More generally, the photonic interposer layer achieves any N×M tile block (where N≥1 and M≥1) and any topology such as T-shaped, L-shaped, X-shaped, etc. Each tile can serve as a node in a computing system. At each node, there can be one or more digital processor chips, one or more analog accelerators, one or more photonic accelerators, one or more memory chips, one or more network interconnect chips, or other devices.

[0156] The photonic interposer systems described herein are engineered in a way that limits manufacturing costs. These platforms can rely on using a common mask set (or at least one common mask) to fabricate multiple tiles. This approach reduces costs in two ways. First, it reduces the additional costs incurred by otherwise obtaining several different mask sets. Second, it allows the fabrication of tiles using standard semiconductor foundries that require the use of the same mask set (or at least one mask) across an entire wafer. Designing tiles that share at least one mask enables the fabrication of multiple tiles on the same semiconductor wafer while utilizing standard, low-cost, step-by-step repetitive manufacturing processes. Thus, in some embodiments, the tiles are exemplified as a common template tile (replica) stitched together in a 1D configuration or a 2D configuration. Some embodiments involve two template tiles, such that each tile of an interposer is formed as an example of a first template tile or as an example of a second template tile. For example, tiles of different templates can alternate in a chessboard-like manner, such that each tile of the first type is adjacent to a tile of the second type. Other configurations are also possible.

[0157] In one example, a photonic interposer comprises a 6×8 tile array, where each tile is an example of a scaled-down mask screenshot from a step-by-step repetitive fabrication process. Each tile is 24.8 mm × 32 mm in size and can support heterogeneous technologies (e.g., general-purpose processors, GPUs, DRAM / HBM stacks, or custom accelerators). With a waveguide pitch of 3 μm, the photonic interposer can well support more than 10,000 optical links escaping from each tile.

[0158] Certain embodiments described herein provide a programmable physical network designed to connect tile pairs together using photonic links. The communicating tiles do not need to be adjacent. For example, the physical network can be programmable so that a tile in the upper left corner can communicate directly with a tile in the lower right corner without retransmission at intermediate tiles. Network configuration time may be less than 10 μs, and communication between any two tiles—whether adjacent or not—may have a relay latency of less than 5 ns. The photonic intermediary layer described herein provides flexibility in forming various logical network topologies (e.g., from a low cardinality high-diameter mesh topology to a high cardinality low-diameter bus topology). For example, a 4×4 photonic intermediary layer can map an all-pair, all-logical network with dedicated channels between each tile pair, and this network can provide a bandwidth of up to 14.4 Tbps per channel (between any two tiles), with a total bi-segmented bandwidth of up to 1851 Tbps. As another example, a single photonic intermediary layer can provide up to 231 Tbps of bandwidth per channel for a 2-ary, 4-winged butterfly network.

[0159] The photonic interposer described herein achieves an efficient heterogeneous architecture solution, thereby providing high bandwidth and low latency between chips via photonic links, while allowing chips designed from different technology nodes and performing different functions to be housed together on a single wafer. Furthermore, since a photonic interposer allows a large chip to be diced into multiple smaller chips, the photonic interposer described herein can solve the thermal constraints associated with large, high-power-consuming chips. The photonic interposer can host these smaller chips and provide energy-efficient communication (similar to on-chip communication) between them.

[0160] In a multi-chip system, each chip is typically connected to a dedicated main memory. Data is typically shared across multiple chips using Remote Direct Memory Access (RDMA) (e.g., via Last-Level Cache (LLC) or L2 cache). The photonic intermediary layer described herein can aggregate the main memories of all chips to form a shared global main memory. All chips can access this shared global main memory via photonic links. For example, LLCs can be partitioned from each chip, and LLCs can be moved to the vicinity of a shared global main memory while achieving low-latency and high-bandwidth communication between L2 cache pairs and LLC pairs on each chip. Keeping all LLCs together enables low-overhead consistency management across LLCs. In some embodiments, the photonic intermediary layer described herein can reduce the overhead of using standard cache coherence protocols (e.g., IV, MESI, and MOESI) across chips, for example, by achieving efficient design of a cache coherence Non-Uniform Memory Access Machine (NUMA) architecture.

[0161] In traditional architectures, processor chips communicate with memory chips (e.g., DRAM and HBM) using high-speed electrical links. However, the capacitance associated with these electrical links limits available bandwidth and leads to power consumption. Recently, co-packaged optics (CPO) has emerged as a potential alternative to electrical links. CPO uses fiber-optic-based communication links to provide communication between the processor and memory. Unfortunately, CPO is not a scalable solution for supporting communication between a processor chip and multiple memory chips using fiber-optic links, and vice versa remains challenging. In contrast, the photonic interposer described herein can host both the processor chip and memory dies on the same substrate, enabling high-bandwidth-density communication. Leveraging its wafer-level properties, the photonic interposer can diffuse a processor across multiple tiles, providing ample area for the processor components and numerous memory controllers. This enables architectures requiring multiple memory controllers per processor chip, such as one processor chip to multiple memory chips and one memory chip to multiple processor chips.

[0162] The photonic intermediary layer described herein can be used in a variety of applications, including machine learning, privacy protection, and graphics applications. The photonic intermediary layer can be used to support communication between analog computing chips (e.g., photons, memristors) and memory chips, communication between digital computing chips (e.g., processors, FPGAs, GPUs) and memory chips, network interconnect chips, digital switch chips, and communication between digital computing chips and analog computing chips.

[0163] Current machine learning models involve massive amounts of data (e.g., typically hundreds of GB to tens of TB). Therefore, a large amount of memory is required to store the model and data. Current technology does not provide sufficient memory in a single chip. The photonic interposer described in this paper provides a solution that integrates multiple memory chips into a single substrate while providing high-bandwidth, low-latency communication between memory chips and computing chips. The result is a reduction in execution time during training and inference operations.

[0164] As data privacy has become a primary consideration in system design, various privacy-preserving computational methods have been proposed. One such method is homomorphic encryption (HE). Memory bandwidth and latency are key bottlenecks in HE-based applications. The photonic intermediary layer described in this paper can alleviate this problem by providing access to memory with high bandwidth and low latency.

[0165] Graphics applications involve irregular access to memory. Moreover, graphics applications involve small data granularity because such applications typically do not use all the data present in a cache. The photonic intermediary layer described herein can overcome this bottleneck by achieving efficient access to memory through high-bandwidth, low-latency photonic links.

[0166] This paper describes the architecture, system, and procedures involving a tile-based photonic intermediary layer. II. Tile-based Photonic Intermediary Layer

[0167] Figure 1-1 illustrates an example computing system based on a photonic interposer layer having nine tiles in a 3×3 topology configuration. The computing system 10 includes a photonic interposer layer 20 patterned with nine tiles 22. This photonic interposer layer supports a processor die (30) located in the middle of the photonic interposer layer 20 and eight memory nodes surrounding the processor die. Some of the memory nodes contain a single memory chip (see, for example, memory die 32). Other memory nodes contain a stacked memory, which contains multiple vertically stacked memory dies (see, for example, stacked memory 34). The dies are stacked on top of a wafer defining the tiles. A die can communicate with the underlying tiles electronically (e.g., using through-silicon vias, copper pillars, microbumps, ball grid arrays, or other electrical interconnects) and / or optically (e.g., using grating couplers, prisms, lenses, or other optical couplers).

[0168] As further elaborated below, tiles can be patterned using optical waveguides and optical distributed networks. An optical distributed network of a tile can selectively place the dies of a particular node in optical communication with any other die of the computing system. For example, the optical distributed network of a tile located below the processor die 30 can be reconfigured depending on the processor's needs. At the start of a routine, the processor may need to access data stored in a first memory node. This read operation involves configuring individual optical distributed networks to place the processor in optical communication with the first memory node. Following this routine, the processor may need to write data to a second memory node. This write operation involves reconfiguring the optical distributed network to place the processor in optical communication with the second memory node.

[0169] Mass production of tiles can be costly. The photonic interposer systems described herein are engineered in a way that limits manufacturing costs. These platforms rely on using a common set of photomasks (a subset) to fabricate multiple tiles. This approach reduces costs in two ways. First, it reduces the additional costs that would otherwise be incurred when obtaining several different sets of photomasks. Second, it allows for the fabrication of tiles using standard semiconductor foundries that require the use of the same set of photomasks (or at least one photomask) across an entire wafer. Designing tiles that share at least one photomask enables the fabrication of numerous tiles on the same semiconductor wafer while utilizing standard, low-cost, step-by-step repetitive manufacturing processes.

[0170] The tiles described herein can be fabricated using microfabrication techniques including, for example, complementary metal-oxide-semiconductor (CMOS) microfabrication techniques. Therefore, some embodiments relate to silicon photonics-based optical interposers. Certain specific microfabrication techniques involve a step-repetition method—whereby a stepper is used to pattern a semiconductor wafer with multiple replicas of a template layout (e.g., a 1x reduction mask). Each tile obtained by the step-repetition method may correspond to a 1x reduction mask. Figures 1-2A to 1-2E illustrate the microfabrication techniques used to fabricate the tiles. Figures 1-3A and 1-3B illustrate examples of tiles patterned using these microfabrication techniques.

[0171] Referring first to Figure 1-2A, this figure illustrates a semiconductor wafer 11. Wafer 11 can be made of any material. For example, wafer 11 can be made of silicon (or otherwise contain silicon). In one example, wafer 11 is a silicon-on-insulator (SOI) wafer. In another example, wafer 11 is a block silicon wafer. Wafer 11 can have any size. For example, the diameter of wafer 11 can be 150 mm, 300 nm, or 450 mm, and other possible values. However, not all wafers need to have a circular shape.

[0172] Figure 1-2B illustrates a set of photomasks that can be used to pattern wafer 11 using photolithography. Photomask set 200 includes three photomasks (201, 202, and 203), although other sets may contain more or fewer photomasks. Each photomask has a specific pattern of opaque and transparent areas. When the photomask is exposed to light, the opaque areas block light, thereby preventing light from illuminating the wafer, while the transparent areas allow light to pass through. As a result, the pattern of the photomasks is transferred onto the wafer.

[0173] Each photomask can define a specific layer of a tile. A photomask can be used to define an optical waveguide. When a wafer undergoes an etching process, only the exposed areas (or only the unexposed areas) are etched away, while other areas remain unetched. When the wafer is exposed to light through this photomask, the photomask can be patterned to form an optical waveguide network. Figure 1-2C illustrates a portion of a photomask that can be used to form a waveguide on wafer 11. The lines of photomask 201 represent opaque areas. The background of photomask 201 is transparent. Exposing photomask 201 to light allows an image of the photomask to be projected onto wafer 11, enabling the waveguide to be patterned in the shape of the opaque areas. In this particular example, the line pattern of the photomask creates a waveguide mesh.

[0174] Some tiles involve the use of different levels of optical waveguides. In some such embodiments, the mask assembly 200 may include a dedicated mask for each waveguide level. Another mask may be used to define n-doped regions. When the wafer undergoes an ion implantation or dopant diffusion process, only exposed areas (or only unexposed areas) are doped, while other areas remain undoped. Using a similar process, another mask may be used to define p-doped regions. Some tiles involve the use of different doping concentrations. In some such embodiments, the mask assembly 200 may include a dedicated mask for each doping concentration. In other embodiments, the mask assembly 200 may include a mask for defining the deposition of semiconductor materials other than silicon (such as germanium and / or other materials of the periodic table, such as group III or group V)). Another mask may be used to define metal contacts. Another mask may be used to define metal traces. Some tiles involve the use of different levels of metal traces. In some such embodiments, the photomask assembly 200 may include a dedicated photomask for one of each metal trace level.

[0175] In some embodiments, wafer 11 is patterned in a step-repeating manner. When wafer 11 is processed in a stepper, a pattern of a photomask is repeatedly exposed across the surface of the wafer in a grid. This process involves moving the wafer back and forth and left and right under the lens of the stepper and exposing the photomask at each step length. The result is that wafer 11 is patterned with multiple copies of the pattern defined by a photomask. This operation can be repeated for each photomask (or at least some photomasks) in this group. Thus, in some embodiments, the tiles are copies of a common template tile stitched together in a 1D or 2D configuration. Other embodiments involve two template tiles, such that each tile of an interposer layer is formed as an example of a first template tile or an example of a second template tile. For example, tiles of different templates can be alternated in a chessboard-like manner, such that each tile of the first type is adjacent only to tiles of the second type. Other configurations are also possible.

[0176] In the example of Figures 1-2D, wafer 11 has been patterned using a grid of tiles 22. The tiles may share the patterns of one or more masks in group 200. For example, the tiles may share the same waveguide mask and / or the same m trace masks. In other embodiments, the tiles share the patterns of all masks in group 200. For example, the tiles may share the same optical waveguide pattern, the same n-doped pattern, the same p-doped pattern, the same contact pattern, the same metal trace pattern, etc.

[0177] In some embodiments, a photomask set 200 is used to pattern the entire surface of wafer 11. However, not all embodiments are limited to this approach, as some portions of wafer 11 may be patterned using a first photomask set, while other portions of wafer 11 may be patterned using a second photomask set. The first photomask set may correspond to a first magnification photomask, and the second photomask set may correspond to a second magnification photomask. The first and second types of magnification photomasks may alternate in a checkerboard-like pattern.

[0178] Once patterned, wafer 11 can contain multiple photonic circuits. In one example, the wafer of Figure 1-2E has been marked to obtain six photonic circuits from wafer 11. The photonic circuits are monolithically integrated with the wafer. This figure identifies a 1×1 photonic circuit with only one tile 22, a 2×2 photonic circuit with four tiles 22, a 2×3 photonic circuit with six tiles 22, and three 3×3 photonic circuits each with nine tiles 22. Separation of a photonic circuit from the wafer involves dicing the wafer along the periphery of the desired photonic circuit. In this case, the photonic circuits described herein can be considered as a wafer-level architecture. Once diced, each photonic circuit forms an independent photonic interposer layer. One of the 3×3 photonic circuits of wafer 11 can be used as a photonic interposer layer for the exemplary computing system of Figure 1-1 (see photonic interposer layer 20).

[0179] Figure 1-3A illustrates an exemplary tile 22. In this example, tile 22 is shaped as a rectangle (although other shapes such as squares or other polygons are also possible). Thus, tile 22 is bounded by four boundaries (boundaries 1, 2, 3, and 4). Boundary 1 is opposite to boundary 2, and boundary 3 is opposite to boundary 4. Boundary 1 is adjacent to boundaries 3 and 4, and boundary 2 is also adjacent to boundaries 3 and 4. Tile 22 includes an optical distributed network 104 coupled to one of waveguides 111, 112, 113, and 114. Waveguide 111 optically couples the optical distributed network 104 to boundary 1. Thus, optical signals coupled from the optical distributed network 104 to waveguide 111 can be transmitted to the outside of the tile by crossing boundary 1. Similarly, waveguide 112 optically couples the optical distributed network 104 to boundary 2, waveguide 113 optically couples the optical distributed network 104 to boundary 3, and waveguide 114 optically couples the optical distributed network 104 to boundary 4. In some embodiments, the boundary of a tile is defined based on a photolithography screenshot (e.g., the boundary is defined by the boundary of a photomask used to fabricate the tile). However, in other embodiments, a photolithography screenshot may define more than one tile. For example, a photomask may be patterned using multiple side-by-side examples of a template tile. In some such embodiments, the boundary of a tile is defined where adjacent examples of template tiles meet.

[0180] While the example illustrations of Figures 1-3A depict waveguides coupling an optical distributed network to each of the boundaries, not all embodiments are configured in this manner. In other embodiments, a tile 22 may include two of these four waveguides, such as waveguides 111 and 112, or waveguides 111 and 113. In yet another embodiment, a tile 22 may include three of these four waveguides, such as waveguides 111, 112, and 113. The optical distributed network 104 includes photonic components (e.g., photonic switches) for routing optical signals inside and outside the tile 22. Furthermore, the optical distributed network 104 may include a transmitter (providing an electro-optical interface with an electronic chip mounted on the tile) and a receiver (providing an optical-electrical interface with an electronic chip mounted on the tile). Examples of optical distributed networks will be discussed in detail in the following sections.

[0181] In some embodiments, a tile may comprise multiple layers of photonic waveguides. Similar to how multiple layers of conductive traces increase the ability of an electronic circuit to route electrical signals, multiple layers of waveguides increase the ability of a tile to route optical signals. In one example, one layer comprises a silicon waveguide, and one or more additional layers comprise silicon nitride waveguides. The choice of material for each waveguide layer may be determined by the wavelength of the light to be routed by the waveguide. For example, silicon and nitride layers may be used to route infrared light in the telecommunications band at wavelengths of approximately 1.3 μm or 1.5 μm. In some instances, the multiple layers of waveguides may also comprise aluminum nitride waveguides for routing visible light down to UV wavelengths or alumina waveguides for routing UV light. Each layer may be configured similarly to one of the configurations illustrated in Figures 1-3A—having an optical distributed network of signals routed within the waveguides of that layer.

[0182] The tile 22 may further include one or more out-of-plane couplers (not shown in Figures 1-3A). An out-of-plane coupler may be configured to emit light outside the xy-plane, for example, in a direction parallel to the z-axis or at an angle relative to the z-axis. An out-of-plane coupler may be further configured to capture light incident from outside the xy-plane. In some embodiments, an out-of-plane coupler enables optical communication between the tile 22 and a die disposed above and / or below the tile. An out-of-plane coupler may be implemented using any suitable optical components, including, for example, optical gratings, lenses, and prisms. In some embodiments, the optical distributed network may be configured such that the same out-of-plane coupler enables optical communication in two directions—from the optical distributed network 104 to a die and from the die to the optical distributed network 104. In some embodiments, an out-of-plane coupler enables optical communication between the tile 22 and an optical fiber.

[0183] The optical distributed network 104 can selectively couple any component of tile 22 to any other component of tile 22, as discussed in detail in the following sections. For example, the optical distributed network 104 can enable light to travel between waveguides 111 and 112, and / or between waveguides 111 and 113, and / or between waveguides 113 and 114. This can be achieved by equipping the optical distributed network with controllable optical switches.

[0184] The tile 22 may further include an electrical connector 117, which can be configured to provide electrical access to the tile from electronic chips mounted on it. For example, the electrical connector 117 may be in the form of a contact pad to provide a landing surface for bonding pads, bumps, vias, or other types of vertical chip-to-chip interconnects. The electrical connector 117 may be coupled to transmitters, receivers, and switches in an optical distributed network, thus providing electrical access to those photonic components from the electronic chips.

[0185] A photonic circuit may comprise multiple tiles connected together to form an optical network. Figure 1-3B illustrates an exemplary 2×3 photonic circuit comprising one of six tiles 22. This photonic circuit is obtained by dicing a group of 2×3 tiles from wafer 11 (see Figure 1-2E). The tiles 22 are configured such that: waveguide 111 of one optical module is aligned with waveguide 112 of the optical module to its left, waveguide 112 of one optical module is aligned with waveguide 111 of the optical module to its right, waveguide 113 of one optical module is aligned with waveguide 114 of the optical module above it, and waveguide 114 of one optical module is aligned with waveguide 113 of the optical module below it. As a result, the optical modules form an optical network. The optical distributed network 104 can route optical signals anywhere inside or outside the network. For example, suppose a processor is mounted on a tile located at the northwest corner of a photonic circuit, and a memory is mounted on a tile located at the southeast corner of the photonic circuit. A read operation may involve reconfiguring the optical distributed network (e.g., by controlling its optical switches) to position the processor in optical communication with the memory. For example, an optical communication path may be configured as follows: 1) coupling the processor to an out-of-plane coupler of the tile to which the processor is mounted, 2) coupling the out-of-plane coupler of the other tile to a waveguide 112 of the same tile, 3) coupling the waveguide 112 of the other tile to a waveguide 111 of an adjacent tile (the uppermost middle tile), 4) coupling the waveguide 112 of the uppermost middle tile to a waveguide 111 of the next adjacent tile (the northeast corner of the photonic circuit), 5) coupling the waveguide 114 of the tile located at the northeast corner to a waveguide 113 of the tile to which the memory is mounted, and 6) coupling the waveguide 113 of the tile to which the memory is mounted to an out-of-plane coupler of the same tile.

[0186] As discussed above, waveguides of adjacent tiles are optically coupled to each other, thereby allowing light to travel from one tile to the next. In some embodiments, the ends of the waveguides may be physically connected (although not all embodiments are limited to this particular configuration, as discussed in further detail below). In other embodiments, a gap may exist between the waveguides. In this example, each waveguide has one end located at a certain distance from the boundary. Thus, a gap is formed at the boundary region. Despite the gap, the waveguides of adjacent tiles are still optically coupled to each other. In this case, light emitted at one end of a waveguide actually travels through free space to the other end of the waveguide.

[0187] In some embodiments, the tile 22 may be patterned according to a common metal trace mask. As a result, the tiles share the same pattern of metal traces. In some embodiments, the tile 22 is patterned according to multiple common masks. As a result, multiple levels of metal traces span different tiles while sharing the same pattern. Some of the metal traces can be used to deliver power across a photonic circuit. For example, some of the metal traces can be configured to form a power grid, as discussed in further detail below. Figures 1-4A illustrate a 2×3 photonic circuit in which each tile 22 shares the same pattern of metal traces. For illustrative purposes, only the metal traces are shown in this figure, although each tile further includes waveguides, one or more out-of-plane couplers, and optical distributed networks. In this example, there are two levels of metal traces. The metal traces of each level are fabricated using the same mask across different tiles. Metal traces in metal trace layer 1 extend horizontally, thereby electrically coupling adjacent tiles in the horizontal direction. Metal traces in metal trace layer 2 extend vertically, thereby electrically coupling adjacent tiles in the vertical direction. Of course, other configurations are also possible. For example, in other embodiments, metal traces in the same layer can electrically couple one tile to all adjacent tiles.

[0188] Metal traces are configured to carry electricity (e.g., signals and / or power) across the boundaries of tiles. This can be achieved by patterning the metal traces to continuously cross the boundaries of tiles. In this example, the metal traces of level 1 continuously cross the vertical boundary, and the metal traces of level 2 continuously cross the horizontal boundary. Metal traces of different levels can be connected to each other using vias. In some embodiments, tiles can share vias with the same pattern. In other words, the same via mask can be used for each tile. In some embodiments, a tile can have more (tens to hundreds) metal traces. Some of these metal traces can be configured to continuously cross tiles, but in some embodiments, most metal traces do not need to be patterned to continuously cross modules. In one example, some metal traces can be patterned such that these metal traces do not reach the ends of a group of tiles, as shown in Figures 1-4B. This forms a moisture barrier between the slicing trace and the metal. Furthermore, these metal traces carrying signals and / or power may be connected to a through-silicon via (TSV), which connects to the substrate and / or other wafers placed on top of the tile. In some embodiments, the metal traces may also be connected to transistor components that can function as electronic switches, amplifiers, or TX / RX components. III. Optical Distributed Network

[0189] This section discusses an architecture for interconnecting tiles of a photonic interposer layer in a manner that achieves high bandwidth, low latency, and high resource utilization. The interconnection can be static or programmable.

[0190] A. Static link

[0191] Figure 2-1A illustrates an example of how tiles in a photonic interposer are interconnected using static connections. This example illustrates an interposer with four tiles in a one-dimensional configuration. Each tile has a transmitter (TX) and a receiver (RX). The transmitter may include (or be coupled to) a light source and an optical modulator. The optical modulator may be configured to encode light using information provided by electronic chips to which the tile is connected. Each receiver may include a photodetector to convert the signal provided by a transmitter into electricity. In this configuration, a waveguide couples the TX of a tile to the RX of an adjacent tile. This configuration is named "one hop to the right" because each waveguide immediately reaches the RX to the right of a TX.

[0192] Figure 2-1B illustrates another example of how tiles in a photonic interposer layer are interconnected using static connections. In this example, a waveguide couples the TX of one tile to the RX of a second adjacent tile. This configuration is named "two jumps to the right" because each waveguide reaches the RX two steps to the right of a TX.

[0193] Figure 2-1C illustrates another example of how tiles in a photonic interposer layer are interconnected using static connections. In this example, a waveguide couples the TX of one tile to the RX of a third adjacent tile. This configuration is named "3 hops to the right" because each waveguide reaches the RX three steps to the right of a TX.

[0194] The configurations of Figures 2-1D, 2-1E, and 2-1F are similar to those of Figures 2-1A, 2-1B, and 2-1C, respectively, except that optical fibers are added to close the loop. The use of optical fibers increases flexibility because information can flow in a closed loop. In Figure 2-1D, an optical fiber loops around the photonic interposer by coupling the TX of tile 4 to the RX of tile 1. In Figure 2-1E, a first optical fiber couples the TX of tile 4 to the RX of tile 2, and a second optical fiber couples the TX of tile 3 to the RX of tile 1. In Figure 2-1F, a first optical fiber couples the TX of tile 4 to the RX of tile 3, a second optical fiber couples the TX of tile 3 to the RX of tile 2, and a third optical fiber couples the TX of tile 2 to the RX of tile 1.

[0195] The configurations in Figures 2-1D, 2-1E, and 2-1F have a drawback: TX can only transmit data in one direction (to the right in these examples), while RX can only receive data from the opposite direction (from the left in these examples). Therefore, this network cannot maintain a bidirectional link between the two pairs of TX and RX modules. To implement a bidirectional link, a complementary network with waveguides cascaded in opposite directions can be included. Examples are shown in Figures 2-1G and 2-1H (implementing a 1-hop and a 2-hop scheme, respectively). In each configuration, links are provided in both directions. TX1, TX2, TX3, and TX4 transmit data in one direction, while TX5, TX6, TX7, and TX8 transmit data in the opposite direction. Similarly, RX1, RX2, RX3, and RX4 receive data from one direction, while RX5, RX6, RX7, and RX8 receive data in the opposite direction. Tile 1 includes TX1, RX1, TX5, and RX5. Tile 2 includes TX2, RX2, TX6, and RX6. Tile 3 includes TX3, RX3, TX7, and RX7. Tile 4 includes TX4, RX4, TX8, and RX8.

[0196] However, this configuration does not provide a bidirectional link between two pairs of adjacent TX and RX modules. In fact, it is desirable for a first watt to transmit to a second watt, and for the second watt to transmit back to the first watt. To implement a bidirectional link between the two pairs of TX and RX modules, it is proposed to implement a "switch" between the TX modules. This is shown in Figure 2-1I. The switch enables the TX module to transmit to an RX connected to a complementary loop. This example illustrates a 2-hop dual-loop architecture with switched TX modules. As a result, TX1 can transmit to RX7, and TX7 can transmit back to RX1, thereby closing a bidirectional link.

[0197] B. Programmable connection

[0198] The static connections discussed above do not allow for reconfiguration based on network needs—the network topology is fixed. However, allowing the network to dynamically reconfigure itself based on user needs can be useful in some applications. Therefore, some embodiments involve programmable connections between tiles in a photonic interposer. The configuration of Figure 2-2A is similar to that of Figure 2-1F because both configurations implement a 3-hop architecture. However, instead of static connections, the configuration of Figure 2-2A includes waveguide buses (four in this example, equal to the number of tiles). Each bus can couple any TX to any RX. Each transmitter and each receiver can be selectively connected to the bus via a switch. Connection points are identified as "nodes" in Figure 2-2A. When a transmitter activates a switch, the transmitter can use a bus waveguide to transmit data. Similarly, when a receiver activates a switch, the receiver can listen for data from a bus waveguide. Three optical fibers are used to close the loop. In this example, the first bus connects TX1 to RX4, the second bus (in conjunction with the first fiber) connects TX2 to RX1, the third bus (in conjunction with the second fiber) connects TX3 to RX2, and the fourth bus (in conjunction with the third fiber) connects TX4 to RX3. The network can be reconfigured using switches to change the number of hops from 3 to 1 or 2.

[0199] To implement a bidirectional link, a one-way architecture with a switched TX can be used (similar to the architecture in Figure 2-1I). This is shown in Figure 2-2B. However, unlike the architecture in Figure 2-1I, this architecture includes buses and nodes, thereby allowing for dynamic reconfiguration of the network.

[0200] Figure 2-2C illustrates another photonic interposer with programmable connections according to certain embodiments. This example includes four tiles, although any number of tiles is possible, whether configured in 1D or 2D. Each tile includes a transceiver 100 and a programmable photonic interconnect 120. Each transceiver includes one or more examples of transceiver units 110. The transceiver unit illustrated in Figure 2-2C includes a laser 101, which may be mounted on the same package as the photonic interposer or located outside the package. In this example, the laser 101 emits light at eight different wavelengths, although a different number of wavelengths is possible. Therefore, the architecture of Figure 2-2C can use wavelength division multiplexing (WDM) to increase data throughput. A TX bus 102 receives light from the laser and optically couples it to multiple modulators 104. Each modulator is coupled to a separate TX module, which may include a digital-to-analog converter and a modulator driver. A PLL times the operation of the TX module. The TX module may then be coupled to an electronic chip mounted on a photonic interposer, corresponding to a tile. Each modulator 104 is—in this example implemented as a ring (or disk) resonator—tuned at a different emission wavelength (λ0…λ7) of laser 101. Thus, each modulator is configured to deliver data to a different WDM channel. On the receiver side, an RX module is coupled to a de-extraction filter 108, in this example implemented as a ring (or disk) resonator. Each de-extraction filter is tuned at a different emission wavelength (λ0…λ7) of laser 101. As a result, each de-extraction filter captures data from RX bus 106 at a specific WDM channel. The RX module can also be coupled to an electronic chip and may include a photodetector, a transimpedance amplifier and an analog-to-digital converter.

[0201] Programmable photonic interconnects allow communication between tiles in a programmable manner (and consequently, between electronic chips mounted on a photonic interposer). As shown in Figure 2-2D, the programmable interconnects form a grid of switchable intersections connected by waveguides, wherein the waveguides are configured to form column buses and row buses. The tiles may further include electrical connectors 117, which may be configured to provide electrical access from electronic chips mounted on the tiles to the tiles. For example, the electrical connectors 117 may be in the form of contact pads, thereby providing a landing surface for bonding pads, bumps, vias, or other types of vertical chip-to-chip interconnects. The electrical connectors 117 may be coupled to transceiver 100.

[0202] In the example of Figure 2-2C, the programmable interconnect has been programmed to allow communication between each tile and every other tile. In this illustration, a first optical path is formed between tile 1 and tile 4, a second optical path is formed between tile 1 and tile 3, and a third optical path is formed between tile 1 and tile 2. Each optical path can support multiple wavelengths.

[0203] Figure 2-2E illustrates an exemplary embodiment of a programmable photonic interconnect 120 according to certain embodiments. This programmable photonic interconnect includes action couplers 126 coupled to each other via waveguides. As further illustrated in Figure 2-2F (illustrating an example of an action coupler), each action coupler can provide a one-to-many waveguide coupling configuration. The action couplers can operate in two directions. When light propagates from a single waveguide, the action coupler can select one of the multiple waveguides to propagate the light, thereby performing a switching operation. One possible embodiment of the action coupler 126 involves a cascaded Mach-Rendt interferometer (MZI), as further illustrated in Figure 2-2F (see MZIs 127 and 128).

[0204] Referring back to Figure 2-2E, the central waveguides of the coupler are coupled to each other in a manner forming a waveguide cross 127. From a system perspective, the waveguide cross 127 presents a challenge because it introduces insertion loss and crosstalk. The following is an example of a waveguide cross developed by the inventors that produces low insertion loss and low crosstalk.

[0205] In some embodiments, the waveguide bus illustrated in FIG2-2D may be bidirectional. In some such embodiments, a tile may use the same bus waveguide instead of having one bus dedicated to transmission and another dedicated to reception for transmission and reception. Alternatively, a transmitter may determine which direction of a bus to transmit data from, and a receiver may determine which direction of a bus to receive data from. According to some embodiments, an example of this embodiment is illustrated in FIG2-3A. On the TX side, the tile includes a coupler 131 configured to form an optical tree. The coupler may be controllable (similar to the operational coupler of FIG2-2F). Each output branch of the tree is coupled to a bus via couplers 133, 134, and 135. Coupler 133 selects one input and one output. Selecting the waveguide provided by the TX as the input allows coupler 133 to place the tile in transmission mode. Choosing one of the outputs allows TX to communicate along the bus from right to left or from left to right, thus achieving communication in both directions. Couplers 134 and 135 determine whether the bus is in add / remove mode (add if transmitting, or remove if receiving) or pass-through mode (bypassing tile 1).

[0206] On the RX side, the tile includes couplers 132 that are also configured to form an optical tree. Each output branch of the tree is coupled to a bus via couplers 133, 134, and 135, which allows for selection of right-to-left or left-to-right direction during transmission. In this example, couplers 134 and 135 are implemented as 1×2 couplers, and coupler 133 is implemented as a 2×2 coupler, although other configurations are possible. The architecture of Figure 2-3B is similar to that of Figure 2-3A because both architectures use coupler 133. However, the architecture of Figure 2-3B replaces couplers 133 and 135 with a 2×2 coupler (137).

[0207] Figures 2-4A and 2-4B illustrate an additional scheme allowing bidirectional propagation along a bus. On the TX side (Figure 2-4A), TX is coupled to an MZI, which in turn is coupled to a resonant add-on filter. Depending on which output of the MZI is selected, the resonant filter is excited in either clockwise or counterclockwise mode. As a result, propagation on the bus occurs from left to right or from right to left. On the RX side (Figure 2-4B), RX is coupled to an MZI, which in turn is coupled to a resonant take-off filter. Depending on which input of the MZI is selected, the resonant filter is selected in either clockwise or counterclockwise mode. As a result, RX selects either a left-to-right or right-to-left bus mode.

[0208] Figure 2-5 illustrates an example of a waveguide crossover that may be used in some embodiments (e.g., in Figure 2-2E). This embodiment involves three waveguide layers (140, 141, and 142). The waveguide layers may be made of, for example, silicon or silicon nitride. In one example, waveguide layer 140 is made of silicon, and waveguide layers 141 and 142 are made of silicon nitride. The waveguide crossover is designed to couple mode A from layer 140 to layer 141, and then to layer 142, and then back from layer 142 to layer 141, and again back to layer 140. A cone may be used to extend and contract mode A in the vertical direction. By pushing mode A out of the plane of layer 140, overlap between mode A and mode B is limited, thus reducing crosstalk. The inventors understand that a 3-layer scheme shown herein is superior to a 2-layer scheme in that the 3-layer scheme can provide the same low insertion loss performance, but may ignore a crosstalk between layers 140 and 142.

[0209] Therefore, some embodiments are directed to a photonic interposer layer comprising a plurality of photonic tiles (e.g., tiles 1 to 4 of FIG. 2-2C) as examples of template photonic tiles. Each of the plurality of photonic tiles includes a transceiver (100), which includes a transmitter and a receiver. Electrical connections (117) coupled to the transceiver are configured to allow electrical communication between the transceiver and the electronic chip when an electronic chip is attached to the photonic interposer corresponding to a photonic tile (for example, as shown in FIG. 1-1). An optically distributed network includes a first set of bus waveguides (e.g., column buses of FIG. 2-2D), a second set of bus waveguides (e.g., row buses of FIG. 2-2D), and a plurality of programmable interconnects (120) optically coupled to one of the transceivers. Each programmable interconnect is configured to selectively position one of the bus waveguides in the first group of bus waveguides for optical communication with one of the bus waveguides in the second group of bus waveguides. Each programmable interconnect includes a waveguide crossover (127) and an active coupler (126).

[0210] In some embodiments, the transceiver includes a plurality of modulators (104) coupled to one of the first bus waveguides in the first group of bus waveguides, the plurality of modulators (104) being tuned relative to each other at different wavelengths, for example, as shown in FIG2-2C. Additionally, a plurality of take-off filters (108) coupled to one of the second bus waveguides in the first group of bus waveguides are tuned relative to each other at different wavelengths. In some embodiments, the plurality of modulators are resonant modulators, and the plurality of take-off filters are resonant take-off filters.

[0211] In some embodiments, the transmitter is configured to transmit data along one of the first bus waveguides in a first direction or a second direction, for example as shown in Figures 2-3A, 2-3B and 2-4A.

[0212] In some embodiments, each of the plurality of photonic tiles further includes a 2×2 coupler (133) coupling the transceiver to a first bus waveguide in the first group of bus waveguides. The 2×2 coupler may include a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal is coupled to an output of the transmitter. The second terminal is coupled to an input of the receiver. The third and fourth terminals are coupled to the first bus waveguide in the first group of bus waveguides.

[0213] In some embodiments, each of the plurality of photonic tiles further includes an interferometer (e.g., the MZI of FIG. 2-4A) having an input and a first output and a second output, and a resonant filter. A transmitter is coupled to the input of the interferometer, and the first and second outputs of the interferometer are coupled to the resonant filter. The resonant filter is coupled to a first busbar waveguide in a first group of busbar waveguides. Additionally, in some embodiments, each of the plurality of photonic tiles further includes an interferometer (e.g., the MZI of FIG. 2-4B) having an output and a first and a second input, and a resonant filter. The resonant filter is coupled to a first busbar waveguide in a first group of busbar waveguides. The first and second inputs of the interferometer are coupled to the resonant filter. A receiver is coupled to the output of the interferometer.

[0214] In some embodiments, the waveguide crossing includes a first waveguide patterned in a first waveguide layer (140), a second waveguide patterned in a second waveguide layer (141), and a third waveguide patterned in a third waveguide layer (142). The second waveguide layer is located between the first and third waveguide layers, and the first and second waveguides are evanescently coupled, as are the second and third waveguides. In some embodiments, the first waveguide layer is made of silicon, and both the second and third waveguide layers are made of silicon nitride.

[0215] In some embodiments, the action coupler includes a first terminal coupled to one of a first additional action couplers, a second terminal coupled to one of a first additional action couplers, and a third terminal coupled to one of the waveguide crossovers, for example, as shown in FIG2-2E.

[0216] In some embodiments, the action coupler includes a first Mach-Rendt interferometer and a second Mach-Rendt interferometer (MZI), for example, as shown in Figures 2-2F. A first terminal corresponds to a first output of one of the first MZIs (128), a second terminal corresponds to a second output of one of the first MZIs, and a third terminal corresponds to an output of one of the second MZIs (127).

[0217] In some embodiments, the bus waveguides in the second set of bus waveguides cross multiple photonic tiles (e.g., tiles 1 to 4 in FIG2-2C).

[0218] Figure 2-6A illustrates another interconnect architecture. The advantage of this architecture compared to the architecture in Figure 2-2C is the omission of waveguide crossovers. The disadvantage is that the transceivers are not fully utilized. In this architecture, each watt contains multiple transceivers 100. Each transceiver is coupled to one of the buses (151, 152, 153, 154, and 155). These buses span the boundaries between watts and do not intersect each other. In this illustration, bus 151 allows communication between watts 1 and 2, and between watts 3 and 4. Bus 152 allows communication between watts 1 and 3. Bus 153 allows communication between watts 2 and 4. Bus 154 allows communication between watts 1 and 4. Bus 155 allows communication between watts 2 and 3. The transceiver-bus connection can be programmed according to the network requirements. Coupler 156 is used to selectively couple a transceiver to a bus or decouple a transceiver from a bus. An exemplary embodiment of coupler 156 shown in Figure 2-6B relates to an MZI configured in a closed-loop configuration. The MZI allows communication in both directions, whether in the transmit or receive direction.

[0219] The utilization rate in the architecture of Figure 2-6A can be improved by including additional buses. For each row of transceivers spanning tiles 1 to 4, there are two buses (e.g., 151A and 151B) to which the transceivers can be switched. One bus can support communication from left to right, while the other bus can support communication from right to left, thereby closing the loop. However, in some embodiments, the two buses can support communication in the same direction. In this illustration, bus 151A positions tile 1 to communicate with tile 4, and bus 151B positions tile 1 to communicate with tile 2, tile 2 to communicate with tile 3, and tile 3 to communicate with tile 4. For example, coupler 156 can be implemented as illustrated in Figure 2-6B. One drawback of this configuration is that the links between tiles at opposite ends of a column (e.g., tiles 1 and 4) are longer than other links, resulting in greater optical loss.

[0220] The architecture of Figure 2-6D solves this problem by using fiber optic connections to remote tiles. In this architecture, the tiles are configured as two blocks of 1×2 tiles. The first block contains tiles 1 and 2, and the second block contains tiles 3 and 4. Each tile contains multiple transceivers 100. Tiles 1 and 2 communicate with each other using buses 161A and 161B. Having two buses allows communication in both directions. For example, the TX of tile 1 can use bus 161A to transmit data to the RX of tile 2, and the TX of tile 2 can use bus 161B to transmit data to the RX of tile 1. Similarly, tiles 3 and 4 communicate with each other using buses 164A and 164B. In one example, the TX of tile 3 can use bus 164A to transmit data to the RX of tile 4, and the TX of tile 4 can use bus 164B to transmit data to the RX of tile 3. Thus, buses 161A, 161B, 164A, and 164B can be considered intra-block buses. Conversely, buses 162A, 162B, 163A, and 164B can be considered inter-block buses. Bus 162A is connected to bus 163B via optical fibers 166A and 168A. Similarly, bus 162B is connected to bus 163A via optical fibers 166B and 168B.

[0221] Compared to the architecture in Figure 2-6C, the architecture in Figure 2-6D shortens the on-chip path connecting tile 1 and tile 4. A portion of the on-chip path connecting tile 1 and tile 4 is replaced with optical fiber. Because the loss introduced by an optical fiber can be lower than the loss introduced by an integrated waveguide, the overall loss is reduced.

[0222] Therefore, some embodiments are directed to a photonic interposer comprising a plurality of photonic tiles (e.g., tiles 1 to 4 of FIG. 2-6D) exemplified as a template photonic tile. Each of the plurality of photonic tiles includes a first transceiver (100). Electrical connections (not shown in FIG. 2-6D) coupled to the first transceiver are configured to allow electrical communication between the first transceiver and the electronic chip when an electronic chip is attached to the photonic interposer corresponding to a photonic tile, for example, as shown in FIG. 1-1. A first bus waveguide and a second bus waveguide (162A and 162B) each traverse the first photonic tile and the second photonic tile, and a third bus waveguide and a fourth bus waveguide (163A and 163B) each traverse the third photonic tile and the fourth photonic tile. A first optical fiber (166A), a first bus waveguide (162A), and a fourth bus waveguide (163B) place the first transceiver of the first photonic tile for optical communication with the first transceiver of the fourth photonic tile. A second optical fiber (166B), a second bus waveguide (162B), and a third bus waveguide (163A) place the first transceiver of the second photonic tile for optical communication with the first transceiver of the third photonic tile.

[0223] In some embodiments, each of the plurality of photonic tiles further includes a second transceiver. The second transceiver of the first photonic tile is in optical communication with the second transceiver of the second photonic tile (e.g., via bus 161A and / or 161B). Similarly, the second transceiver of the third photonic tile may be in optical communication with the second transceiver of the fourth photonic tile (e.g., via bus 164A and / or 164B).

[0224] In some embodiments, the interposer further includes a third optical fiber (168A). The third optical fiber (168A), the first bus waveguide (162A), and the fourth bus waveguide (163B) place the first transceiver of the first photonic tile in further optical communication with the first transceiver of the fourth photonic tile. The first optical fiber, the third optical fiber, the first bus waveguide, the fourth bus waveguide, the first transceiver of the first photonic tile, and the first transceiver of the fourth photonic tile can form a closed loop. The interposer may further include a fourth optical fiber (168B). The fourth optical fiber (168B), the second bus waveguide (162B), and the third bus waveguide (163A) place the first transceiver of the second photonic tile in further optical communication with the first transceiver of the third photonic tile. The second optical fiber, the fourth optical fiber, the second bus waveguide, the third bus waveguide, the first transceiver of the second photonic tile, and the first transceiver of the third photonic tile can also form a closed loop.

[0225] C. Wavelength-based tile recognition

[0226] The architecture discussed in conjunction with Figures 2-1A to 2-6D utilizes WDM to increase the aggregate bandwidth of each watt-to-watt optical link. In other embodiments, wavelengths can be used to uniquely identify each watt. For example, in a 4-watt architecture, wavelength λ0 uniquely identifies watt 1, wavelength λ1 uniquely identifies watt 2, wavelength λ2 uniquely identifies watt 3, and wavelength λ3 uniquely identifies watt 4. Thus, a receiver can easily identify the source of data collected from a bus by determining the wavelength of the supporting data. An example is shown in Figure 2-7A. This architecture comprises four watts. A first set of transceivers 100 is connected via bus 171, a second set of transceivers 100 is connected via bus 172, and a third set of transceivers 100 is connected via bus 173. Each transceiver is labeled with a pair of numbers (x and y). The first digit (x) identifies the transmission wavelength of the transceiver's transmitter. The second digit (2) identifies the wavelength at which the transceiver's receiver is configured for reading. It should be noted that all transceivers of the same x number in a given tile are identical. This allows the system to uniquely identify the transmitter by wavelength.

[0227] In the example of Figure 2-7B, each tile in a column has a unique transmission wavelength. However, the wavelength is reused in different columns. The first column contains tiles 1 to 4, and the second column contains tiles 5 to 8. In this example, wavelength λ0 uniquely identifies tiles 1 and 5, wavelength λ1 uniquely identifies tiles 2 and 6, wavelength λ2 uniquely identifies tiles 3 and 7, and wavelength λ3 uniquely identifies tiles 4 and 8. Bus group 181 (containing three buses) allows communication among the tiles (tiles 1 to 4) in the first column. Bus group 183 (containing three buses) allows communication among the tiles (tiles 5 to 8) in the second column. Bus group 182 (containing eight buses) allows communication between each tile in the first column and each tile in the second column. Each watt contains a transmitter and a receiver, represented herein as a resonant modulator (TX) and a resonant off-response filter (RX). The wavelengths in parentheses indicate the transmission wavelength (for a TX) and the off-response wavelength of the resonant off-response filter (for an RX).

[0228] The architecture of Figure 2-7C is similar to that of Figure 2-7A, but the architecture of Figure 2-7C further includes a programmable optical return 190, which allows for a one-way simplex communication channel. One example of programmable optical return illustrated in Figure 2-7D is implemented using MZI. IV. Die-to-Die (D2D) Interface

[0229] The photonic interposer described herein can be used to interconnect application-specific integrated circuits (ASICs) in a way that is impractical (e.g., too expensive or energy inefficient) to use conventional interfaces in other ways. In recent years, new die-to-die (D2D) interface standards have emerged, allowing small chips from different sources to communicate with each other. D2D interfaces utilize extremely short channels to connect two chips within a common package to achieve power efficiency and extremely high bandwidth efficiency, which is not possible with traditional chip-to-die interfaces. A D2D interface can be viewed as being divided into a physical layer (PHY), a link layer, and a transfer layer. The PHY layer can be implemented using a high-speed SerDes architecture for parallel-to-serial and serial-to-parallel data conversion. The primary function of a SerDes is to minimize the number of I / O interconnects.

[0230] Currently, as electronic interposers and silicon bridges gradually become mainstream products, the industry is paying increasing attention to advanced packaging. Examples of D2D interfaces include Advanced Interface Buses (AIBs), Universal High-Speed ​​Chip Interconnects (UCIe), and Low Voltage Package Interconnects (LIPINCON), among others. Wire Bundles (BoWs) are a relatively new D2D interface designed to standardize a portion of the interconnect, and these interconnects are expected to become more important in future generations of chips. These interfaces are designed for high-bandwidth communication between electronic ASICs positioned at relatively close proximity (e.g., a few millimeters apart).

[0231] The inventors have recognized and understand that the relative proximity set by D2D interfaces imposes a practical limitation on the types of computing architectures that can be achieved using such interfaces. Given the constraints of electrical interconnects, the maximum die-to-die distance (a few millimeters in humid conditions) set by such interfaces ensures high bandwidth and reliability. The photonic interposer described herein extends the applicability of conventional D2D interfaces to ASIC-to-ASIC distances larger than those of conventional electronic interposers. In one example, the use of a photonic interposer enables AIB-based communication between a pair of ASICs, for example, ASICs separated by a distance greater than 1 cm, greater than 1.5 cm, greater than 2.5 cm, greater than 3 cm, greater than 5 cm, or greater than 10 cm. Similarly, the use of a photonic interposer enables UCIe-based communication between a pair of ASICs, for example, ASICs separated by a distance greater than 1 cm, greater than 1.5 cm, greater than 2.5 cm, greater than 3 cm, greater than 5 cm, or greater than 10 cm. By incorporating a SerDes interface, one of the photonic interposers, a single photonic channel can be used to multiplex wires into a single photonic link, whether it is a spatial channel (a waveguide or an optical fiber), a wavelength channel, or a polarization channel. In some embodiments, a photonic channel can use non-return-to-zero (NRZ) to support 56 Gbps or higher using PAM4 modulation.

[0232] Figure 2-8A illustrates an ASIC equipped with an AIB interface. More specifically, the ASIC includes a "Northwest" AIB unit, a "Southwest" AIB unit, a "Southeast" AIB unit, and a "Northeast" AIB unit. Each AIB contains 24 channels (although other numbers of channels are also possible). Figure 2-8B illustrates how the AIB interface uses one of the photonic interposer types described herein to achieve a connection between two ASICs (ASIC 0 and ASIC 1). One transmitter port in ASIC 0 supports 128 wires, each supporting speeds between 1.5 Gbps and 2.5 Gbps (e.g., 2 Gbps). Using an 8:1 SerDes, signals from 8 wires can be multiplexed to generate speeds between 12 Gbps and 20 Gbps (e.g., 16 Gbps). In some embodiments, the SerDes can be formed directly on a photonic interposer (e.g., using a transistor in an SOI wafer that hosts the photonic interposer). A modulator formed in a photonic interposer converts the data obtained from the SerDes into an optical signal to be transmitted using a waveguide formed on the interposer or optical fiber. On the receiver side, a photodetector receives the signal, the SerDes performs demultiplexing, and a wire provides the data to the ASIC 1 via an AIB receiver port.

[0233] Figure 2-8C illustrates a photonic interposer 20 that hosts 16 ASICs with an AIB interface. Each ASIC can be mounted on an individual tile of the photonic interposer, for example, in a configuration similar to that shown in Figure 1-1. An external laser module couples light to the interposer using a grating coupler, although edge coupling is also possible. Waveguides formed in the interposer and / or optical fiber support communication between the ASICs via the AIB interface. Each of the static or programmable photonic interconnects described herein can be used to support communication between ASICs. It should be noted that the AIB interface discussed in conjunction with Figures 2-8A to 2-8C can be replaced with other D2D interfaces, such as UCIe.

[0234] Figure 2-9A illustrates a pair of ASICs (ASIC 0 and ASIC 1) communicating with each individual tile (tile 0 and tile 1) of an interposer layer. In this example, a BoW interface is used. Although optical fiber may be used in other embodiments, communication occurs via waveguides formed in the photonic interposer layer. In some embodiments, to reduce the number of waveguides crossing tile boundaries, WDM and / or polarization diversity can be used to multiplex the signal in a single waveguide or optical fiber. In the example of Figure 2-9B, one polarization is used for one transmission direction, and another polarization is used for the opposite direction.

[0235] The photonic intermediary layer described herein achieves several types of computer architectures, including those illustrated in Figures 2-10A, 2-10B, 2-10C, and 2-10D. In the example of Figure 2-10A, a photonic intermediary layer 20 hosts 16 ASICs. Of these ASICs, only one ASIC (ASIC 0) uses fiber optic cable to interface with components outside the intermediary layer 20. The ASICs communicate with each other using any of the interconnects described herein. In the example of Figure 2-10B, fiber optic cable is used to close the loop. As a result, a ring network architecture can be formed. This architecture is particularly suitable for applications involving pipelined operation using multiple ASICs. In the example of Figure 2-10C, each ASIC communicates with its adjacent ASICs and forms further links to allow communication between ASICs located at opposite ends of a row or column. This allows for a 2D hypertriangle architecture. Finally, in the example of Figure 2-10D, each ASIC communicates with every other ASIC to form a full-to-full architecture. This architecture is particularly suitable for smaller layer sizes, parallel batch processing, sequential graphics processing, and HPC / AI clusters where multi-tenancy is desired.

[0236] The inventors have learned that a larger number of hops (in terms of photonic tiles) will require longer photonic paths and / or more photonic switches / crossings. This can lead to increased optical loss and crosstalk. The topology in Figure 2-10A (an all-to-all topology) represents the baseline topology. The topologies in Figures 2-10B to 2-10D are achieved by reducing the number of hops used in a particular optical link relative to the topology in Figure 2-10A. Thus, the optical loss of the links in the topologies of Figures 2-10B to 2-10D is lower than that of the links shown in Figure 2-10A. For efficiency reasons, the laser power / current can be reduced to decrease the amount of redundant light used in each optical link.

[0237] Additional topologies are also possible, where the number of hops for a particular TX / RX link is higher in the reconfigured topology than in the baseline topology. In this case, that particular optical link may require a higher laser power (to compensate for higher losses or crosstalk) to achieve the same performance (e.g., baud and BER). Higher laser power can be achieved by routing the additional power to that link (e.g., from that optical link with a reduced number of hops) without increasing the overall system laser power. Otherwise, additional laser modules or increased laser module output may be required. Another solution is to use a different communication protocol, which is either slower or has fewer bits (e.g., from PAM-4 to NRZ, or from QAM-16 to QAM-4) or accepts a higher bit / symbol error rate, which can be improved by using error correction codes. VI. Clock Distribution

[0238] The inventors have recognized and understood that it is impractical to use a single global clock to synchronize an entire photonic interposer and the electronic chips connected to that photonic interposer. This is partly because the global clock distribution scheme is very complex and requires a large amount of power to operate.

[0239] In some embodiments, clock and data restoration (CDR) can be performed by generating a local clock within each tile. CDR restoration can be performed on each TX / RX pair, wherein the optical communication channel traverses the boundary between one tile and another. In some embodiments, a quasi-synchronous scheme can be used to perform CDR. Alternatively, in some embodiments, a uniform synchronous scheme can be used to perform CDR. Both schemes are discussed below.

[0240] A. Quasi-synchronization scheme

[0241] In a quasi-synchronous scheme, the clock can be transmitted within the same optical channel in which data is transmitted. Therefore, the same TX circuitry and the same RX circuitry are used for transmitting / receiving data and the clock. Considering CDR overhead, this can be achieved by operating at a bandwidth slightly higher than that required for transmitting data alone. Several protocols can be used, including an 8b / 10b protocol, a 64b / 66b protocol, a 128b / 130b protocol, or a 256b / 257b protocol. Generally, an Xb / Yb protocol transforms X bits of data into a string of Y bits to achieve DC balance, thereby providing sufficient state changes for clock restoration and data alignment. An example of a DC-balanced data string is that, in a string of at least 20 bits, the difference between the counts of 1s and 0s may not exceed 2, and / or the number of consecutive 1s or 0s (in a sequence) may not exceed 5. In some embodiments, a linear feedback shift register may be used to implement DC balancing. Clock recovery implemented according to these schemes depends on data transformations (e.g., rising and / or falling edges).

[0242] The quasi-synchronous scheme described herein relies on dissimilar local oscillators (LOs), one LO located on the transmit side of a channel and another LO located on the receive side of the channel. Having dissimilar LOs can lead to clock drift. In some embodiments, clock drift can be compensated for using a resilient first-in-first-out (FIFO) scheme, where the FIFO depth is established by the length of a packet measured in parts per million (PPM).

[0243] Figure 3-1 is a block diagram illustrating one of the quasi-synchronous clock distribution schemes according to certain embodiments. In this example, the data path involves communication from a photonic transmitter (TX) 301 located in tile 1 to a photonic receiver (RX) 203 located in tile 2. Routing between tiles can be performed using any of the architectures discussed above. The optical communication channel 303 (whether implemented as a bus waveguide of a photonic interposer or as an optical fiber) supports data using an Xb / Yb protocol. The system includes a local oscillator (LO) 310 on the RX side and an LO 316 on the RX side. Each LO may include a dedicated crystal, or alternatively, the LO may be fed by a common crystal. Where appropriate, a PLL can be used to multiply the frequency of LO 310 by a predefined factor to achieve a higher clock frequency. The system further includes an Xb / Yb encoder 312 on the transmission side and a corresponding Xb / Yb decoder 314 on the receiving side.

[0244] B. Uniform step scheme

[0245] In the synchronizing scheme, the clock system is transmitted using a different optical channel relative to the data. Having a different optical channel may involve a different propagation medium (e.g., a different waveguide or optical fiber), or the same propagation medium but with different wavelengths or polarizations.

[0246] Figure 3-2 is a block diagram illustrating one of the clock distribution schemes according to certain embodiments. As in a previous example, the data path involves communication from a photonic transmitter (TX) 301 located in tile 1 to a photonic receiver (RX) 203 located in tile 2. However, the clock is transmitted using channel 352, and the data is transmitted using channel 350. The channel may represent a physical propagation medium, or different wavelengths or different polarizations in a common medium. In this scheme, the transmitter includes an LO 310, but the receiver lacks a separate LO. Instead, a PLL 354 restores the clock based on the signal transmitted through clock channel 352. Where appropriate, PLL 311 can be used to multiply the frequency of LO 310 by a predefined factor to achieve a higher clock frequency. VII. Equalization

[0247] The inventors have developed techniques involving analog and / or digital equalization to improve data throughput in photonic interposers. Equalization improves data throughput by reducing inter-symbol interference (ISI) and thus by reducing bit error rate (BER). Equalization can be performed on the transmitter side of one channel, on the receiver side of one channel (or both). Equalization can amplify high-frequency content and allow for lower BER operation. Several types of equalization techniques can be used, including but not limited to pre-emphasized feedforward equalization (FFE), continuous-time linear equalization (CTLE), and discrete feedback equalization (DFE). Photonic interposers utilizing the equalization techniques described herein can be fast enough to support clock frequencies exceeding 10 GHz, 15 GHz, or even 25 GHz, representing a substantial improvement over conventional processors.

[0248] Figure 3-3A is a block diagram illustrating a portion of a photonic interposer configured to perform equalization. On the transmit side, an FFE unit 360 performs pre-emphasis and / or de-emphasis. On the receive side, unit 362 performs DFE and / or CTLE. In some embodiments, the system may determine whether equalization (whether FFE, DFE, or CTLE) is performed based on whether communication between tile 1 and tile 2 occurs within a common photonic interposer or across two dissimilar photonic interposers. Alternatively, the system may determine whether equalization is performed based on whether communication between tile 1 and tile 2 occurs using a bus waveguide or an optical fiber.

[0249] In addition to determining whether equalization is applied, in some embodiments, the characteristics of the equalizer can be adaptively changed depending on the nature of the channel. For example, the system can determine the S11 and / or S21 parameters of the channel, and based on that information, the number of taps of the DFE / CTLE unit 362 can be adjusted. Figure 3-3B is a block diagram illustrating an example of an adaptive equalizer. An ADC 370 placed at the end of the channel digitizes the channel output by generating state samples y[n], y[n-1], y[n-2], etc. The DFE / CTLE unit 362 generates an output w[n] by calculating a linear combination of state samples y[n], y[n-1], y[n-2], etc. The linear combination can be expressed as follows: where ci represents a coefficient of the channel response (whether real or complex). Here, M determines how many previous state samples y[n] are used to implement equalization. M indicates the number of taps of the equalizer. M is a finite number, and the digit equalizer 400 implements a finite impulse response (FIR) filter. However, in other embodiments, a digit equalizer 400 may implement an infinite impulse response (IIR) filter. Each state sample y[ni] corresponds to a past (where i > 0) or current (where i = 0) digitization of the amplitude of the analog signal, and w[n] corresponds to the calculated steady-state output value of the current set of digit inputs. In the example of Figure 3-3B, the DFE / CTLE unit 362 includes a plurality of registers 372, a plurality of digit multipliers 374, and a digit adder 376. Each register 372 records a state sample (y) at a different time. For example, one register may record y[n-1], another register may record y[n-2], and so on. The registers allow the equalizer to remember historical state samples. The digit multiplier 374 multiplies a state sample by a corresponding coefficient. For example, one of the digit multipliers can multiply the coefficient c1 by the state sample y[n-1]. The digit adder 376 adds the results of the digit multiplications together. As a result, the output w[n] represents a linear combination of the historical state samples.

[0250] The number M, representing the number of taps, can be dynamically adjusted during operation. This means that the system does not analyze the channel characteristics by transmitting a known signal, but rather adjusts the number of taps based on the payload itself (the data carrying actual information transmitted from TX to RX). Adjusting the number of taps involves changing the number of registers and digital multipliers involved in equalization. Furthermore, the value of the coefficient ci can be determined based on the characteristics of the channel. VIII. Channel Tuning

[0251] Some embodiments relate to optical interconnects that rely on resonant devices, such as ring or disk modulators and ring or disk filters. The high refractive index contrast of silicon relative to silicon oxide results in extremely high mode confinement, enabling the use of resonant devices with a very small footprint while maintaining low optical loss. In one example, a ring modulator may have a diameter of less than 5 μm, with a quality factor (Q) exceeding 10⁵. Because resonant devices can be made very small without sacrificing optical loss, such devices are superior to other types of modulators and filters when device density is extremely important (such as in photonic interposers described herein).

[0252] However, the use of resonant devices presents a challenge. A prerequisite for resonant operation is that the relationship between the output wavelength of a laser and the resonant wavelength of a resonator remains constant over time. Unfortunately, both the output wavelength of a laser and the resonant wavelength of a resonator suffer from thermal drift—a phenomenon caused by unpredictable changes in local temperature leading to wavelength variations. Furthermore, the resonant wavelength of the resonator is also subject to nonlinear effects, such as two-photon absorption in silicon, especially when the resonator traps light and increases the optical flux density. When the output wavelength of the laser and the resonant wavelength of the resonator drift relative to each other, the operation of a photonic interlayer is significantly degraded.

[0253] Despite thermal drift, the inventors have developed a technique for locking a resonant device. Figures 3-4A to 3-4C illustrate a sequence of wavelengths used to lock a transmitter. As shown in Figure 3-4A, the transmitter in this example can transmit data along a bus waveguide 410 in one direction or in the opposite direction. The transmitter includes a resonant modulator 400, a modulator driver 402, a heater 404, an MZI 406, monitoring detectors 411, 412, 413, and 414, and a resonant addition filter 408 coupled to the bus waveguide 410. The modulator driver 402 drives the modulator 400 with data. As a result, the light provided by the laser is modulated with the data. Depending on which output of the MZI is selected, the modulated light is coupled to the bus waveguide in one direction (e.g., from right to left) or in the opposite direction (e.g., from left to right). Adding a filter ensures that the data to be added to the bus waveguide is at the desired wavelength, thus allowing bus waveguide 410 to support WDM. In this example, the added filter is a second-order filter designed to flatten the frequency response across the passband of interest.

[0254] The first tuning step is illustrated in Figure 3-4A. Here, a signal in the form of a linear ramp controls the heater 404, thereby causing a shift in the resonant frequency of the modulator 400. While the modulator is ramping, a controller (not shown in Figure 3-4A) monitors the outputs (e.g., the sum of the outputs) of detectors 414 and 412. By determining the point where the detector outputs are maximized, it can be determined what value of the ramp will cause the modulator to lock onto the laser. Sweeping the modulator in this way ensures that the resonant wavelength of the modulator is tuned (or only slightly tuned) relative to the wavelength of the laser. In the following steps, the heater is driven at a value that maximizes the outputs of detectors 414 and 412.

[0255] The steps illustrated in Figure 3-4B involve tuning the MZI 406. This step ensures that 100% (or close to 100%) of the modulator's output optical power is transmitted in one direction or the other in the bus waveguide. This is to avoid sending data in the wrong direction in the bus waveguide. At this step, a signal in the form of a linear ramp controls the MZI 406, thereby causing a shift in the percentage of power appearing from the MZI's output. While the MZI is ramping, the controller monitors the output of detector 414 or detector 412 depending on the desired transmission direction. For example, if the desired direction is from right to left, the controller monitors the output of detector 414. By determining the point where the output of detector 414 is minimized, it can be inferred that all power is being transmitted in the desired direction. In contrast, if the desired direction is from left to right, the controller monitors the output of detector 412.

[0256] The steps illustrated in Figure 3-4C involve tuning the added filter 408. Regarding the modulator 400, a heater (not shown in Figure 3-4C) can be placed near the added filter to cause a wavelength change when a signal is applied. Tuning the filter ensures that the desired wavelength is transmitted over the bus waveguide. At this step, a signal in the form of a linear ramp controls a heater near the added filter 408, thereby causing a shift in the filter's resonant frequency. While the filter is ramping, the controller monitors the output of detector 413 or detector 411 depending on the desired transmission direction. For example, if the desired direction is from right to left, the controller monitors the output of detector 411. By determining the point where the output of detector 411 is minimized, it can be inferred that all power is transmitted over the bus waveguide at the desired wavelength. Conversely, if the desired direction is from left to right, the controller monitors the output of detector 413. If it is determined after the steps in Figure 3-4C that the MZI 406 is no longer properly tuned, the controller may repeat the steps in Figure 3-4C and / or Figure 3-4B.

[0257] Figures 3-5A and 3-5B illustrate a sequence used for tuning a receiver. As shown in Figure 3-5A, the receiver in this example can receive data transmitted along bus waveguide 410 from one direction or the opposite direction. The resonant off-filter 420 is the counterpart of the resonant addition filter 408, as the resonant off-filter 420 selects which wavelength is delivered to the receiver, thus allowing the bus waveguide to support WDM. In this example, the off-filter is a second-order filter used to flatten the frequency response across the passband of interest. Monitoring detectors 424 and 425 monitor the state of the off-filter. MZI 426 determines whether the direction of the received data is from left or right. Monitoring detectors 434 and 435 monitor the state of the MZI. Receiver 440 includes a photodetector and electronic receiver circuitry (e.g., a transimpedance amplifier and an ADC).

[0258] The steps illustrated in Figure 3-5A involve tuning the take-off filter 420. Regarding the modulator 400, a heater (not shown in Figure 3-5A) can be placed near the take-off filter to cause a wavelength change when a signal is applied. Tuning the filter ensures that the desired wavelength is received from the bus waveguide. At this step, a signal in the form of a linear ramp controls the heater near the take-off filter 420, thereby causing a shift in the filter's resonant frequency. While the filter is ramping, the controller monitors the output of detector 413 or detector 411 depending on the desired transmission direction. For example, if the desired direction is from left to right, the controller monitors the output of detector 425 and / or the output of detector 424. By determining the point where the output of detector 425 is maximized and / or the output of detector 424 is minimized, it can be inferred that all power received from the bus waveguide is at the desired wavelength. In contrast, if the desired direction is from right to left, the controller monitors that the output of detector 424 needs to be maximized and / or the output of detector 425 needs to be minimized.

[0259] The steps illustrated in Figure 3-5B involve tuning the MZI 426. This step ensures that 100% (or close to 100%) of the optical power supplied to the receiver is received from one direction or the other. This is to avoid receiving data from the wrong direction of the bus waveguide. At this step, a signal in the form of a linear ramp controls the MZI 426, thereby causing a shift in the percentage of power received from the input of the MZI, which is ultimately transmitted to the RX 440. While the MZI is ramping, the controller monitors the output of detector 434 or detector 435. By determining the point where the output of detector 435 is maximized and / or the output of detector 434 is minimized, it can be inferred that all power is received from the desired direction.

[0260] Utilizing the resonant properties of wavelength division multiplexing (WDM) transmission discussed above, the inventors have further developed a technique involving jitter to allow a receiver to uniquely identify a specific transmitter. Jitter involves modulating a resonant component at a relatively low frequency (e.g., between 1 kHz and 1000 kHz) to uniquely identify a signal propagating through that component. In some embodiments, the slow frequency should be supported by a modulation element such as a thermo-optical heater. Essentially, a component marks a signal with a signature in the form of a specific jitter frequency. Each component can jitter at a slightly different frequency. In architectures with several components in series, component identification becomes particularly important. In some embodiments, a detector may rely on frequency jitter to identify which transmitter has transmitted certain data. In one example, a jittered signal is used to lock a receiver's offload filter to a specific modulator. It is important to note that the jittered signal can be applied to non-resonant components associated with transmission at a specific wavelength (e.g., the MZI in component 406).

[0261] Figure 3-6A illustrates a technique for locking a receiver to a particular transmitter using jitter according to certain embodiments. In this example, multiple transmitters and multiple receivers are coupled in series along the length of bus waveguide 410. The transmitters are coupled to the bus waveguide via an addition filter 408, and the receivers are coupled to the bus waveguide via a removal filter 420. The architecture of the transmitters is similar to that shown in Figure 3-4A, and the architecture of the receivers is similar to that shown in Figure 3-5A. In this case, the signal that will be maximized / minimized by the detectors (424 and 425) in the RX device has been jittered. Analog circuitry can be constructed to capture the signal at a specific jitter frequency, for example, using null or heterodyne circuitry, wherein the local oscillator can be generated locally by the RX device. Other TX-RX transmission pairs in the series will use a different jitter frequency. It is important to note that different jitter frequencies are not rational fractions of each other; for example, f1 / f2 is not a rational fraction a / b, where a and b are integers. Therefore, by using a signal at a specific jitter frequency associated with a particular TX-RX transmission pair, components within and between TX-RX transmission pairs can be locked to the correct pair (and will not be confused by signals from another TX-RX pair). In some embodiments, a receiver's offload filter can be locked to a particular transmitter's modulator by jittering the modulator at a certain frequency and then maximizing / minimizing the signal at that specific frequency by the (primary and tap) detectors in the RX device. Furthermore, in some embodiments, multiple components in the same TX-RX transmission link can be jittered using the same jitter frequency, so that all detectors in the TX-RX transmission link only need to generate a single jitter frequency for locking. In other embodiments, different components in the same TX-RX transmission link can jitter at different frequencies, allowing detectors in the TX-RX link to distinguish error signals from different components along the link. The jitter frequency may be slower than the frequency (in the MHz range) of the crystal oscillator typically used to build a PLL.

[0262] In some embodiments, an FIR digital bandpass filter (not shown in Figures 3-6A) programmed to identify a specific jitter frequency may be coupled to a detector. In these embodiments, locking between a transmitter and a receiver may involve programming an FIR digital bandpass filter to accept only signals jittering at a specific frequency.

[0263] Figure 3-6B illustrates one optical channel supporting communication between multiple transmitter-receiver pairs. Transmitter TX1 and receiver RX1 form a pair—data transmitted by TX1 is directed to RX1. Transmitter TX2 and receiver RX2 form another pair—data transmitted by TX2 is directed to RX2. Transmitter TX3 and receiver RX3 form another pair—data transmitted by TX3 is directed to RX3. Transmitter TX4 and receiver RX4 form another pair—data transmitted by TX4 is directed to RX4. Each TX-RX pair uses a unique jitter frequency (TX1-RX1 for f1, TX2-RX2 for f2, TX3-RX3 for f3, and TX4-RX4 for f4). Each pair can use a unique wavelength in the optical channel: λ1, λ2, λ3, and λ4. IX. Redundancy

[0264] The inventors have recognized and understand that the limited yield associated with microscale manufacturing processes negatively impacts the scalability of photonic interposers. The yield associated with a manufacturing process is represented by the fraction of defect-free components divided by the total number of manufactured components. The yield of a manufacturing process is generally below 100% and is attributed to a variety of factors, including, for example, equipment performance, system complexity, and operator skill.

[0265] Certain types of defects can impair the functionality of a photonic circuit. When light encounters one of these defects, it results in partial or complete loss of optical power. Other types of defects can impair the functionality of electronic circuitry and / or wiring that is part of a watt (e.g., a modulator driver or a transimpedance amplifier). When an electrical signal encounters one of these defects, it results in signal attenuation or complete loss.

[0266] A. Fiber optic attachment redundancy

[0267] The limited yield of fiber optic attachment can have a particularly severe impact. Fiber optic attachment enables photonic integrated circuits (an example of photonic interposer systems) to communicate with the outside world using optical fibers. Fiber optic attachment can be performed using either passive or active procedures. In a passive procedure, a fiber is attached to a wafer without any feedback on whether or to what extent the light is coupled. In an active procedure, the wafer provides feedback, which can be used to improve optical alignment before the fiber is secured to the wafer. Active procedures offer higher coupling efficiency than passive procedures, but are more expensive. Unfortunately, both types of procedures have limited yields. Furthermore, wafer operators cannot determine whether a fiber optic attachment has yielded a good result until the package is fully (or nearly fully) assembled. This is because fiber optic attachment is a final step in the packaging of a photonic integrated circuit.

[0268] Whether through edge coupling, vertical coupling, or using V-groove, the yield in industrial environments remains around 95% when attaching multiple (16 or 32) fibers at once. The types of fiber attachment described in this article refer to attaching a single fiber (e.g., a single-mode fiber, a polarization-maintaining fiber, or a multi-core fiber) or a fiber array (e.g., a V-groove fiber array or a fiber ribbon). Applications requiring many fibers (such as optically interconnected servers) demand higher fiber attachment yields. If a particular system requires N attachment sites to achieve a yield, then the system's yield is , where is the probability of a single attachment site yielding. Even at ~90%, the yield rapidly drops to ~20%. A more fault-tolerant attachment strategy is needed to improve system yield. Current focus is on improving the yield of the fiber attachment itself by introducing new encapsulation procedures, such as better exponentially matched epoxy / glue or better active alignment during the attachment process. However, such procedures are often insufficient.

[0269] The inventors have developed a method for increasing fiber optic attachment yield, which involves fiber redundancy. This can be achieved by having more fiber optic attachments than are required to operate a photonic integrated circuit. A controller identifies which fiber attachment or subset of fiber attachments provides better performance. These fibers are utilized during chip operation, while other fibers remain unused. This process can be executed in real time, thus allowing the controller to continuously monitor the quality of fiber optic attachments during operation.

[0270] Figure 4-1A illustrates a photonic integrated circuit (PIC) 900 having a photonic circuit 902 and multiple fiber optic attachments. The PIC 900 may represent any of the photonic interposers described herein. In these embodiments, the photonic circuit 902 may include tiles, transceivers, and photonic interconnects, as described above. However, fiber redundancy can be used in conjunction with any type of PIC. At each attachment point, an optical fiber 908 is coupled to a waveguide 907 of the PIC via an optical chip to a fiber coupler 906 (e.g., an edge coupler, a V-groove, a grating). As shown, an additional k-1 fiber attachments (a total of k fiber attachments) are provided instead of just a single fiber attachment. An optical switch 904 on the PIC selects which of the k fiber attachments is used for operation of the PIC. A controller 903 monitors the performance of each fiber attachment and controls the operation of the optical switch 904.

[0271] Different methods can be used to monitor the performance of a fiber optic attachment. In one example, a photodetector 909 coupled to waveguide 907 using a tap coupler monitors the optical power present in the waveguide (only one photodetector 909 is shown in Figure 4-1A). The photodetector 909 provides information indicating the optical power present in each waveguide 907 to a controller 909. Based on this information, the controller 909 can determine which subset of k fiber optic attachments provides the best performance (this could be one or more fiber optic attachments). The controller 909 can then control an optical switch 904 to select the waveguide corresponding to the subset of fiber optic attachments that best performs the attachment. In another example, the photonic integrated circuit 902 may include a system for monitoring the quality of channels corresponding to various fiber optic attachments. For example, the photonic integrated circuit 902 may monitor the bit error rate (BER), eye diagram quality factor, power, and / or signal-to-noise ratio (SNR) associated with each channel. In this example, controller 909 can control optical switch 904 to select waveguides one after another in a sequential manner, thus allowing photonic circuit 902 to monitor the quality of each channel individually. Photonic circuit 902 provides controller 909 with information indicating the quality of various channels. Based on this information, controller 909 can determine which subset of k fiber attachments provides the best performance (this may be one or more fiber attachments). Controller 909 can then control optical switch 904 to select the waveguide corresponding to the best performing fiber attachment subset. In some embodiments where fiber attachment performance can be measured before final system assembly, the worst performing fiber attachment subset does not need to be connected to other optical devices or connectors. In other embodiments where fiber attachment performance cannot be measured before final assembly, all fiber attachments can be performed, and subset selection can then be performed.

[0272] Whether the PIC 900 is used as a transmitter or a receiver, the redundancy scheme illustrated in Figure 4-1A is employed. Figure 4-1B is a block diagram illustrating a pair of PIC 900s connected to each other using k optical fibers, some of which are provided solely for redundancy. One PIC operates as a transmitter; in this PIC, photonic circuitry 902 operates as a TX photonic circuit. The other PIC operates as a receiver; in this PIC, photonic circuitry 902 operates as an RX photonic circuit. Individual controllers 909 monitor the quality of the fiber attachment and control individual optical switches 904 to select the waveguide corresponding to the subset of fiber attachments that best performs the attachment.

[0273] If the probability of a single fiber attachment operating normally is p, then the overall probability that at least one of k fiber attachments will operate correctly using fiber redundancy is equal to 1 - (1 - p)k. This quantity is always greater than p, thus improving the yield. For example, consider a system requiring 16 functional fiber attachment sites. By using redundant fiber attachments at each attachment site, the system yield can be increased to nearly 100%, even if the success probability of a single fiber attachment is low. The results are shown in Figure 4-1C. Figure 4-1C illustrates the overall system yield (in %) of a system with 16 fiber attachment sites, which is a function of the number of attachments at each attachment site. Having a single attachment (1 on the x-axis) means no redundant fiber attachment is used. Having N attachments (N on the x-axis) means N-1 redundant fiber attachments are used. As can be seen from this figure, regardless of the initial probability of a fiber optic splice operating correctly, the overall system yield approaches 100% as the number of splices increases.

[0274] B. Tile redundancy

[0275] The inventors have further understood that not all tiles in a photonic interposer are of high yield. For example, some tiles may have defective transmitters, receivers, interconnects, and / or switches. This can negatively impact the performance of a network because electronic chips mounted on defective tiles may become unusable. Furthermore, not all electronic chips mounted on a photonic interposer are of high yield. To avoid these problems, the inventors have developed a solution involving tile redundancy.

[0276] Figure 4-2 illustrates a photonic interposer layer having multiple tiles, one of which is provided for redundancy. Electronic chips 911, 912, 913, 914, 915, and 916 are mounted on the photonic interposer layer 20 corresponding to their respective tiles. Depending on the situation, another electronic chip 917 may be placed on the redundant tile. Chip 917 can also provide redundancy in case one of the other electronic chips malfunctions. For example, chip 917 may be a copy of one of the other chips. In this example, the tile corresponding to chip 914 does not produce yield. In response, the photonic interposer layer can be reconfigured to functionally swap the non-yield tile and the redundant tile. Using the programmable interconnects described above, optical signals directed to the non-yield tile can be redirected to the redundant tile. Depending on the situation, redundant chip 917 can be used instead of chip 914.

[0277] In some embodiments, wafer-level testing can be used to determine whether tiles of a photonic wafer produce yield. This method allows an operator to determine the quality of a wafer without having to individually test different portions of the wafer. A disadvantage of this method is that once a particular portion of a wafer is designed for a specific purpose, tiles of that wafer portion are ultimately encapsulated as part of a photonic interposer, regardless of whether those tiles produce yield.

[0278] In some embodiments, the performance of a tile can be monitored in real time during operation. This can be achieved using a power monitoring grid, one example of which is shown in Figures 4-3. The power monitoring grid includes multiple photodetectors (e.g., photodetector 909 in Figure 4-1A) located at different locations in a photonic interposer. The photodetectors can be coupled to various photonic components via tap couplers. Using the power monitoring grid, it can be determined, for example, that a particular tile is not operating as expected. Using this information, the system can decide to reconfigure itself to functionally swap the tile with one of the redundant tiles. This operation can be performed during operation of the photonic interposer. X. Fabrication of Grating-Based Packaging

[0279] The photonic interposer described herein requires light to operate, whether provided by a laser or other type of light source. Unfortunately, due to the low optical emissivity of silicon, monolithically integrating a laser with a photonic interposer is challenging. Instead, it is generally more practical to use an external laser (located in the same package or on the same circuit board as the interposer) and guide the light emitted by the external laser into the wafer. This can be performed via edge coupling or surface coupling. Edge coupling involves coupling an optical mode from an optical fiber to a waveguide through one of the side surfaces of the wafer. In contrast, surface coupling involves coupling an optical mode from an optical fiber to a waveguide through the top surface of the wafer. To guide light from outside the plane of the top surface into a waveguide extending parallel to the top surface of the wafer, a grating coupler is typically used. A grating coupler is a flat structure formed on or immediately below the top surface of a photonic wafer.

[0280] The inventors have recognized and understand that the presence of particles or other types of debris on the top surface of a wafer can negatively affect fiber-grating coupling efficiency. This is because particles cause scattering. Unfortunately, particle-free operation is difficult to achieve due to the various fabrication steps that occur after the formation of a grating but before the fiber is attached to the top surface of the wafer.

[0281] The inventors have developed a fabrication process that limits the accumulation of particles or other debris on the top surface of a photonic wafer, thereby improving the efficiency of fiber Bragg gratings. In some embodiments, this can be achieved by forming a temporary protective layer positioned to protect the grating during process steps that are more likely to generate unwanted particles. Once those process steps are complete, the temporary protective layer can be removed, exposing the grating to air for subsequent fiber attachment. The temporary protective layer can be formed before or after the electronic wafer (e.g., ASIC) is bonded to the photonic interposer. Examples of protective layers include photoimageable dielectrics (e.g., polyimide or photoresist) and glass (e.g., an adhesive with a UV-release property). Other materials are also possible. Furthermore, in some embodiments, particle-free processing can be achieved using a custom molding process designed to encapsulate the electronic wafer even without contact with the grating coupler.

[0282] Figure 5-1 is a schematic diagram illustrating an optical fiber coupled to a grating coupler formed on a photonic interposer according to certain embodiments. An optical fiber 1120 is placed above a grating coupler 1110 formed on the top surface of a photonic interposer 1130. The optical fiber 1120 forms a non-zero angle with respect to the surface of the photonic interposer 1130. In this example, the optical fiber also forms a non-zero angle with respect to an axis perpendicular to the top surface of the interposer, although in some embodiments, the optical fiber may be parallel to the vertical axis. Light emitted from the fiber core 1122 of the optical fiber 1120 is coupled to the grating coupler 1110. The grating then transports the light to the waveguide 1121.

[0283] Figure 5-2A is a top view of a photonic interposer 1130 patterned to form a photonic circuit, which can be used as a photonic interposer once diced from a wafer. An electronic chip 1210 is mounted on the photonic interposer. The electronic chip is encapsulated by an encapsulating material 1220, which can be formed using a molding compound. Region 1230 includes grating couplers formed on the top surface of the wafer. These regions are not covered by the encapsulating material to allow for subsequent fiber attachment.

[0284] Figure 5-2B is a cross-sectional side view of a portion of the wafer in Figure 5-2A, illustrating the y-axis in an xz plane. This figure shows a plurality of electronic wafers mounted on the top surface of a photonic interposer. The electronic wafers are encapsulated by encapsulating material 1220. Region 1230 is exposed to air.

[0285] Figure 5-3A shows the cut photonic interposer layer of Figure 5-2B. Region 1230 remains exposed to air, allowing optical fibers to be attached in a subsequent step. Connectors 1310 formed on the bottom surface of the photonic interposer layer allow the photonic interposer layer to be connected to a circuit board 1340. Examples of connectors 1310 include ball grid arrays (BGAs), copper pillars, C4 bumps, pins, etc.

[0286] Figure 5-3B is a cross-sectional side view of a package after an optical fiber 1120 has been attached to the top surface of an interposer 1130. When the optical fiber is attached, the fiber core is optically coupled to a grating coupler. In this illustration, the interposer 1130 is mounted on a printed circuit board (PCB) 1340 via a connector 1310 passing through an underfill 1330. A cover 1320, such as a heat diffuser, is placed on top of an electronic chip. The optical fiber 1120 is coupled to a grating coupler on one side of the package via a steering optics assembly 1350, which steering the light propagating inside the optical fiber to a direction at a non-zero angle relative to the top surface of the photonic interposer, thereby allowing the fiber mode to couple to the grating.

[0287] Figures 5-4, 5-5, and 5-6 are flowcharts illustrating one of the various procedures for fabricating an encapsulated photonic interposer. These fabrication procedures are designed to prevent (or at least limit) the accumulation of particles or debris corresponding to the fiber Bragg grating, thereby achieving low-loss, high-efficiency fiber-grating coupling. As discussed in further detail below, the procedures in Figures 5-4 and 5-5 involve temporary protective layers. The procedure in Figure 5-6 involves a custom molding process.

[0288] Referring first to Figures 5-4, this fabrication process begins at step 4A in a packaging facility, which involves obtaining a photonic interposer 1130 (e.g., the photonic interposer of Figures 1-3B or the photonic interposer described herein) patterned with one or more grating couplers and covering region 1230 (where the gratings are patterned) with a protective material 1438. As a result, the grating couplers are covered. The photonic interposer may be received at a packaging facility of a semiconductor foundry, where a wafer is patterned with photonic and electronic circuitry, thereby including the grating couplers. Examples of materials that can be used for the protective material 1438 include photoimageable film (PIF) (e.g., polyimide or photoresist). At step 4B, an electronic chip 1210 (e.g., an ASIC, processor, memory, etc.) is placed on the photonic interposer. At step 4C, the electronic wafer 1210 is encapsulated with an encapsulating material 1220 through a process such as large-scale reflow and wafer-level mold underfill (WL MUF). It should be noted that the protective film applied in step 4A prevents molding compound from covering the grating coupler at step 4C and further maintains the cleanliness of the grating coupler, avoiding any contaminants and particles released during subsequent back-side polishing and CMP process steps 4D. This encapsulation provides protection for the wafer and enables subsequent TSV display process steps. At step 4D, the encapsulating material is removed from the top of the electronic wafer via planarization (e.g., CMP) or back-side polishing to allow attachment of a carrier mount 1638, which occurs at step 4E (after a flip step). At step 4F, after the TSV display process, a connector 1310 (e.g., BGA) is attached to the bottom surface of the photonic interposer. It should be noted that attaching the connector 1310 to the interposer may generate particles or other debris. However, this attachment step occurs while the grating coupler is covered by the protective material 1438. As a result, particles or debris generated during the attachment step do not affect the cleanliness of the top surface of the patterned grating coupler. At step 4G, the carrier mount 1638 is removed from the top of the electronic chip. At step 4H, a UV-releasable tape 1330 is applied (e.g., tape cutting). At step 4I, the protective material 1438 is removed from the top surface of the photonic interposer, leaving the grating coupler exposed to air. Where appropriate, a plasma process may be used to perform a cleaning step to ensure the cleanliness of the fiber attachment and optical coupling surfaces. At step 4J, the photonic interposer is separated into multiple systems, each system comprising one or more electronic chips and one or more grating couplers, for example by a micro-cut or mechanical saw. At step 4K, a photonic interposer is attached to the circuit board 1340 by a process such as mass reflow, capillary underfill (CUF), and urea-formaldehyde (UF) resin curing. In addition, a cover 1320 is attached to an electronic chip, wherein the cover can be used as a heat diffuser.In addition, an open / short circuit (O / S) test is performed to ensure a good electrical connection between the photonic interposer and the circuit board. Finally, an optical fiber 1120 is attached to the top surface of the interposer. As a result, the fiber is optically coupled to a grating coupler.

[0289] Figure 5-5 is a flowchart illustrating one of the alternative methods for fabricating a photonic package according to certain embodiments. The method of Figure 5-5 is similar to the method of Figure 5-4 in some variations. The main difference is that a protective material 1538 is formed after attaching the wafer to the photonic interposer and after the encapsulation step. Step 5A involves obtaining a photonic interposer 1130 patterned with one or more grating couplers and placing the wafer 1210 on the interposer. In step 5B, the electronic wafer 1210 is encapsulated with an encapsulation material 1220 through processes such as large-scale reflow and wafer-level mold underfill (WL MUF). As described above, encapsulation provides protection for the wafer and enables subsequent TSV display process steps. In step 5C, a protective material 1538 (e.g., a glass cover with a UV-releasable adhesive) is placed on the area where the grating couplers are formed on the interposer. The attachment of the protective glass maintains the cleanliness of the grating coupler, preventing the release of any contaminants and particles during subsequent back-side polishing and CMP process step 5D. In step 5D, the top surface is planarized or back-side polished. In step 5E, after the TSV display process, the interposer is flipped and the connector 1310 (e.g., BGA) is attached to the bottom surface of the photonic interposer. As mentioned above, attaching the connector 1310 to the interposer may generate particles or other debris. However, this attachment step occurs while the grating coupler is covered by the protective material 1538, thereby maintaining the cleanliness of the patterned top surface of the grating coupler. In step 5F, the protective material 1538 is removed, thus exposing the grating coupler to air. Plasma cleaning is performed, where appropriate, on the top surface of the photonic interposer. Subsequent steps are similar to those illustrated in Figures 5-4, including fiber attachment.

[0290] Figure 5-6 is a flowchart illustrating one of the alternative methods for fabricating a photonic package according to certain embodiments. The method of Figure 5-6 differs from the methods of Figures 5-4 and 5-5 in that a protective material is not used to cover the grating coupler. Instead, a custom-designed molding process is performed to encapsulate the electronic chip, while avoiding debris covering and contaminating the grating coupler due to the encapsulation step. Subsequent steps are similar to those illustrated in conjunction with Figure 5-4.

[0291] In step 6A, wafer 1210 is mounted on interposer 1130. In step 6B, encapsulation material 1120 is formed using a custom molding process to avoid covering area 1230. As a result, contamination from the molding step is prevented (or at least limited), which would otherwise affect the cleanliness of the grating coupler. Therefore, this process avoids leaving impurities on the top of the grating coupler. In step 6C, the top surface of the package is planarized or back-side ground. In step 6D, the package is mounted on carrier mount 1638. In step 6E, after the TSV display process, the device is flipped, and connector 1310 is attached to the bottom surface of the interposer. In step 6F, carrier mount 1638 is removed. In step 6G, the interposer is cut. In step 6H, an optical fiber is attached to the top surface of the interposer for coupling to a grating coupler. XI. Power Distribution

[0292] Figure 5-7 is a cross-sectional side view of a photonic package mounted on a circuit board comprising a power delivery system according to certain embodiments. The package of Figure 5-7 includes a circuit board 1740, a socket 1730, a substrate 1720, a photonic interposer 1714, an electronic chip 1712, a cover 1732, a cold plate 1734, a voltage regulator module (VRM) 1750, a connector 1752, and a power bus 1754. The photonic interposer 1714 and the electronic chip 1712 mounted on the photonic interposer have characteristics similar to those of the interposer and chip described in detail above. The cover 1732 covers the electronic chip and is in thermal contact with the electronic chip. The cover 1732 and the cold plate 1734 located on top of the cover transfer the heat generated by the electronic chip to the outside of the package. As shown in Figures 5-7, a photonic interposer 1714 is disposed on a substrate 1720 (e.g., an organic substrate), and the substrate 1720 is disposed on a socket 1730. The socket 1730 is further disposed on the top surface of the circuit board 1740.

[0293] The package in Figure 5-7 relies on power bus 1754, VRM 1750, and connector 1752 to deliver power to the photonic interposer and the electronic chip. As illustrated in Figure 5-8A, a VRM receives power from the power bus and provides regulated power output to the electronic components to prevent voltage fluctuations caused by loads generated by the electronic chip from exceeding permissible values. The inventors have learned that, compared to an embodiment where the VRM and power bus are placed on a circuit board close to an interposer, mounting the VRM 1750 and power bus 1754 on the bottom surface of circuit board 1740 (on the opposite side of the circuit board relative to the interposer) reduces the lateral extension of circuit board 1740, thereby reducing power losses that would otherwise result from longer lateral paths used for power delivery. As a result, the design is more compact and easier to integrate with other electronic systems. In this configuration, connector 1752 interconnects the VRM with the corresponding electronic chip by traversing multiple layers: interposer 1714, substrate 1720, socket 1730, and circuit board 1740. Connector 1752 involves a series of different types of vias, the nature of which depends on the substrate through which it is traversed.

[0294] Figure 5-8B is a cross-sectional side view illustrating how power can be delivered from the VRM to the electronic chip. In some embodiments, a VRM delivers power to one electronic chip. In other embodiments, a VRM delivers power to multiple electronic chips. In Figure 5-8B, a VRM is shown delivering power to four electronic chips via connector 1752. XII. Additional Notes

[0295] Having thus described several aspects and embodiments of the technology of this application, it should be understood that those skilled in the art will readily grasp various changes, modifications, and improvements. Such changes, modifications, and improvements are intended to fall within the spirit and scope of the technology described in this application. Therefore, it should be understood that the foregoing embodiments are merely presented by way of example and, within the scope of the appended claims and their equivalents, may be practiced differently than those specifically described. Furthermore, if two or more features, systems, articles, materials, and / or methods do not contradict each other, any combination of such features, systems, articles, materials, and / or methods is included within the scope of this invention.

[0296] Moreover, as explained, certain states can be embodied as one or more methods. Actions performed as part of a method can be ordered in any suitable manner. Thus, embodiments can be constructed in which actions are performed in a different order than that described, and may include performing certain actions simultaneously, even if shown as sequential actions in the illustrative embodiments.

[0297] All definitions defined and used herein should be understood to be within the general meaning of dictionary definitions, definitions in referenced documents, and / or the general meaning of the defined terms.

[0298] Unless otherwise expressly indicated, the indefinite articles “a and an” as used herein and in the claims shall be understood to mean “at least one”.

[0299] The phrase “and / or” as used herein and in the claims shall be understood to mean “any one or both” of the elements in such combination, that is, elements that are combined in some cases and separated in others.

[0300] As used herein and in the claims, the phrase "at least one" in relation to a list of one or more elements shall be understood to mean at least one element selected from any one or more elements in the list of elements, but does not necessarily include each and at least one of each element specifically listed in the list of elements, and does not exclude any combination of elements in the list of elements. This definition also allows for the presence, as appropriate, of elements other than those specifically identified in the list of elements referred to by the phrase "at least one," whether related to or unrelated to those elements as specifically defined.

[0301] The terms "approximately" and "about" may be used in some embodiments to mean within ±20% of a target value, in some embodiments within ±10% of a target value, in some embodiments within ±5% of a target value, and in some embodiments still within ±2% of a target value. The terms "approximately" and "about" may include the target value. [Simplified Explanation of the Diagram]

[0080] The various aspects and embodiments of this application will be illustrated with reference to the following figures. It should be understood that the figures are not necessarily drawn to scale. Objects appearing in multiple figures are indicated by the same element symbols in all the figures in which they appear.

[0081] Figure 1-1 illustrates a computing system based on a photonic intermediary layer according to certain embodiments.

[0082] Figure 1-2A illustrates a semiconductor wafer according to one of certain embodiments.

[0083] Figure 1-2B illustrates a set of photomasks according to one of certain embodiments.

[0084] Figure 1-2C illustrates an example photomask for forming an optical waveguide according to certain embodiments.

[0085] Figure 1-2D illustrates the wafer of Figure 1-2A patterned according to the photomask assembly of Figure 1-2B according to certain embodiments.

[0086] FIG1-2E identifies photonic circuits formed on the patterned wafer of FIG1-2D according to certain embodiments.

[0087] Figure 1-3A illustrates an example tile of a patterned wafer of Figure 1-2E according to certain embodiments.

[0088] Figure 1-3B illustrates one type of group of tiles as illustrated in Figure 1-3A according to certain embodiments.

[0089] Figures 1-4A illustrate a group of tiles with a shared, identical metallic trace pattern according to certain embodiments.

[0090] Figure 1-4B illustrates a group of tiles that share the same metallic trace pattern and produce a moisture barrier according to certain embodiments.

[0091] Figure 2-1A illustrates an architecture in which tiles of a photonic interposer layer are interconnected using static connections according to certain embodiments.

[0092] Figure 2-1B illustrates another architecture in which the tiles of one of the photonic intermediary layers are interconnected using static connections according to certain embodiments.

[0093] Figure 2-1C illustrates yet another architecture in which the tiles of one of the photonic intermediary layers are interconnected using static connections according to certain embodiments.

[0094] Figure 2-1D illustrates an architecture in which tiles of a photonic interposer layer according to certain embodiments are interconnected using static connections and an optical fiber.

[0095] Figure 2-1E illustrates an architecture in which tiles of a photonic interposer layer according to certain embodiments are interconnected using static connections and two optical fibers.

[0096] Figure 2-1F illustrates an architecture in which tiles of one of the photonic interposer layers according to certain embodiments are interconnected using static connections and three optical fibers.

[0097] Figure 2-1G illustrates another architecture in which the tiles of one of the photonic interposer layers according to certain embodiments are interconnected using static connections and two optical fibers.

[0098] Figure 2-1H illustrates another architecture in which the tiles of one of the photonic interposer layers according to certain embodiments are interconnected using static connections and four optical fibers.

[0099] Figure 2-1I illustrates another architecture in which the tiles of one of the photonic interposer layers according to certain embodiments are interconnected using static connections and four optical fibers.

[0100] Figure 2-2A illustrates an architecture in which tiles of a photonic intermediary layer are interconnected using programmable connections according to certain embodiments.

[0101] Figure 2-2B illustrates another architecture in which the tiles of one of the photonic intermediary layers according to certain embodiments are interconnected using programmable connections.

[0102] Figure 2-2C illustrates another architecture in which the tiles of one of the photonic intermediary layers according to certain embodiments are interconnected using programmable connections.

[0103] FIG2-2D illustrates a tile of a photonic intermediary layer, which is further illustrated in detail in FIG2-2C according to certain embodiments.

[0104] Figure 2-2E illustrates an example of a programmable photonic interconnect according to certain embodiments.

[0105] Figure 2-2F illustrates an example of an action coupler according to certain embodiments.

[0106] Figure 2-3A illustrates an architecture with one of the bidirectional bus according to certain embodiments.

[0107] Figure 2-3B illustrates another architecture with bidirectional bus according to certain embodiments.

[0108] Figure 2-4A illustrates a photonic circuit according to certain embodiments for coupling a transmitter to a bidirectional bus.

[0109] Figure 2-4B illustrates a photonic circuit according to certain embodiments for coupling a receiver to a bidirectional bus.

[0110] Figure 2-5 illustrates an example of a waveguide crossover according to certain embodiments.

[0111] Figure 2-6A illustrates another architecture in which the tiles of one of the photonic intermediary layers according to certain embodiments are interconnected using programmable connections.

[0112] Figure 2-6B illustrates an example of a coupler used in the example of Figure 2-6A according to certain embodiments.

[0113] Figure 2-6C illustrates an architecture in which tiles of a photonic intermediary layer are interconnected using programmable connections according to certain embodiments.

[0114] Figure 2-6D illustrates another architecture in which the tiles of one of the photonic interposer layers according to certain embodiments are interconnected using programmable connections and optical fibers.

[0115] Figure 2-7A illustrates one architecture for wavelength-based tile recognition according to certain embodiments.

[0116] Figure 2-7B illustrates another architecture for wavelength-based tile recognition according to certain embodiments.

[0117] Figure 2-7B-1 illustrates another architecture for wavelength-based tile identification according to certain embodiments.

[0118] Figure 2-7C illustrates another architecture for wavelength-based tile recognition according to certain embodiments.

[0119] Figure 2-7D illustrates an example of programmable optical return used in the example of Figure 2-7C according to certain embodiments.

[0120] Figure 2-8A illustrates one of the ASICs having an Advanced Interface Bus (AIB) interface according to certain embodiments.

[0121] Figure 2-8B illustrates an ASIC-ASIC connection using an AIB interface and an optical link according to certain embodiments.

[0122] Figure 2-8C illustrates a photonic intermediary layer that manages multiple ASICs communicating with each other via an AIB interface according to certain embodiments.

[0123] Figure 2-9A is a block diagram illustrating one pair of ASICs interconnected using a wire bundle (WoR) interface according to certain embodiments.

[0124] Figure 2-9B is a block diagram illustrating one of a pair of ASICs interconnected using a wire bundle (WoR) interface according to certain embodiments.

[0125] Figure 2-10A is a schematic diagram illustrating one of the computing network architectures using a photonic intermediary layer according to certain embodiments.

[0126] Figure 2-10B is a schematic diagram illustrating one of the computing network architectures using a photonic intermediary layer according to certain embodiments.

[0127] Figure 2-10C is a schematic diagram illustrating one of the computing network architectures using a photonic intermediary layer according to certain embodiments.

[0128] Figure 2-10D is a schematic diagram illustrating one of the computing network architectures using a photonic intermediary layer according to certain embodiments.

[0129] Figure 3-1 is a block diagram illustrating one of the quasi-synchronous clock distribution schemes according to certain embodiments.

[0130] Figure 3-2 is a block diagram illustrating one of the time-synchronous clock distribution schemes according to certain embodiments.

[0131] Figure 3-3A is a block diagram illustrating a portion of a photonic intermediary layer configured to perform equalization according to certain embodiments.

[0132] Figure 3-3B is a block diagram illustrating one example of an adaptive equalizer according to certain embodiments.

[0133] Figures 3-4A to 3-4C illustrate a sequence for tuning one of a transmitters according to certain embodiments.

[0134] Figures 3-5A and 3-5B illustrate sequences for tuning one of a receivers according to certain embodiments.

[0135] Figure 3-6A illustrates a technique, according to certain embodiments, for using jitter to lock a receiver to one of a particular transmitter.

[0136] Figure 3-6B illustrates one of the optical channels supporting communication between multiple transmitter-receiver pairs according to certain embodiments.

[0137] Figure 4-1A illustrates a photonic integrated circuit (PIC) having a photonic circuit and one of a plurality of optical fiber attachments according to certain embodiments.

[0138] Figure 4-1B is a block diagram illustrating a pair of PICs using k optical fibers connected to each other according to certain embodiments, some of which are provided only for redundancy.

[0139] Figure 4-1C illustrates the overall system yield (in %) of a system with one of 16 fiber optic attachment points according to certain embodiments as a function of the number of attachments at each point.

[0140] Figure 4-2 illustrates a photonic intermediary layer having one of a plurality of tiles according to certain embodiments, one of which is provided for redundancy.

[0141] Figure 4-3 is a schematic diagram illustrating one of the power monitoring grids embedded in a photonic intermediary layer according to certain embodiments.

[0142] Figure 5-1 is a schematic diagram illustrating one of the optical fibers coupled to a grating coupler according to certain embodiments.

[0143] Figure 5-2A is a schematic diagram illustrating a wafer patterned with multiple photonic circuits according to certain embodiments.

[0144] FIG5-2B is a cross-sectional view of a wafer of FIG5-2A according to certain embodiments.

[0145] Figure 5-3A is a side view of one of the photonic intermediary layers according to certain embodiments.

[0146] Figure 5-3B is a side view of one of the encapsulated photonic intermediary layers according to certain embodiments.

[0147] Figure 5-4 is a flowchart illustrating one of the procedures for fabricating an encapsulated photonic intermediary layer according to certain embodiments.

[0148] Figure 5-5 is a flowchart illustrating one of the procedures for fabricating an encapsulated photonic interposer according to certain embodiments.

[0149] Figures 5-6 are flowcharts illustrating one of the procedures for fabricating an encapsulated photonic intermediary layer according to certain embodiments.

[0150] Figures 5-7 are schematic diagrams illustrating, according to certain embodiments, one of a voltage regulator module (VRM) encapsulated in a photonic intermediary layer.

[0151] Figure 5-8A is a block diagram illustrating one of a VRMs according to certain embodiments.

[0152] Figure 5-8B is a schematic diagram illustrating one of the packages in which a VRM is used to perform power delivery to an electronic chip according to certain embodiments.

Claims

1. A photonic interposer, comprising: A plurality of photonic tiles, exemplified as a template photonic tile, each of the plurality of photonic tiles comprising: a transceiver including a transmitter and a receiver; electrical connections coupled to the transceiver, the electrical connections being configured to allow electrical communication between the transceiver and the electronic chip when an electronic chip is attached to the photonic interposer corresponding to the photonic tile; and an optically distributed network comprising a first set of bus waveguides, a second set of bus waveguides, and a plurality of programmable interconnections optically coupled to the transceiver, each programmable interconnection being configured to selectively position one of the first set of bus waveguides for optical communication with one of the second set of bus waveguides, wherein each programmable interconnection includes a waveguide crossing and an active coupler.

2. The photonic intermediary layer as described in claim 1, wherein the transceiver includes: A plurality of modulators coupled to a first bus waveguide in the first group of bus waveguides, the plurality of modulators being tuned relative to each other at different wavelengths; and a plurality of drop filters coupled to a second bus waveguide in the first group of bus waveguides, the plurality of drop filters being tuned relative to each other at different wavelengths.

3. The photonic interposer layer of claim 2, wherein the plurality of modulators are resonant modulators and the plurality of de-filters are resonant de-filters.

4. The photonic intermediary layer of claim 1, wherein the transmitter is configured to transmit data along one of the first bus waveguides in the first set of bus waveguides in a first direction or in a second direction.

5. The photonic interposer layer of claim 4, wherein each of the plurality of photonic tiles further includes a 2×2 coupler that couples the transceiver to one of the first bus waveguides in the first set of bus waveguides.

6. The photonic interposer layer as claimed in claim 5, wherein the 2×2 coupler includes a first terminal, a second terminal, a third terminal, and a fourth terminal, wherein: The first terminal is coupled to one of the outputs of the transmitter, the second terminal is coupled to one of the inputs of the receiver, and the third and fourth terminals are coupled to the first bus waveguide in the first group of bus waveguides.

7. The photonic interposer layer of claim 4, wherein each of the plurality of photonic tiles further includes an interferometer having an input and a first output and a second output, and a resonant filter, wherein: The transmitter is coupled to the input of the interferometer, and the first and second outputs of the interferometer are coupled to the resonant filter, and the resonant filter is coupled to the first bus waveguide in the first group of bus waveguides.

8. The photonic interposer layer of claim 4, wherein each of the plurality of photonic tiles further includes an interferometer having an output and a first input and a second input, and a resonant filter, wherein: The resonant filter is coupled to the first bus waveguide in the first group of bus waveguides, the first input and the second input of the interferometer are coupled to the resonant filter, and the receiver is coupled to the output of the interferometer.

9. The photonic interposer layer of claim 1, wherein the waveguide crossing includes a first waveguide patterned in a first waveguide layer, a second waveguide patterned in a second waveguide layer, and a third waveguide patterned in a third waveguide layer, wherein: The second waveguide layer is located between the first waveguide layer and the third waveguide layer, and the first waveguide is evanescently coupled to the second waveguide, and the second waveguide is evanescently coupled to the third waveguide.

10. The photonic interposer layer of claim 9, wherein the first waveguide layer is made of silicon, and both the second and third waveguide layers are made of silicon nitride.

11. The photonic intermediary layer of claim 1, wherein the action coupler comprises: Coupled to a first terminal of a first additional function coupler, coupled to a second terminal of the first additional function coupler, and coupled to a third terminal of the waveguide crossover.

12. The photonic interposer of claim 11, wherein the action coupler includes first and second Mach-Zehnder interferometers (MZIs), wherein the first terminal corresponds to a first output of the first MZI, the second terminal corresponds to a second output of the first MZI, and the third terminal corresponds to an output of the second MZI.

13. The photonic interposer layer of claim 1, wherein the bus waveguides in the second set of bus waveguides traverse multiple photonic tiles.

14. The photonic intermediary layer of claim 1, wherein each of the plurality of photonic tiles further comprises: A polarization splitter coupled to both the transmitter and the receiver; and an optical fiber coupler coupled to the polarization splitter.

15. The photonic intermediary layer of claim 1, wherein the plurality of photonic tiles are arranged in two dimensions and form a plurality of rows of photonic tiles and a plurality of columns of photonic tiles.

16. The photonic interposer layer of claim 1, wherein each of the plurality of photonic tiles is 24.8 mm × 32 mm in size.

17. A computing system comprising a photonic interposer as claimed in claim 1 and a first application-specific integrated circuit (ASIC) disposed on the photonic interposer, wherein the first ASIC includes a first sequencer-deserializer (SerDes) coupled to a first transmitter of the photonic interposer and a second SerDes coupled to a first receiver of the photonic interposer.

18. The computing system of claim 17 further includes a plurality of through silicon vias (TSVs) coupling the first SerDes to the first transmitter.

19. The computing system of claim 17, wherein the first ASIC includes a Universal Chiplet Interconnect Express (UCIe) interface coupled to the first SerDes and configured to allow communication between the first ASIC and a second ASIC.

20. The computing system of claim 17, wherein the second ASIC is mounted on the photonic interposer layer.

Images