Semiconductor memory devices

Abstract

This invention provides a highly integrated semiconductor memory device. The invention includes: a semiconductor substrate; a plurality of semiconductor regions disposed on the semiconductor substrate, arranged in a first direction and extending along a second direction; a first gate electrode and a second gate electrode arranged in the second direction, covering the plurality of semiconductor regions and extending along the first direction; a plurality of first interlayer connection point contact electrodes disposed between the first gate electrode and the second gate electrode, respectively electrically connected to memory cells; a plurality of second interlayer connection point contact electrodes disposed opposite to the first gate electrode in the second direction, electrically connected to a sense amplifier circuit; and a plurality of third interlayer connection point contact electrodes disposed opposite to the second gate electrode in the second direction, connected to a voltage generation circuit. In the region opposite to the second gate electrode in the second direction, the plurality of semiconductor regions are physically continuous and electrically connected.

Claims

1. A semiconductor memory device, comprising: Semiconductor substrate; A plurality of first semiconductor regions are disposed on the semiconductor substrate, arranged in a first direction and extending along a second direction intersecting the first direction; a first gate electrode and a second gate electrode are arranged in the second direction, extending along the first direction and covering the plurality of first semiconductor regions; a plurality of first interlayer connection point contact electrodes are disposed between the first gate electrode and the second gate electrode, connected to the plurality of first semiconductor regions, and electrically connected to a plurality of first memory cells respectively; a plurality of second interlayer connection point contact electrodes are disposed on the opposite side of the plurality of first interlayer connection point contact electrodes in the second direction relative to the first gate electrode, connected to the plurality of first semiconductor regions, and electrically connected to a plurality of first sense amplifier circuits respectively. And a plurality of third interlayer connection point contact electrodes, disposed on the opposite side of the plurality of first interlayer connection point contact electrodes in the second direction relative to the second gate electrode, connected to the plurality of first semiconductor regions, and electrically connected to the voltage generation circuit respectively. In the region on the opposite side of the plurality of first interlayer connection point contact electrodes in the second direction relative to the second gate electrode, the plurality of first semiconductor regions are physically continuous and electrically connected.

2. The semiconductor memory device as claimed in claim 1, wherein, The first gate electrode is the gate electrode of a plurality of first transistors electrically connected to the plurality of first interlayer connection point contact electrodes and the plurality of second interlayer connection point contact electrodes. The second gate electrode is the gate electrode of a plurality of second transistors electrically connected to the plurality of first interlayer connection point contact electrodes and the plurality of third interlayer connection point contact electrodes.

3. The semiconductor memory device as claimed in claim 1, further comprising: A third gate electrode is disposed on the opposite side of the second gate electrode relative to the plurality of third interlayer connection point contact electrodes in the second direction, extending throughout the plurality of first semiconductor regions and along the first direction; and a plurality of fourth interlayer connection point contact electrodes are disposed on the opposite side of the third gate electrode relative to the plurality of third interlayer connection point contact electrodes in the second direction, connected to the plurality of first semiconductor regions, and electrically connected to the plurality of second memory cells respectively.

4. The semiconductor memory device as claimed in claim 3, wherein, The third gate electrode is the gate electrode of a plurality of third transistors that electrically connect the plurality of fourth interlayer connection point contact electrodes to the plurality of third interlayer connection point contact electrodes.

5. The semiconductor memory device as claimed in claim 3, further comprising: A fourth gate electrode is disposed on the opposite side of the third gate electrode in the second direction relative to the plurality of fourth interlayer connection point contact electrodes, extending throughout the plurality of first semiconductor regions and along the first direction; and a plurality of fifth interlayer connection point contact electrodes are disposed on the opposite side of the plurality of fourth interlayer connection point contact electrodes in the second direction relative to the fourth gate electrode, connected to the plurality of first semiconductor regions, and electrically connected to the plurality of second sense amplifier circuits respectively.

6. The semiconductor memory device as claimed in claim 5, wherein, The fourth gate electrode is the gate electrode of a plurality of fourth transistors that electrically connect the plurality of fourth interlayer connection point contact electrodes to the plurality of fifth interlayer connection point contact electrodes.

7. The semiconductor memory device as claimed in claim 1, wherein, The number of the plurality of third-layer inter-connection point contact electrodes is consistent with the number of the plurality of first semiconductor regions arranged in the first direction.

8. The semiconductor memory device as claimed in claim 1, wherein, The number of the plurality of third-layer inter-connection point contact electrodes is not the same as the number of the plurality of first semiconductor regions arranged in the first direction.

9. The semiconductor memory device as claimed in claim 1, further comprising: A plurality of second semiconductor regions are disposed on the opposite side of the first gate electrode in the second direction relative to the plurality of second interlayer connection point contact electrodes, arranged in the first direction and extending along the second direction; a fifth gate electrode extends along the first direction throughout the plurality of second semiconductor regions; a first gate insulating film is disposed between the plurality of first semiconductor regions and the first gate electrode; a second gate insulating film is disposed between the plurality of first semiconductor regions and the second gate electrode; and a third gate insulating film is disposed between the plurality of second semiconductor regions and the fifth gate electrode.

10. The semiconductor memory device as claimed in claim 9, wherein, The thickness of the first gate insulating film in a third direction intersecting the first and second directions is greater than the thickness of the third gate insulating film in that third direction.

11. The semiconductor memory device as claimed in claim 9, wherein, The thickness of the second gate insulating film in a third direction intersecting the first and second directions is greater than the thickness of the third gate insulating film in that third direction.

12. The semiconductor memory device as claimed in claim 9, wherein, The thickness of the first gate insulating film in a third direction intersecting the first and second directions is the same as the thickness of the third gate insulating film in that third direction.

13. The semiconductor memory device as claimed in claim 9, wherein, The thickness of the second gate insulating film in a third direction intersecting the first and second directions is the same as the thickness of the third gate insulating film in that third direction.

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