Methods for fabricating a 3-dimensional memory structure of nor memory strings

Abstract

A method for manufacturing a 3-D NOR memory array involves placing thin-film storage transistors for each NOR memory string in a shaft or in a portion of a trench between adjacent shafts.

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing memory volumetric circuits. Specifically, this invention relates to a method for manufacturing thin-film storage transistors in a three-dimensional memory structure formed on the surface of a semiconductor substrate. Cross-reference to related applications

[0002] This application relates to and asserts priority to U.S. Provisional Patent Application No. ______ filed in July 2020 entitled “Methods for Fabricating a 3-Dimensional Memory Structure of NOR Memory Strings” (“Related Application I”) Serial No. ______.

[0003] This application also relates to (i) U.S. Patent Application No. 16 / 510,610, filed July 12, 2019, entitled “Fabrication Method For a 3-Dimensional NOR Memory Array”; and (ii) U.S. Provisional Patent Application No. 62 / 950390, filed December 19, 2019, entitled “Process For Preparing A Channel Region Of A Thin-Film Transistor In A 3-Dimensional Thin-Film Transistor Array”. The full disclosures of related applications I, II and III (collectively referred to as the “Related Applications”) are hereby incorporated by reference. [Previous Technology]

[0005] High-density memory arrays, such as 3D arrays of NOR memory strings, have been disclosed, for example, in U.S. Patent Application Publication 2017 / 0092371A1 (“Structural Reference I”), entitled “Capacitive-Coupled Non-Volatile Thin-film Transistor Strings in Three-Dimensional Arrays”, and in U.S. Patent Application Publication 2018 / 0366489A1 (“Structural Reference II”), entitled “3-Dimensional NOR Memory Array Architecture and Methods for Fabrication Thereof”. The disclosures of Structural Reference I and II (collectively referred to as the “Structural References”) are hereby incorporated by reference in their entirety. In addition to providing high-density and high-capacity memory circuits, these 3-D NOR memory arrays can also be operated to provide memory circuits at a highly satisfactory speed, which compete with conventional memory circuits (e.g., as dynamic random access memory ("DRAM")) that have much lower circuit density and significantly higher power dissipation.

[0006] In some instances of the structural reference, the 3D NOR memory array comprises a plurality of stacks of NOR memory strings, each stack having a plurality of NOR memory strings stacked on top of another. In that context, the NOR memory strings comprise a plurality of storage cells sharing a common drain region ("common bit line") and a common source region ("common source line"), the storage cells being disposed on one or both sides along the length of the NOR memory string. Each storage cell is controlled by a conductor ("word line" or "local word line") extending substantially orthogonal to the memory string. Each word line may be shared by multiple storage cells in different NOR memory strings along its length. [Summary of the Invention]

[0007] According to a specific embodiment of the present invention, a method for manufacturing a 3-D NOR memory array provides each thin-film storage transistor of a NOR memory string in a shaft or in a portion of a trench between adjacent shafts.

[0008] According to a specific example, the method may include: (i) disposing a semiconductor structure above a planar surface of a semiconductor substrate, the semiconductor structure including a plurality of active multilayers stacked on top of each other along a first direction substantially perpendicular to the planar surface, wherein adjacent active multilayers are electrically isolated from each other by a layer of dielectric material (e.g., silicon oxide (SiOC)), and wherein each active multilayer may include a first semiconductor layer and a second semiconductor layer having a first conductivity type separated by a dielectric material; (ii) disposing a plurality of shafts arranged in a regular pattern along a second direction and a third direction, the second direction and the third direction being substantially orthogonal to each other and each orthogonal to the first direction, each shaft extending through the semiconductor structure at a depth along the first direction and having a predetermined range along the second direction; (iii) A plurality of trenches are provided in the semiconductor structure, each trench extending at a depth along the first direction and at a length along the third direction, each trench (a) intersecting with a plurality of shafts in the second direction, and (b) having a width along the second direction smaller than the extent of each shaft; and (iv) forming in (a) each shaft or in a portion of each trench between adjacent shafts: (1) a third semiconductor layer having a second conductivity type opposite to the first conductivity type, the third semiconductor layer being formed adjacent to and in contact with the first semiconductor layer and the second semiconductor layer of each active multilayer, (2) a charge trapping layer adjacent to the third semiconductor layer; and (3) a conductor layer (in contact with the charge trapping layer). The conductor layer may include, for example, a metal liner (e.g., titanium nitride) and a filler conductive material (tungsten (W)).

[0009] In that specific instance, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the charge trapping layer, and the conductor of each active multilayer provide a common bit line, a common source line, a channel region, a charge storage layer, and a gate electrode for one of the thin-film storage transistors in a NOR memory string.

[0010] When the third semiconductor layer is formed in a trench, the adjacent trench is filled with an insulating material. Similarly, when the third semiconductor layer is formed in a trench, the adjacent trench is filled with the insulating material.

[0011] In one specific embodiment, each of the active multilayers may further include a conductor layer adjacent to and in contact with at least one of the first semiconductor layer and the second semiconductor layer. The conductor layer in each active multilayer may be formed by replacing one of the sacrificial layers in each active multilayer. The conductor layer may be formed using a conductive material (e.g., tungsten) formed by atomic layer deposition (ALD).

[0012] In one specific example, the charge trapping layer includes a tunneling layer (e.g., silicon oxide), a charge storage layer, and a barrier layer (e.g., silicon oxide, aluminum oxide, or both).

[0013] In one specific example, before the trenches are formed in the semiconductor structure, the shafts are lined with a dielectric liner (e.g., an oxide liner) and the shafts are filled with a sacrificial material (e.g., carbon or tungsten).

[0014] The invention will be better understood after considering the following detailed description in conjunction with the accompanying drawings.

Implementation Method

[0016] Figure 1 is a schematic top view of a modular unit (i.e., "tile") 100 in a memory structure including a 3-D NOR memory array according to a specific embodiment of the present invention. The tile 100 is typically formed on a planar surface of a semiconductor substrate, such as a single-crystal epitaxial layer of a silicon wafer. In this detailed description, to facilitate visualization of the 3D structure, a linear coordinate reference system is used, which assumes that the planar surface is in the XY plane and that the normal to the planar surface is in the Z direction orthogonal to the XY plane.

[0017] In some instances, the semiconductor substrate may include a support circuitry system beneath or on a 3-D NOR memory array for forming therein or on the 3-D NOR memory array. Such support circuitry may include both analog and digital circuitry. Some examples of such support circuitry include shift registers, latches, sense amplifiers, reference cells, power supply lines, bias and reference voltage generators, inverters, NAND, NOR, mutexes and other logic gates, input / output drivers, address decoders (e.g., bit line and word line decoders), other memory elements, data encoding and decoding circuitry (including, for example, error detection and correction circuitry), sequencers, and state machines. This detailed description begins with a semiconductor substrate in which such support circuitry, if present, has been formed in a conventional manner. This detailed description and the skill of one of ordinary skill in the art inform any constraints or associated design options imposed or available in various specific embodiments of the invention by means of one or more methods performed in the formation of support circuitry in the semiconductor substrate.

[0018] As shown in Figure 1, the chip 100 includes an "array" portion 101 disposed between "step portions" 102a and 102b. Thin-film storage transistors of the NOR memory strings in the chip 100 are formed in the array portion 101, and the step portions 102a and 102b allow connection via conductive vias to the common bit line of the NOR memory strings and, where appropriate, to the common source line. (Structural references disclose a scheme in which the common source line is pre-charged during programming, read, and erase operations to serve as a virtual voltage reference source, thereby avoiding the need for continuous electrical connections to the supporting circuitry during such operations). In Figure 1, the array portion 101 and the step portions 102a and 102b are not drawn to scale. For example, the area of ​​the array portion 101 may be much larger than either of the step portions 102a and 102b.

[0019] FIG2a(i) shows a cross-section in the ZX plane of a memory structure 200 after the deposition of numerous material layers (discussed below) according to a specific embodiment of the present invention. Initially, a pad oxide 201 (e.g., silicon oxide) is disposed above the planar surface of a semiconductor substrate. Then, an etch stop layer 202 (e.g., tungsten (W), tungsten nitride (WN), aluminum oxide (AlO), or aluminum nitride (AlN)) is disposed. Next, a silicon oxide (SiOC) layer 203 is disposed to isolate the etch stop layer 202 from the layer to be deposited below. Subsequently, active multilayers 204 (a total of eight layers, as shown in FIG2a(i)) are deposited successively. The active multilayer 204 comprises, in the following deposition order: (i) a silicon nitride (SiN) layer 204a, (ii) an N+-doped amorphous silicon (or polycrystalline silicon) layer 204b, (iii) a sacrificial oxide layer 204c, (iv) an N+-doped amorphous silicon (or polycrystalline silicon) layer 204d, and (v) a SiN layer 204e. A SiOC layer, indicated as SiOC layer 203 in Figure 2a(i), is deposited between adjacent active multilayers. An isolating SiOC layer 205 is then deposited on top of the active multilayer 204. The resulting structure is the memory structure 200 of Figure 2.

[0020] FIG2a(ii) illustrates the continuation recessing and etching steps for generating the stepped portions 102a or 102b of FIG1 according to a specific embodiment of the present invention. As shown in FIG2a(ii), the surface of the memory structure 200 is patterned to form a mask layer 210, thereby exposing a first portion of the memory structure 211, as shown in FIG2a(i)(1). Then, the exposed portion of the isolation SiOC layer 205 is removed to expose a portion of the underlying active multilayer 204. Then, the other exposed portion of the active multilayer 204 is removed to expose a portion of the underlying SiOC layer 203. The resulting structure is shown in FIG2a(ii)(2). Then, the mask layer 210 is recessed to expose a new portion of the isolation SiOC layer 205. The exposed SiOC layers 205 and 203 are removed, the active multilayer 204 is removed, and the masking layer 210 is recessed. This process is repeated seven times to form a stepped structure 102a or 102b. Subsequently, oxide is deposited to fill the removed portions of the active multilayer 204. A chemical mechanical polishing (CMP) step is performed to remove the masking layer 210 and planarize the top surface of the memory structure 200.

[0021] This description describes the formation of the stepped structures 102a and 102b prior to the detailed processing of the array portion 101. However, the array portion 101 may also be processed before the stepped structures 102a and 102b are formed.

[0022] Next, a hard mask layer 215 (e.g., a carbon hard mask) is deposited over the memory structure 200 and patterned using photolithography. Figure 2b(i) is a top view of the array portion 101 of the memory structure 200, showing the hard mask 215 patterned to provide a plurality of openings 217 to expose corresponding portions of the memory structure 200. In Figure 2b(i), the openings 217 are shown as circular; however, any suitable shape (e.g., oval) can be used. A series of etching steps remove the exposed portions of the isolation layers 205 and 203 and the active multilayer 204 until the etch termination layer 202 is reached, thereby forming a shaft 218. Figure 2b(ii) shows a cross-section of the memory structure 200 along line A-A' in Figure 2b(i) after the etching steps according to a specific embodiment of the invention. (In this description, a "row" of objects refers to objects aligned along the Y direction, and a "column" of objects refers to objects aligned along the X direction.) In Figure 2b(i), adjacent rows of openings 217 are staggered relative to each other, such that the separation between the closest openings in adjacent rows is greater than the separation when such openings are aligned in the X direction. In one specific example, adjacent rows of openings 217 are spaced 160 nm apart along the X direction, and each of the openings 217 may have a diameter of 100 nm. Shafts 218 may be up to 2 micrometers deep, allowing the etching step to have an aspect ratio of less than 20.

[0023] The shaft 218 may be lined with an oxide liner 220 and filled with a sacrificial material 221 (e.g., a bonding layer of carbon or tungsten (W) and titanium nitride (TiN)). The surface of the memory structure 200 may then be planarized using CMP or etched back when carbon is used as the sacrificial material. After the shaft 218 is filled with the sacrificial material 221, a hard mask 225 is deposited and patterned to form linear openings 240 that expose portions of the memory structure 200 that overlap with the rows of the filled shaft 218 (i.e., along the Y direction) (e.g., each 60 nm wide in one specific example). According to one specific example of the invention, Figures 2c(i) and 2c(ii) show a top view and a cross-sectional view (in the XZ plane along line A-A' of Figure 2c(i), respectively) of the memory structure 200 generated after patterning the hard mask 225.

[0024] A series of successive etchings remove portions of the SiOC layer 205, active multilayer 204, and etch-stop layer 202 that are successively exposed beneath the straight portion 240 of the hard mask 225, thereby dividing the memory structure 200 into numerous stacks separated by trenches 245. Because the etching is designed to be selective for the oxide lines 220 and the sacrificial material 221 in the filled shafts 218, the filled shafts 218 become pillars 231 of the sacrificial material 221, surrounded by an oxide liner layer 220 on their cylindrical surfaces. Additional wet etching can be provided to remove any stringers of various materials. The hard mask 225 can then be removed (e.g., by CMP or by ashing, where appropriate). According to a specific embodiment of the present invention, Figures 2d(i) and 2d(ii) respectively show a top view and a cross-sectional view of the memory structure 200 generated after the removal of the hard mask 225 (in the XZ plane along line A-A' of Figure 2d(i).

[0025] The trench 245 can then be filled with silicon oxide, for example using atomic layer deposition (ALD) or spin coating techniques. Excess oxide on the top surface of the memory structure 200 can then be removed using, for example, CMP. Thereafter, the pillars 231 are removed using, for example, suitable wet etching. According to a specific embodiment of the invention, Figures 2e(i) and 2e(ii) respectively show a top view and a cross-sectional view of the memory structure 200 formed after the removal of the pillars 231 (in the XZ plane along line A-A' of Figure 2e(i).

[0026] Removal of the guide post 231 restores the shaft 218 within the silicon oxide filler of the trench 245 and exposes the active multilayer 204. Through the shaft 218, the SiN layers 204a and 204e of each of the active multilayers 204 can be removed using, for example, silicon nitride wet etching. According to a specific embodiment of the invention, Figures 2f(i) and 2f(ii) respectively show a top view and a cross-sectional view of the memory structure 200 generated after removing the SiN layers 204a and 204e from each of the active multilayers 204 in the XZ plane (along line A-A' of Figure 2f(i)).

[0027] The ALD step deposits conductive material into the cavity created by removing SiN layers 204a and 204e from each of the active multilayers 204. The conductive material may include, for example, a metal liner (e.g., titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN)), followed by a refractory metal (e.g., tungsten (W), tungsten nitride (WN), or molybdenum (Mo)). Subsequently, anisotropic separation etching removes the conductive material from shaft 218. Conductor layers 204f and 204g, which replace SiN layers 204a and 204e in each active multilayer, may be recessed, for example, by 10 nm. According to a specific embodiment of the present invention, Figures 2g(i) and 2g(ii) respectively show a top view and a cross-sectional view in the XZ plane (along line A-A' of Figure 2g(i)) of the memory structure 200 formed after replacing the SiN layers 204a and 204e of each of the active multilayers 204 with conductor layers 204f and 204g. Conductor layers 204f and 204g are selectively chosen conductor layers formed adjacently and in contact with N+ amorphous silicon layers 204b and 204d, depending on the situation. The N+ amorphous silicon layers 204b and 204d of each active multilayer 204 will become the common bit line and common source line of the NOR memory string to be formed. Conductor layers 204f and 204g reduce the resistivity in the common bit line and common source line.

[0028] Next, the sacrificial oxide layer 204c, N+ amorphous silicon layer 204b, and N+ amorphous silicon layer 204d of each active multilayer 204 can be recessed to create cavities for depositing channel material for thin-film storage transistors. Then, the polycrystalline silicon layer 250 intended to form the channel region of the thin-film storage transistor is deposited, etched back for separation, and recessed to remove longitudinal material. According to a specific embodiment of the present invention, Figures 2h(i) and 2h(ii) respectively show a top view and a cross-sectional view (in the XZ plane along line A-A' of Figure 2h(i)) of the memory structure 200 generated after the channel polycrystalline silicon layer 250 is recessed.

[0029] The charge trapping layer 251 is then conformally deposited on the sidewall of the shaft 218. The charge trapping layer 251 may be multilayered, including a tunneling dielectric layer (e.g., silicon oxide), a storage layer (e.g., silicon nitride), and a barrier dielectric layer (e.g., silicon oxide, aluminum oxide, or both). The shaft 218 may then be filled with a conductive material 252 (e.g., a tungsten-TiN bonding layer) that forms gate electrodes ("word lines") for storage cells in each active multilayer 204 along the length of the gate electrodes. According to a specific embodiment of the invention, FIG2i shows a cross-sectional view in the XZ plane of the memory structure 200 formed after the deposition of the conductive material 252.

[0030] In the method illustrated in Figures 2a to 2i, each thin-film storage transistor is formed within one of the shafts 218, which accommodates a curved channel region, a charge trapping layer 251, and a gate electrode formed of conductive material 252. In this specific example, the straight portion of the trench 245 provides isolation between the thin-film storage transistors. Alternatively, the thin-film storage transistors may be formed within the straight portion of the trench 245, wherein an insulating material fills the shafts 218 to provide isolation between the thin-film storage transistors. The method of this alternative will now be described.

[0031] According to an alternative embodiment of the invention, after removing the rigid mask 225, as shown in Figures 2e(i) and 2e(ii), the SiN layers 204a and 204e are replaced with conductor layers 204f and 204g, respectively, in substantially the same manner as described above in conjunction with Figures 2e to 2g, except that the removal of SiN layers 204a and 204 begins from the straight portion of trench 245 rather than through shaft 218, because the oxide liner 220 and sacrificial material 221 have not yet been removed. The conductor layers 204f and 204g that replace SiN layers 204a and 204e in each active multilayer can be recessed, for example, by 10 nm. According to an alternative embodiment of the invention, Figures 3a(i) and 3a(ii) show a top view and a cross-sectional view of the memory structure 200 formed after the conductor layers 204f and 204g are recessed in the XZ plane (along line A-A' of Figure 3a(i), respectively.

[0032] Subsequently, the sacrificial oxide layer 204c, N+ amorphous silicon layer 204b, and N+ amorphous silicon layer 204d of each active multilayer 204 can be recessed to create cavities for depositing channel material for thin-film storage transistors. Then, the polycrystalline silicon layer 250 intended to form the channel region of the thin-film storage transistor is deposited, etched back for separation, and recessed to remove longitudinal material. According to an alternative embodiment of the invention, Figures 3b(i) and 3b(ii) respectively show a top view and a cross-sectional view of the memory structure 200 generated after recessing the channel polycrystalline silicon layer 250 in the XZ plane (along line A-A' of Figure 3b(i)).

[0033] The charge trapping layer 251 is then conformally deposited on the sidewall of the trench 245. The charge trapping layer 251 may be multilayered, including: (i) a tunneling layer (e.g., any silicon oxide (SiOx), silicon nitride (SiN), silicon oxynitride (SiON), any aluminum oxide (AlOx), any hafnium oxide (HfOx), zirconium oxide (ZrOx), any hafnium silicon oxide (HfSixOy), any hafnium zirconium oxide (HfZrO) or any combination thereof); (ii) a charge storage layer (e.g., silicon nitride (SiN), hafnium oxide (HfO2) or hafnium silicon oxynitride (HfSiON)); and (iii) a barrier layer (e.g., any silicon oxide (SiOx), any aluminum oxide (AlOx) or both).

[0034] The trench 245 may then be filled with a conductive material 252 (e.g., a tungsten-TiN bonding layer), which forms a gate electrode ("word line") for use along the length of the gate electrode in each active multilayer 204 storage cell. Excess conductive material on the top surface of the memory structure 200 may be removed by CMP. According to a specific embodiment of the invention, Figures 3c(i) and 3c(ii) show a top view and a cross-sectional view of the memory structure 200 formed after deposition and planarization of the conductive material 252 in the XZ plane (along line A-A' of Figure 3c(i)).

[0035] Subsequently, the posts 231 in the shaft 218 are removed using, for example, a suitable wet etching process. The removal of the posts 231 restores the shaft 218 in the conductive material 252 of the trench 245. The shaft 218 can then be filled with a suitable insulating material 255 (e.g., silicon oxide). Excess insulating material on the top of the memory structure 200 can be removed by CMP. According to a specific embodiment of the invention, Figures 3d(i) and 3d(ii) respectively show a top view and a cross-sectional view of the memory structure 200 formed after the deposition of the insulating material 255 in the XZ plane (along line A-A' of Figure 3d(i)).

[0036] The above detailed description is provided to illustrate specific examples of the invention and is not intended to be limiting. Numerous variations and modifications are possible within the scope of the invention. The invention is set forth in the appended claims. [Simplified Explanation of the Diagram]

[0015] [Figure 1] is a schematic top view of a modular cell ("cell chip") 100 in a memory structure including a 3-D NOR memory array according to a specific embodiment of the present invention. [Figure 2a(i)] shows a cross-section of the memory structure 200 in the ZX plane after deposition of numerous material layers (discussed below) according to a specific embodiment of the present invention. [Figure 2a(ii)] illustrates the continuous recess and etching steps for producing the stepped portions 102a or 102b of Figure 1 according to a specific embodiment of the present invention. [Figure 2b(i)] is a top view of the array portion 101 of the memory structure 200. [Figure 2b(ii)] shows a cross-section of the memory structure 200 in the XZ plane along line A-A' in Figure 2b(i) after the etching steps produce the shafts 218 up to the etch termination layer 202 according to a specific embodiment of the present invention. [Figure 2c(i)] and [Figure 2c(ii)] respectively show a top view and a cross-sectional view (in the XZ plane along line A-A' of Figure 2c(i)) of a memory structure 200 generated after patterning the hard mask 225, according to a specific embodiment of the present invention. [Figure 2d(i)] and [Figure 2d(ii)] respectively show a top view and a cross-sectional view (in the XZ plane along line A-A' of Figure 2d(i)) of a memory structure 200 generated after removing the hard mask 225, according to a specific embodiment of the present invention. [Figure 2e(i)] and [Figure 2e(ii)] respectively show a top view and a cross-sectional view (in the XZ plane along line A-A' of Figure 2e(i)) of a memory structure 200 generated after removing the guide post 231, according to a specific embodiment of the present invention. [Figure 2f(i)] and [Figure 2f(ii)] respectively show a top view and a cross-sectional view (in the XZ plane along line A-A' of Figure 2f(i)) of a memory structure 200 generated after removing SiN layers 204a and 204e from each active multilayer exposed along the sidewall of shaft 218 according to a specific embodiment of the present invention. [Figure 2g(i)] and [Figure 2g(ii)] respectively show a top view and a cross-sectional view (in the XZ plane along line A-A' of Figure 2g(i)) of a memory structure 200 generated after replacing SiN layers 204a and 204e of each active multilayer with conductor layers 204f and 204g according to a specific embodiment of the present invention. [Figure 2h(i)] and [Figure 2h(ii)] respectively show a top view and a cross-sectional view (in the XZ plane along line A-A' of Figure 2g(i)) of a memory structure 200 formed after recessing the channel polysilicon layer 250 according to a specific embodiment of the present invention. [Figure 2i] shows a cross-sectional view in the XZ plane of a memory structure 200 formed after depositing conductive material 252 according to a specific embodiment of the present invention.[Fig. 3a(i)] and [Fig. 3a(ii)] respectively show a top view and a cross-sectional view (in the XZ plane along line A-A' of Fig. 3a(i)) of a memory structure 200 formed after recessing conductor layers 204f and 204g according to an alternative embodiment of the present invention. [Fig. 3b(i)] and [Fig. 3b(ii)] show a top view and a cross-sectional view (in the XZ plane along line A-A' of Fig. 3b(i)) of a memory structure 200 formed after depositing channel polycrystalline silicon layer 250 according to an alternative embodiment of the present invention. [Fig. 3c(i)] and [Fig. 3c(ii)] show a top view and a cross-sectional view (in the XZ plane along line A-A' of Fig. 3c(i)) of a memory structure 200 formed after depositing and planarizing conductive material 252 according to an alternative embodiment of the present invention. [Fig. 3d(i)] and [Fig. 3d(ii)] respectively show a top view and a cross-sectional view (in the XZ plane along line A-A' of Fig. 3d(i)) of a memory structure 200 generated after deposition and planarization of the isolation material 255 according to an alternative specific example of the present invention.

Claims

1. A method for manufacturing a 3D memory structure, comprising: disposing a semiconductor structure above a planar surface of a semiconductor substrate, the semiconductor structure comprising a plurality of active multilayers stacked one on top of another along a first direction substantially perpendicular to the planar surface, wherein adjacent active multilayers are electrically isolated from each other by a dielectric material of a first layer, and wherein each active multilayer comprises a first semiconductor layer and a second semiconductor layer having a first conductivity type separated by a dielectric material of a second layer; disposing a plurality of shafts arranged in a regular pattern along a second direction and a third direction, the second direction and the third direction being substantially orthogonal to each other and each orthogonal to the first direction, each shaft extending through the semiconductor structure at a depth along the first direction and having a predetermined range along the second direction; The semiconductor structure comprises a plurality of trenches, each trench extending at a depth along a first direction and at a length along a third direction, each trench (a) intersecting with a plurality of shafts in a second direction, and (b) having a width along the second direction smaller than the predetermined range of each shaft; and forming in (i) each shaft or (ii) a portion of each trench between adjacent shafts: (a) a third semiconductor layer having a second conductivity type opposite to the first conductivity type, the third semiconductor layer being formed adjacent to and contacting the first semiconductor layer and the second semiconductor layer of each active multilayer, (b) a charge trapping layer adjacent to the third semiconductor layer; and (c) a conductor layer in contact with the charge trapping layer.

2. The method of claim 1, wherein the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the charge trapping layer, and the conductor of each active multilayer provide a common bit line, a common source line, a channel region, a charge storage layer, and a gate electrode for the thin-film storage transistor in the NOR memory string.

3. The method of claim 1, wherein when the third semiconductor layer is formed in each shaft, the portion of each trench between adjacent shafts is filled with an insulating material.

4. The method of claim 1, wherein when the third semiconductor layer is formed in the portion of each trench between adjacent shafts, each shaft is filled with an insulating material.

5. The method of claim 1, wherein each of the active multilayers further comprises a conductor layer adjacent to and in contact with at least one of the first semiconductor layer and the second semiconductor layer.

6. The method of claim 1, wherein the conductor layer is formed by replacing the sacrificial layer in each active multilayer, the sacrificial layer is removed through the shaft (or through the portion of each trench between adjacent shafts) and the conductor material of atomic layer deposition (ALD) is deposited.

7. The method of claim 6, wherein the conductor material comprises tungsten.

8. The method of claim 1, wherein the dielectric material of the first layer and the dielectric material of the second layer comprise silicon carbide (SiOC).

9. The method of claim 1, wherein the charge trapping layer comprises a tunneling layer, a charge storage layer, and a blocking layer.

10. The method of claim 9, wherein the tunneling layer comprises one or more of the following: any silicon oxide (SiOx), silicon nitride (SiN), silicon oxynitride (SiON), any aluminum oxide (AlOx), any hafnium oxide (HfOx), zirconium oxide (ZrOx), any hafnium silicon oxide (HfSixOy), and any hafnium zirconium oxide (HfZrO).

11. The method of claim 9, wherein the charge storage layer comprises one or more of the following: silicon nitride (SiN), hafnium oxide (HfO2), and hafnium oxynitride (HfSiON).

12. The method of claim 10, wherein the barrier layer comprises one or more of the following: any silicon oxide (SiOx) and aluminum oxide (AlOx).

13. The method of claim 6, wherein the conductor material comprises a metal liner and a refractory metal.

14. The method of claim 13, wherein the metal liner comprises one or more of the following: titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

15. The method of claim 13, wherein the refractory metal comprises one or more of the following: tungsten (W), tungsten nitride (WN), and molybdenum (Mo).

16. The method of claim 1, further comprising lining the shaft with a dielectric liner before forming the trench in the semiconductor structure.

17. The method of claim 16, wherein the dielectric liner comprises an oxide liner.

18. The method of claim 16, further comprising filling the shaft with sacrificial material.

19. The method of claim 18, wherein the sacrificial material comprises carbon or tungsten (W).

20. The method of claim 19, further comprising providing an adhesive layer of titanium nitride to surround the sacrificial material.

21. The method of claim 18, wherein when the third semiconductor layer is formed in the shaft, forming the third semiconductor layer comprises: removing the sacrificial material from the shaft; recessing the first semiconductor layer and the second semiconductor layer and the dielectric material of the second layer into each active multilayer to create a cavity; and depositing the third semiconductor layer.

22. The method of claim 21, wherein the charge-capturing layer is conformally deposited on the sidewall of the shaft.

23. The method of claim 22, wherein the conductor layer is formed by depositing a conductive material to fill each shaft after the charge trapping layer has been formed.

24. The method of claim 1, wherein when the third semiconductor layer is formed in the portion of each trench between adjacent shafts, forming the third semiconductor layer comprises: recessing the first semiconductor layer and the second semiconductor layer and the dielectric material of the second layer into each active multilayer to create a cavity by means of the exposed portion of each trench between adjacent shafts; and depositing the third semiconductor layer.

25. The method of claim 24, wherein the charge-capturing layer is conformally deposited on the sidewall of the portion of each trench between adjacent shafts.

26. The method of claim 25, wherein the conductor layer is formed by depositing a conductive material to fill each portion of each trench between adjacent shafts after the charge trapping layer has been formed.

27. The method of claim 26, further comprising filling the shaft with sacrificial material.

28. The method of claim 1, further comprising providing an etch stop layer between the first semiconductor layer and the second semiconductor layer and the planar surface of the semiconductor substrate.

29. The method of claim 28, wherein the etch stop layer comprises one or more of tungsten (W), tungsten nitride (WN), aluminum oxide (AlO), or aluminum nitride (AlN).

30. The method of claim 28, further comprising a pad oxide layer between the etch stop layer and the planar surface of the semiconductor substrate.

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