Method of simultaneous-silicidation on source and drain of nmos and pmos transistors

Abstract

This document discloses a method and apparatus for forming metal-oxide-semiconductor (MOSFET) devices. The formation method includes utilizing silicon-germanium seed layers deposited on n-channel MOSFET (NMOS) and p-channel MOSFET (PMOS) devices. The seed layer can be one seed layer or two doped seed layers deposited over both the NMOS source / drain region and the PMOS source / drain region, wherein a first doped seed layer is deposited over the PMOS source / drain region, and a second doped seed layer is deposited over the NMOS source / drain region. The seed layer enables the simultaneous formation of silica over both the PMOS and NMOS source / drain regions. The silica formation consumes the seed layer and forms a silica layer whose composition varies with the composition of the absorbed seed layer.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to apparatus and methods for manufacturing field-effect transistors (FETs). Prior Technology

[0002] A FET is a series of transistors that rely on an electric field generated by a voltage at the gate to control the current between the drain and source. One of the many types of FETs is the metal-oxide-semiconductor FET (MOSFET). The fabrication of a MOSFET device involves multiple deposition and patterning operations performed to form and electrically connect and / or isolate various features of the device. At least one silica layer is typically formed on top of the source / drain region of an n-channel metal-oxide-semiconductor (NMOS) device and a p-channel metal-oxide-semiconductor (PMOS) device during the MOSFET fabrication process to reduce the contact resistance between the metal and the source / drain region. Given the many processing operations involved in MOSFET fabrication, the nucleation of the silica layer can be challenging; the silica layer can be a metal silicate including polycrystalline (“poly”) metal silicates.

[0003] Typically, metal silicide layer formation involves at least two operations to enable the formation of a first silicide layer on an NMOS device and a second silicide layer on a PMOS device. Traditionally, metal silicides are formed using plasma with a reactive metal source gas on a source / drain epitaxial substrate via initial metal deposition / nucleation. This initial metal deposition / nucleation is followed by thermal annealing for complete silanization between the metal and the epitaxial substrate. However, plasma-based metal deposition / nucleation is non-selective, and the metal film, thin film, is deposited on both the dielectric surface of the substrate and the epitaxial film surface. Without plasma initiation, initial metal deposition / nucleation is difficult, and the metal source material reacts inconsistently with the substrate surface for initial silicide nucleation. The quality and ease of metal silicide nucleation depend heavily on the characteristics of the substrate surface, the metal within the silicide, and the temperature. The use of Si, SiGe, and Ge substrates further alters the metal source material deposition behavior. It has been found that Ge-containing substrates can enhance silicide nucleation / formation even without plasma assistance. Due to the different types of epitaxial films on the source / drain regions of NMOS (Si:P, Si:CP, Si:As, etc.) and PMOS (SiGeB, Ge:B, SiGeSn:B, etc.) devices, metal silicides can be formed separately on NMOS and PMOS devices under different processing conditions (temperature, pressure, deposition time, etc.). It is difficult to simultaneously form silicide layers on both NMOS and PMOS devices in a single-step silicide process. The ability to simultaneously form silicide layers on both NMOS and PMOS devices reduces the formation time of MOSFET devices.

[0004] Therefore, a process and equipment are still needed to simultaneously form silicon films on both NMOS and PMOS devices using a single siliconization process. Summary of the Invention

[0005] The embodiments disclosed herein generally relate to a method for processing a substrate. The method includes positioning a substrate having an n-channel metal-oxide-semiconductor (NMOS) element and a p-channel metal-oxide-semiconductor (PMOS) element disposed thereon in a processing chamber. After positioning the substrate in the processing chamber, a seed layer is simultaneously deposited over the NMOS source / drain regions of the NMOS element and the PMOS source / drain regions of the PMOS element. The seed layer comprises both silicon and germanium. After depositing the seed layer, a metal silicide is simultaneously deposited over the NMOS source / drain regions and the PMOS source / drain regions.

[0006] In another embodiment, a method of processing a substrate includes positioning a substrate having an n-channel metal-oxide-semiconductor (NMOS) element and a p-channel metal-oxide-semiconductor (PMOS) element disposed thereon in a first processing chamber. After positioning the substrate, a first crystalline layer is selectively deposited in the first processing chamber over the NMOS source / drain region of the NMOS element. The first crystalline layer comprises both silicon and germanium. A second crystalline layer is selectively deposited over the PMOS source / drain region of the PMOS element. The second crystalline layer comprises both silicon and germanium. After depositing the first and second crystalline layers, a metal silicate is simultaneously deposited over both the NMOS source / drain region and the PMOS source region. The first and second crystalline layers are consumed during the deposition of the metal silicate.

[0007] In another embodiment, a system for substrate processing is described. The system includes a first processing chamber. The first processing chamber includes a chamber body, a substrate support, a first chamber cover, one or more processing gas inlets, and one or more exhaust ports. The system also includes a controller. The controller is configured to perform a method. The method includes depositing a seed layer on a substrate disposed within the chamber body, wherein the deposition of the seed layer is performed over NMOS source / drain regions and PMOS source / drain regions within the substrate. The seed layer includes both silicon and germanium. The method further includes, after depositing the seed layer, simultaneously depositing a metallide over the NMOS source / drain regions and the PMOS source / drain regions. Simple Explanation of the Diagram

[0008] To gain a more detailed understanding of the features described above in this disclosure, reference can be made to embodiments for a more specific description of the disclosure briefly outlined above, some of which are shown in the accompanying drawings. However, it should be noted that the drawings illustrate only exemplary embodiments and should not be construed as limiting their scope, and other equivalent embodiments are permissible.

[0009] Figure 1 is a schematic diagram of a system for forming a semiconductor component according to an embodiment of the present disclosure.

[0010] Figure 2A is a schematic diagram of a first type of deposition chamber according to an embodiment of the present disclosure.

[0011] Figure 2B is a schematic diagram of a second type of deposition chamber according to an embodiment of the present disclosure.

[0012] Figures 3A to 3D are partial schematic diagrams of MOSFET device formation operations according to embodiments of the present disclosure.

[0013] Figures 4A to 4E are partial schematic diagrams of MOSFET device formation operations according to other embodiments of the present disclosure.

[0014] Figure 5 is a flowchart of a method for forming a part of a MOSFET device according to an embodiment of the present disclosure.

[0015] Figure 6 is a flowchart of another method for forming part of a MOSFET element according to an embodiment of the present disclosure.

[0016] Figures 7A to 7E are partial schematic diagrams of MOSFET device formation according to some other embodiments of the present disclosure.

[0017] Figures 8A to 8F are partial schematic diagrams of the formation of a MOSFET element according to an additional embodiment of the present disclosure.

[0018] Figure 9 is a flowchart of another method for forming a MOSFET device according to an embodiment of the present disclosure.

[0019] Figure 10 is a flowchart of some further methods for forming MOSFET devices according to embodiments of the present disclosure.

[0020] To facilitate understanding, the same reference numerals have been used as much as possible to indicate common elements in the figures. It is contemplated that elements and features of one embodiment can be advantageously combined in other embodiments without further explanation. Implementation

[0021] This disclosure includes methods and apparatus for improving MOSFET manufacturing processes. The MOSFET manufacturing process is improved by simplifying the siliconization integration process and reducing the dependence of siliconization on the substrate surface element composition within the source / drain regions of NMOS and PMOS (such as Si:P, Si:CP, Si:As films for NMOS and SiGe:B, Ge:B, SiGeSn:B films for PMOS). In the embodiments described herein, siliconization operations are performed simultaneously over the source / drain regions of both NMOS and PMOS, and a seed layer is consumed.

[0022] After a seed layer of silicon-germanium (SiGe) or doped silicon-germanium (e.g., SiGeB or SiGeP) is deposited on the source / drain regions of both NMOS and PMOS devices, a silicide operation is performed using a single deposition operation. The seed layer enables simultaneous formation of silicides on the source / drain regions of both the NMOS and PMOS devices. The seed layer is consumed during silicide deposition, and metallic germanium silicide is formed on both the NMOS and PMOS devices.

[0023] Figure 1 is a schematic diagram of a system 100 for forming semiconductor components (such as MOSFET elements) according to an embodiment of the present disclosure. System 100 is a cluster of tools including a first chamber 102, a second chamber 104, a third chamber 106, a fourth chamber 108, a fifth chamber 110, and a central transfer chamber 112, which defines a transfer space 118 accommodating a central transfer robot 116. System 100 further includes a controller 120 coupled to system 100. The controller is programmed to execute multiple instructions for operating system 100 to manufacture MOSFET elements, including operations of the central transfer robot 116 and operations of chambers 102 to 110 and loading chamber 114. As shown in Figure 2A, controller 120 includes a programmable central processing unit (CPU) 252 operating in conjunction with memory 235 and a large storage area device, an input control unit, and a display unit (not shown). Controller 120 includes hardware for monitoring substrate processing via sensors in the processing chambers and for monitoring precursor, process gas, and purge gas flows. Support circuitry 258 is conventionally coupled to CPU 252 to support the processor. Central transfer robot 116 is configured to transfer substrates between loading chamber 114 and one or more chambers 102 to 110 via transfer space 118.

[0024] Although not shown in Figure 1, the chambers 102, 104, 106, 108, and / or 110 of system 100 may further include one or more distal plasma sources and one or more gas sources for precursor gas, carrier gas, and other process gases. System 100 may also include multiple components, such as sensors and controllers configured to measure and control pressure, temperature, airflow, and gas composition in some or all of the chambers 102 to 110. Thus, system 100 can be configured to form desired structures and elements, including MOSFET elements, such as NMOS and PMOS elements. In one example, one or more of the chambers 102 to 110 are maintained under vacuum pressure, and the substrate moving between them is not exposed to ambient air. In one embodiment, system 100 is used to fabricate MOSFET elements in multiple operations. The substrate can move in and between one or more chambers 102 to 110. In one embodiment, the first chamber 102 is therefore used for siliconization operations. In one example, when the first chamber 102 is a metal silicate formation chamber, the substrate is conveyed through the transport space 118 and is not exposed to ambient air during transport to / from the first chamber 102. In some embodiments, the first chamber 102 is used for silicate operations, including metal silicate formation using, for example, a CVD process.

[0025] In one embodiment, the first chamber 102 is a metal silicate deposition chamber, which in one example may be a chemical vapor deposition (CVD) chamber. The second chamber 104 is an NMOS chamber, such as an NMOS chamber for source-drain epitaxy (e.g., an epitaxial deposition chamber), and may be coupled to one or more precursor sources of Si, P, C, and / or As for NMOS formation. The third chamber 106 is a PMOS chamber, such as a PMOS chamber for source-drain epitaxy, and may be coupled to one or more precursor sources of Si, Ge, and / or B for PMOS formation. The fourth chamber 108 is a plasma chamber into which dopant sources and Ar and He gas sources may be introduced to facilitate plasma ignition. The plasma chamber can be used for various MOSFET fabrication operations, including etching operations. The fifth chamber 110 is a pre-cleaning chamber, allowing oxides to be removed from the substrate surface before or during operations in the MOSFET device fabrication process.

[0026] In one example, a PMOS device may be fabricated in a chamber of system 100 including a third chamber 106, and an NMOS device may be fabricated in a chamber including a second chamber 104. In addition to one or more of the first chambers 102, both NMOS and PMOS devices, as well as other types of MOSFET devices, may be fabricated using a third chamber 106 or a second chamber 104 configured as a metallide forming chamber, a fourth chamber 108 configured as a plasma chamber, or a fifth chamber 110 configured as a pre-cleaning chamber. That is, according to embodiments, various combinations of chambers 102 to 108 may be used to fabricate NMOS or PMOS devices.

[0027] When the first chamber 102 is configured as a metal silicide deposition chamber, the metal silicide formation operation as discussed herein can be performed in the first chamber 102. This process can alternatively be performed in the metal silicide deposition chamber after a seed layer deposition operation. The seed layer deposition operation can be performed in the third chamber 106 (when the third chamber 106 is configured as a PMOS chamber). The use of chambers 102 to 110 in system 100 is discussed in detail below.

[0028] Figure 2A is a schematic diagram of a first type of deposition chamber 200a according to an embodiment of the present disclosure. The deposition chamber 200a can be any of the chambers 102 to 106 in Figure 1. The deposition chamber 200a is an epitaxial deposition chamber and is therefore typically used as a second chamber 104 and / or a third chamber 106 within system 100. The deposition chamber 200a is used to grow an epitaxial film on a substrate (such as substrate 202). The deposition chamber 200a generates a precursor crossflow on the top surface 250 of substrate 202.

[0029] The deposition chamber 200a includes an upper body 256, a lower body 248 disposed below the upper body 256, and a flow module 212 disposed between the upper body 256 and the lower body 248. The upper body 256, the flow module 212, and the lower body 248 form the chamber body. Within the chamber body are a substrate support 206, an upper dome 208, a lower dome 210, a plurality of upper lamps 241, and a plurality of lower lamps 243. As shown, a controller 120 is connected to the deposition chamber 200a and is used to control the process, such as the process described herein. The substrate support 206 is disposed between the upper dome 208 and the lower dome 210. The plurality of upper lamps 241 are disposed between the upper dome 208 and a cover 254. The cover 254 includes a plurality of sensors 253 disposed therein for measuring the temperature within the deposition chamber 200a. The plurality of lower lamps 243 are disposed between the lower dome 210 and a substrate and a bottom plate 252. Multiple lower lights 243 form a lower light assembly 245.

[0030] A processing space 236 is formed between an upper dome 208 and a lower dome 210. The processing space 236 has a substrate support 206 disposed therein. The substrate support 206 includes a top surface on which a substrate 202 is disposed. The substrate support 206 is attached to a shaft 218. The shaft is connected to a motion assembly 220. The motion assembly 220 includes one or more actuators and / or adjustment devices that provide movement and / or adjustment of the shaft 218 and / or the substrate support 206 within the processing space 236. The motion assembly 220 includes a rotary actuator 222 that rotates the shaft 218 and / or the substrate support 206 about a longitudinal axis A of the deposition chamber 200. The motion assembly 220 further includes a vertical actuator 224 to raise and lower the substrate support 206 in the z-direction. The motion assembly includes a tilt adjustment device 226 for adjusting the planar orientation of the substrate support 206 and a lateral adjustment device 228 for adjusting the position of the shaft 218 and the substrate support 206 left and right within the processing space 236.

[0031] The substrate support 206 may include a lifting rod hole 207 disposed therein. The lifting rod hole 207 is sized to accommodate a lifting rod 232 for lifting the substrate 202 from the substrate support 206 before or after performing a deposition process. When the substrate support 206 is lowered from the processing position to the transport position, the lifting rod 232 may rest on the lifting rod stop 234.

[0032] The flow module 212 includes a plurality of process gas inlets 214, a plurality of purge gas inlets 264, and one or more exhaust gas outlets 216. The process gas inlets 214 and purge gas inlets 264 are disposed on one side of the flow module 212 opposite to the one or more exhaust gas outlets 216. One or more flow guides 246 are disposed below the process gas inlets 214 and the one or more exhaust gas outlets 216. The flow guides 246 are disposed above the purge gas inlets 264. A liner 263 is disposed on the inner surface of the flow module 212 and protects the flow module 212 from reactive gases used during the deposition process. The process gas inlets 214 and purge gas inlets 264 are positioned to allow gas to flow parallel to the top surface 250 of the substrate 202 disposed within the processing space 236. The process gas inlets 214 are fluidly connected to a process gas source 251. The purge gas inlets 264 are fluidly connected to a purge gas source 262. The one or more exhaust gas outlets 216 are fluidly connected to an exhaust pump 257.

[0033] Figure 2B is a schematic diagram of a second type of deposition chamber 200b according to an embodiment of the present disclosure. The deposition chamber 200b can be any of the chambers 102 to 108 in Figure 1. The deposition chamber 200b is a chemical vapor deposition (CVD) chamber and is therefore typically used as the first chamber 102 within system 100. The deposition chamber 200b is used to grow silicon on a substrate (such as substrate 202).

[0034] The deposition chamber 200b includes a chamber body 280, a chamber cover 282, a nozzle 270, a substrate support 211, and a discharge outlet 217. The chamber body 280, chamber cover 282, and nozzle 270 define a processing space 237. The chamber cover 282 is disposed on top of the chamber body 280, while the nozzle 270 is disposed below or inside the chamber cover 282.

[0035] Nozzle 270 may alternatively be a board stack and is not limited to the nozzle design disclosed herein. Nozzle 270 includes one or more orifices 272 through which process gas flows into process space 237. Process gas may flow into process space 237 from process gas source 231. Process gas source 231 controls the amount and flow rate of process gas entering process space 237. Process gas source 231 is configured to deliver silicon-containing precursors and / or metal-containing precursors. In some embodiments, process gas source 231 may include multiple process gas sources 231, such that process gas source 231 is a gas panel. Nozzle 270 is connected to radio frequency (RF) power source 274. RF power source 274 is configured to provide bias between substrate support 206 and nozzle 270. Alternatively, RF power source 274 may be connected to substrate support 206, and nozzle 270 may be grounded.

[0036] A substrate support 211 is disposed within the processing space 237 and configured to support a substrate, such as substrate 202. The substrate support 211 includes a planar upper surface sized to receive substrate 202. The substrate support 211 is connected to a shaft 213. The shaft 213 extends from the underside of the substrate support 211 and is configured to rise, lower, or rotate. In some embodiments, the shaft 213 and the substrate support 211 are connected to one or more motors or actuators in a manner similar to that of the shaft 218 and substrate support 206 of the deposition chamber 200a of FIG. 2A. The shaft 213 and the substrate support 211 are grounded.

[0037] The exhaust outlet 217 is connected to both the processing space 237 and the exhaust pump 259. The exhaust outlet 217 and the exhaust pump 259 remove gas from the processing space 237. The exhaust outlet 217 is disposed through the chamber body 280.

[0038] Figures 3A to 3D are partial schematic diagrams of the formation of a MOSFET element 300a according to an embodiment of the present disclosure. Figure 5 shows a method 500 for forming the MOSFET element 300a. The MOSFET element 300a of Figure 3A is shown after the formation of an NMOS source / drain region 320, a PMOS source / drain region 321, and a gate within a substrate 301 (such as substrate 202). The NMOS source / drain region 320 is disposed within a p-well region 310. The PMOS source / drain region 321 is disposed within an n-well region 315. Multiple MOSFET elements 300a may exist within a single substrate 301, such that multiple NMOS source / drain regions 320 and multiple PMOS source / drain regions 321 exist within the substrate 301.

[0039] The NMOS source / drain region 320 and p-well region 310 are part of the NMOS device 302. The PMOS source / drain region 320 and n-well region 315 are part of the PMOS device 304. A gate 341 is disposed on a first surface 342 of the substrate 301, between the NMOS source / drain regions 320. Another gate 341 is disposed on a second surface 344 of the substrate 301, between the PMOS source / drain regions 321. A third surface 343 of the substrate 301 is disposed between the NMOS device 302 and the PMOS device 304. In some embodiments, the third surface 343 may include additional device features or layers.

[0040] Gate 341 includes an intermediate layer 345 and a gate element 340. In some embodiments, gate 341 is a high-dielectric-constant metal gate. The intermediate layer 345 is disposed on a first surface 342 and a second surface 344, between the NMOS source / drain region 320 and the PMOS source / drain region 321. The intermediate layer 345 may include a polysilicon material and / or an insulating material. In some embodiments, the insulating material is silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium aluminate, hafnium silicate nitride, or a combination thereof. Gate element 340 is formed on the intermediate layer 345 disposed on a substrate 301 and includes an offset layer deposited on the side of the gate (not shown). Gate element 340 may include polysilicon, silicate material, or metallic material. Exemplary materials found within gate element 340 include tantalum, tungsten, tungsten nitride, tantalum nitride, or titanium nitride. Metals (such as aluminum) may also be included in the gate element in combination with other materials. Gate element 340 may include a gate metal layer, a gate material layer, and a metallic material. The gate metal layer includes any one of tantalum, tungsten, tungsten nitride, tantalum nitride, or titanium nitride. The gate material layer may be a polycrystalline silicon layer. The metallic material may be a highly conductive metal, such as aluminum, copper, tungsten, silver, gold, and other similar materials. The metallic material may also be an alloy of any of the described highly conductive metals. The gate 341 shown herein is not intended to be limiting and may include a variety of additional materials and structures. In some embodiments, at least a portion of the gate 341 is formed at a temperature of about 800°C to about 1000°C (e.g., about 850°C to about 950°C). After the gate 341 is formed, an etching process may be performed to remove the dielectric layer over the NMOS source / drain region 320 and the PMOS source / drain region 321. At least one heat treatment may be performed during the formation of the gate 341.

[0041] The NMOS source / drain region 310 and the PMOS source / drain region 321 are formed within an epitaxial deposition chamber (such as deposition chamber 200a in FIG. 2A). The NMOS source / drain region 320 may be formed within a second chamber 104. The PMOS source / drain region 321 may be formed within a third chamber 106. The NMOS source / drain region 320 is doped with phosphorus and / or arsenic, such that the NMOS source / drain region 320 includes silicon and phosphorus and / or arsenic dopants. The PMOS source / drain region 321 is doped with germanium, tin and / or boron, such that the PMOS source / drain region 321 includes silicon and germanium and / or boron dopants. Therefore, the NMOS source / drain region 320 may include a Si:P or Si:As composition, while the PMOS source / drain region 321 may include a SiGeB, SiGe, GeB, or GeSnB composition. The NMOS source / drain region 320 and the PMOS source / drain region 321 have a crystal structure.

[0042] Figure 3B shows a MOSFET device 300a after the deposition of a seed layer 325. The seed layer 325 deposition is performed during a first operation 502 of the formation method 500 shown in Figure 5. During the first operation 502, the surface of the substrate 301 is exposed to a process gas. The process gas may include silicon-containing gases and germanium-containing gases. Exemplary process gases include one or a combination of dichlorosilane, methane, ethane, trichlorosilane, germane, digermane, or germanium tetrachloride. The process gas is introduced into the process space of the deposition chamber (e.g., the process space 236 of deposition chamber 200a) through a process gas inlet (such as process gas inlet 214). The process gas is introduced by one or more inlets. In the embodiments described herein, multiple process gas inlets are used to introduce the process gas and allow it to flow parallel to the top surface of the substrate 301. As the process gas flows into the chamber, silicon and germanium of the process gas are deposited to form a seed layer 325 (alternatively described as a thin layer) over both the NMOS source / drain region 320 and the PMOS source / drain region 321. During the first operation 502 of depositing the seed layer 325, the process chamber (such as a first epitaxial deposition chamber (e.g., deposition chamber 200a)) is maintained at a temperature below about 550°C (e.g., below about 500°C, such as below about 450°C). In some embodiments, the seed layer 325 is deposited at a temperature between about 550°C and about 400°C (e.g., between about 500°C and about 400°C). During the deposition of the seed layer 325, the process chamber is also maintained at a pressure of about 5 Torr to about 300 Torr (e.g., about 10 Torr to about 100 Torr).

[0043] In the first operation 502, the seed layer 325 is formed to a thickness of about 1 nm to about 6 nm (e.g., about 2 nm to about 5 nm, such as about 2.5 nm to about 5 nm). In some embodiments, the seed layer 325 is about half the thickness of the silica layer 330 formed in the second operation 504, such as less than about 60% of the thickness of the silica layer 330. The seed layer 325 is deposited using an epitaxial deposition process and is therefore selectively deposited on both the NMOS source / drain region 320 and the PMOS source / drain region 321. The seed layer 325 comprises about 5% to 75% germanium, such as about 10% to about 60% germanium, such as about 10% to about 50% germanium, such as about 10% to about 40% germanium, such as about 10% to about 30% germanium. It has been determined that the germanium concentration within the silicon-germanium (SiGe) seed layer allows for silicide formation in both the PMOS source / drain region 321 and the NMOS source / drain region 320. The germanium concentration is selected to improve silicide film morphology / uniformity while reducing germanium agglomeration. The germanium concentration is also selected to meet the contact resistance reduction specification at the interface between the NMOS and PMOS devices. It has been found that a germanium concentration of approximately 10% to approximately 30% can be used as a seed layer to maintain silicide morphology and uniformity at the interface when deposited on the PMOS source / drain region 321. Furthermore, it has been found that at germanium concentrations of approximately 10% to approximately 30%, the seed layer 325 enhances silicide nucleation on the NMOS source / drain region 321. The seed layer 325 in Figures 3B and 5 is an undoped seed layer and is typically composed of silicon and germanium or substantially composed of silicon and germanium.

[0044] After the seed layer 325 is deposited during the first operation 502, the flow of the processing gas can be stopped and the processing space can be purged. The processing space can be pumped to a delivery pressure, and the substrate 301 can be removed from the first epitaxial deposition chamber (such as deposition chamber 200a). The substrate 301 can be moved to a second epitaxial deposition chamber or a CVD processing chamber for the second operation 504. In other embodiments, the substrate 301 can remain in the first epitaxial deposition chamber, and the second operation 504 is performed in the first epitaxial deposition chamber.

[0045] During the second operation 504, substrate 301 is exposed to a silica-forming gas. The silica-forming gas may include a combination of silicon, germanium, and metallic materials. The metallic material may be any of titanium, nickel, cobalt, platinum, nickel, or alloys thereof. The silica-forming gas is introduced at a temperature below about 500°C (e.g., below about 450°C, such as below about 400°C). As described herein, the second operation is performed in one of a first epitaxial deposition chamber (e.g., deposition chamber 200a), a second epitaxial deposition chamber (e.g., deposition chamber 200a), or a CVD processing chamber (e.g., deposition chamber 200b). During exposure to the silica-forming gas, the processing chamber is also maintained at a pressure of about 3 Torr to about 300 Torr (e.g., about 5 Torr to about 100 Torr).

[0046] When the silica-forming gas flows into the processing chamber, the silicon, germanium, and metallic materials in the silica-forming gas react to form metallic germanium silicate on top of the source / drain regions. As described in the second operation 504, a silicate layer 330 is formed over each of the NMOS source / drain regions 320 and PMOS source / drain regions 321. The silicate layer 330 is shown in FIG. 3C and completely consumes the seed layer 325. The NMOS source / drain regions 320 and PMOS source / drain regions 321 may react and consume slightly during silanization after the seed layer 325 has been completely reacted and consumed due to the formation of the silicate layer 330. The seed layer 325 is completely consumed because any residual seed layer would cause an increase in the transistor's resistance. A silicon layer 330 is selectively deposited simultaneously onto each of the NMOS source / drain regions 320 and the PMOS source / drain regions 321. Using a seed layer 325 with similar composition and physical properties on both the NMOS source / drain regions 320 and the PMOS source / drain regions 321 enables the simultaneous deposition of the silicon layer 330. The seed layer 325 improves the selectivity for both the NMOS source / drain regions 320 and the PMOS source / drain regions when under the same processing conditions and using the same precursor. The simultaneous deposition of the silicon layer 330 contributes to achieving similar silicon thickness and characteristics. Furthermore, the simultaneous deposition of the silicon layer 330 reduces the number of processing steps required to form the MOSFET device 300a.

[0047] The silica layer 330 is formed to a thickness of about 4 nm to about 12 nm (e.g., about 5 nm to about 10 nm, such as about 6 nm to about 9 nm). In some embodiments, the silica layer 330 is about twice the thickness of the seed layer 325 formed in the first operation 502, such as greater than about 200% of the thickness of the seed layer 325. The silica layer 330 is deposited using an epitaxial deposition process or a CVD process, and is therefore selectively deposited over the seed layer 325 above both the NMOS source / drain region 320 and the PMOS source / drain region 321. In some embodiments, the silica layer 330 is formed using a plasma CVD process, but the plasma CVD process is non-selective.

[0048] Depositing the silica layer 330 in an epitaxial deposition chamber is advantageous because the silica layer 330 is highly selective during deposition. The silica layer 330 is formed only over the NMOS source / drain regions 320 and PMOS source / drain regions 321 through reaction with the seed layer 325, and not over other exposed portions of the substrate 301 or the gate 341. Using an epitaxial deposition chamber further allows the same chamber to be used for both seed layer 325 deposition and silica layer 330 formation. The contact resistance at the interface between the silica layer and the seed layer 325 can be tuned by dopant concentration, layer thickness, and germanium concentration. It is also shown that silica deposition consumes a small portion of the substrate 301 after the seed layer is completely consumed, and allows for conformal growth of the silica layer 330 over the source / drain regions 320, 321. Although thermal CVD selectively deposits silica layers 330 and exhibits good nucleation and film morphology, plasma CVD processes have been shown to be non-selective because plasma forms highly reactive metal sources.

[0049] The silicate layer 330 comprises approximately 35% to approximately 65% ​​metallic material, such as approximately 40% to approximately 60% metallic material, such as approximately 45% to approximately 55% metallic material, or such as approximately 50% metallic material. The silicate layer 330 may further comprise approximately 5% to approximately 65% ​​germanium, such as approximately 10% to approximately 45% germanium, or such as approximately 25% to approximately 40% germanium. The silicate layer 330 may further comprise approximately 5% to approximately 65% ​​silicon, such as approximately 10% to approximately 45% silicon, or such as approximately 25% to approximately 40% silicon. The silicate layer 330 of Figures 3C and 5 may be a titanium-containing layer, such as a Ti-Si-Ge layer. Additional silicate layer 330 materials may include NiSi, TiSi, TiSi2, NiGe, TiGe, or TiGe2. In the embodiments of the above-described silicate layer, the ratio of metal to silicon or metal to germanium is from about 0.2:1 to about 2:1, such as from about 0.5:1 to about 1.5:1, such as from about 0.5:1 to about 1:1.

[0050] In the third operation 506, a nitride layer 332 is deposited on the silicate layer 330. In some embodiments, the nitride layer 332 is formed using an N₂ precursor, an H₂ precursor, and / or an NH₃ precursor. In some embodiments, the N₂ precursor, H₂ precursor, and / or NH₃ precursor may be converted into plasma during the deposition of the nitride layer 332. The nitride layer 332 is a metal nitride layer because some of the metallic material from the silicate layer 330 is consumed by the nitride layer 331 during the formation of the nitride layer 332. In some embodiments, the nitride layer 332 is a titanium nitride (TiN) layer. The nitride layer 332 is deposited to protect the top of the silicate layer 330 from oxidation when exposed to the atmosphere. The nitride layer 332 also facilitates metal wetting on the dielectric sidewalls during contact metal filling as described herein. The nitride layer 332 may have a thickness of about 1 nm to 6 nm (e.g., about 2 nm to 5 nm). In one embodiment, the nitride layer 332 is deposited in a plasma CVD processing chamber (e.g., deposition chamber 200b of FIG. 2B). Thus, if the substrate 301 is disposed in a first epitaxial deposition chamber or a second epitaxial deposition chamber, the substrate 301 is moved to the first CVD processing chamber or a direct plasma nitriding (DPN) chamber for deposition of the nitride layer 332. If the substrate 301 is already in a CVD processing chamber, the nitride layer 332 may be formed in the same CVD processing chamber or a different CVD processing chamber (e.g., a second CVD processing chamber).

[0051] After depositing silicon layer 330 and nitride layer 332, a metal contact layer 335 is deposited over each of the PMOS source / drain region 321 and NMOS source / drain region 320 during a fourth operation 508. The contact metal layer 335 is shown in Figure 3D. The metal contact layer 335 is deposited within the CVD processing chamber and includes a deposited TiN layer for wetting the nitride layer 332 over the PMOS source / drain region 321 and NMOS source / drain region 320. The metal contact layer 335 further includes a tungsten (W), cobalt (Co), or copper (Cu) filler. The metal contact layer 335 is shown herein as selectively deposited over the PMOS source / drain region 321 and NMOS source / drain region 320, but in some embodiments it is additionally deposited over other portions of the substrate 301.

[0052] Figures 4A to 4E are partial schematic diagrams of the formation of the MOSFET element 300b according to method 600 shown in Figure 6. The MOSFET element 300b in Figure 4A is similar to the MOSFET element 300a in Figure 3A.

[0053] Referring to Figures 4B and 6, in the first operation 602, a first crystalline layer 327 is deposited over the PMOS source / drain region 321. Before depositing the first crystalline layer 327 over the PMOS source / drain region 321, a dielectric coating may be formed over the NMOS source / drain region 320 to protect the NMOS source / drain region 320. After the NMOS source / drain region 320 is protected by the dielectric layer, during the first operation 602, the surface of the substrate 301 is exposed to a first processing gas within the first epitaxial deposition chamber. The first processing gas may include a silicon-containing gas, a germanium-containing gas, and a first dopant. Examples of silicon-containing gases, germanium-containing gases, and first dopants include dichlorosilane, methane, ethane, trichlorosilane, germanane, digerane, germanium tetrachloride, diborane, boron trichloride, phosphine, phosphorus trichloride, arsine, tert-butylarsine (TBA), or arsenic trichloride. The first process gas is introduced into the process space of the first epitaxial deposition chamber (e.g., process space 236 of deposition chamber 200a) through a process gas inlet (such as process gas inlet 214). The first process gas is introduced by one or more inlets. In the embodiments described herein, multiple process gas inlets are used to introduce the first process gas and allow it to flow parallel to the top surface of substrate 301. As the first process gas flows into the first epitaxial deposition chamber, silicon, germanium, and dopants of the first process gas are deposited to form a first crystalline layer 327 (alternatively described as a first thin layer) over the PMOS source / drain region 321. During the first operation 602, the processing chamber is maintained at a temperature below about 550°C (e.g., below about 500°C, such as below about 450°C). In some embodiments, the first crystal layer 327 is deposited at a temperature between about 550°C and about 400°C (e.g., between about 500°C and about 400°C). During the deposition of the first crystal layer 327, the processing chamber is also maintained at a pressure of about 5 Torr to about 300 Torr (e.g., about 10 Torr to about 100 Torr).

[0054] The first crystal layer 327 is formed to a thickness of about 1 nm to about 6 nm (e.g., about 2 nm to about 5 nm, such as about 2.5 nm to about 5 nm). In some embodiments, the first crystal layer 327 is about half the thickness of the silica layer 331b formed in the third operation 606, such as less than about 40% of the thickness of the silica layer 331b. The first crystal layer 327 is deposited using an epitaxial deposition process and is therefore selectively deposited on the PMOS source / drain region 321. The first crystal layer 327 comprises about 5% to 75% germanium, such as about 10% to about 60% germanium, such as about 10% to about 50% germanium, such as about 10% to about 40% germanium, such as about 10% to about 30% germanium. The germanium concentration within the first silicon-germanium (SiGe) seed layer has been determined to allow for the silanization of both the PMOS source / drain region 321 and the NMOS source / drain region 320. The germanium concentration is selected to improve the silicide film morphology / uniformity while reducing germanium agglomeration. The germanium concentration is also selected to meet the contact resistance reduction specification at the interface between the NMOS and PMOS devices. The first seed layer 327 in Figure 4B is the first doped seed layer and includes silicon, germanium, and a first dopant. The first dopant may be a boron dopant, such that the first seed layer 327 includes a silicon-germanium-boron layer (SiGeB). The first seed layer 327 includes a dopant concentration of approximately 5 × 10¹⁹ atoms / cm³ to approximately 1 × 10²² atoms / cm³ (such as approximately 1 × 10²⁰ atoms / cm³ to approximately 1 × 10²¹ atoms / cm³).

[0055] After the first crystal layer 327 is deposited during the first operation 602, the flow of the process gas can be stopped and the process space can be purged. The process space can be pumped to a delivery pressure, and the substrate 301 can be removed from the first epitaxial deposition chamber (such as deposition chamber 200a). Then, before depositing a similar protective dielectric layer (not shown) over the PMOS source / drain region 321 in the process chamber, the protective dielectric layer (not shown) can be etched away over the NMOS source / drain region 320. The substrate 301 can then be moved to the second epitaxial deposition chamber for the second operation 604.

[0056] In the second operation 604, a second crystalline layer 326 is deposited over the NMOS source / drain region 320. During the second operation 604, the surface of the substrate 301 is exposed to a second process gas within the second epitaxial deposition chamber. The second process gas may include a silicon-containing gas, a germanium-containing gas, and a second dopant. Some examples of silicon-containing gases, germanium-containing gases, and second dopants include one or a combination of dichlorosilane, methane, ethane, trichlorosilane, germanane, digerane, or germanium tetrachloride. The second process gas is introduced into the processing space of the second epitaxial deposition chamber (e.g., processing space 236 of deposition chamber 200a) through a process gas inlet (such as process gas inlet 214). The second process gas is introduced by one or more inlets. In the embodiments described herein, multiple process gas inlets are used to introduce the second process gas and allow it to flow parallel to the top surface of the substrate 301. As the second processing gas flows into the second epitaxial deposition chamber, silicon, germanium, and a second dopant of the second processing gas are deposited as described in the second operation 604 to form a second crystal layer 326 (alternatively described as a second thin layer over the NMOS source / drain region 320). During the second operation 604, the processing chamber is maintained at a temperature below about 550°C (e.g., below about 500°C, such as below about 450°C). In some embodiments, the second crystal layer 326 is deposited at a temperature between about 550°C and about 400°C (e.g., between about 500°C and about 400°C). During the deposition of the second crystal layer 326, the second processing chamber is also maintained at a pressure of about 5 Torr to about 300 Torr (e.g., about 10 Torr to about 100 Torr).

[0057] The second crystal layer 326 is formed with a thickness of about 1 nm to about 6 nm (e.g., about 2 nm to about 5 nm, such as about 2.5 nm to about 5 nm). In some embodiments, the second crystal layer 326 is about half the thickness of the silicate layer 331a formed in the third operation 606, such as less than about 40% of the thickness of the silicate layer 331a. The second crystal layer 326 is deposited using an epitaxial deposition process and is therefore selectively deposited on the NMOS source / drain region 320. The second crystal layer 326 comprises about 5% to 75% germanium, such as about 10% to about 60% germanium, such as about 10% to about 50% germanium, such as about 10% to about 40% germanium, such as about 10% to about 30% germanium. The second crystal layer 326 of Figures 4C and 6 is a second doped seed layer and comprises silicon, germanium, and a second dopant. The second dopant can be a phosphorus dopant or an arsenic dopant, such that the second crystal layer includes a silicon-germanium-phosphorus layer (SiGeP). The second crystal layer 326 includes a dopant concentration of about 5 × 10¹⁹ atoms / cm³ to about 1 × 10²² atoms / cm³ (such as about 1 × 10²⁰ atoms / cm³ to about 1 × 10²¹ atoms / cm³).

[0058] The first crystal layer 327 and the second crystal layer 326 can be deposited separately to allow the seed layer to be doped with boron, phosphorus, carbon, germanium, gallium, tin, arsenic, or other dopants. Doping of the NMOS source / drain regions 320 and PMOS source / drain regions 321 can reduce resistance-capacitance requirements and improve contact resistance between the deposited layers. The germanium concentration between the first crystal layer and the second crystal layer 326 is comparable to ensure simultaneous silicide formation in both the NMOS and PMOS source / drain regions. Compared to the dominant role of Ge atoms in the seed layer, dopant atoms (such as phosphorus, arsenic, and boron) play a smaller role in silicide nucleation and formation.

[0059] After depositing the second crystalline layer 326, the protective dielectric coating on the PMOS source / drain region 321 is removed by etching, and both the PMOS source / drain region 321 and the NMOS source / drain region 320 are exposed, as shown in Figure 4C.

[0060] In some embodiments, the deposition order of the first crystalline layer 327 and the second crystalline layer 326 is swapped, such that the second crystalline layer 326 is deposited on the NMOS source / drain region 320 before the first crystalline layer 327 is deposited on the PMOS source / drain region 321. Therefore, the first operation 602 and the second operation 604 are swapped, such that the first operation 602 is performed after the second operation 604, as described above. This also means that the application and removal of the protective dielectric coating over both the NMOS source / drain region 320 and the PMOS source / drain region 321 will be performed in reverse order.

[0061] During the third operation 606, the substrate 301 is exposed to a silica-forming gas. The silica-forming gas may include a combination of silicon, germanium, and metallic materials. The third operation 606 is similar to the second operation 504 of the formation method 500 of FIG. 5. The metallic material may be any of titanium, nickel, cobalt, platinum, or alloys thereof. The silica-forming gas is introduced at a temperature below about 500°C (e.g., below about 450°C, such as below about 400°C). The third operation 606 as described herein is performed in one of a first epitaxial deposition chamber, a second epitaxial deposition chamber, or a CVD processing chamber. During exposure to the silica-forming gas, the processing chamber is also maintained at a pressure of about 3 Torr to about 300 Torr (e.g., about 5 Torr to about 100 Torr).

[0062] When the silica-forming gas flows into the processing chamber, silicon, germanium, and metallic materials of the silica-forming gas are deposited. As shown in Figure 4D, after each of the first crystal layer 327 and the second crystal layer 326 has completely reacted and been consumed, silica layers 331a and 331b are formed over each of the NMOS source / drain region 320 and the PMOS source / drain region 321. Simultaneously, each of the NMOS silica layer 331a formed over the NMOS source / drain region 320 and the PMOS silica layer 331b formed over the PMOS source / drain region 321 is formed. During formation, silica layers 331a and 331b completely consume each of the first crystal layer 327 and the second crystal layer 326. The silica layer 331b deposited over the PMOS source / drain region 321 consumes the first crystal layer 327, and the silica layer 331a deposited over the NMOS source / drain region 320 consumes the second crystal layer 326. The PMOS source / drain region 321 and the NMOS source / drain region 320 can be partially reacted and consumed during silanization after the first crystal layer 327 and the second crystal layer 326 have been completely reacted and consumed by the metal source. The silica layers 331a and 331b formed after formation are doped differently depending on the composition of the seed crystal layer they absorb.

[0063] As shown in Figure 4D, silicon layers 331b and 331a completely consume the first crystalline layer 327 and the second crystalline layer 326, respectively. Silicon layers 331a and 331b are simultaneously and selectively deposited on each of the NMOS source / drain regions 320 and PMOS source / drain regions 321. The simultaneous deposition of silicon layers 331a and 331b helps to obtain similar silicon thickness and properties over both the NMOS source / drain regions 320 and PMOS source / drain regions 321. The simultaneous deposition of silicon layers 331a and 331b further reduces the number of processing steps required to form the MOSFET device 300b.

[0064] Silicone layers 331a and 331b are formed to a thickness of about 4 nm to about 12 nm (e.g., about 5 nm to about 10 nm, such as about 6 nm to about 9 nm). In some embodiments, silicone layers 331a and 331b are about twice the thickness of the seed layers 326 and 327 formed in the first operation 602 and the second operation 604, such as being more than about 200% thicker than the seed layers 326 and 327. Silicone layers 331a and 331b are deposited using epitaxial deposition or CVD processes, and are therefore selectively deposited over both the NMOS source / drain region 320 and the PMOS source / drain region 321 of the seed layers 326 and 327. In some embodiments, silicone layers 331a and 331b are formed using a plasma CVD process, but the plasma CVD process is non-selective. Silicide layers 331a and 331b comprise a composition of approximately 35% to approximately 65% ​​metallic material, such as approximately 40% to approximately 60% metallic material, such as approximately 45% to approximately 55% metallic material, and such as approximately 50% metallic material. Silicide layers 331a and 331b may also comprise approximately 5% to 65% germanium, such as approximately 25% to approximately 45% germanium, and such as approximately 25% to approximately 40% germanium. Silicide layers 331a and 331b may also comprise approximately 5% to 65% silicon, such as approximately 25% to approximately 45% silicon, and such as approximately 25% to approximately 40% silicon. The silicate layers 331a and 331b in Figures 4D and 6 are titanium-containing layers, such as Ti-Si-Ge layers.

[0065] The fourth operation 608 of the formation method 600 in Figure 6 is similar to the third operation 506 of the formation method 500 in Figure 5. As shown in Figure 4D, the fourth operation 608 similarly forms a nitride layer 332 on top of the silicon layers 331a and 331b. The fifth operation 610 of the formation method 600 in Figure 6 is similar to the fourth operation 508 of the formation method 500 in Figure 5. The fifth operation 610 includes forming a metal contact layer 335 over each of the PMOS source / drain region 321 and the NMOS source / drain region 320, as shown in Figure 4E.

[0066] Figure 9 illustrates a method for forming a MOSFET element 300c as shown in Figures 7A to 7E, according to another embodiment of this disclosure. The MOSFET element 300c of Figure 7A is shown after a dummy gate 346, an NMOS source / drain region 320, and a PMOS source / drain region 321 have been formed in a substrate 301. The dummy gate 346, as described herein, is used to define the source / drain regions of the NMOS and PMOS transistors. In a later processing operation, the dummy gate 346 is removed and replaced with a gate 341. The NMOS source / drain region 320 and the PMOS source / drain region 321 are similar to those described with respect to Figures 3A to 3D.

[0067] A dummy gate 346 is disposed on a first surface 342 of substrate 301, between the NMOS source / drain regions 320. Another dummy gate 346 is disposed on a second surface 344 of substrate 301, between the PMOS source / drain regions 321. The dummy gate 346 comprises a silicon-based material. The silicon-based material of the dummy gate 346 is disposed on the first surface 342 and the second surface 344, between the NMOS source / drain regions 320 and the PMOS source / drain regions 321. The silicon-based material may include polycrystalline silicon, amorphous silicon, microcrystalline silicon, or combinations thereof.

[0068] The first operation 902 of the MOSFET formation method 900 is similar to the first operation 502 of the formation method 500 described with respect to Figures 3B and 5. During the first operation 902, a seed layer 325 is formed on the NMOS source / drain region 320 and the PMOS source / drain region 321. The seed layer 325 has been described in more detail above with reference to Figures 3B and 5. The temperature of the deposition chamber during the formation of the seed layer 325 is below 800°C, such as below 750°C, such as below 700°C, such as about 500°C to about 700°C. Since the dummy gate 346 does not limit the maximum deposition temperature to a temperature below 500°C, an elevated temperature can be utilized during the first 902. During the operation in which the gate 341 has been formed on the substrate 301 before the deposition of the seed layer 325, the deposition temperature is lower to prevent damage to the gate 346.

[0069] After the seed layer 325 is formed during the first operation 902, the substrate 301 is removed from the epitaxial deposition chamber and placed into the etching chamber. In some embodiments, the etching chamber may be a cleaning chamber. During the second operation 904, the dummy gate 346 is etched away in the etching chamber. The dummy gate 346 is etched away to expose the first surface 342 and the second surface 344. The dummy gate 346 is removed and replaced with a gate 341 comprising an intermediate layer 345 and a gate element 340, as shown in FIG7C. The gate 341 is formed in the second operation 904 using multiple processing steps, which are described in detail with reference to FIG3A.

[0070] After the gate 341 is formed during the second operation 904, the substrate 301 is transferred to one of the first epitaxial deposition chamber, the second epitaxial deposition chamber, or the CVD chamber. After the substrate 301 is transferred to the appropriate deposition chamber, a third operation 906 is performed, in which the substrate is exposed to a silicate forming gas. The silicate forming gas is similar to that described in the second operation 504 of the formation method 500 with respect to Figures 3C and 5. After the silicate forming gas is introduced, a silicate layer 330 is formed over each of the NMOS source / drain regions 320 and the PMOS source / drain regions 321 during the third operation 906. The silicate layer 330 is shown in Figure 7D and completely consumes the seed layer 325. The silicate layer 330 is simultaneously and selectively deposited on each of the NMOS source / drain regions 320 and the PMOS source / drain regions 321.

[0071] After the silicon layer 330 is formed during the third operation 906, the substrate is exposed to a nitride forming gas, and a nitride layer 332 is formed during the fourth operation 908. The fourth operation 908 is similar to the nitriding process described in the third operation 506 of the formation method 500 of FIG. 5.

[0072] After the formation of nitride layer 332, a metal contact layer 335 is deposited over each of the PMOS source / drain regions 321 and NMOS source / drain regions 320 during the fifth operation 910. The contact metal layer 335 is shown in Figure 7E. The deposition of the contact metal layer 335 is similar to that described with respect to the fourth operation 508 of Figures 3D and 5.

[0073] Figures 8A to 8F are partial schematic diagrams of the formation of MOSFET element 300d according to the formation method 1000 of Figure 10. The MOSFET element 300d in Figure 8A is similar to the MOSFET element 300c in Figure 7A.

[0074] Figure 8B shows the MOSFET device 300d after the deposition of the first crystal layer 327. The deposition of the first crystal layer 327 is performed during the first operation 1002 of the formation method 1000 shown in Figure 10. During the first operation 1002, the surface of the substrate 301 is exposed to a first process gas in the first epitaxial deposition chamber. The deposition of the first crystal layer 327 is similar to that described in the first operation 602 of the formation method 600 of Figure 6, as shown in Figure 4B. In some embodiments where the first crystal layer 327 is deposited as described herein, the temperature during deposition is higher than the temperature described in the formation method 600 of Figure 6. The temperature of the deposition chamber during the formation of the first crystal layer 327 is below 800°C, such as below 750°C, such as below 700°C, such as about 500°C to about 700°C. Since the dummy gate 346 does not limit the maximum deposition temperature to a temperature below 500°C, the increased temperature is utilized. During the operation in which the gate 341 has been formed on the substrate 301 before the deposition of the first crystal layer 327, the deposition temperature is low to prevent the gate 346 from being damaged.

[0075] After the deposition of the first crystal layer 327, the substrate 301 is transferred to a second epitaxial deposition chamber, and a second crystal layer 326 is deposited by introducing a second process gas into the second epitaxial deposition chamber during a second operation 1004. The second crystal layer 326 is formed after and during the introduction of the second process gas, as shown in FIG8C. The second crystal layer 326 is similar to that described herein with respect to the second operation 604 of FIGS. 4B and 6. Similar to the formation of the first crystal layer 327 during the first operation 1002, the second operation 1004 is performed at a temperature below 800°C, such as below 750°C, such as below 700°C, such as about 500°C to about 700°C.

[0076] As previously described with respect to the first operation 602 and the second operation 604 of FIG6, the deposition order of the first crystalline layer 327 and the second crystalline layer 326 can also be interchanged, such that the second crystalline layer 326 is deposited on the NMOS source / drain region 320 before the first crystalline layer 327 is deposited on the PMOS source / drain region 321. Therefore, the first operation 1002 and the second operation 1004 are interchanged, such that the first operation 1002 is performed after the second operation 1004, as described above. This also means that the application and removal of the protective dielectric coating over both the NMOS source / drain region 320 and the PMOS source / drain region 321 will be performed in reverse order.

[0077] After depositing the second crystalline layer 326, a third operation 1006 is performed. During the third operation 1006, the substrate 301 is removed from the second epitaxial deposition chamber and transferred to the etching chamber. While in the etching chamber, the dummy gate 346 is removed. Then, the dummy gate 346 is replaced with a gate 341 comprising an intermediate layer 345 and a gate element 340, as shown in FIG8D. The removal of the dummy gate 346 and its replacement with the gate 341 are described in more detail with respect to the second operation 904 of FIG7C and FIG9.

[0078] After the gate 341 is formed during the third operation 1006, the substrate 301 is transferred to one of the first epitaxial deposition chamber, the second epitaxial deposition chamber, or the CVD chamber. After the substrate 301 is transferred to the appropriate deposition chamber, a fourth operation 1008 is performed to expose the substrate to a silicate forming gas. The silicate forming gas is similar to that described in the second operation 504 of the formation method 500 of Figures 3C and 5. After the silicate forming gas is introduced, silicate layers 331a and 331b are formed over the NMOS source / drain regions 320 and the PMOS source / drain regions 321. During the fourth operation 1008, an NMOS silicate layer 331a is formed over each of the NMOS source / drain regions 320, and a PMOS silicate layer 331b is formed over each of the PMOS source / drain regions 321. Silicone layers 331a and 331b are shown in Figure 8E and completely consume seed layers 326 and 327. Silicone layers 331a and 331b are simultaneously and selectively deposited on each of the NMOS source / drain regions 320 and PMOS source / drain regions 321.

[0079] After silicon layers 331a and 331b are formed during the fourth operation 1008, the substrate is exposed to a nitride forming gas, and a nitride layer 332 is formed during the fifth operation 1010, as shown in FIG8E. The fifth operation 1010 is similar to the nitriding process described in the third operation 506 of the formation method 500 of FIG5.

[0080] After the formation of nitride layer 332, during the sixth operation 1012, a metal contact layer 335 is deposited over each of the PMOS source / drain regions 321 and NMOS source / drain regions 320. The contact metal layer 335 is shown in Figure 8F. The deposition of the contact metal layer 335 is similar to that described with respect to the fourth operation 508 of Figures 3D and 5.

[0081] The embodiments described herein generally relate to the formation of MOSFET devices. MOSFET devices include NMOS devices and PMOS devices. Historically, it has been difficult to grow thick silica films with good morphology and uniformity over both the NMOS source / drain regions and the PMOS source / drain regions. This document describes a method for forming MOSFET devices in which a single silica formation step is performed and silica is deposited simultaneously over each of the NMOS and PMOS source / drain regions. Simultaneous deposition is achieved at least in part by forming a silicon-germanium seed layer. In some embodiments, the silicon-germanium seed layer may be formed as a first doped silicon-germanium seed layer over the PMOS source / drain region and a second doped silicon-germanium seed layer over the NMOS source / drain region. Dopants are used to reduce the contact resistance on the barrier between layers, but this increases the complexity of device formation.

[0082] Although the foregoing describes embodiments of the present disclosure, other and further embodiments of the present disclosure may be conceived without departing from the basic scope of the present disclosure, and the scope of the present disclosure is defined by the scope of the appended claims.

[0083] 100: System 102: First Chamber 104: Second Chamber 106: Third Chamber 108: Fourth Chamber 110: Fifth Chamber 112: Central Transmission Chamber 114: Loading chamber 116: Central Conveying Robot 118: Teleportation Space 120: Controller 200: Deposition chamber 202:Substrate 206: Substrate support 207: Lifting rod hole 208: Up to the Dome 210: Lower Dome 211: Substrate support 212: Flow Module 213: Axis 214: Processing gas inlet 216: Emission gas outlet 217: Emission outlet 218: Axis 220: Motion Components 222: Rotary actuator 224: Vertical Actuator 226: Tilting adjustment device 228: Lateral adjustment device 231: Processing gas sources 232: Lifting boom 234: Lifting rod stop 235: Memory 236: Processing space 237: Processing Space 241: Lighting 243: Lowering the Light 245: Lower Light Assembly 246: Flow guide 248: Lower Main Body 250: Top surface 251: Processing gas sources 252: Central Processing Unit 253: Sensor 254: Cover 256: Upper Main Body 257: Discharge Pump 258: Support Circuit 259: Discharge Pump 262: Purified gas source 263: Padding 264: Purified Gas Inlet 270: Sprayer Head 272: Kong 274: RF Power Source 280: Main body of the chamber 282: Chamber cover 301:Substrate 302: NMOS device 304: PMOS device 310: NMOS source / drain region 315:n-well region 320: NMOS source / drain region 321: PMOS source / drain region 325: Seed layer 326: Second crystal layer 327: First crystal layer 330: Silicone layer 331: Nitride layer 332: Nitride layer 335: Contact metal layer 340: Gate element 341: Gate 342: First Surface 343: Third Surface 344: Second Surface 345: Intermediate Layer 346: Dummy gate 500: Formation Method 502: First Operation 504: Second Operation 506: Third Operation 508: Fourth Operation 600: Formation Method 602: First Operation 604: Second Operation 606: Third Operation 608: Fourth Operation 610: Fifth Operation 900: Method 902: First Operation 904: Second Operation 906: Third Operation 908: Fourth Operation 910: Fifth Operation 1000: Formation Method 1002: First Operation 1004: Second Operation 1006: Third Operation 1008: Fourth Operation 1010: Fifth Operation 1012: Sixth Operation 200a: Deposition chamber 200b: Deposition chamber 300a: MOSFET device 300b: MOSFET device 300c: MOSFET device 300d: MOSFET device 331a: Silicon layer 331b: Silicon layer

[0084] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of processing a substrate, comprising the steps of: positioning a substrate having an n-channel metal-oxide-semiconductor (NMOS) element and a p-channel metal-oxide-semiconductor (PMOS) element disposed thereon in a processing chamber; selectively depositing a seed layer over an NMOS source / drain region of the NMOS element and a PMOS source / drain region of the PMOS element, the seed layer comprising both silicon and germanium; and after depositing the seed layer, simultaneously depositing a metal silicide over the NMOS source / drain region and the PMOS source / drain region.

2. The method of claim 1, wherein the crystal layer is a SiGe layer with a germanium molecule concentration of 5% to 75% of the crystal layer.

3. The method of claim 2, wherein the crystal layer is deposited from a precursor containing silicon and germanium.

4. The method of claim 1, wherein the crystal layer has a thickness of less than 5 nm.

5. The method of claim 1, wherein the crystalline layer is deposited during a thermal deposition process.

6. The method of claim 1, wherein the crystal layer is consumed during the deposition of the metal silicate.

7. The method of claim 6, wherein the metal silicate comprises silicon, germanium, and at least one of titanium, nickel, cobalt, or platinum.

8. The method of claim 1, wherein a contact metal layer is deposited on the metal silicate after the deposition of the metal silicate.

9. A method of processing a substrate, comprising the steps of: positioning a substrate having an n-channel metal-oxide-semiconductor (NMOS) element and a p-channel metal-oxide-semiconductor (PMOS) element disposed thereon in a first processing chamber; selectively depositing a first crystalline layer over an NMOS source / drain region of the NMOS element in the first processing chamber, the first crystalline layer comprising both silicon and germanium; selectively depositing a second crystalline layer over a PMOS source / drain region of the PMOS element, the second crystalline layer comprising both silicon and germanium; and after depositing the first crystalline layer and the second crystalline layer, simultaneously depositing a metal silicate over the NMOS source / drain region and the PMOS source region, the first crystalline layer and the second crystalline layer being consumed during the deposition of the metal silicate.

10. The method of claim 9, wherein selective deposition of the second crystalline layer is performed in a second processing chamber.

11. The method of claim 10, wherein both the first crystal layer and the second crystal layer comprise silicon, germanium, and one or more dopants.

12. The method of claim 11, wherein the one or more dopants include boron, phosphorus, carbon, gallium, arsenic or tin.

13. The method of claim 12, wherein the first crystalline layer further comprises phosphorus, and the second crystalline layer further comprises boron.

14. The method of claim 9, further comprising forming one or more gate structures on the substrate.

15. The method of claim 14, wherein the crystal layer is deposited at a temperature below 500°C, and the one or more gate structures are formed prior to the deposition of the crystal layer.

16. The method of claim 14, wherein the crystal layer is deposited at a temperature of 500°C to 750°C, and the one or more gate structures are formed after the deposition of the crystal layer and before the deposition of the metal silicate.

17. A system for substrate processing, comprising: A first processing chamber includes: a chamber body; a substrate support; a first chamber cover; one or more processing gas inlets; and one or more exhaust ports; and a controller configured to perform a method comprising the steps of: depositing a crystalline layer on a substrate disposed within the chamber body, wherein the deposition of the crystalline layer, comprising both silicon and germanium, is performed over an NMOS source region, an NMOS drain region, a PMOS source region, and a PMOS drain region within the substrate; and after the deposition of the crystalline layer, simultaneously depositing a metallide over the NMOS source region, the NMOS drain region, the PMOS source region, and the PMOS drain region.

18. The system as described in claim 17, further comprising: An upper dome is disposed between the base plate support and the chamber cover; a plurality of upper lights are disposed between the upper dome and the chamber cover; and a lower dome.

19. The system of claim 17, wherein during the deposition of the crystalline layer on the substrate, a first precursor flows out from the one or more process gas inlets, the first precursor comprising a germanium and silicon-containing precursor.

20. The system of claim 17, further comprising a second processing chamber, the second processing chamber including: A second chamber main body; a second base plate support; A first chamber cover; one or more second process gas inlets; and one or more second discharge ports.

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