Methods for filling a gap and related systems and devices

Abstract

A method and related system for filling a gap member included in a substrate are disclosed. The method includes the step of providing a substrate including one or more gap members into a reaction chamber. The one or more gap members include an upper portion and a lower portion, the upper portion including an upper surface and the lower portion including a lower surface. The method further includes the step of subjecting the substrate to a plasma treatment. Thus, the upper surface is suppressed while the lower surface is substantially unaffected. Next, the method includes the step of selectively depositing a silicon-containing material on the lower surface.

Description

Technical Field

[0001] This invention generally relates to methods and systems suitable for forming electronic devices. More specifically, this invention relates to methods and systems that can be used to deposit a material in gaps, trenches, and the like. Prior Technology

[0002] The scaling of semiconductor devices has led to significant improvements in the speed and density of integrated circuits. However, with the miniaturization of wiring pitch in large-scale integrated devices, the hole-free filling of high aspect ratio gaps or trenches (e.g., trenches with an aspect ratio of three or higher) is becoming increasingly difficult due to limitations of existing deposition processes. Therefore, there is a need for processes that can effectively fill high aspect ratio components (e.g., gaps such as trenches) on semiconductor substrates (e.g., logic and / or memory devices in the context). Processes that effectively fill high aspect ratio components using silicon-containing materials, such as silicon oxide, have specific requirements to withstand subsequent chemical mechanical polishing (CMP) steps and etching processes.

[0003] Any discussion presented in this section, including discussions of problems and solutions, is included in this invention solely for the purpose of providing background context. Such discussions should not be construed as an admission that any or all information was known at the time of completion of this invention or otherwise constituted prior art. Summary of the Invention

[0004] Various embodiments of the present invention relate to gap-filling methods, structures and apparatus formed using such methods, and equipment for performing such methods and / or for forming such structures and / or apparatuses. The ways in which the various embodiments of the present invention address the deficiencies of prior methods and systems are discussed in more detail below.

[0005] This invention discloses a method for filling a gap member. The method, in a given sequence, includes the step of positioning a substrate on a substrate support in a reaction chamber. The substrate includes one or more gap members. The one or more gap members include an upper portion and a lower portion, the upper portion including an upper surface and the lower portion including a lower surface. The method further includes a step of subjecting the substrate to a plasma pretreatment. The plasma treatment results in a suppression of the upper surface while simultaneously leaving the lower surface substantially unaffected. The method further includes a step of selectively depositing a silicon-containing material on the lower surface. The step of depositing the silicon-containing material on the lower surface includes a cyclic process. The cyclic deposition process includes a plurality of sub-cycles. A sub-cycle, in a given sequence, includes: a step of exposing the substrate to a silicon precursor comprising an amine group and two or more silicon atoms. The substrate is specifically exposed to the silicon precursor in a silicon precursor pulse to form a chemisorbed silicon precursor on the lower surface. A subcycle further includes a step of pulsed plasma treatment after exposing the substrate to a silicon precursor, thereby allowing one or more reactive species contained in the plasma to react with the chemisorbed silicon precursor on the lower surface.

[0006] In some embodiments, the amino group is selected from NH2, NHRi and NRiRii, and at least one of Ri and Rii is a C1 to C4 alkyl group.

[0007] In some embodiments, the silicon precursor comprises a compound selected from the list of monoaminosilanes, monosilaneamines, and monocyclic siloxanes.

[0008] In some embodiments, the silicon precursor comprises an alkylaminosilane.

[0009] In some embodiments, the silicon precursor comprises a compound selected from SiR1R3R4-SiR2R5R6, SiR1R3R4-SiR5R6-SiR2R7R8 and SiR1R3R4-SiR2R5-SiR6R7R8, wherein R1 and R2 are NR9R10, and R3, R4, R5, R6, R7, R8, R9 and R10 are independently selected from H and a C1 to C4 alkyl group.

[0010] In some embodiments, the silicon precursor comprises a compound selected from R1-SiH2-SiH3, R1-SiH2-SiH2-SiH2-R2 and R1-SiH2-SiHR2-SiH3, wherein R1 and R2 are independently selected from NH2, NHR9 and NR9R10, and R9 and R10 are independently selected from H and a C1 to C4 alkyl group.

[0011] In some embodiments, at least one of R3 and R4 is a C1 to C4 alkyl group.

[0012] In some embodiments, the silicon precursor comprises a silaneamine.

[0013] In some embodiments, the silicon precursor comprises a compound whose chemical structure can be represented according to the formula (1). (1) R11 and R12 are independently selected from H and C1 to C4 alkyl groups.

[0014] In some embodiments, the silicon precursor comprises a cyclosiloxane containing at least one amino group.

[0015] In some embodiments, the cyclosiloxane further comprises one or more C1 to C4 alkyl substituents.

[0016] In some embodiments, the amino group is selected from NH 2, NHR 13 and NR 13R 14, and R 13 and R 14 are independently selected from H and a C1 to C4 alkyl group.

[0017] In some embodiments, the plasma pretreatment includes subjecting the substrate to an inert gas plasma.

[0018] In some embodiments, the plasma pretreatment includes subjecting the substrate to a nitrogen-containing plasma.

[0019] In some embodiments, the plasma pretreatment includes subjecting the substrate to a first plasma treatment and subjecting the substrate to a second plasma treatment.

[0020] In some embodiments, the first plasma treatment includes generating a nitrogen-containing plasma in the reaction chamber.

[0021] In some embodiments, the nitrogen-containing plasma is a plasma containing N2.

[0022] In some embodiments, the second plasma treatment includes generating an inert gas plasma in the reaction chamber.

[0023] In some embodiments, the inert gas plasma is an argon plasma.

[0024] In some embodiments, the substrate system is maintained at a temperature of at least 100°C to at most 500°C.

[0025] In some embodiments, the reaction chamber is maintained at a pressure of at least 1 Torr and at most 20 Torr.

[0026] In some embodiments, the method includes performing a plurality of supercycles. A supercycle includes the step of subjecting the substrate to a plasma pretreatment and the step of selectively depositing a silicon-containing material onto the lower surface.

[0027] In some embodiments, the post-pulse plasma treatment of the silicon precursor includes generating an oxygen-containing plasma in the reaction chamber, and the silicon-containing material comprises silicon oxide.

[0028] In some embodiments, the oxygen-containing plasma is an O2-containing plasma.

[0029] In some embodiments, the step of selectively depositing a material onto the lower surface is performed at a growth rate of at least 0.1 Å per subcycle to at most 10 Å per subcycle.

[0030] This document further describes a semiconductor processing apparatus. It includes a reaction chamber, which in turn includes a substrate support for supporting a substrate. The substrate includes one or more gap members. The semiconductor processing apparatus further includes a heater configured to heat the substrate within the reaction chamber. The semiconductor processing apparatus further includes a first plasma gas source in fluid communication with the reaction chamber via a first plasma gas valve. The semiconductor processing apparatus further includes a second plasma gas source in fluid communication with the reaction chamber via a second plasma gas valve. The semiconductor processing apparatus further includes a third plasma gas source in fluid communication with the reaction chamber via a third plasma gas valve. The semiconductor processing apparatus further includes a plasma module comprising a radio frequency power source configured to generate a plasma within the reaction chamber. The semiconductor processing apparatus further includes one or more silicon precursor sources in fluid communication with the reaction chamber via one or more precursor valves. The semiconductor processing apparatus further includes a controller configured to cause the apparatus to perform a method as described herein.

[0031] These and other embodiments will become apparent to those skilled in the art from the following detailed description of certain embodiments with reference to the accompanying drawings. The invention is not limited to any of the specific embodiments disclosed. Simple Explanation of the Diagram

[0032] A more complete understanding of embodiments of the present invention can be obtained by considering the following illustrative drawings, with reference to the embodiments and the claims. [Figure 1] is a schematic diagram of a plasma-enhanced atomic layer deposition (PEALD) apparatus suitable for depositing a structure and / or performing a method according to at least one embodiment of the present invention. [Figure 2] shows a schematic diagram of a substrate (200) including a gap member (210). [Figure 3] shows a schematic diagram of an embodiment of the method as described herein. [Figure 4] shows a schematic diagram of one embodiment of the method as described herein. [Figure 5] shows a schematic diagram of a portion of an embodiment of a method for selectively depositing a silicon-containing material on the lower surface of a gap member included in a substrate. [Figure 6] shows a transmission electron microscope (TEM) image of silicon oxide deposited in a gap member by one embodiment of the method as described herein. All drawings follow the following numbering system: 1 – Substrate; 2 – Lower stage / conductive plate electrode; 3 – Reaction chamber; 4 – Upper electrode / conductive plate electrode; 5 – Transfer chamber; 6 – Exhaust line; 11 – Interior of the reaction chamber; 12 – Electrically grounded side; 13 – Circular tube; 14 – Separator plate; 16 – Interior of the transfer chamber; 7 – Exhaust line; 21 – Gas line; 22 – Gas line; 24 – Gas sealing line; 25 – Power supply; 200 – Substrate; 210 – Gap member; 211 – Upper portion; 212 – Lower portion; 311 – Step of positioning a substrate on a substrate support; 312 – Step of subjecting the substrate to a plasma treatment; 315 – Post-plasma rinsing; 316 – Step of depositing a material on a surface; 317 – Deposition Post-plasma rinsing; 318 – End of method; 319 – Repeat; 411 – Step of positioning a substrate on a substrate support; 412 – Step of subjecting the substrate to a first plasma treatment; 413 – Inter-plasma rinsing; 414 – Step of subjecting the substrate to a first plasma treatment; 415 – Post-plasma rinsing; 416 – Step of depositing a silicon-containing material on a surface; 417 – Post-deposition rinsing; 418 – End of method; 419 – Repeat; 511 – Start of method; 512 – Step of exposing a substrate to a silicon precursor; 513 – Rinsing; 514 – Step of exposing the substrate to a precursor followed by plasma treatment; 515 – Rinsing; 516 – End of method; 517 – Repeat. It will be understood that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be particularly enlarged relative to other elements to help improve the understanding of the illustrated embodiments of the invention. Implementation

[0033] The following descriptions of exemplary embodiments of methods, structures, apparatuses, and systems are exemplary and intended for illustrative purposes only; they are not intended to limit the scope of the invention or the claims. Furthermore, the listing of multiple embodiments having the stated components is not intended to exclude other embodiments having additional components or other embodiments incorporating different combinations of the stated components. For example, various embodiments are presented as exemplary embodiments and may be enumerated in the appendix. Unless otherwise noted, exemplary embodiments or components thereof may be combined or used separately.

[0034] In this invention, "gas" may include materials that are gases, vaporized solids, and / or vaporized liquids at normal temperature and pressure (NTP), and may consist of a single gas or a mixture of gases depending on the context. Gases other than process gases (i.e., gases not introduced through gas distribution assemblies, multi-port injection systems, other gas distribution devices, or the like) may be used, for example, to seal reaction spaces, and may include sealing gases such as rare gases. The terms "rare gas" and "inert gas" as used herein are used interchangeably. In some cases, the term "precursor" may refer to a compound that participates in a chemical reaction to generate another compound, and in a systemic sense, it refers to a compound that constitutes a thin film matrix or a major framework of a thin film, or is incorporated into a thin film as a component thereof; the term "reactant" may be used interchangeably with the term "precursor."

[0035] As used herein, the term "substrate" can refer to any one or more underlying materials that can be used to form or on which a device, a circuit, or a thin film is formed. A substrate may include a bulk material (such as silicon (e.g., single-crystal silicon)), other group IV materials (such as germanium) or other semiconductor materials (such as group II-VI or group III-V semiconductors), and may include one or more layers overlaid or under the bulk material.

[0036] Furthermore, in this invention, any two numbers of a variable can constitute the working range of the variable, and any indicated range may include or exclude endpoints. Additionally, any numerical value of the indicated variable (regardless of whether such numerical value is indicated as "about") may refer to an exact value or an approximate value and include equivalent values, and may refer to an average, median, representative value, multiple value, or the like. Further, in some embodiments of this invention, the terms "including," "constituted by," and "having" independently mean "typically or broadly comprising," "comprising," "consisting essentially of," or "consisting of." In some embodiments of this invention, any defined meaning does not necessarily exclude the usual and conventional meaning.

[0037] As used herein, the term "comprising" means including certain components, but does not exclude the presence of other components, provided that such presence does not render the scope of the claim or the embodiments impossible to implement. In some embodiments, the term "comprising" includes "consisting of". As used herein, the term "consisting of" means that no other components are present in the apparatus / method / product except for those described below. When the term "consisting of" is used to refer to a compound, it means that the chemical compound contains only the listed components.

[0038] As used herein, the term "rinsing" refers to a process step in which precursors and / or active species are removed from a reaction chamber. During a rinsing, an inert or substantially inert gas may be supplied to the reaction chamber. Alternatively or additionally, the reaction chamber may be vented during a rinsing.

[0039] This document describes a method for filling a gap member. The gap member is contained in a substrate and may be located on or near the surface of the substrate. Optionally, the substrate may contain multiple gap members, such as a plurality of gap members. A gap member includes an upper portion and a lower portion, the upper portion including an upper surface and the lower portion including a lower surface. Suitable substrates include semiconductor wafers, such as silicon wafers. The method of the present invention can be used during the manufacture of various semiconductor devices and is particularly suitable for filling gap members having a high aspect ratio and a specific small width, such as a width of less than 10 nm and an aspect ratio greater than 2, 5, 10, or 20. The method includes a step of positioning the substrate on a substrate support in a reaction chamber. The method further includes a step of subjecting the substrate to a plasma pretreatment. The plasma pretreatment results in a suppression of the upper surface while leaving the lower surface substantially unaffected. After the plasma pretreatment, the method further includes a step of selectively depositing a silicon-containing material on the lower surface. Optionally, a rinse is performed before the step of selectively depositing the material onto the lower surface. It should be understood that no plasma is generated in the reaction chamber during the rinse. It should also be understood that the step of selectively depositing a silicon-containing material onto the lower surface comprises a cyclic process, which includes sub-steps that can be repeated continuously until a desired thickness of silicon-containing material has been deposited on the lower surface. Exemplary silicon-containing materials include silicon oxide and silicon carbide. The cyclic process comprises a plurality of cycles, also referred to as sub-cycles. A sub-cycle comprises, in sequence: a step of exposing the substrate to a silicon precursor in a silicon precursor pulse, and a step of pulse plasma treatment after exposing the substrate to the silicon precursor. Optionally, the step of exposing the substrate to the silicon precursor is performed before a rinse. Optionally, the step of exposing the substrate to the silicon precursor is immediately followed by a rinse. It should be understood that no plasma is generated in the reaction chamber during these rinses. The step of exposing the substrate to a silicon precursor results in the chemisorption of the silicon precursor on the lower surface. In other words, by exposing the substrate to the silicon precursor, more silicon precursor is chemisorbed onto the unpassivated lower surface compared to the plasma-passivated upper surface. The step of pulse plasma treatment following the exposure of the substrate to a silicon precursor results in a reaction between one or more reactive species contained in the plasma and the silicon precursor chemisorbed on the lower surface during the exposure of the substrate to the silicon precursor. In some embodiments, the method includes completely filling the gap portion with the silicon-containing material. This can be accomplished, for example, by repeating the cycle until the silicon-containing material fills the entire gap portion.

[0040] Advantageously, such methods offer a very short cycle time. In fact, the deposition time required to achieve a specific film thickness can be reduced by 50% or more, thus resulting in higher yields and less process-induced damage to the underlying layer. An example of process-induced damage is plasma-induced damage.

[0041] In some embodiments, the cycle process includes at least two sub-cycles and up to 20,000 sub-cycles. For example, a cycle deposition process may include 2 sub-cycles, 3 sub-cycles, 5 sub-cycles, 10 sub-cycles, 20 sub-cycles, 30 sub-cycles, 60 sub-cycles, 100 sub-cycles, 200 sub-cycles, 500 sub-cycles, 1000 sub-cycles, 2000 sub-cycles, 5000 sub-cycles, 10000 sub-cycles, or more.

[0042] In some embodiments, the post-pulse plasma treatment of the silicon precursor includes generating an oxygen-containing plasma in the reaction chamber, and the silicon-containing material comprises silicon oxide. In some embodiments, the oxygen-containing plasma is an O2-containing plasma. Therefore, the method described herein can be used in a variety of applications, such as for seamless SiO2-filled gap components for shallow trench isolation purposes. Such seamless shallow trench isolation can advantageously reduce leakage current, etch resistance, and improve resilience associated with chemical mechanical polishing processes. Furthermore, such SiO2 films can have an extremely low carbon content. Additionally, such SiO2 films can have an extremely low nitrogen content.

[0043] In some embodiments, the post-silicon precursor pulsed plasma treatment includes exposing the substrate to an oxygen plasma, with O2 used as a plasma gas. In some embodiments, O2 is supplied to the reaction chamber at a flow rate of at least 100 sccm to at most 10,000 sccm, or at least 200 sccm to at most 5,000 sccm, or at least 500 sccm to at most 1,000 sccm. In some embodiments, the oxygen plasma is generated by an RF generator operating at a plasma power of at least 50 W to at most 200 W. In some embodiments, the oxygen plasma is generated during an oxygen plasma pulse for at least 0.1 seconds to at most 10 seconds, or at least 0.2 seconds to at most 5 seconds, or at least 0.5 seconds to at most 2 seconds. In some embodiments, the substrate is immediately rinsed after exposure to the oxygen plasma, and the rinsing lasts for at least 0.2 seconds to at most 10 seconds, or at least 1 second to at most 5 seconds. It should be understood that no plasma is generated in the reaction chamber during this flushing process.

[0044] In some embodiments, the step of selectively depositing a material on the lower surface is performed at a growth rate of at least 0.1 Å / cycle to at most 10 Å / cycle, for example, at least 0.2 Å / cycle to at most 3 Å / cycle or at least 0.3 to at most 1 Å / cycle. For example, the material is deposited on the lower surface at a growth rate of 0.49 Å / cycle. In some embodiments, the growth rate on the upper surface is at least 2 to at most 20 times slower than on the upper surface. In some embodiments, the growth rate on the upper surface is at least 2 to at most 5 times slower than on the upper surface. In some embodiments, the growth rate on the upper surface is at least 5 to at most 10 times slower than on the upper surface. In some embodiments, the growth rate on the upper surface is at least 10 to at most 20 times slower than on the upper surface. In some embodiments, the growth rate on the upper surface is less than 0.1 Å / cycle. In some embodiments, the growth rate on the upper surface is 0 Å / cycle.

[0045] It was unexpectedly discovered that using a specific silicon precursor could achieve a high growth rate and bottom-up growth. Therefore, in some embodiments, the silicon precursor comprises an amino group and two or more silicon atoms.

[0046] In some embodiments, the silicon precursor comprises a compound selected from the list of monoaminosilanes, monosilaneamines, and monocyclic siloxanes. Exemplary silicon precursors and methods for their preparation are disclosed, for example, in WO2015048237A2, WO2015047914A1, and US10192734B2.

[0047] In some embodiments, the amino group is selected from NH₂, NHR₃, and NR₃Ri₂. In some embodiments, Ri and Ri₂ are hydrocarbon groups. In some embodiments, Ri and Ri₂ are the same. In some embodiments, Ri and Ri₂ are different. In some embodiments, Ri and Ri₂ are independently selected from a C1 to C4 alkyl or alkenyl group. In some embodiments, at least one of Ri and Ri₂ is a C1 to C4 alkyl group.

[0048] In some embodiments, the silicon precursor comprises an alkylamino silane. In some embodiments, the silicon precursor is a disilane or trisilane comprising one or more amino groups.

[0049] In some embodiments, the silicon precursor system is selected from SiR1R3R4-SiR2R5R6, SiR1R3R4-SiR5R6-SiR2R7R8, and SiR1R3R4-SiR2R5-SiR6R7R8. It should be understood that R1 and R2 are NR9R10, and R3, R4, R5, R6, R7, R8, R9, and R10 are independently selected from H and hydrocarbon groups. In some embodiments, R3, R4, R5, R6, R7, R8, R9, and R10 are independently selected from H, C1 to C4 alkyl, C1 to C4 alkenyl, and C4 to C8 aryl. In some embodiments, R3, R4, R5, R6, R7, R8, R9, and R10 are independently selected from H and C1 to C4 alkyl groups. In some embodiments, at least one of R3, R4, R5, R6, R7, R8, R9, and R10 is H. In some embodiments, at least one of R3, R4, R5, R6, R7, R8, R9, and R10 is methyl. In some embodiments, at least one of R3, R4, R5, R6, R7, R8, R9, and R10 is ethyl. In some embodiments, at least one of R3, R4, R5, R6, R7, R8, R9, and R10 is propyl. In some embodiments, at least one of R3, R4, R5, R6, R7, R8, R9, and R10 is isopropyl. In some embodiments, all of R3, R4, R5, R6, R7, R8, R9, and R10 are methyl. In some embodiments, the silicon precursor comprises dimethylaminopentamethyldisilane.

[0050] In some embodiments, the silicon precursor is selected from R1-SiH2-SiH3, R1-SiH2-SiH2-SiH2-R2, and R1-SiH2-SiHR2-SiH3, wherein R1 and R2 are independently selected from NH2, NHR9, and NR9R10, and wherein R9 and R10 are independently selected from H and a C1 to C4 hydrocarbon group. In some embodiments, R9 and R10 are independently selected from H, C1 to C4 alkyl, C1 to C4 alkenyl, and C4 to C8 aryl. In some embodiments, R9 and R10 are independently selected from H and a C1 to C4 alkyl. In some embodiments, at least one of R9 and R10 is H. In some embodiments, at least one of R9 and R10 is methyl. In some embodiments, at least one of R9 and R10 is ethyl. In some embodiments, at least one of R9 and R10 is propyl. In some embodiments, at least one of R9 and R10 is isopropyl. In some embodiments, R9 and R10 are methyl. In some embodiments, at least one of R3 and R4 is a C1 to C4 alkyl group. In some embodiments, the silicon precursor comprises an alkylaminosilane selected from diisopropylaminodisilane and diethylbutylaminodisilane.

[0051] In some embodiments, the silicon precursor comprises a silaneamine.

[0052] In some embodiments, the precursor may be represented by a chemical formula according to molecular formula (i). (i)

[0053] R11 and R12 are independently selected from H and a C1 to C4 alkyl group. In some embodiments, at least one of R11 and R12 is H. In some embodiments, at least one of R11 and R12 is methyl. In some embodiments, at least one of R11 and R12 is ethyl. In some embodiments, at least one of R11 and R12 is propyl. In some embodiments, at least one of R11 and R12 is butyl. In some embodiments, at least one of R11 and R12 is isopropyl. In some embodiments, R11 and R12 are isopropyl.

[0054] In some embodiments, the silicon precursor comprises a cyclosiloxane containing at least one amino group. In some embodiments, the amino group is selected from NH₂, NHR₁, and NR₁R₂i. In some embodiments, Ri and Ri₂ are hydrocarbon groups. In some embodiments, Ri and Ri₂ are the same. In some embodiments, Ri and Ri₂ are different. In some embodiments, Ri and Ri₂ are independently selected from a C1 to C4 alkyl or alkenyl group. In some embodiments, at least one of Ri and Ri₂ is a C1 to C4 alkyl group. In some embodiments, the amino group is selected from NH₂, NHR₁₃, and NR₁₃R₁₄, and R₁₃ and R₁₄ are independently selected from H and a C1 to C4 alkyl group.

[0055] In some embodiments, the cyclosiloxane further comprises one or more C1 to C4 alkyl substituents. In some embodiments, at least one of the C1 to C4 alkyl substituents is methyl. In some embodiments, at least one of the C1 to C4 alkyl substituents is ethyl. In some embodiments, at least one of the C1 to C4 alkyl substituents is propyl. In some embodiments, at least one of the C1 to C4 alkyl substituents is butyl. A suitable siloxane system includes 2-diethylamino-2,4,6,8-tetramethylcyclotetrasiloxane.

[0056] It should be understood that the application of the plasma pretreatment results in a suppression of the upper surface while simultaneously leaving the lower surface substantially unaffected, or at least less affected than the upper surface. In other words, the reaction of the upper surface with a precursor that can be subsequently supplied to the reaction chamber can be appropriately reduced. Alternatively, subjecting the substrate to the plasma pretreatment can result in a suppression gradient in the gap portion. Specifically, the suppression is stronger in the upper portion of the gap than in the lower portion. In other words, the suppression gradually decreases from the upper portion to the lower portion of the gap. Without being limited to any particular theory or mode of operation, it is believed that the suppression of the upper surface is due to the consumption of reactive surface groups such as hydroxyl and amine groups near the top of the surface, while conversely, it is believed that reactive surface groups near the lower surface, i.e., near the bottom of the trench, are less or unaffected by the plasma pretreatment.

[0057] Plasma pretreatment using no more than one type of plasma advantageously results in a short cycle time. Furthermore, when the plasma is maintained for only a short time, for example from at least 5 seconds to at most 15 seconds, a dielectric layer, such as SiO2, with advantageous properties such as low leakage and high breakdown voltage can be obtained. When this dielectric layer is deposited on or near a channel region in a transistor (e.g., a silicon transistor or a thin-film transistor), a high electron mobility can be advantageously obtained within the channels of the transistor.

[0058] In some embodiments, the plasma pretreatment results in a passivation gradient, i.e., a gradually changing passivation intensity from the upper surface to the lower surface. In this example, the step of exposing the substrate to a precursor can result in a gradual change in the density of the chemisorbed precursor per unit area from the lower surface to the upper surface. The silicon precursor post-pulse plasma treatment then allows one or more reactive species contained in the plasma to react with the chemisorbed precursor to form a material. Since more precursor is chemisorbed on the lower surface compared to the upper surface, more material is formed on the lower surface than on the upper surface. In other words, the material is selectively grown in a bottom-up manner.

[0059] In some embodiments, the plasma pretreatment includes subjecting the substrate to an inert gas plasma. In some embodiments, the inert gas plasma is an argon plasma.

[0060] In some embodiments, the plasma pretreatment includes subjecting the substrate to a nitrogen-containing plasma. In some embodiments, the nitrogen-containing plasma is an N₂ plasma. In some embodiments, the nitrogen-containing plasma is an NH₃ plasma.

[0061] In some embodiments, the plasma pretreatment includes exposing the substrate to an H₂-N₂ plasma. It should be understood that an H₂-N₂ plasma refers to a plasma using a plasma gas comprising H₂ and N₂. An H₂-N₂ plasma can be advantageously used to fill a gap with a silicon-containing material using an alkylaminosilane (such as bis(diethylamino)silane).

[0062] In some embodiments, the plasma pretreatment includes subjecting the substrate to a hydrogen-containing plasma. In some embodiments, the hydrogen-containing plasma is an H₂ plasma.

[0063] In some embodiments, the plasma pretreatment includes subjecting the substrate to a first plasma treatment and a second plasma treatment. It should be understood that the first and second plasma treatments are different, i.e., not identical. Optionally, the first and second plasma treatments are separated by a rinsing process. It should be understood that no plasma is generated in the reaction chamber during the rinsing process.

[0064] In some embodiments, the first plasma treatment includes generating a nitrogen-containing plasma in the reaction chamber. In some embodiments, the nitrogen-containing plasma is an N2-containing plasma. In other words, in some embodiments, a plasma gas system containing N2 is used to generate the nitrogen-containing plasma.

[0065] In some embodiments, the second plasma treatment includes generating an inert gas-containing plasma in the reaction chamber. In some embodiments, the inert gas-containing plasma is an argon-containing plasma.

[0066] In some embodiments, the first plasma treatment includes generating a nitrogen plasma in the reaction chamber, and the second plasma treatment includes generating an inert gas plasma in the reaction chamber. In such embodiments, the material selectively deposited after the first and second plasma treatments, such as silicon oxide shallow trench isolation, can advantageously be a component with low to negligible C residues and a high-quality film. Furthermore, when the substrate comprises Si fins, these plasma treatments advantageously limit or prevent the oxidation of such silicon fins. Additionally, using an inert gas plasma after the nitrogen plasma can advantageously reduce or eliminate the amount of N-containing surface groups (also referred to as nitrogen residues) on the substrate.

[0067] In some embodiments, the first plasma treatment includes exposing the substrate to a nitrogen plasma, wherein the nitrogen plasma comprises N2. In some embodiments, the N2 is supplied to the reaction chamber at a flow rate of at least 200 sccm to at most 2000 sccm, or at least 400 sccm to at most 1200 sccm, or at least 600 sccm to at most 1000 sccm. In some embodiments, the nitrogen plasma is generated by an RF generator at a plasma power of at least 100 W to at most 1000 W, for example at least 200 W to at most 500 W. In some embodiments, the N2 plasma is generated for at least 5 seconds to at most 50 seconds, for example for at least 10 seconds to at most 20 seconds. In some embodiments, the N2 plasma system is generated for at least 0.01 seconds to at most 50 seconds, for example, for at least 0.2 seconds to at most 20 seconds, for example, for at least 0.5 seconds to at most 10 seconds, for example, for at least 1 second to at most 5 seconds. In some embodiments, the N2 plasma system is immediately followed by a rinse lasting at least 1 second to at most 5 seconds. In some embodiments, the N2 plasma system is immediately followed by a rinse lasting at least 0.1 seconds to at most 10 seconds. It should be understood that no plasma is generated in the reaction chamber during this rinse. It should also be understood that a rinse time of at least 1 second may be particularly advantageous when the plasma gas is changed from one process step to another, such as when the substrate is subjected to a first plasma treatment and then a second plasma treatment.

[0068] In some embodiments, the second plasma treatment includes exposing the substrate to an argon plasma, wherein the plasma gas comprises Ar. In some embodiments, Ar is provided to the reaction chamber at a flow rate of at least 1 slm to at most 10 slm or at least 2 slm to at most 5 lm. In some embodiments, the argon plasma is generated by an RF generator at a plasma power of at least 100 W to at most 1000 W, for example at least 200 W to at most 500 W. In some embodiments, the generation of the argon plasma lasts for at least 5 seconds to at most 50 seconds, for example at least 10 seconds to at most 20 seconds. In some embodiments, the argon plasma is followed by a rinsing for at least 0.1 seconds to at most 2 seconds, for example at least 0.2 seconds to at most 1 second. It should be understood that no plasma is generated in the reaction chamber during this rinsing. It should be noted that the above values ​​are given when using a 300 mm wafer as the substrate, and these values ​​can be easily adapted to different substrate sizes if needed.

[0069] In some embodiments, the substrate system is maintained at a temperature of at least 100°C to at most 500°C, or at least 100°C to at most 200°C, or at least 200°C to at most 300°C, or at least 300°C to at most 400°C, or at least 400°C to at most 500°C.

[0070] In some embodiments, the reaction chamber is maintained at a pressure of at least 0.1 Torr to at most 200 Torr, or at least 0.2 Torr to at most 100 Torr, or at least 0.5 Torr to at most 50 Torr, or at least 1 Torr to at most 20 Torr, or at least 2 Torr to at most 10 Torr, for example, the reaction chamber may be maintained at a pressure of 5 Torr.

[0071] In some embodiments, the silicon precursor pulse system has a duration of at least 1 second to at most 20 seconds, or at least 2 seconds to at most 10 seconds, or at least 3 seconds to at most 5 seconds. In some embodiments, the silicon precursor pulse system has a duration of at least 0.1 seconds to at most 20 seconds, or at least 0.2 seconds to at most 10 seconds, or at least 0.5 seconds to at most 5 seconds, or at least 1 second to at most 2 seconds. In some embodiments, the silicon precursor pulse system is immediately followed by rinsing, and the rinsing has a duration of at least 0.2 seconds to at most 20 seconds, or at least 0.5 seconds to at most 10 seconds, or at least 1 second to at most 5 seconds. It should be understood that no plasma is generated in the reaction chamber during this rinsing.

[0072] In some embodiments, the method includes performing a plurality of supercycles consecutively. A supercycle includes the step of subjecting the substrate to a plasma pretreatment and the step of selectively depositing a silicon-containing material onto the lower surface. In some embodiments, the method includes performing the supercycle at least 5 to at most 10,000 times, or at least 10 to at most 5,000 times, or at least 20 to at most 2,000 times, or at least 50 to at most 1,000 times, or at least 100 to at most 500 times. In some embodiments, the method includes performing the supercycle at least 5 to at most 50 times, or at least 10 to at most 20 times. In some embodiments, the consecutive supercycles are separated by a rinse. It should be understood that no plasma is generated in the reaction chamber during the rinse.

[0073] This document further describes a semiconductor processing apparatus. The apparatus includes a reaction chamber, a heater, a first plasma gas source, a second plasma gas source, a plasma module, one or more precursor sources, and a controller. Optionally, the apparatus further includes a third plasma gas source. A substrate support suitably allows support of a substrate including one or more gap members. The heater is constructed and configured to heat the substrate in the reaction chamber. The first plasma gas source is in fluid communication with the reaction chamber via a first plasma gas valve. The first plasma gas source may be configured to, for example, provide a nitrogen-containing gas and / or an inert gas to the reaction chamber. The second plasma gas source is in fluid communication with the reaction chamber via a second plasma gas valve. The second plasma gas source may be configured to, for example, provide an oxygen-containing gas to the reaction chamber. When present, the third plasma gas source may be in fluid communication with the reaction chamber via a third plasma gas valve. The third plasma gas source may be configured to, for example, supply a nitrogen-containing gas and / or an inert gas to the reaction chamber. The plasma module includes a radio frequency power source configured to generate a plasma in the reaction chamber. The one or more precursor sources are fluidly connected to the reaction chamber via one or more precursor valves. Suitable, the semiconductor processing apparatus may further include an exhaust system for discharging reaction products, carrier gases, and unused precursors and co-reactants. The controller includes a processor and one or more memory modules and is programmed or otherwise configured to perform the methods described herein.

[0074] Optionally, the system is configured to supply at least one of the precursors to the reaction chamber via a carrier gas. Suitable carrier gases include inert gases. In other words, in some embodiments, the semiconductor processing system includes a gas injection system comprising a precursor delivery system that uses a carrier gas to deliver the precursor to one or more reaction chambers.

[0075] The method provided by the present invention can be performed in any suitable apparatus, including in one embodiment of a semiconductor processing system as shown in FIG1. ​​FIG1 is a schematic diagram of a plasma-enhanced atomic layer deposition (PEALD) apparatus that can be used in some embodiments of the present invention. In this diagram, a plasma can be generated between the electrodes by arranging a pair of conductive plate electrodes (2, 4) parallel to each other and facing each other in the interior (11) (reaction zone) of a reaction chamber (3), applying RF power (e.g., 13.56 MHz and / or 27 MHz) from a power source (25) to one side and electrically grounding the other side (12). Of course, the semiconductor processing apparatus does not need to generate plasma during a step in which a precursor is provided to the reaction chamber, or during rinsing between consecutive process steps, nor does it need to apply RF power to either of the electrodes during such steps or rinsing. A temperature regulator may be provided in a lower stage (2), i.e., in the lower electrode. A substrate (1) is placed thereon, and its temperature is kept constant at a given temperature. The upper electrode (4) can also serve as a spray plate, and various gases, such as a plasma gas, a reactant gas, and / or, if present, a dilution gas and a precursor gas, can be introduced into the reaction chamber (3) via a gas line (21) and a gas line (22) and via the spray plate (4), respectively. In addition, a circular pipe (13) with an exhaust line (7) is provided in the reaction chamber (3), and the gas system inside the reaction chamber (3) (11) is discharged through the circular pipe. In addition, a transfer chamber (5) is provided below the reaction chamber (3) and has a gas sealing line (24) to introduce sealing gas into the interior (11) of the reaction chamber (3) via the interior (16) of the transfer chamber (5), wherein a separation plate (14) is provided for separating the reaction zone and the transfer zone.

[0076] It should be noted that a gate valve by which a wafer can be transferred to or from the transfer chamber (5) is omitted in this figure. The transfer chamber is also provided with an exhaust line (6). In some embodiments, the deposition and surface treatment of silicon oxide are performed in the same reaction space so that all steps can be performed continuously without the need for intermediate steps such as venting the reaction chamber, emptying the reaction chamber, or exposing the substrate to the atmosphere.

[0077] Figure 2 shows a schematic diagram of a substrate (200) including a gap member (210). The gap member (210) includes an upper portion (211) and a lower portion (212). The upper portion (211) includes an upper surface, and the lower portion (212) includes a lower surface. By subjecting the substrate (200) to a first plasma treatment and a second plasma treatment, the upper surface can be substantially suppressed. In other words, compared to the lower surface, the first and second plasma treatments can appropriately make the upper surface less reactive to a precursor.

[0078] Figure 3 shows a schematic diagram of an embodiment of the method as described herein. The method includes a step (311) of positioning a substrate on a substrate support. The substrate includes a gap member. The substrate is then subjected to a plasma treatment as described herein (312). Optionally, the reaction chamber is then rinsed using a plasma post-rinse (315). The rinsing may be performed, for example, by a substantially inert gas such as a rare gas. Exemplary inert gases include He, Ne, Ar, Xe, and Kr. The method further includes a step (316) of depositing a silicon-containing material on the lower surface of the gap member using the techniques described herein. Optionally, the reaction chamber is then rinsed using a deposition post-rinse (317). It should be understood that no plasma is generated in the reaction chamber during these rinsing processes. The steps from subjecting the substrate to a plasma treatment (312) to depositing a silicon-containing material on the lower surface of the gap member (316) can optionally be repeated (319) one or more times, thereby resulting in a plurality of supercycles including a subsequent plasma treatment and an immediate deposition step. Optionally, the subsequent supercycles are separated by a rinsing. Thus, a silicon-containing material is deposited in the gap member. The method ends (318) when a desired amount of material has been deposited in the gap.

[0079] Figure 4 shows a schematic diagram of one embodiment of the method described herein. The method includes a step (411) of positioning a substrate on a substrate support. The substrate includes a gap member. The substrate is then subjected to a first plasma treatment (412) as described herein. Optionally, the reaction chamber is then rinsed using an inter-plasma flush (413). The flushing may be performed, for example, by a substantially inert gas such as a rare gas. Exemplary inert gases include He, Ne, Ar, Xe, and Kr. The method further includes a step (414) of subjecting the substrate to a second plasma treatment as described herein. Optionally, the reaction chamber is then rinsed using a post-plasma flush (415). The method further includes a step (416) of depositing a silicon-containing material onto the lower surface of the gap member using the techniques described herein. Optionally, the reaction chamber is then rinsed using a post-deposition flush (417). It should be understood that no plasma is generated in the reaction chamber during these flushes. The steps from subjecting the substrate to a first plasma treatment (412) to depositing a silicon-containing material on the lower surface of the gap member can optionally be repeated (419) one or more times, thereby resulting in a plurality of supercycles including subsequent first and second plasma treatments and an immediate deposition step. Thus, a silicon-containing material is deposited in the gap member. When a desired amount of silicon-containing material has been deposited in the gap, the method ends (418).

[0080] Figure 5 shows a schematic diagram of an embodiment of a method for selectively depositing a silicon-containing material on the lower surface of a gap member included in a substrate. The portion of the method shown in Figure 5 corresponds to step (316) of depositing a silicon-containing material on a lower surface as shown in Figure 3 and / or step (416) of depositing a silicon-containing material on a lower surface as shown in Figure 4, and is initiated after a step of subjecting the substrate to a plasma treatment, or after a step of subjecting the substrate to a first plasma treatment and a second plasma treatment, or optionally after a rinse immediately following such a step (511). The substrate is exposed to a silicon precursor chemically adsorbed on the lower surface as described herein (512). Optionally, the reaction chamber is then rinsed (513). The method then includes a step of subjecting the substrate to a third plasma treatment (514). Optionally, the reaction chamber is then rinsed (515). It should be understood that no plasma is generated in the reaction chamber during these rinses. The steps from exposing the substrate to a silicon precursor (512) to subjecting the substrate to a third plasma treatment (514) can optionally be repeated (517) one or more times, thereby resulting in multiple sub-cycles. Thus, a silicon-containing material is deposited in the gap member. The method ends (516) when a desired amount of silicon-containing material has been deposited in the gap.

[0081] Figure 6 shows a transmission electron microscope (TEM) image of silicon oxide deposited in a gap component by one embodiment of the method described herein. Specifically, it involves a plurality of supercycles comprising sequential plasma pretreatment and steps for selectively depositing silicon oxide onto the lower surface. These plasma pretreatments include a step of exposing the substrate to a nitrogen plasma and a subsequent step of exposing the substrate to an argon plasma. During the nitrogen plasma, N₂ is used at a flow rate of 800 sccm, a plasma power of 300 W (i.e., radio frequency (RF) power) is used, the N₂ plasma is maintained for 8 seconds, and a 2-second inter-plasma rinse time is used. During the argon plasma, Ar is used at a flow rate of 3.7 slm, a plasma power of 500 W (RF power) is used, the argon plasma is maintained for 8 seconds, and a 5-second post-plasma rinse time is used. Diisopropylaminotrisilylanamine was used as a silicon precursor. The post-precursor pulsed plasma treatment involved exposing the substrate to an O2 plasma. During the O2 plasma treatment, an O2 flow rate of 800 sccm and a plasma power (RF power) of 100 W were used. The O2 plasma treatment was maintained for 1 second. After the O2 plasma treatment, the reaction chamber was rinsed for 2 seconds. The above process was repeated for 100 supercycles. The reaction chamber was maintained at a pressure of 5 Torr, and the substrate was maintained at a temperature of 300°C. By using this process, a growth rate of 2.29 Å / cycle and a growth rate of 0.93 Å / cycle were obtained in the unpassivated lower portion of the gap components. Therefore, a surprisingly high growth rate was achieved in the bottom-up growth of the gap components.

[0082] In the process shown in Figure 6, after each subcycle including a silicon precursor-silicon precursor post-pulse plasma treatment, a plasma pretreatment, i.e., a plasma suppression, is used. Alternatively, this plasma pretreatment can be repeated only every few subcycles, such as every 3 subcycles, every 5 subcycles, every 10 subcycles, every 20 subcycles, or every 50 subcycles. Although such alternative process flows come at the cost of top-bottom selectivity, they can advantageously increase throughput and reduce plasma-induced damage, such as Si or Ge oxidation.

[0083] Figure 7 shows selected components of an embodiment of a plasma-enhanced atomic layer deposition (PEALD) apparatus (700) that can be used to perform the methods described herein. The apparatus (700) includes a gas line (710), a bypass valve (720), a bypass line (730), a reactor (740), and an exhaust line (750). Such apparatus, including a bypass valve (720), can suitably increase throughput in the methods described herein. In particular, the bypass valve (720) can be used to allow continuous gas flow, even when a specific process gas is not required in the reaction chamber. Therefore, using a bypass valve (720) allows the use of a gas stabilization step to be avoided during the processing of multiple wafers and makes it easier to switch to different gas compositions for processing steps, thereby increasing throughput.

[0084] Furthermore, this bypass valve system allows for the continuous flow of certain gases and reduces particulate contamination by avoiding pressure pulse channels. Moreover, the flow can be initiated in bypass mode, thus preventing initial particle bursts into the chamber at the start (first wafer effect, pre-recipe requirements, etc.).

[0085] The gas line (710) may be a line carrying any of the gases described herein, such as a precursor gas line, an inert gas line, a nitrogen gas line, or an oxygen gas line. Advantageously, the device (700) includes multiple gas lines, such as a precursor gas line, an inert gas line, a nitrogen gas line, and an oxygen gas line.

[0086] Therefore, in some embodiments, the silicon precursor is transferred through a silicon precursor bypass channel during the step of subjecting the substrate to a plasma pretreatment.

[0087] Alternatively, during the step of exposing the substrate to a silicon precursor, a plasma gas system is transferred through a plasma gas bypass conduit.

[0088] In some embodiments, during the step of depositing a silicon-containing material, the plasma gas system used during the plasma pretreatment is diverted using a bypass valve.

[0089] In some embodiments, the silicon precursor is transferred using a bypass valve during the plasma pretreatment and during the pulsed plasma treatment step after exposing the substrate to a silicon precursor.

[0090] In some embodiments, the plasma gas system used during the step of subjecting the substrate to a plasma pretreatment and during the step of exposing the substrate to a silicon precursor, and during the step of pulsed plasma treatment after exposing the substrate to a silicon precursor, is diverted via a bypass valve.

[0091] The exemplary embodiments described herein do not limit the scope of the invention, as these embodiments are merely examples of examples of embodiments of the invention, and the scope of the invention is defined by the claims and their legal equivalents described below. Any equivalent embodiments are intended to be within the scope of the invention. In fact, in addition to what is shown and described herein, various modifications disclosed herein will be apparent to those skilled in the art from this specification, such as substitutions of the described elements and combinations thereof. Such modifications and embodiments are also intended to fall within the scope of the claims described below.

[0092] In this invention, where conditions and / or structures are not specified, those skilled in the art can readily provide such conditions and / or structures that fall under routine experimental matters, in view of this description.

[0093] 1:Substrate 2: Lower platform / conductive plate electrode 3: Reaction Chamber 4: Upper electrode / conductive plate electrode 5: Transfer Room 6: Exhaust pipe 7: Exhaust pipe 11: The interior of the reaction chamber 12: Electrical grounding side 13: Round tube 14: Divider 16: The interior of the transfer chamber 21: Gas pipeline 22: Gas pipeline 24: Gas-tight pipeline 25: Power Supply 200:Substrate 210: Clearance component 211: Upper part 212: Lower part 311: Steps for positioning a substrate on a substrate support 312: Step of subjecting the substrate to a plasma treatment 315: Post-plasma rinsing 316: Steps for depositing a material on the following surface 317: Post-sedimentation flushing 318: End of Method 319: Repeat 411: Step of positioning a substrate on a substrate support 412: Step of subjecting the substrate to a first plasma treatment 413: Plasma Room Flushing 414: Step of subjecting the substrate to a first plasma treatment 415: Post-plasma rinsing 416: Steps for depositing a silicon-containing material on the following surface 417: Post-sedimentation flushing 418: End of Method 419: Repeat 511: Method Begins 512: Step of exposing a substrate to a silicon precursor 513: Rinse 514: Step of exposing the substrate to a precursor and then exposing it to plasma treatment 515: Rinse 516: End of Method 517: Repeat 700: Equipment 710: Gas pipeline 720: Bypass valve 730: Bypass line 740: Reactor 750: Exhaust line

Claims

1. A method for filling a gap in a substrate surface, the method comprising: - A step of positioning a substrate on a substrate support in a reaction chamber, the substrate including one or more gap members, the one or more gap members including an upper portion and a lower portion, the upper portion including an upper surface and the lower portion including a lower surface; - A step of subjecting the substrate to a plasma pretreatment, thereby suppressing the upper surface and simultaneously leaving the lower surface substantially unaffected; and - A step of selectively depositing a silicon-containing material on the lower surface; wherein the step of selectively depositing a silicon-containing material on the lower surface includes a cycle process, the cycle process including a plurality of sub-cycles, a sub-cycle including in a given order: - A step of exposing the substrate to a silicon precursor in a silicon precursor pulse, thereby forming a chemisorbed silicon precursor on the lower surface; and - A step of pulse plasma treatment after exposing the substrate to a silicon precursor, thereby allowing one or more active species in the plasma to react with the chemisorbed silicon precursor on the lower surface; The silicon precursor includes an amino group and two or more silicon atoms.

2. The method as claimed in claim 1, wherein the amino group is selected from NH2, NHRi and NRiRii, and at least one of Ri and Riii is a C1 to C4 alkyl group.

3. The method as described in claim 1 or 2, wherein the silicon precursor comprises a compound selected from the list of monoaminosilanes, monosilaneamines, and monocyclic siloxanes.

4. The method as described in claim 1, wherein the silicon precursor comprises an alkylaminosilane.

5. The method as claimed in claim 1, wherein the silicon precursor comprises a compound selected from SiR1R3R4-SiR2R5R6, SiR1R3R4-SiR5R6-SiR2R7R8 and SiR1R3R4-SiR2R5-SiR6R7R8, wherein R1 and R2 are NR9R10, and R3, R4, R5, R6, R7, R8, R9 and R10 are independently selected from H and a C1 to C4 alkyl group.

6. The method as described in claim 1 or 2, wherein the silicon precursor comprises a silaneamine.

7. The method as claimed in claim 6, wherein the silicon precursor comprises a compound (1) whose chemical structure can be represented by a chemical structure according to the molecular formula (1), wherein R11 and R12 are independently selected from H and a C1 to C4 alkyl group.

8. The method as claimed in claim 1, wherein the silicon precursor comprises a cyclosiloxane comprising at least one amino group.

9. The method as described in claim 1 or 2, wherein the plasma pretreatment includes subjecting the substrate to an inert gas plasma.

10. The method as described in claim 1 or 2, wherein the plasma pretreatment includes subjecting the substrate to a nitrogen-containing plasma.

11. The method as described in claim 1 or 2, wherein the plasma pretreatment includes subjecting the substrate to a nitrogen- and hydrogen-containing plasma.

12. The method as claimed in claim 1 or 2, wherein the plasma pretreatment includes subjecting the substrate to a first plasma treatment and subjecting the substrate to a second plasma treatment.

13. The method as claimed in claim 12, wherein the first plasma treatment includes generating a nitrogen-containing plasma in the reaction chamber.

14. The method as described in claim 13, wherein the nitrogen-containing plasma is an N2-containing plasma.

15. The method as claimed in claim 12, wherein the second plasma treatment includes generating an inert gas-containing plasma in the reaction chamber.

16. The method as described in claim 1 or 2, comprising executing a plurality of superloops, each superloop comprising: - The step of subjecting the substrate to a plasma pretreatment; And - the step of selectively depositing a silicon-containing material on the lower surface.

17. The method as claimed in claim 1 or 2, wherein the post-pulse plasma treatment of the silicon precursor includes generating an oxygen-containing plasma in the reaction chamber, and wherein the silicon-containing material comprises silicon oxide.

18. The method as claimed in claim 1 or 2, wherein during the step of subjecting the substrate to a plasma pretreatment, the silicon precursor is transferred through a silicon precursor bypass channel.

19. The method as claimed in claim 1 or 2, wherein during the step of exposing the substrate to a silicon precursor, a plasma gas system is transferred through a plasma gas bypass conduit.

20. A semiconductor processing apparatus, comprising: - A reaction chamber, including a substrate support for supporting a substrate including one or more gap members; - A heater configured to heat the substrate in the reaction chamber; - A first plasma gas source fluidly connected to the reaction chamber via a first plasma gas valve; - A second plasma gas source fluidly connected to the reaction chamber via a second plasma gas valve; - A third plasma gas source fluidly connected to the reaction chamber via a third plasma gas valve; - A plasma module including a radio frequency power source configured to generate a plasma in the reaction chamber; - One or more silicon precursor sources fluidly connected to the reaction chamber via one or more precursor valves; and - A controller configured to cause the device to perform a method as described in any one of claims 1 to 19.

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