Semiconductor package

Abstract

A semiconductor package according to an embodiment includes: a first insulating layer; and a first through electrode portion that penetrates the first insulating layer and has a shape that extends in a first direction; wherein the first through electrode portion includes: a plurality of first through electrodes that are spaced apart from each other in a second direction perpendicular to the first direction and in a thickness direction; wherein at least one of the plurality of first through electrodes includes: a first sub-through electrode and a second sub-through electrode that are spaced apart from each other in the first direction; and wherein at least one of the first sub-through electrode and the second sub-through electrode has a width in the first direction that is greater than a width in the second direction.

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor package, and more specifically to a semiconductor package including a through electrode with a large area. [Previous Technology]

[0002] As electronic components become smaller, lighter, and more integrated, the linewidth of circuits is becoming smaller and smaller. Specifically, as semiconductor chip design rules are integrated at the nanometer scale, the linewidth of the packaging substrate or printed circuit board on which the semiconductor chip is mounted is reduced to a few micrometers or smaller.

[0003] Various methods have been proposed to increase the circuit integration of printed circuit boards, that is, to reduce the linewidth of the circuit. Semi-additive process (SAP) and modified semi-additive process (MSAP) have been proposed to prevent linewidth loss of the circuit during the etching step so as to form patterns after copper plating.

[0004] Subsequently, this technology has employed an embedded trace substrate (hereinafter referred to as "ETS") method in which copper foil is embedded in an insulating layer to implement finer circuit patterns. The ETS method manufactures the circuit by embedding the copper foil circuit in the insulating layer rather than forming the copper foil circuit on the surface of the insulating layer. For this reason, there is no circuit loss due to etching, which is advantageous for optimizing circuit spacing.

[0005] Meanwhile, in recent years, efforts have been made to develop and improve 5G or pre-5G communication systems to meet the demand for wireless data traffic. Here, 5G communication systems use ultra-high frequency (millimeter wave (mmWave)) bands (6-gigabit (6GHz), 28-gigabit (28GHz), 38-gigabit (38GHz) or higher frequencies) to achieve high data rates.

[0006] Furthermore, technologies such as beamforming, massive MIMO, and array antenna integration are being developed to reduce path loss of radio waves in the extremely high frequency band and increase the propagation distance of radio waves in 5G communication systems. Considering that such frequency bands can be composed of hundreds of active antennas of wavelength, the antenna system becomes relatively large.

[0007] Since these antennas and AP modules are patterned or mounted on printed circuit boards, low loss of the printed circuit boards is extremely important. This means that several substrates constituting an active antenna system must be integrated into a compact unit, namely the antenna substrate, the antenna feed substrate, the transceiver substrate, and the baseband substrate.

[0008] Meanwhile, recently, circuit boards including large-area vias have been developed to improve heat dissipation or shielding properties. Large-area vias can be formed by filling large-diameter via holes with metal material. However, filling the interior of large-diameter via holes with metal material is not easy, and therefore, conventional large-area vias include recessed areas that are recessed towards the interior of the via holes on a surface. In addition, the recessed areas can affect the via hole processing during additional lamination, and therefore, the reliability of the printed circuit board is affected.

[0009] An embodiment provides a circuit board with a novel structure and a semiconductor package including the circuit board.

[0010] An embodiment provides a circuit board with a novel structure and a semiconductor package including the circuit board, the novel structure being able to minimize pits in large area channels.

[0011] The technical problems to be solved in the embodiments are not limited to those mentioned above, and another technical problem not mentioned will be clearly understood by those skilled in the art from the following description.

[0012] A semiconductor package according to an embodiment includes: a first insulating layer; and a first through electrode portion that penetrates the first insulating layer and has an elongated shape in a first direction; wherein the first through electrode portion includes: a plurality of first through electrodes that are spaced apart from each other in a second direction perpendicular to the first direction and in a thickness direction; wherein at least one of the plurality of first through electrodes includes: a first sub-through electrode and a second sub-through electrode that are spaced apart from each other in the first direction; and wherein at least one of the first sub-through electrode and the second sub-through electrode has a width in the first direction that is greater than its width in the second direction.

[0013] In addition, the semiconductor package further includes: a first-first pad disposed on an upper surface of a first insulating layer; and a first-second pad disposed on a lower surface of the first insulating layer, wherein the upper surfaces of a plurality of first through electrodes are in contact with a first-first pad, and wherein the lower surfaces of a plurality of first through electrodes are in contact with a first-second pad.

[0014] In addition, the width of the upper surface of the first sub-penetrating electrode is greater than the width of the lower surface of the first sub-penetrating electrode; wherein the width of the first sub-penetrating electrode in the first direction is the width of the upper surface of the first sub-penetrating electrode in the first direction; and wherein the width of the first sub-penetrating electrode in the second direction is the width of the upper surface of the first sub-penetrating electrode in the second direction.

[0015] In addition, the width of the upper surface of the second sub-penetrating electrode is greater than the width of the lower surface of the second sub-penetrating electrode; wherein the width of the second sub-penetrating electrode in the first direction is the width of the upper surface of the second sub-penetrating electrode in the first direction; and wherein the width of the second sub-penetrating electrode in the second direction is the width of the upper surface of the second sub-penetrating electrode in the second direction.

[0016] In addition, at least one of the first and second sub-penetrating electrodes has a width in the first direction that is 25 times or less the thickness of the first insulating layer.

[0017] In addition, the width of the first-first pad in the first direction is 15 times greater than the thickness of the first insulating layer.

[0018] In addition, the plurality of first through electrodes include a first-first through electrode and a first-second through electrode spaced apart from each other in a second direction, wherein the first sub-through electrode of the first-first through electrode is spaced apart from the second sub-through electrode of the first-first through electrode in a first direction by a first interval; and wherein the first sub-through electrode of the first-first through electrode is spaced apart from the first sub-through electrode of the first-second through electrode in a second direction by a second interval different from the first interval.

[0019] In addition, the first interval is smaller than the second interval.

[0020] In addition, the semiconductor package further includes a second through electrode portion, which includes a second-first through electrode and a second-second through electrode that penetrate the first insulating layer, wherein the first-first through electrode and the first-second through electrode constitute a first through electrode group, and wherein the second-first through electrode and the second-second through electrode constitute a second through electrode group spaced apart from the first through electrode group in a second direction.

[0021] In addition, the second through electrode group is spaced apart from the first through electrode group by a third interval in the second direction; and the third interval is different from the first interval and the second interval.

[0022] In addition, the third interval is larger than the first interval and the second interval.

[0023] In addition, the first-first pad includes: a first pad region that overlaps with the first through electrode portion in the thickness direction; and a second pad region other than the first pad region; wherein the layer structure of the first pad region is different from the layer structure of the second pad region.

[0024] In addition, the first padding region has a first number of layers, and the second padding region has a second number of layers that is less than the first number of layers.

[0025] In addition, the semiconductor package further includes: an adhesive component disposed on the first-first pad; and a wafer attached to the adhesive component.

[0026] In addition, the chip includes a first AP chip and a second AP chip, wherein the first AP chip corresponds to a central processing unit (CPU) and the second AP chip corresponds to a graphics processing unit (GPU).

[0027] The circuit board of the embodiment includes a first passage portion. The first passage portion includes a plurality of first passages spaced apart from each other in a second direction. In this case, each of the plurality of first passages includes a plurality of sub-passages spaced apart from each other in the first direction. In addition, each of the plurality of sub-passages has a strip shape in which the width in the first direction is greater than the width in the second direction. In the embodiment, each of the first passages includes a plurality of sub-passages extending in the first direction, and therefore, the embodiment reduces the number of electroplating processes compared to the comparative example. For example, the comparative example does not include a plurality of sub-passages as in the embodiment, but includes an integrated passage made of a single passage. However, when the width of the passage is not considered at all as in the comparative example, the pit size increases with the increase of the width of the passage, and therefore, there is a problem of an increase in the number of electroplating processes.

[0028] In contrast, when the width of the passage exceeds a certain level compared to the thickness of the insulating layer, the embodiment consists of a plurality of sub-passages to minimize the pits in the passage, and therefore, it is possible to reduce the number of electroplating processes by reducing the pit size during the electroplating process.

[0029] Furthermore, in this embodiment, the plurality of first channels are divided into a first channel group and a second channel group spaced apart in a second direction, with the spacing between the first channel group and the second channel group being greater than the spacing between the plurality of first channels. Therefore, this embodiment maintains that the plating speed of the first channels included in the first channel group and the plating speed of the first channels included in the second channel group are substantially the same. Thus, it is possible to maintain the flatness of the plating by minimizing plating deviation. In addition, this embodiment can improve the heat dissipation characteristics in the edge region by dividing the plurality of first channels into the first channel group and the second channel group as described above, and thus improve reliability. [Simplified Explanation of the Diagram]

[0030] Figure 1a is a cross-sectional view showing the circuit board according to the comparative example.

[0031] Figure 1b is a plan view showing the pathways included in the circuit board of Figure 1a.

[0032] Figure 2 is a cross-sectional view showing the circuit board according to an embodiment.

[0033] Figure 3 is a plan view of a specific layer of the circuit board in Figure 2.

[0034] Figure 4 is a detailed plan view of the passage area in Figure 3.

[0035] Figure 5 is a detailed view of the passage area in Figure 3.

[0036] Figure 6 is a view used to explain the processing conditions of the passage hole in the embodiment.

[0037] Figure 7 is a view showing the structure of the first passage portion according to an embodiment, and Figure 8 is a view showing a modified example of the first passage portion of Figure 7.

[0038] Figure 9 is a view showing the packaging substrate according to an embodiment.

Implementation Method

[0039] In the following, embodiments of the invention will be described in detail with reference to the accompanying drawings.

[0040] However, the spirit and scope of the present invention are not limited to one part of the described embodiments, and may be implemented in various other forms within the spirit and scope of the present invention, and one or more of the elements of the embodiments may be selectively combined and substituted.

[0041] Furthermore, unless otherwise expressly defined and described, the terminology (including technical and scientific terms) used in the embodiments of the present invention is to be regarded as having the same meaning as commonly understood by those skilled in the art to which this invention pertains, and terms such as those defined in common dictionaries are to be interpreted as having a meaning consistent with their meaning in the context of the relevant field. Moreover, the terminology used in the embodiments of the present invention is for describing embodiments and is not intended to limit the invention.

[0042] In this specification, the singular form may also include the plural form, unless specifically stated in the phrase, and may include at least one of all combinations, which may be a combination of A, B and C when described in "at least one (or more) of A, B and C". In addition, when describing elements of embodiments of the present invention, terms such as first, second, A, B, (a) and (b) may be used.

[0043] These terms are used only to distinguish an element from other elements, and are not limited to the nature, order, or sequence of elements. In addition, when an element is described as being "connected," "coupled," or "in contact" with another element, this includes not only when the element is directly "connected," "coupled," or "in contact" with another element, but also when the element is "connected," "coupled," or "in contact" with another element between the element and other elements.

[0044] Additionally, when described as being formed or disposed "above" or "below" of each element, "above" or "below" may include not only when the two elements are directly connected to each other, but also when one or more other elements are formed or disposed between the two elements. Furthermore, when expressed as "above" or "below", based on an element, it may not only include the upper direction but may also include the lower direction.

[0045] In the following, embodiments of the invention will be described in detail with reference to the accompanying drawings.

[0046] Before describing the embodiments of the present invention, a comparative example to be compared with the embodiments of the present invention will be described.

[0047] Meanwhile, the pathway described below may be referred to as a "penetrating electrode", and the pathway portion may also be referred to as a "penetrating electrode portion".

[0048] FIG1a is a cross-sectional view showing the circuit board according to the comparative example, and FIG1b is a plan view showing the pathways included in the circuit board of FIG1a.

[0049] Referring to Figures 1a and 1b, the circuit board of the comparative example includes a large area of ​​vias.

[0050] Specifically, the circuit board of the comparative example includes an insulating layer 10, a first pad 20, a third pad 30, a first pass portion V1, and a second pass portion V2.

[0051] The first pad 20 is disposed on the first surface of the insulating layer 10. The first surface is the lower surface of the insulating layer 10.

[0052] The second pad 30 is disposed on a second surface opposite to the first surface of the insulating layer 10. The second surface is the upper surface opposite to the lower surface of the insulating layer 10.

[0053] The circuit board includes a passageway through the insulating layer 10. For example, the circuit board of the comparative example includes a first passageway portion V1 and a second passageway portion V2 through the insulating layer 10.

[0054] The first path portion V1 includes a large-area path. Furthermore, the second path portion V2 includes a normal path. For example, the first path portion V1 includes a large-area heat dissipation path or the like formed for heat dissipation purposes. Furthermore, the second path portion V2 includes a path (e.g., a signal transmission path) with a width smaller than the width of the first path portion V1.

[0055] In this case, the embodiment has the characteristic of a large area of ​​passage, and therefore the first passage portion V1 of the comparative example will be described in comparison.

[0056] The first passage portion V1 includes a plurality of passages that are spaced apart from each other while being connected together to the first pad 20 and the second pad 30.

[0057] Each of the plurality of paths constituting the first path portion V1 is a large-area path. For example, the circuit board of the comparative example includes large-area paths. In addition, large-area paths have a larger area than normal paths. For example, the first path portion V1 includes a plurality of large-area paths whose width in a first direction (e.g., longitudinal direction) is greater than their width in a second direction (e.g., width direction).

[0058] The first passage portion V1, as described above, is formed by filling the interior of the passage hole with a metallic material. In this case, it is difficult to completely fill the interior of the passage hole in a large-area passage as described above in a single electroplating process. For example, when a large-area passage is formed by filling the interior of the passage hole with only one electroplating process, a pit is generated in the third direction (e.g., in the thickness direction) of the entire area of ​​the second pad 30 in the area overlapping with the first passage portion V1. A pit means that the central portion of the first passage portion V1 or the upper surface of the second pad 30 overlapping with the first passage portion V1 in the third direction is not flat but concave.

[0059] Therefore, in the comparative example, a plurality of electroplating processes are performed to form the first pass portion V1 and the second pad 30.

[0060] Specifically, the second pad 30 and the first passage portion V1 are integrally formed together. For example, the second pad 30 and the first passage portion V1 are formed by performing at least five or more electroplating processes on the passage hole and the second surface of the insulating layer 10.

[0061] That is, when the large-area first passage portion V1 and the second pad 30 are formed, the large-area passage hole constituting the first passage portion V1 is not only completely filled by one or two electroplating processes, but also pits are generated in the first passage portion V1 and the second pad 30. Therefore, when forming the first passage portion V1 and the second pad 30 in the comparative example, at least 5 electroplating processes are performed to form the first passage portion V1 and the second passage portion V2.

[0062] In this case, the via hole used to configure the first passage portion V1 in the comparative example is formed only by considering the size of the area (e.g., heat dissipation area) that forms the first passage portion V1. That is, the size of the via hole constituting the first passage portion V1 in the comparative example is determined by the area width.

[0063] Specifically, the plurality of first passage portions V1 have a strip shape that extends in a first direction (e.g., longitudinal direction) and is spaced apart from each other in a second direction (e.g., width direction).

[0064] That is, the first passage portion V1 includes a first-first passage V1-1, a first-second passage V1-2, a first-third passage V1-3, a first-fourth passage V1-4, a first-fifth passage V1-5, and a first-sixth passage V1-6 spaced apart from each other in a second direction (e.g., in the width direction). The first-first passage V1-1, the first-second passage V1-2, the first-third passage V1-3, the first-fourth passage V1-4, the first-fifth passage V1-5, and the first-sixth passage V1-6 are arranged to be spaced apart from each other in the insulating layer 10 in a second direction (e.g., in the width direction).

[0065] Here, the width W1 of each of the first-first passage V1-1, the first-second passage V1-2, the first-third passage V1-3, the first-fourth passage V1-4, the first-fifth passage V1-5 and the first-sixth passage V1-6 in the first direction (e.g., the longitudinal direction) is determined by the width of the area in the first direction.

[0066] That is, the first passage portion V1 in the comparative example is formed only with regard to heat dissipation characteristics, and therefore, the width W1 of each of the first-first passage V1-1, the first-second passage V1-2, the first-third passage V1-3, the first-fourth passage V1-4, the first-fifth passage V1-5 and the first-sixth passage V1-6 in the first direction (e.g., the longitudinal direction) is the same as the width of the area in the first direction.

[0067] For example, when the width of the area in the first direction (e.g., the longitudinal direction) is 1000 μm, the first width W1 of each of the passages constituting the first passage portion V1 in the first direction (e.g., the longitudinal direction) corresponds to 1000 μm. For example, when the width of the area in the first direction (e.g., the longitudinal direction) is 2000 μm, the first width W1 of each of the passages constituting the first passage portion V1 in the first direction (e.g., the longitudinal direction) corresponds to 2000 μm. For example, when the width of the area in the first direction (e.g., the longitudinal direction) is 3000 μm, the first width W1 of each of the passages constituting the first passage portion V1 in the first direction (longitudinal direction) corresponds to 3000 μm. In this case, a normal circuit board has a width of 2430 μm or more in the first direction of the area, and in the comparative example, each passage constituting the first passage portion V1 has a width of 2430 μm or more in the first direction (e.g., the longitudinal direction).

[0068] Therefore, the first width W1 of each passage constituting the first passage portion V1 in the first direction (e.g., the longitudinal direction) is maximized in the comparative example, and therefore, there is a problem that it is highly susceptible to pitting.

[0069] For example, when the first width W1 in the first direction (e.g., the longitudinal direction) exceeds a predetermined level or is greater than the height of each passage constituting the first passage portion V1, the size of the pit generated in the process of electroplating the first passage portion V1 increases significantly.

[0070] Therefore, the problem with the comparative example is that the number of electroplating processes used for the first pass portion V1 is increased.

[0071] For example, generally speaking, the plurality of channels constituting the first channel portion V1 are formed simultaneously by an electroplating process. That is, even if the number of the plurality of channels constituting the first channel portion V1 increases, the number of electroplating processes used to form the plurality of channels does not increase.

[0072] However, considering only the width of the area in the first direction (e.g., the longitudinal direction) to determine the width of the passage constituting the first passage portion V1 in the comparative example, the number of electroplating processes used to form the plurality of passages is greatly increased. For example, as described above, the size of the pit increases as the width of the passage constituting the first passage portion V1 increases in the first direction (e.g., the longitudinal direction). Therefore, the number of electroplating processes increases to remove the pit. Specifically, when the width of the passage constituting the first passage portion V1 in the first direction (e.g., the longitudinal direction) exceeds 2000 μm, at least four or more electroplating processes are performed in the comparative example to completely remove the pit.

[0073] At this time, a normal circuit board has a multilayer structure, and therefore, the electroplating process described above should be performed four or more times for each layer. For example, when the number of insulating layers is 10 and the number of electroplating processes for removing the pits of the passage for each layer is 4, the problem with the comparative example is that 40 electroplating processes must be performed to form the passage portion on a circuit board. Therefore, the problem with the comparative example is that the product yield decreases as the number of electroplating processes for removing the pits increases. In addition, when the number of electroplating processes for forming the first passage portion V1 increases, the problem with the comparative example is that the number or thickness of the grinding processes performed to planarize the upper surface of the second pad 30 increases.

[0074] Therefore, embodiments including large-area channels limit the width of the large-area channels in a first direction (e.g., longitudinal direction) based on the height of the large-area channels. Embodiments reduce the number of electroplating processes used to form the channel portions, thereby increasing product yield.

[0075] FIG2 is a cross-sectional view of the circuit board according to the embodiment, FIG3 is a plan view of a specific layer of the circuit board of FIG2, FIG4 is a detailed plan view of the passage area of ​​FIG3, FIG5 is a detailed view of the passage area of ​​FIG3, and FIG6 is a view for explaining the processing conditions of the passage hole in the embodiment.

[0076] In the following, the circuit board according to the embodiment will be described in detail with reference to Figures 2 to 6.

[0077] The circuit board of the embodiment includes an insulating layer, a circuit pattern layer, a via portion, and a protective layer. The via portion includes a large-area via portion. For example, the via portion includes a large-area via portion in which the width in a first direction (e.g., longitudinal direction) is greater than the width in a second direction (e.g., width direction). For example, the large-area via portion may include a large-area via whose width in the first direction (e.g., longitudinal direction) is at least twice the width in the second direction (e.g., width direction). In this case, the embodiment allows for a reduction in the number of electroplating processes to form a via portion consisting of a large-area via and pads connected thereto. Therefore, in the following, the large-area vias and pads of the circuit pattern layer connected thereto included in the circuit board will be described primarily. However, the embodiment is not limited thereto, and in addition to the large-area via portion and pads connected thereto, the circuit board may further include at least one of traces, normal-sized vias, die mount pads, core pads, and BGA pads.

[0078] The insulating layer 110 may have a planar structure. Although the insulating layer 110 is illustrated in the figures as consisting of four layers, the embodiment is not limited thereto. For example, the circuit board may include three or fewer insulating layers, and alternatively, it may include five or more insulating layers.

[0079] The insulating layer 110 forms a substrate on which a circuit capable of altering wiring is formed, and may include a printed circuit board, wiring board and insulating substrate made of any insulating material capable of forming circuit patterns on its surface.

[0080] For example, the insulating layer 110 may be rigid or flexible. For example, the insulating layer 110 may include glass or plastic. Specifically, the insulating layer 110 may include: chemically strengthened / semi-strengthened glass, such as soda lime glass or aluminosilicate glass; or strengthened or flexible plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or sapphire.

[0081] Additionally, the insulating layer 110 may include an optically isotropic film. For example, the insulating layer 110 may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), or an optically isotropic polymethyl methacrylate (PMMA).

[0082] Furthermore, the insulating layer 110 may be formed of a material including inorganic fillers and insulating resins. For example, as materials constituting the insulating layer 110, thermosetting resins such as epoxy resins and resins containing reinforcing materials such as inorganic fillers (such as silicon dioxide and alumina) and thermoplastic resins such as polyimide may be used. Specifically, Ajinomoto Build-up Film (ABF), FR-4, Bismalleimide Triazine (BT), Photo Imagable Dielectric Resin (PID), BT, etc.

[0083] In addition, the insulating layer 110 may be curved when it has a partially curved surface. That is, the insulating layer 110 may be curved when it has a partially flat surface and a partially curved surface. Specifically, the insulating layer 110 may be curved when it has curved ends or a surface including random curvature, and may be curved or curved.

[0084] This insulating layer 110 may include a first insulating layer 111, a second insulating layer 112 disposed on a second surface of the first insulating layer 111, a third insulating layer 113 disposed on a second surface of the second insulating layer 112, and a fourth insulating layer 114 disposed on a second surface of the third insulating layer 113. The first surface may be an upper surface, and the second surface may be a lower surface, but is not limited thereto.

[0085] The circuit pattern layer may be placed on the surface of the insulating layer 110.

[0086] For example, a first circuit pattern layer 121 may be disposed on a first surface of a first insulating layer 111. For example, a second circuit pattern layer 122 may be disposed on a second surface of a first insulating layer 111 or a first surface of a second insulating layer 112. For example, a third circuit pattern layer 123 may be disposed on a second surface of a second insulating layer 112 or a first surface of a third insulating layer 113. For example, a fourth circuit pattern layer 124 may be disposed on a second surface of a third insulating layer 113 or a first surface of a fourth insulating layer 114. For example, a fifth circuit pattern layer 125 may be disposed on a second surface of a fourth insulating layer 114.

[0087] The circuit pattern layer described above may be wiring for transmitting electrical signals. Alternatively, the circuit pattern layer described above may be a heat transfer pad. For this purpose, the circuit pattern layer described above may be formed of a metallic material with high electrical conductivity or high thermal conductivity.

[0088] For this purpose, the circuit pattern layer may be formed from at least one metallic material selected from the following: gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Alternatively, the circuit pattern layer may be formed from a paste or solder paste containing one of the metallic materials selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) and possessing excellent bonding strength. Preferably, the circuit pattern layer may be formed from copper (Cu), which has high conductivity and a relatively low price.

[0089] The circuit pattern layer can be formed by additive, subtractive, modified semi-additive process (MSAP) and semi-additive process (SAP), which are typical printed circuit board manufacturing processes and will be omitted in detail herein.

[0090] On the other hand, the circuit pattern layer includes pads (P). For example, the first circuit pattern layer 121 may include pads P1 and P2. For example, the second circuit pattern layer 122 may include pads P1 and P2. For example, the third circuit pattern layer 123 may include pads P1 and P2. For example, the fourth circuit pattern layer 124 may include pads P1 and P2. For example, the fifth circuit pattern layer 125 may include pads P1 and P2. Pads P1 and P2 may be pass pads. For example, pads P1 and P2 may be formed in areas that overlap with the first pass portion V1 and the second pass portion V2 in a third direction (e.g., the thickness direction), as will be described later. For example, pads P1 and P2 may be directly connected to the first pass portion V1 and the second pass portion V2, as will be described later.

[0091] At the same time, the passage portion can be formed to pass through the insulating layer 110.

[0092] For example, the passage portion may be formed to pass through the first insulating layer 111. For example, the passage portion may be formed to pass through the second insulating layer 112. For example, the passage portion may be formed to pass through the third insulating layer 113. For example, the passage portion may be formed to pass through the fourth insulating layer 114.

[0093] The passage portion passing through each insulating layer may include a first passage portion V1 and a second passage portion V2. The first passage portion V1 and the second passage portion V2 may be classified according to their size. For example, the size of the first passage portion V1 may be larger than the size of the second passage portion V2. For example, the width of the first passage portion V1 in a first direction may be greater than the width of the second passage portion V2 in a second direction. For example, the area of ​​the first passage portion V1 may be larger than the area of ​​the second passage portion V2. For example, the area of ​​the first passage portion V1 may be at least twice the area of ​​the second passage portion V2. For example, the first passage portion V1 may be a large-area passage, and the second passage portion V2 may be a normal passage. For example, the first passage portion V1 may be a heat dissipation passage or a shielding passage with heat dissipation or shielding functions, and the second passage portion V2 may be a signal transmission passage with signal transmission functions, but is not limited thereto.

[0094] That is, the first passage portion V1 can be disposed in each insulating layer. For example, the first passage portion V1 can be a part of the passage portion 131 disposed in the first insulating layer 111. For example, the first passage portion V1 can be a part of the passage portion 132 disposed in the second insulating layer 112. For example, the first passage portion V1 can be a part of the passage portion 133 disposed in the third insulating layer 113. For example, the first passage portion V1 can be a part of the passage portion 134 disposed in the fourth insulating layer 114.

[0095] In this case, the circuit board of the embodiment is in the design or structure of the first pass portion V1, and therefore the first pass portion V1 will be described in more detail. Meanwhile, the first pass portion V1 described below can be any of the pass portions disposed in a plurality of insulating layers.

[0096] Therefore, the first pass portion V1 formed in any of the first to fourth insulating layers will be described in detail below.

[0097] In the following description, the first passage portion V1 formed in the first insulating layer 111 will be mainly described. However, the first passage portion V1 formed by the first insulating layer 111 described below may be formed in at least one of the second insulating layer 112, the third insulating layer 113 and the fourth insulating layer 114.

[0098] The first passage portion V1 can be connected to the first pad P1 formed on the first and second surfaces of the first insulating layer 111. In addition, the second passage portion V2 can be connected to the second pad P2 formed on the first and second surfaces of the first insulating layer 111.

[0099] For example, the first-first-first-paste P1-1 of the first pad P1 may be formed on the first surface of the first insulating layer 111. In addition, the first-second-paste P1-2 of the first pad P1 may be formed on the second surface of the first insulating layer 111 opposite to the first surface.

[0100] The first passage portion V1 is disposed through the first insulating layer 111, and therefore, the first passage portion V1 can be connected to the first-first pad P1-1 and the first-second pad P1-2. For example, the first surface of the first passage portion V1 can be directly connected to or in direct contact with the first-first pad P1-1. For example, the second surface of the first passage portion V2 can be directly connected to or in direct contact with the first-second pad P1-2.

[0101] Accordingly, the second-first pad (not shown) of the second pad P2 may be formed on the first surface of the first insulating layer 111, and the second-second pad (not shown) of the second pad P2 may be formed on the second surface of the first insulating layer 111. Therefore, the second passage portion V2 may be directly connected to or in direct contact with the second-first pad and the second-second pad of the second pad P2.

[0102] The first passage portion V1 may be formed in a specific area of ​​the first insulating layer 111. For example, the first passage portion V1 may be formed in a heat dissipation area of ​​the first insulating layer 111. Here, the heat dissipation area may be an area for dissipating heat generated by the chip mounted on the circuit board of the embodiment to the outside. For example, the chip may be mounted on the outermost or inner side of the circuit board. In addition, the heat dissipation area may mean an area that overlaps with the mounted chip in the thickness direction. However, the embodiment is not limited to this, and the first passage portion V1 may be disposed in an area other than the heat dissipation area.

[0103] For example, the first insulating layer 111 may include a first region R1 and a second region R2 on which the first passage portion V1 is disposed. Furthermore, the first passage portion V1 may be formed in the first region R1 and the second region R2 of the first insulating layer 111, respectively. For example, as shown in FIG3, a first pad P1 is formed on the first insulating layer 111. The first pad P1 may mean a first-first pad P1-1 disposed on a first surface of the first insulating layer 111, or it may mean a first-second pad P1-2 disposed on a second surface of the first insulating layer 111.

[0104] In addition, the trace T1 for the extension line used to transmit signals may be formed on the first surface or the second surface of the first insulating layer 111.

[0105] The first passage portion V1 may include a plurality of passages spaced apart from each other. The first passage portion V1 may be formed by forming a plurality of passage holes through the first insulating layer 111 and simultaneously filling the interior of the formed passage holes with a conductive material.

[0106] The via can be formed by any of the following processing methods, including mechanical, laser, and chemical treatment. When forming the via by processing, methods such as grinding, drilling, and wiring can be used; when forming the via by laser treatment, UV or CO2 laser methods can be used; and when forming the via by chemical treatment, drugs including aminosilanes and ketones can be used, thereby opening at least one of the plurality of insulating layers.

[0107] On the other hand, laser processing is used as a cutting method, in which light energy is concentrated on the surface to melt and evaporate a portion of the material to obtain the desired shape, and it can easily process complex formations by computer programs, and can process composite materials that are difficult to cut by other methods.

[0108] In addition, laser processing can have a cutting diameter of at least 0.005 mm and has a wide range of advantages in the possible thickness range.

[0109] For laser-processed drilling, yttrium aluminum garnet (YAG) lasers, CO2 lasers, or ultraviolet (UV) lasers are preferred. YAG lasers can process both copper foil layers and insulating layers, while CO2 lasers can process only the insulating layer.

[0110] When forming a via, a first via portion V1 can be formed by filling the interior of the via with a conductive material. The metal material forming the first via portion V1 can be any material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni) and palladium (Pd), and the conductive material can be filled by any of the following methods: electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet printing and dispensing.

[0111] Meanwhile, the first passage portion V1 may include a plurality of passages having a strip shape extending in a first direction (length direction). In addition, the plurality of passages constituting the first passage portion V1 may be spaced apart from each other in a second direction (width direction) perpendicular to the first direction (length direction).

[0112] For example, the first passage portion V1 includes a plurality of first passages spaced apart from each other in the second direction (width direction). For example, the plurality of first passages constituting the first passage portion V1 may include a first-first passage V1-1, a first-second passage V1-2, a first-third passage V1-3, a first-fourth passage V1-4, a first-fifth passage V1-5, and a first-sixth passage V1-6.

[0113] In this case, each of the first-first passage V1-1, the first-second passage V1-2, the first-third passage V1-3, the first-fourth passage V1-4, the first-fifth passage V1-5 and the first-sixth passage V1-6 may have a strip shape that extends in the first direction (length direction).

[0114] In this case, each of the first-first pathway V1-1, the first-second pathway V1-2, the first-third pathway V1-3, the first-fourth pathway V1-4, the first-fifth pathway V1-5 and the first-sixth pathway V1-6 may include the first sub-pathway V1A and the second sub-pathway V1B.

[0115] For example, the first-first passage V1-1 may include a first sub-passage V1A and a second sub-passage V1B spaced apart from each other in the first direction (length direction). For example, the first-second passage V1-2 may include a first sub-passage V1A and a second sub-passage V1B spaced apart from each other in the first direction (length direction). For example, the first-third passage V1-3 may include a first sub-passage V1A and a second sub-passage V1B spaced apart from each other in the first direction (length direction). For example, the first-fourth passage V1-4 may include a first sub-passage V1A and a second sub-passage V1B spaced apart from each other in the first direction (length direction). For example, the first-fifth passage V1-5 may include a first sub-passage V1A and a second sub-passage V1B spaced apart from each other in the first direction (length direction). For example, the first-sixth passage V1-6 may include a first sub-passage V1A and a second sub-passage V1B spaced apart from each other in the first direction (length direction).

[0116] Therefore, the first sub-paths V1A of each of the paths constituting the first path portion V1 can be spaced apart from each other in the second direction (width direction). In addition, correspondingly, the second sub-paths V1B of each of the paths constituting the first path portion V1 can be spaced apart from each other in the second direction (width direction).

[0117] In summary, the first passage portion V1 of the embodiment includes a plurality of first passages spaced apart from each other in the second direction. Furthermore, each of the plurality of first passages includes a first sub-passage V1A and a second sub-passage V1B extending in the first direction. Additionally, each of the first sub-passage V1A and the second sub-passage V1B is a large-area passage having a strip shape with a width in the first direction greater than its width in the second direction.

[0118] In this case, the width of the first surface of each of the first sub-channel V1A and the second sub-channel V1B is different from the width of its second surface. For example, a via hole constituting the first sub-channel V1A and the second sub-channel V1B can be formed by a laser process. In this case, the width of the portion directly contacted by the laser is greater than the width of the opposite portion due to the characteristics of the laser process. For example, a laser can be disposed on the first surface of the first insulating layer 111 to form a via hole through the first insulating layer 111. In this case, the first surface of the first insulating layer 111 is positioned close to the laser. Therefore, the width of the first surface of the via hole formed in the first insulating layer 111 is greater than the width on its second surface. For example, the via hole has an inverted trapezoidal shape, wherein the width of the first surface is greater than the width of the second surface due to the characteristics of the laser process. Therefore, the width of the first surface of the first sub-channel V1A (e.g., the upper width) is greater than the width of the second surface of the first sub-channel V1A (e.g., the lower width). Furthermore, the width of the first surface of the second sub-channel V1B is greater than the width of the second surface. Therefore, the width of the channel described below may refer to the width on the first surface having a relatively wide width (e.g., the upper width of the first channel portion disposed in the first insulating layer).

[0119] Meanwhile, each of the pathways constituting the first pathway portion V1 in the embodiment is configured as a plurality of sub-paths spaced apart from each other in the first direction (length direction). For example, each of the plurality of first pathways constituting the first pathway portion V1 in the embodiment includes a plurality of sub-paths spaced apart from each other in the first direction (length direction). For example, the comparative example does not include a plurality of sub-paths as in the embodiment, but includes an integrated pathway made of a single pathway. However, when the width of the pathway is not considered at all as in the comparative example, the pit size increases with the increase of the pathway width, and therefore, there is a problem of an increase in the number of electroplating processes.

[0120] On the other hand, the embodiment forms a plurality of sub-paths instead of a single path in the first direction (length direction) in order to minimize the pits in the path. Therefore, the embodiment can reduce the pit size during the electroplating process by having a plurality of sub-path structures instead of a single integrated structure, as in the comparative example, and thus the number of electroplating processes can be reduced.

[0121] For example, when the width of the area of ​​the first passage portion V1 in the embodiment in the first direction (longitudinal direction) exceeds 25 times the thickness H1a of the first insulating layer 111, at least two sub-passages can be arranged in the first direction (length direction) instead of one passage.

[0122] For example, when the width of the area of ​​the first passage portion V1 in the first direction (longitudinal direction) exceeds 21 times the thickness H1a of the first insulating layer 111, at least two sub-passages can be arranged in the first direction (length direction) instead of one passage. For example, when the width of the area of ​​the first passage portion V1 in the first direction (longitudinal direction) exceeds 19 times the thickness H1a of the first insulating layer 111, at least two sub-passages can be arranged in the first direction (length direction) instead of one passage. For example, when the width of the area of ​​the first passage portion V1 in the first direction (longitudinal direction) exceeds 17 times the thickness H1a of the first insulating layer 111, at least two sub-passages can be arranged in the first direction (length direction) instead of one passage. For example, when the width of the area of ​​the first passage portion V1 in the first direction (longitudinal direction) exceeds 15 times the thickness H1a of the first insulating layer 111, at least two sub-passages can be arranged in the first direction (length direction) instead of one passage.

[0123] For example, the width W1 of the first sub-path V1A constituting each of the first paths in the first direction (length direction) does not exceed 25 times the thickness H1a of the first insulating layer 111. For example, the width W1 of the first sub-path V1A constituting each of the first paths in the first direction (length direction) does not exceed 21 times the thickness H1a of the first insulating layer 111. For example, the width W1 of the first sub-path V1A constituting each of the first paths in the first direction (length direction) does not exceed 19 times the thickness H1a of the first insulating layer 111. For example, the width W1 of the first sub-path V1A constituting each of the first paths in the first direction (length direction) does not exceed 17 times the thickness H1a of the first insulating layer 111. For example, the width W1 of the first sub-path V1A constituting each of the first paths in the first direction (length direction) does not exceed 15 times the thickness H1a of the first insulating layer 111.

[0124] For example, the width W1 of the second sub-path V1B constituting each of the first paths in the first direction (length direction) does not exceed 25 times the thickness H1a of the first insulating layer 111. For example, the width W1 of the second sub-path V1B constituting each of the first paths in the first direction (length direction) does not exceed 21 times the thickness H1a of the first insulating layer 111. For example, the width W1 of the second sub-path V1B constituting each of the first paths in the first direction (length direction) does not exceed 19 times the thickness H1a of the first insulating layer 111. For example, the width W1 of the second sub-path V1B constituting each of the first paths in the first direction (length direction) does not exceed 17 times the thickness H1a of the first insulating layer 111. For example, the width W1 of the second sub-path V1B constituting each of the first paths in the first direction (length direction) does not exceed 15 times the thickness H1a of the first insulating layer 111.

[0125] Meanwhile, as described above, the width of the first surface of each of the first sub-path V1A and the second sub-path V1B may be greater than the width of the second surface. That is, the upper width of the first sub-path V1A and the second sub-path V1B disposed in the first insulating layer 111 may be greater than their lower width. In addition, the width W1 of each of the first sub-path V1A and the second sub-path V1B may mean a relatively larger upper width.

[0126] For example, the thickness H1a of the first insulating layer 111 may be 40 μm to 70 μm. For example, the thickness H1a of the first insulating layer 111 may be 45 μm to 65 μm. For example, the thickness H1a of the first insulating layer 111 may be 50 μm to 60 μm.

[0127] In this case, the width of the first region R1, where the first passage portion V1 is disposed, in the first direction (length direction) can be 2430 μm, which is 21 times larger than the thickness H1a of the first insulating layer 111. Here, the width of the first passage of the first passage portion V1 in the comparative example in the first direction (length direction) is 2430 μm, which corresponds to the width of the first region R1 in the first direction (length direction). In this case, as described above, when the width of the first passage in the first direction (length direction) exceeds 21 times the thickness H1a of the first insulating layer 111, the pit size increases, and there is a problem of an increase in the number of electroplating processes, thereby complicating the manufacturing process.

[0128] Meanwhile, the thickness H1a of the first insulating layer 111 may correspond to the distance or length in the third direction (thickness direction) between the circuit pattern layers disposed on its first and second surfaces. For example, the thickness H1a of the first insulating layer 111 may correspond to the distance or length between the lower surface of the first circuit pattern layer 121 and the upper surface of the second circuit pattern layer 122.

[0129] The thickness of each of the second insulating layer 112, the third insulating layer 113 and the fourth insulating layer 114 may correspond to the thickness H1a of the first insulating layer 111.

[0130] The thickness H1b of the second insulating layer 112 may correspond to the thickness H1a of the first insulating layer 111. For example, the thickness H1b of the second insulating layer 112 may correspond to the distance or length between the lower surface of the second circuit pattern layer 122 and the third circuit pattern layer 123. For example, the thickness H1b of the second insulating layer 112 may be 40 μm to 70 μm. For example, the thickness H1b of the second insulating layer 112 may be 45 μm to 65 μm. For example, the thickness H1b of the second insulating layer 112 may be 50 μm to 60 μm.

[0131] The thickness H1c of the third insulating layer 113 may correspond to the thickness H1a of the first insulating layer 111. For example, the thickness H1c of the third insulating layer 113 may correspond to the distance or length between the lower surface of the third circuit pattern layer 123 and the upper surface of the fourth circuit pattern layer 124. For example, the thickness H1c of the third insulating layer 113 may be 40 μm to 70 μm. For example, the thickness H1c of the third insulating layer 113 may be 45 μm to 65 μm. For example, the thickness H1c of the third insulating layer 113 may be 50 μm to 60 μm.

[0132] The thickness H1d of the fourth insulating layer 114 may correspond to the thickness H1a of the first insulating layer 111. For example, the thickness H1d of the fourth insulating layer 114 may correspond to the distance or length between the lower surface of the fourth circuit pattern layer 124 and the upper surface of the fifth circuit pattern layer 125. For example, the thickness H1d of the fourth insulating layer 114 may be 40 μm to 70 μm. For example, the thickness H1d of the fourth insulating layer 114 may be 45 μm to 65 μm. For example, the thickness H1d of the fourth insulating layer 114 may be 50 μm to 60 μm.

[0133] Therefore, the first passage constituting the first passage portion V1 in the embodiment described above is configured in at least two lines including a plurality of sub-passages rather than in one line, making it possible to simplify the manufacturing process by minimizing the pit size generated in each passage, and thereby reducing the number of electroplating processes.

[0134] For example, when the thickness H1a of the first insulating layer 111 is 55 μm, the width of the plurality of first channels constituting the first channel portion V1 in the first direction (length direction) does not exceed 1385 μm.

[0135] At the same time, the width of the first region R1 in the first direction (length direction) can also be limited to the width W5 of the first pad P1 connected to the first passage portion V1 in the first direction (length direction).

[0136] For example, when the width W5 of the first pad P1 connected to the first passage portion V1 in the first direction (length direction) exceeds 15 times the thickness H1a of the first insulating layer 111, each of the first passages constituting the first passage portion V1 includes a first sub-passage V1A and a second sub-passage V1B. For example, when the width W5 of the first pad P1 connected to the first passage portion V1 in the first direction (length direction) exceeds 17 times the thickness H1a of the first insulating layer 111, each of the first passages constituting the first passage portion V1 includes a first sub-passage V1A and a second sub-passage V1B. For example, when the width W5 of the first pad P1 connected to the first passage portion V1 in the first direction (length direction) exceeds 19 times the thickness H1a of the first insulating layer 111, each of the first passages constituting the first passage portion V1 includes a first sub-passage V1A and a second sub-passage V1B. For example, when the width W5 of the first pad P1 connected to the first passage portion V1 in the first direction (length direction) exceeds 21 times the thickness H1a of the first insulating layer 111, each of the first passages constituting the first passage portion V1 includes a first sub-passage V1A and a second sub-passage V1B. For example, when the width W5 of the first pad P1 connected to the first passage portion V1 in the first direction (length direction) exceeds 25 times the thickness H1a of the first insulating layer 111, each of the first passages constituting the first passage portion V1 includes a first sub-passage V1A and a second sub-passage V1B. Therefore, compared to the comparative example, the embodiment can reduce the number of electroplating processes used to form the first passage portion V1.

[0137] For example, when a via with a width of 2000 μm in the first direction (longitudinal direction) is completely filled to form a via, the comparative example requires at least five electroplating processes. In contrast, by completely filling two vias with a width of 1000 μm in the first direction (length direction) to form two sub-vias in the embodiment, only two or three electroplating processes can be performed for this purpose. Therefore, in the above case, compared with the comparative example in one layer, the embodiment can reduce the number of electroplating processes by at least one. Furthermore, the embodiment can further reduce the number of electroplating processes compared with the comparative example as the number of layers of the circuit board increases.

[0138] Simultaneously, the width W2 of the first sub-path V1A or the second sub-path V1B constituting each of the first paths in the first path portion V1 in the second direction can be determined by the processing conditions of the via hole corresponding to the first sub-path V1A or the second sub-path V1B. For example, when the via hole is formed by laser processing, the width W2 in the second direction can be determined by the size of the laser processing point. For example, the width W2 of the first sub-path V1A or the second sub-path V1B in the second direction can be 70 μm to 130 μm. For example, the width W2 of the first sub-path V1A or the second sub-path V1B in the second direction can be 80 μm to 120 μm. For example, the width W2 of the first sub-path V1A or the second sub-path V1B in the second direction can be 90 μm to 110 μm.

[0139] Simultaneously, the first sub-path V1A and the second sub-path V1B of each of the first paths constituting the first path portion V1 may be spaced apart by a first interval W3. In this case, the first interval W3 may be smaller than the width W2 of the first sub-path V1A or the second sub-path V1B in the second direction. For example, the first interval W3 may be 40 μm to 100 μm. For example, the first interval W3 may be 50 μm to 90 μm. For example, the first interval W3 may be 60 μm to 80 μm.

[0140] Simultaneously, each of the first passages constituting the first passage portion V1 may be spaced apart from each other in the second direction as described above. In this case, each of the first passages constituting the first passage portion V1 may be spaced apart from each other in the second direction by a second interval W4. In this case, the second interval W4 may be a spacing interval between sub-passages that are adjacent to each other in the second direction. For example, the second interval W4 may mean the spacing interval between the first sub-passage V1A of the first-first passage V1-1 and the first sub-passage V1A of the first-second passage V1-2.

[0141] In this case, the second interval W4 may be larger than the first interval W3. For example, the second interval W4 may be 45 μm to 105 μm. For example, the second interval W4 may be 55 μm to 95 μm. For example, the second interval W4 may be 65 μm to 85 μm.

[0142] This can be considered as the processing conditions for the vias constituting the first passage portion V1. That is, referring to FIG6, a plurality of vias for forming the first passage portion V1 in the embodiment are formed in the first insulating layer 111. In this case, the vias can be as follows.

[0143] The via may include a first-first-passage via VHA1-1 corresponding to the first sub-passage V1A of the first-first-passage V1-1 of the first passage portion V1. Additionally, the via may include a first-second-passage via VHB1-1 corresponding to the second sub-passage V1B of the first-first-passage V1-1 of the first passage portion V1. Furthermore, the via may include a second-first-passage via VHA1-2 corresponding to the first sub-passage V1A of the first-second-passage V1-2 of the first passage portion V1. Additionally, the via may include a second-second-passage via VHB1-2 corresponding to the second sub-passage V1B of the first-second-passage V1-1 of the first passage portion V1.

[0144] At this time, a first-first-passage hole VHA1-1, a first-second-passage hole VHB1-1, a second-first-passage hole VHA1-2, and a second-second-passage hole VHB1-2 can be formed by laser processing point LP. The laser processing point LP has a diameter corresponding to the width W2 in a second direction of the first sub-passage V1A or the second sub-passage V1A, as described above. In this case, the laser processing point LP can be circular. Therefore, the laser processing process should be performed while moving the laser processing point LP in the first direction to form a strip-shaped passage hole that extends in the first direction. For example, laser processing is performed at a plurality of processing points while moving the laser processing point LP in the first direction to form a passage hole. For example, as shown in FIG6, the laser process should be performed at 23 laser processing points to form a passage hole. At this time, the laser process has processing errors according to process characteristics, and therefore, the first interval W3 and the second interval W4 are adjusted so that adjacent passages are not connected to each other.

[0145] In this case, of the first-first-pass hole VHA1-1, the first-second-pass hole VHB1-1, the second-first-pass hole VHA1-2, and the second-second-pass hole VHB1-2, the first-first-pass hole VHA1-1 is spaced apart from the first-second-pass hole VHB1-1 in the first direction. Furthermore, the first-first-pass hole VHA1-1 is spaced apart from the second-first-pass hole VHA1-2 in the second direction. Furthermore, the second-first-pass hole VHA1-2 is spaced apart from the second-second-pass hole VHB1-2 in the first direction. Furthermore, the first-second-pass hole VHB1-1 is spaced apart from the second-second-pass hole VHB1-2 in the second direction. Here, the processing error to be considered differs depending on the direction of separation. For example, when the passage holes are spaced apart from each other in the first direction, the processing error can be considered at only one processing point. Alternatively, when the passage holes are spaced apart from each other in the second direction, the processing error can be considered at all processing points (e.g., 23 processing points).

[0146] For example, the laser processing of the first-first-pass hole VHA1-1 and the first-second-pass hole VHB1-1 can be prevented from being connected to each other by the following: the first interval W3 is determined by considering only the processing error of the first end point E1, which is the last processing point of the first-first-pass hole VHA1-1, and the first start point S1, which is the first processing point of the first-second-pass hole VHB1-1.

[0147] Similarly, the laser processing of the second-first access hole VHA1-2 and the second-second access hole VHB1-2 can be prevented from being connected to each other by determining the first interval W3 by only considering the processing error of the second end point E2, which is the last processing point of the second-first access hole VHA1-2, and the second start point S2, which is the first processing point of the second-second access hole VHB1-2.

[0148] In other words, in the case of the first interval W3, the processing error can be considered only for one laser processing point, and thus can be set to be less than the second interval W4.

[0149] In contrast, the second interval W4 used to prevent the first-first access hole VHA1-1 and the second-first access hole VHA1-2 from connecting with each other should be set by taking into account the processing errors at all processing points (e.g., 23 processing points) of the first-first access hole VHA1-1 and the processing errors at all processing points (e.g., 23 processing points) of the second-first access hole VHA1-2.

[0150] For example, the second interval W4 used to prevent the first-second passage hole VHB1-1 and the second-second passage hole VHB1-2 from connecting with each other should be set by taking into account the processing errors at all processing points (e.g., 23 processing points) of the first-second passage hole VHB1-1 and the processing errors at all processing points (e.g., 23 processing points) of the second-second passage hole VHB1-2.

[0151] In other words, the second interval (W4) should be set taking into account the processing error of all laser processing points, and therefore, it can be set to be greater than the first interval W3.

[0152] Simultaneously, the gasket P1 of the embodiment is connected to each of the first surface and the second surface of the first passage portion V1. For example, the first-first gasket P1-1 of the embodiment is directly connected to or in contact with the first surface of the first passage portion V1. For example, the first-first gasket P1-1 of the embodiment is commonly connected to the first surface of each of the first passages constituting the first passage portion V1. For example, the first-first gasket P1-1 of the embodiment is commonly connected to the first surface of each of the first sub-passage V1A and the second sub-passage V1B of the first passage. For example, the first-second gasket P1-2 of the embodiment is directly connected to or in contact with the second surface of the first passage portion V1. For example, the first-second gasket P1-2 of the embodiment is commonly connected to the second surface of each of the first passages constituting the first passage portion V1. For example, in the embodiment, the first and second pads P1-2 are jointly connected to the second surface of each of the first sub-channel V1A and the second sub-channel V1B of the first passage.

[0153] As described above, each of the plurality of first passages constituting the first passage portion V1 of the embodiment is not composed of a single passage, but rather includes a plurality of sub-passages spaced apart from each other in a first direction. Therefore, compared with the comparative example, the embodiment can reduce the number of electroplating processes used to form the first passage portion V1.

[0154] Simultaneously, the first passage portion V1 of the embodiment can be formed by a plurality of electroplating processes. In this case, the first passage portion V1 and the first-first pad P1-1 can be integrally formed with each other. For example, the first passage portion V1 and the first-first pad P1-1 can be formed simultaneously by an electroplating process. Therefore, the first passage portion V1 and the first-first pad P1-1 can be substantially referred to as a single configuration. However, in the embodiment, the portion formed in the passage hole of the first insulating layer 111 in the plating formed by the electroplating process is called the first passage portion V1, and the portion formed on the first surface of the first insulating layer 111 and the first surface of the first passage portion is called the first-first pad P1-1.

[0155] The first-first pad P1-1 and the first passage portion V1 can be formed by a plurality of electroplating processes. For example, the first-first pad P1-1 and the first passage portion V1 can be formed by forming a plating layer according to two electroplating processes. Therefore, the first-first pad P1-1 and the first passage portion V1 may include a plurality of plating layers formed by a plurality of electroplating processes.

[0156] For example, the first-first pad P1-1 and the first passage portion V1 may include a seed layer, a first plating layer, a second plating layer and a third plating layer.

[0157] The seed layer may be a seed layer used to form the first plating layer, the second plating layer and the third plating layer by electroplating. The seed layer may be formed on the first surface of the first insulating layer 111 and on the inner wall of the through hole formed in the first insulating layer 111.

[0158] The seed layer may include a first portion 151 formed on the inner wall of the via hole and a second portion 152 formed on the first surface of the first insulating layer 111. In addition, the first portion 151 of the seed layer may constitute the first via portion V1. Furthermore, the second portion 152 of the seed layer may constitute the first-first pad P1-1.

[0159] A first plating layer can be formed by performing a primary electroplating using a seed layer. The first plating layer may include a first portion 161 formed on a first portion 151 of the seed layer and a second portion 162 formed on a second portion 152 of the seed layer. The first portion 161 of the first plating layer may constitute a first via portion V1. Additionally, the second portion 162 of the first plating layer may constitute a first-first pad P1-1. The first portion 161 of the first plating layer may partially fill the interior of the via hole. The second portion 162 of the first plating layer may be formed to have a predetermined height on the second portion 152 of the seed layer.

[0160] The first portion 161 of the first plating layer may include a concave portion. For example, the upper surface of the first portion 161 of the first plating layer may have a curved surface that is concave in a downward direction. In this case, the lowermost end of the upper surface of the first portion 161 of the first plating layer may be lower than the first surface of the first insulating layer 111. For example, the via formed in the first insulating layer 111 may not be completely filled by the first plating layer. For example, at least a portion of the via (e.g., the concave portion) may not be filled by the first portion 161 of the first plating layer.

[0161] The second coating may be formed on the first coating by performing secondary electroplating using a seed layer.

[0162] The second coating includes a first portion 171 formed on a first portion 161 of the first coating and a second portion 172 formed on a second portion 162 of the first coating. The first portion 171 of the second coating may fill the concave portion of the first portion 161 of the first coating. The first portion 171 of the second coating may constitute a first passage portion V1. In addition, the second portion 172 of the second coating may constitute a first-first gasket P1-1.

[0163] A third plating layer 180 may be formed on the second portion 162 of the first plating layer and the second portion 172 of the second plating layer. The third plating layer 180 may constitute the first-first pad P1-1. The third plating layer 180 may be formed on the second portion 162 of the first plating layer and the second portion 172 of the second plating layer by performing flash plating. The third plating layer 180 may be selectively formed to planarize the first surface of the first-first pad P1-1. For example, the third plating layer 180 may be formed non-selectively. However, it is preferable to form the third plating layer 180 for the reliability of the first-first pad P1-1. For example, when the third plating layer 180 is not formed, the first surface of the first-first pad P1-1 is divided into a portion corresponding to the second portion 162 of the first plating layer and a portion corresponding to the second portion 172 of the second plating layer. Furthermore, the divided portion may be considered as a stain. Therefore, in the embodiment, the third coating is formed on the second portion 162 of the first coating and the second portion 172 of the second coating to solve the staining problem as described above, while the first surface of the first-first pad P1-1 is flat.

[0164] Therefore, the first-first pad P1-1 can be divided into a plurality of regions.

[0165] For example, the first-first pad P1-1 may include a first pad region PR1 that overlaps with the first passage portion V1 in the third direction (thickness direction) and a second pad region PR2 other than the pad region PR1.

[0166] In this case, the first pad region PR1 and the second pad region PR2 may have different layer structures. For example, the layer constituting the first pad region PR1 may be different from the layer constituting the second pad region PR2. For example, the number of plating layers constituting the first pad region PR1 may be different from the number of plating layers constituting the second pad region PR2.

[0167] For example, the first pad region PR1 may include a first portion 151 of the seed layer, a first portion 161 of the first plating layer, a second portion 172 of the second plating layer, and a third plating layer 180. Alternatively, the second pad region PR2 may include a second portion 152 of the seed layer, a second portion 162 of the first plating layer, and a third plating layer 180. For example, the number of layers constituting the first pad region PR1 may be greater than the number of layers constituting the second pad region PR2.

[0168] As described above, the first passage of the first passage portion V1 in the embodiment is not in a single column, but is configured in at least two columns including a plurality of sub-passages while being spaced apart from each other in a first direction. Therefore, the embodiment minimizes the pit size generated in each passage and reduces the number of electroplating processes to simplify the manufacturing process.

[0169] At the same time, the circuit board includes a protective layer. The protective layer may be disposed on the outermost insulating layer of the circuit board. For example, the protective layer includes: a first protective layer 141 disposed on a first surface of a first insulating layer 111 which is the first outermost insulating layer; and a second protective layer 142 disposed on a second surface of a fourth insulating layer 114 which is the second outermost insulating layer.

[0170] The first protective layer 141 includes an opening (not shown) that exposes at least a portion of the first surface of the first circuit pattern layer 121 disposed on the first surface of the first insulating layer 111. The first protective layer 141 may be a solder resist, but is not limited thereto.

[0171] The second protective layer 142 includes an opening (not shown) that exposes at least a portion of the second surface of the fifth circuit pattern layer 125 disposed on the second surface of the fourth insulating layer 114. The second protective layer 142 may be a solder resist, but is not limited thereto.

[0172] FIG7 is a view showing the structure of the first passage portion according to the embodiment, and FIG8 is a view showing a modified example of the first passage portion of FIG7.

[0173] Referring to FIG7, as described above, the first path portion V1 in the embodiment may include a plurality of first paths spaced apart from each other in the second direction. In addition, the plurality of first paths may include a plurality of sub-paths spaced apart from each other in the first direction.

[0174] For example, the first path portion V1 may include a first-first path V1-1, a first-second path V1-2, a first-third path V1-3, a first-fourth path V1-4, a first-fifth path V1-5, a first-sixth path V1-6, a first-seventh path V1-7, a first-eighth path V1-8, a first-ninth path V1-9, a first-tenth path V1-10, a first-eleventh path V1-11, a first-twelfth path V1-12, a first-thirteenth path V1-13, a first-fourteenth path V1-14, and a first-fifteenth path V1-15, each containing a plurality of sub-paths. That is, the number of first paths including the first sub-path V1A and the second sub-path V1B in the embodiment can be determined by the width W6 of the first region R1 on which the first path portion V1 is disposed in the second direction.

[0175] In this case, as shown in FIG8, the second interval W4 corresponding to the spacing width in the second direction of each of the first passages constituting the first passage portion V1 can be the same as each other.

[0176] However, generally speaking, relative to the first surface of the first-first pad P1-1, the heat generated by the wafer is concentrated in the edge region, which is the boundary region. In this case, when the second spacing W4 in the second direction is the same throughout the entire region as described above, the heat dissipation characteristics in the edge region may decrease.

[0177] Furthermore, when electroplating large-area strip-shaped channels, the electroplating speed in each region varies depending on the electroplating characteristics. For example, in the structure shown in Figure 7, the electroplating speed of the first-first channel V1-1, the first-second channel V1-2, the first-third channel V1-3, the first-fourth channel V1-4, the first-fifth channel V1-5, the first-sixth channel V1-6, the first-tenth channel V1-10, the first-eleventh channel V1-11, the first-twelfth channel V1-12, the first-thirteenth channel V1-13, the first-fourteenth channel V1-14, and the first-fifteenth channel V1-15 located in the edge region can be higher than the electroplating speed of the first-seventh channel V1-7, the first-eighth channel V1-8, and the first-ninth channel V1-9 located in the center. For example, when using an electroplating solution to electroplat a large area channel, copper particles are concentrated in the edge area compared to the central area, and therefore, the electroplating speed in the edge area increases. As a result, the thickness in the edge area of ​​the first-first pad P1-1 can appear to be thicker than the thickness in the central area, and therefore, the process time for planarizing the first-first pad P1-1 can be increased.

[0178] Therefore, the interval between the first passages located in the edge region of the first passage portion V1 is smaller than the interval between the first passages located in the center.

[0179] For example, the plurality of first paths in the first path portion V1 of the embodiment, including the first sub-path V1A and the second sub-path V1B, can be divided into a plurality of groups. For example, the first path portion V1 may include a first path group G1V1 disposed in a first edge region and a second path group G2V1 disposed in a second edge region, spaced apart from the first path group G1V1 by a third interval W7.

[0180] The first pathway group G1V1 includes a plurality of first pathways spaced apart from each other by a second interval W4 in the second direction. The first pathway group G1V1 includes a first sub-path V1A and a second sub-path V1B, and specifically, may include a first-first pathway V1-1, a first-second pathway V1-2, a first-third pathway V1-3, a first-fourth pathway V1-4, a first-fifth pathway V1-5, a first-sixth pathway V1-6 and a first-seventh pathway V1-7 spaced apart from each other in the second direction.

[0181] Accordingly, the second pathway group G2V1 may include a plurality of first pathways spaced apart from each other by a second interval W4 in the second direction. The second pathway group G2V1 includes a first sub-path V1A and a second sub-path V1B, and specifically, may include a second-first pathway V2-1, a second-second pathway V2-2, a second-third pathway V2-3, a second-fourth pathway V2-4, a second-fifth pathway V2-5, a second-sixth pathway V2-6, and a second-seventh pathway V2-7 spaced apart from each other in the second direction.

[0182] Simultaneously, the first pathway group G1V1 may be separated from the second pathway group G2V1 by a third interval W7. In this case, the third interval W7 may be larger than the first interval W3 and the second interval W4. For example, the third interval W7 may be 60 μm to 120 μm. For example, the third interval W7 may be 70 μm to 120 μm. For example, the third interval W4 may be 80 μm to 100 μm.

[0183] In other words, the embodiment includes a region in the third interval W7 corresponding to the first region R1 where no passage is formed. Furthermore, the plating rate of the first passage included in the first passage group G1V1 and the plating rate of the first passage included in the second passage group G2V1 are maintained substantially the same by means of the region where no passage is formed, and therefore, it is possible to maintain planarization by minimizing plating deviation. In addition, the embodiment can improve the heat dissipation characteristics in the edge region by dividing the first passage group G1V1 and the second passage group G2V1 as described above, and therefore, improve reliability.

[0184] Figure 9 is a view showing the packaging substrate according to an embodiment.

[0185] Referring to FIG9, the packaging substrate may include the circuit board of FIG2.

[0186] Specifically, the encapsulation substrate may include a first adhesive component 210 disposed on a circuit pattern layer exposed through an opening in the first protective layer 141 of the circuit board. In addition, the encapsulation substrate may include a second adhesive component 240 disposed on a circuit pattern layer exposed through an opening in the second protective layer 142 of the circuit board.

[0187] The first adhesive component 210 and the second adhesive component 240 may have different shapes. For example, the first adhesive component 210 may have a hexahedral shape. For example, the cross-section of the first adhesive component 210 may include a rectangular shape. For example, the cross-section of the first adhesive component 210 may include a rectangular or square shape. The second adhesive component 240 may have a spherical shape. For example, the cross-section of the second adhesive component 240 may include a circular or semi-circular shape. For example, the cross-section of the second adhesive component 240 may include a partially or completely circular shape. For example, the cross-sectional shape of the second adhesive component 240 may include a flat surface on one side and a curved surface on the opposite side. The second adhesive component 240 may be a solder ball, but is not limited to this.

[0188] Chip 220 may be mounted on the first adhesive component 210. For example, chip 220 may include a driver IC chip. For example, chip 220 may refer to various chips including sockets or devices other than driver IC chips. For example, chip 220 may include at least one of diode chips, power IC chips, touch sensor IC chips, MLCC chips, BGA chips, and chip capacitors. For example, chip 220 may be a power management integrated circuit (PMIC). For example, chip 220 may be a memory chip, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, or the like. For example, chip 220 may be an application processor (AP) chip, such as a central processing unit (e.g., CPU), graphics processing unit (e.g., GPU), digital signal processor, encryption processor, microprocessor, and microcontroller, or a logic chip, such as an analog-to-digital converter or application-specific IC (ASIC). Although the figures illustrate only one chip mounted on the package substrate, the embodiments are not limited thereto. The package substrate may include a plurality of chips, and the plurality of chips may include a first AP chip corresponding to a central processing unit (CPU) and a second AP chip corresponding to a graphics processing unit (GPU).

[0189] The molding layer 230 may be formed on the circuit board. The molding layer 230 may be disposed to cover the mounted chip 220. For example, the molding layer 230 may be formed of an epoxy mold compound (EMC) to protect the mounted chip 220, but is not limited thereto.

[0190] The circuit board of the embodiment includes a first passage portion. The first passage portion includes a plurality of first passages spaced apart from each other in a second direction. In this case, each of the plurality of first passages includes a plurality of sub-passages spaced apart from each other in the first direction. In addition, each of the plurality of sub-passages has a strip shape in which the width in the first direction is greater than the width in the second direction. In the embodiment, each of the first passages includes a plurality of sub-passages extending in the first direction, and therefore, the embodiment reduces the number of electroplating processes compared to the comparative example. For example, the comparative example does not include a plurality of sub-passages as in the embodiment, but includes an integrated passage made of a single passage. However, when the width of the passage is not considered at all as in the comparative example, the pit size increases with the increase of the width of the passage, and therefore, there is a problem of an increase in the number of electroplating processes.

[0191] In contrast, when the width of the passage exceeds a certain level compared to the thickness of the insulating layer, the embodiment consists of a plurality of sub-passages to minimize the pits in the passage, and therefore, it is possible to reduce the number of electroplating processes by reducing the pit size during the electroplating process.

[0192] Furthermore, in this embodiment, the plurality of first channels are divided into a first channel group and a second channel group spaced apart in a second direction, with the spacing between the first channel group and the second channel group being greater than the spacing between the plurality of first channels. Therefore, this embodiment maintains that the plating speed of the first channels included in the first channel group and the plating speed of the first channels included in the second channel group are substantially the same. Thus, it is possible to maintain the flatness of the plating by minimizing plating deviation. In addition, this embodiment can improve the heat dissipation characteristics in the edge region by dividing the plurality of first channels into the first channel group and the second channel group as described above, and thus improve reliability.

[0193] The features, structures, effects, etc., described in the above embodiments are included in at least one embodiment, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc., described in each embodiment can be combined or modified by those skilled in the art to which the embodiments pertain, and used in other embodiments. Therefore, content related to such combinations and variations should be interpreted as being included within the scope of the embodiments.

[0194] The embodiments have been primarily described above, but these are merely examples and not limiting. Those skilled in the art regarding the embodiments should understand that various modifications and applications not described above are possible without departing from the fundamental characteristics of the embodiments of the present invention. For example, each component specifically shown in the embodiments can be implemented by modification. Furthermore, differences related to such modifications and applications should be interpreted as including within the scope of the embodiments set forth in the appended claims.

Claims

1. A semiconductor package comprising: a first insulating layer; and a first through-electrode portion penetrating the first insulating layer and having a shape elongating in a first direction; wherein the first through-electrode portion includes: A plurality of first through electrodes, which are spaced apart from each other in a second direction perpendicular to the first direction and in a thickness direction; At least one of the plurality of first through electrodes includes: a first sub-through electrode and a second sub-through electrode, which are spaced apart from each other in the first direction; and at least one of the first sub-through electrodes and the second through electrode has a width in the first direction that is greater than a width in the second direction, wherein the plurality of first through electrodes includes a first-first through electrode and a first-second through electrode that are spaced apart from each other in the second direction, wherein a first sub-through electrode of the first-first through electrode is spaced apart from a second sub-through electrode of the first-first through electrode in the first direction by a first interval; and wherein the first sub-through electrode of the first-first through electrode is spaced apart from a first sub-through electrode of the first-second through electrode in the second direction by a second interval that is different from the first interval.

2. The semiconductor package of claim 1, further comprising: a first-first pad disposed on an upper surface of the first insulating layer; and a first-second pad disposed on a lower surface of the first insulating layer, wherein the upper surfaces of the plurality of first through electrodes are in common contact with a first-first pad, and wherein the lower surfaces of the plurality of first through electrodes are in common contact with a first-second pad.

3. The semiconductor package of claim 1, wherein the width of the upper surface of one of the first sub-through electrodes of the plurality of first through electrodes is greater than the width of the lower surface of one of the first sub-through electrodes of the plurality of first through electrodes; wherein the width of each of the first sub-through electrodes of the plurality of first through electrodes in the first direction is the width of the upper surface of each of the first sub-through electrodes of the plurality of first through electrodes in the first direction; and wherein the width of each of the first sub-through electrodes of the plurality of first through electrodes in the second direction is the width of the upper surface of each of the first sub-through electrodes of the plurality of first through electrodes in the second direction.

4. The semiconductor package of claim 1, wherein the width of an upper surface of one of the second sub-through electrodes of the plurality of first through electrodes is greater than the width of a lower surface of one of the second sub-through electrodes of the plurality of first through electrodes; wherein the width of each of the second sub-through electrodes of the plurality of first through electrodes in the first direction is the width of the upper surface of each of the second sub-through electrodes of the plurality of first through electrodes in the first direction; and wherein the width of each of the second sub-through electrodes of the plurality of first through electrodes in the second direction is the width of the upper surface of each of the second sub-through electrodes of the plurality of first through electrodes in the second direction.

5. The semiconductor package of claim 2, wherein at least one of the first sub-through electrode and the second sub-through electrode of the plurality of first through electrodes has a width in the first direction that is 25 times or less the thickness of the first insulating layer.

6. The semiconductor package of claim 5, wherein the width of the first-first pad in the first direction is 15 times greater than the thickness of the first insulating layer.

7. The semiconductor package of claim 1, wherein the first gap is smaller than the second gap.

8. The semiconductor package of claim 1, further comprising: a second through electrode portion including a second-first through electrode and a second-second through electrode penetrating the first insulating layer, wherein the first-first through electrode and the first-second through electrode constitute a first through electrode group, and wherein the second-first through electrode and the second-second through electrode constitute a second through electrode group spaced apart from the first through electrode group in the second direction.

9. The semiconductor package of claim 8, wherein the second through electrode group is spaced apart from the first through electrode group by a third space in the second direction; and wherein the third space is different from the first space and the second space.

10. The semiconductor package of claim 9, wherein the third spacing is greater than the first spacing and the second spacing.

11. The semiconductor package of claim 2, wherein the first-first pads comprise: A first pad region that overlaps with the first through electrode portion in the thickness direction; and a second pad region other than the first pad region; wherein a layer structure of the first pad region is different from a layer structure of the second pad region.

12. The semiconductor package of claim 11, wherein the first pad region has a first number of layers, and wherein the second pad region has a second number of layers less than the first number of layers.

13. The semiconductor package of claim 2, further comprising: an adhesive component disposed on the first-first pad; and a wafer attached to the adhesive component.

14. The semiconductor package of claim 13, wherein the chip includes a first AP chip and a second AP chip, wherein the first AP chip corresponds to a central processing unit (CPU) and wherein the second AP chip corresponds to a graphics processing unit (GPU).

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