Conformal titanium silicon nitride-based thin films and methods of forming same

Abstract

The disclosed technology generally relates to the formation of a titanium nitride-based thin film, and more specifically to a conformal and smoothing thin film based on titanium nitride and a method thereof. In one embodiment, a method for forming a diffusion barrier comprising TiSiN includes exposing a semiconductor substrate to one or more first deposition stages alternating with one or more second deposition stages. Exposing the semiconductor substrate to the one or more first deposition stages includes alternating exposure of the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor and a silicon (Si) precursor without intermediate exposure to the N precursor, and then exposing the semiconductor substrate to the N precursor.

Description

Technical Field

[0001] The present invention is generally related to the formation of a titanium nitride-based thin film, and more specifically to a titanium nitride-based conformal and smoothing thin film. Prior Technology

[0002] Titanium nitride (TiN)-based thin films have been widely used in the fabrication of various structures in integrated circuits (ICs). For example, TiN has been used in diffusion barriers, various electrodes, and metallization structures. This widespread use of TiN in IC manufacturing can be attributed to its structural, thermal, and electrical properties. As the size of various IC structures shrinks, TiN is formed on features with increasingly smaller dimensions and more complex morphologies. For example, as technology nodes scale down to 10 nm and even smaller, there is a need for conformally conformally lining thin films (e.g., diffusion barriers) with high aspect ratio trenches and vias as small as a few nanometers. Although techniques such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) have been used in the IC industry to form TiN diffusion barriers, the increasing demand for conformality of TiN films deposited in smaller trenches or vias may ultimately limit their use. On the other hand, although atomic layer deposition (ALD) has been proven for conformal deposition of TiN films, some electrical properties (e.g., conductivity) and physical properties (e.g., surface roughness) of these films may be inferior to those formed using other methods such as physical vapor deposition (PVD). Therefore, there is a need for a deposition method to form TiN-based films for IC manufacturing that possess superior properties (including barrier properties, surface smoothness, and step coverage) compared to TiN films formed by (e.g.) PVD and CVD. Summary of the Invention

[0003] In one embodiment, a method for forming a diffusion barrier comprising TiSiN includes exposing a semiconductor substrate to one or more first deposition stages that alternate with and do not overlap with one or more second deposition stages. Exposing the semiconductor substrate to the one or more first deposition stages includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor and the silicon (Si) precursor without intermediate exposure to the N precursor, and then exposing the semiconductor substrate to the N precursor.

[0004] In another embodiment, a method for forming a diffusion barrier comprising TiSiN includes exposing a semiconductor substrate to one or more first deposition stages that alternate with and do not overlap with one or more second deposition stages. Exposing the semiconductor substrate to the one or more first deposition stages includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor, followed by a silicon (Si) precursor, followed by the N precursor.

[0005] In another embodiment, a method for forming a diffusion barrier comprising TiSiN includes exposing a semiconductor substrate to one or more first deposition stages that alternate with and do not overlap with one or more second deposition stages. Exposing the semiconductor substrate to the one or more first deposition stages includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to the one or more second deposition stages includes exposing the semiconductor substrate to the Ti precursor for a Ti precursor exposure duration, followed by a silicon (Si) precursor for a Si precursor exposure duration, followed by the N precursor. The ratio of the Si precursor exposure duration to the Ti precursor exposure duration is between 2 and 130.

[0006] In another embodiment, a method for forming a diffusion barrier comprising TiSiN includes exposing a semiconductor substrate to one or more first deposition stages that alternate with and do not overlap with one or more second deposition stages. Exposing the semiconductor substrate to the one or more first deposition stages includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to the one or more second deposition stages includes exposing the semiconductor substrate to the Ti precursor, the silicon (Si) precursor, and the N precursor. Exposing the semiconductor substrate to one or more of the Ti precursor, the Si precursor, and the N precursor during the one or more second deposition stages includes undersaturating the main surface of the semiconductor substrate.

[0007] In another embodiment, a method includes forming a diffusion barrier comprising TiSiN having a modulus exceeding 290 GPa and a Si content exceeding 2.7 atomic percent by exposing a semiconductor substrate to one or more first deposition stages alternating with one or more second deposition stages. Exposing the semiconductor substrate to the one or more first deposition stages includes alternating exposure of the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor, followed by a silicon (Si) precursor, followed by the N precursor.

[0008] In another embodiment, a method includes forming a diffusion barrier comprising TiSiN having a hardness exceeding 20 GPa and a Si content exceeding 2.7 atomic percent by exposing a semiconductor substrate to one or more first deposition stages alternating with one or more second deposition stages. Exposing the semiconductor substrate to the one or more first deposition stages includes alternating exposure of the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor, followed by a silicon (Si) precursor, followed by the N precursor.

[0009] In another embodiment, a method includes forming a diffusion barrier comprising TiSiN by exposing a semiconductor substrate to one or more first deposition stages alternating with one or more second deposition stages. The diffusion barrier has a crystalline texture such that the sum of the area of ​​the diffusion barrier exhibited by grazing incident X-ray diffraction at the (002) peak and the area at the (111) and (222) peaks exceeds 0.4, and a Si content exceeding 2.7 atomic percent. Exposing the semiconductor substrate to the one or more first deposition stages includes alternating exposure of the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor, followed by a silicon (Si) precursor, followed by the N precursor.

[0010] In another embodiment, a method includes forming a diffusion barrier comprising TiSiN by exposing a semiconductor substrate to one or more first deposition stages alternating with one or more second deposition stages. The diffusion barrier has a nanocrystalline structure with an average grain size of less than about 6.5 nm and a Si content of more than 2.7%. Exposing the semiconductor substrate to the one or more first deposition stages includes alternating exposure of the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor, followed by a silicon (Si) precursor, followed by the N precursor.

[0011] In another embodiment, a semiconductor structure includes a semiconductor substrate comprising a plurality of trenches or vias formed thereon, wherein the trenches or vias include dielectric sidewall surfaces and an aspect ratio greater than 5. A diffusion barrier layer comprises TiSiN conformally lining the surfaces of the trenches or vias, wherein the diffusion barrier layer has a Si content of 2.7 atomic% to 9 atomic% and a modulus of 290 GPa to 350 GPa.

[0012] In another embodiment, a semiconductor structure includes a semiconductor substrate comprising a plurality of trenches or vias formed thereon, wherein the trenches or vias include dielectric sidewall surfaces and an aspect ratio greater than 5. A diffusion barrier layer comprising TiSiN is conformally lining the surfaces of the trenches or vias, wherein the diffusion barrier layer has a Si content of 2.7 atomic% to 9 atomic% and a hardness of 20 GPa to 40 GPa.

[0013] In another embodiment, a semiconductor structure includes a semiconductor substrate comprising a plurality of trenches or vias formed thereon, wherein the trenches or vias include dielectric sidewall surfaces and an aspect ratio greater than 5. A diffusion barrier layer comprising TiSiN is conformally lining the surface of the trenches or vias, wherein the diffusion barrier layer has a Si content of 2.7 atomic% to 9 atomic% and a crystalline texture such that the area of ​​the grazing incident X-ray spectrum exhibited at the (002) peak is in a ratio of 0.4 to 4.5 of the sum of the areas at the (111) and (222) peaks.

[0014] In another embodiment, a semiconductor structure includes a semiconductor substrate comprising a plurality of trenches or vias formed thereon, wherein the trenches or vias include dielectric sidewall surfaces and an aspect ratio greater than 5. A diffusion barrier layer comprising TiSiN is conformally lining the surface of the trenches or vias, wherein the diffusion barrier layer has a Si content of 2.7 atomic% to 9 atomic% and a nanocrystalline structure with an average grain size of about 5.0 nm to 6.5 nm. Simple Explanation of the Diagram

[0015] Embodiments of the invention will now be described with reference to the accompanying drawings by way of non-limiting examples.

[0016] Figures 1A to 1D schematically illustrate different nucleation and growth mechanisms of thin films under different growth modes.

[0017] Figure 2 is a cross-sectional transmission electron micrograph of a TiN layer grown on a silicon substrate with a specific morphology by atomic layer deposition.

[0018] Figure 3 schematically illustrates a cross-sectional view of a semiconductor structure comprising a thin film of TiSiN or TiAlN formed on a semiconductor substrate according to an embodiment.

[0019] Figure 4 schematically illustrates a cross-sectional view of a via lined with a thin film, including TiSiN or TiAlN, of different thicknesses at different portions of the via.

[0020] Figure 5A is a flowchart illustrating a method for forming a thin film including TiSiN or TiAlN according to an embodiment.

[0021] Figure 5B illustrates a flowchart of a deposition cycle for forming a thin film including TiSiN or TiAlN according to an embodiment.

[0022] Figure 5C illustrates a deposition cycle for forming a thin film including TiSiN or TiAlN according to an embodiment.

[0023] Figure 5D is a diagram illustrating a sequence of deposition cycles for forming thin films including TiSiN or TiAlN according to an embodiment.

[0024] Figure 6A shows a cross-sectional transmission electron micrograph of a TiSiN thin film obtained from the portion above the high aspect ratio via according to the embodiment, and a diffraction pattern of the corresponding selected area.

[0025] Figure 6B shows a cross-sectional transmission electron micrograph of a TiSiN thin film in the middle portion of the high aspect ratio via shown in Figure 6A, according to an embodiment, and a diffraction pattern of the corresponding selected area.

[0026] Figure 6C shows a cross-sectional transmission electron micrograph of the TiSiN thin film below the high aspect ratio via shown in Figures 6A and 6B, according to the embodiment, and the corresponding diffraction pattern of the selected area.

[0027] Figure 7A shows a selected area diffraction pattern obtained by self-lining a substantially amorphous thin film including TiSiN in a high aspect ratio via according to an embodiment.

[0028] Figure 7B shows a selected area diffraction pattern obtained by self-lining a partially crystalline thin film including TiSiN in a high aspect ratio via according to the embodiment.

[0029] Figure 7C shows a selected area diffraction pattern obtained by self-lining a substantially crystalline thin film including TiSiN in a high aspect ratio via according to the embodiment.

[0030] Figure 8 shows the grazing incidence X-ray diffraction spectrum obtained from a substantially amorphous thin film including TiSiN according to the embodiment.

[0031] Figure 9 is a graph showing the resistivity of experimentally measured values ​​that vary depending on the silicon content of the TiSiN thin film according to the embodiments.

[0032] Figure 10A is a cross-sectional transmission electron micrograph obtained from a substantially uniform thin film including TiSiN according to the embodiment.

[0033] Figure 10B is a cross-sectional transmission electron micrograph of a nanolayered thin film comprising alternating TiN regions or layers and SiN regions or layers, according to an embodiment.

[0034] Figure 11 schematically illustrates a portion of a semiconductor device according to an embodiment, including contacts or metal lines formed by filling openings with metal through a thin film lining comprising TiSiN or TiAlN.

[0035] Figure 12 is a cross-sectional transmission electron micrograph of an ultrathin TiN layer grown on a substrate with a specific morphology by atomic layer deposition.

[0036] Figure 13 is a flowchart illustrating a vapor deposition cycle for forming a thin film including TiSiN according to some embodiments.

[0037] Figure 14 is a flowchart illustrating a vapor deposition cycle for forming a thin film including TiSiN according to an embodiment.

[0038] Figure 15 is a flowchart illustrating a vapor deposition cycle for forming a thin film including TiSiN according to an embodiment.

[0039] Figure 16 is a flowchart illustrating a vapor deposition cycle for forming a thin film including TiSiN according to an embodiment.

[0040] Figure 17 is a flowchart illustrating a vapor deposition cycle for forming a thin film including TiSiN according to some other embodiments.

[0041] Figure 18A is a graph showing the experimentally measured Si content of TiSiN thin films, where the Si content is shown as varying according to the ratio of the number of first deposition stages to the number of second deposition stages.

[0042] Figure 18B is a graph of experimentally measured grazing-incidence X-ray diffraction spectra of TiSiN thin films, where different curves correspond to TiSiN thin films with different ratios of the number of first deposition stages to the number of second deposition stages.

[0043] Figure 18C is a graph showing the resistivity of TiSiN thin films with equal Si content, as illustrated in Figure 18A.

[0044] Figures 19A to 19B are graphs of resistivity measured experimentally based on the Ti exposure time during the second deposition stage of the deposition cycle shown in Figure 17, where the exposure time to dichlorosilane, the Si precursor, is fixed at 60 seconds and 90 seconds, respectively.

[0045] Figures 20A to 20C are cross-sectional transmission electron micrographs of high aspect ratio TiSiN films with linings formed during the second deposition stage of the deposition cycle shown in Figure 17, obtained for personal use.

[0046] Figures 21A to 21C are graphs of resistivity measured experimentally based on the Ti exposure time during the second deposition stage of the deposition cycle shown in Figure 17, where the exposure time for chlorosilane, one of the Si precursors, is fixed at 3.5 seconds, 30 seconds, and 90 seconds, respectively.

[0047] Figures 22A to 22C are cross-sectional transmission electron micrographs of high aspect ratio TiSiN films with linings formed at different Ti exposure times during the second deposition stage of the deposition cycle shown in Figure 17, obtained for personal use.

[0048] Figures 23A to 23B are graphs of resistivity measured experimentally based on the Ti exposure time during the second deposition stage of the deposition cycle shown in Figure 17, where the exposure time to dichlorosilane, the Si precursor, is fixed at 5 seconds and 30 seconds, respectively.

[0049] Figures 24A to 24B are cross-sectional transmission electron micrographs of high aspect ratio TiSiN films with linings formed at different Ti exposure times during the second deposition stage of the deposition cycle shown in Figure 17, obtained for personal use.

[0050] Figures 25A and 25B are transmission electron micrographs of lower and higher resolution cross-sections obtained from a high aspect ratio structure of a self-made TiSiN thin film with a liner.

[0051] Figure 26A is a flowchart illustrating a method for forming a nano-layered thin film according to some embodiments.

[0052] Figure 26B is a flowchart illustrating a method for forming nano-layered thin films using a vapor deposition cycle similar to that illustrated in Figure 13, according to some embodiments.

[0053] Figure 26C is a flowchart illustrating a method for forming nano-layered thin films using a vapor deposition cycle similar to that illustrated in Figure 17, according to some embodiments.

[0054] Figure 27A is a graph showing the resistivity experimentally measured on various nanolayer films deposited according to the methods illustrated in Figures 26A and 26C, based on some embodiments.

[0055] Figure 27B is a graph of experimentally measured grazing incidence X-ray diffraction spectra of various nanolayered films deposited according to the methods illustrated in Figures 26A and 26C, based on some embodiments.

[0056] Figures 28A and 28B are cross-sectional transmission electron micrographs of a high aspect ratio structure of a self-contained nano-layered film with a liner, according to some embodiments.

[0057] Figure 29 is a flowchart illustrating a vapor deposition cycle for forming a thin film including TiSiN according to some embodiments.

[0058] Figure 30 is a graph illustrating the tunability of the Si content of TiSiN films according to the embodiments, by tuning the precursor exposure time and / or the ratio of the number of first deposition stages to the number of second deposition stages.

[0059] Figures 31A to 31I are experimentally measured grazing incidence X-ray diffraction (XRD) spectra of the TiSiN thin films according to the examples.

[0060] Figure 32 is a graph showing the ratio (R) of the area at the (002) peak to the sum of the areas at the (111) and (222) peaks, depending on the Si content measured from the TiSiN thin film according to the embodiment.

[0061] Figure 33 is a graph showing the estimated average nanocrystal size based on the Si content calculated from measured grazing incidence X-ray diffraction (XRD) spectra from Figure 31A to Figure 31I.

[0062] Figure 34 is a graph showing the hardness values ​​as measured on the TiSiN film according to the embodiments, based on the Si content.

[0063] Figure 35 is a graph showing the modulus values ​​varying according to the Si content of the TiSiN thin film in the embodiments.

[0064] Figure 36 shows transmission electron micrographs of lower and higher resolution cross sections obtained from the high aspect ratio structure of the self-used TiSiN thin film with lining according to the embodiment.

[0065] Figure 37A is an atomic force microscope image of the TiSiN thin film deposited according to the embodiment.

[0066] Figure 37B shows an atomic force microscope image of a TiN thin film as a comparative example. Implementation

[0067] [Any citation of priority claims is included] []

[0068] Any and all applications that identify foreign or domestic priority claims in the filing information sheet filed together with this application are incorporated herein by reference in accordance with 37 CFR 1.57.

[0069] This application is a partial continuation of U.S. Application No. 16 / 595,916, filed October 8, 2019, entitled "CONFORMAL TITANIUM NITRIDE-BASED THIN FILMS AND METHODS OF FORMING THE SAME," and claims priority under 35 USC § 119(e) to U.S. Provisional Application No. 63 / 171,970, filed April 7, 2021, entitled "CONFORMAL TITANIUM NITRIDE-BASED THIN FILMS AND METHODS OF FORMING THE SAME," and also claims priority under 35 USC § 119(e) to U.S. Provisional Application No. 63 / 171,970, filed April 7, 2021, entitled "CONFORMAL TITANIUM NITRIDE-BASED THIN FILMS AND METHODS OF FORMING THE SAME." The priority claim of U.S. Provisional Patent Application No. 63 / 172,002 concerning “SAME” is hereby expressly incorporated herein by reference in its entirety.

[0070] As described above, the integrated circuit (IC) industry requires conformal thin films (e.g., TiN-based films) with superior physical and barrier properties, as well as methods for forming such films. To address these and other needs, this paper discloses at least partially amorphous films comprising TiSiN and / or TiAlN, and a periodic vapor deposition method (which may be atomic layer deposition (ALD)) for forming such films. These films exhibit the conformal properties of films deposited by ALD, while also possessing barrier properties superior to or matching those of TiN films formed by existing physical vapor deposition (PVD) and chemical vapor deposition (CVD) methods. Thin films comprising TiSiN and / or TiAlN can be used as conformal diffusion barriers. Thin films are formed using a method suitable for substrates with relatively large surface areas due to the presence of morphology (e.g., openings in the dielectric, such as trenches or vias, which can be high (e.g., >1) aspect ratio vias and trenches with an area density such that the exposed surface area exceeds at least twice that of a flat substrate). This method involves exposing a semiconductor substrate to one or more vapor deposition cycles at relatively high pressures (e.g., >1 Torr), wherein such vapor deposition cycles include exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor. Thin films comprising TiSiN and / or TiAlN deposited according to the methods disclosed herein advantageously exhibit excellent diffusion barrier properties, along with excellent conformability, step height coverage, and low surface roughness. These and other properties of the thin film can be advantageously tuned by controlling the nanoscale morphology of the film to varying degrees of crystallinity and / or uniformity through tuning program conditions.

[0071] As described herein, unless explicitly limited, a compound whose constituent elements do not have a particular stoichiometric ratio should be understood to encompass all possible non-zero concentrations of each element. For example, titanium nitride (TiN) should be understood to encompass all possible stoichiometric and non-stoichiometric compositions of titanium nitride that can be expressed by the general formula Ti xN, where x>0, including TiN, Ti 3N 4, Ti 4N 3, Ti 6N 5, Ti 2N, and TiN 2, as well as other non-stoichiometric compositions of Ti and N. Similarly, silicon nitride (SiN) should be understood to encompass all possible stoichiometric and non-stoichiometric compositions of silicon nitride that can be expressed by the general formula Si yN, including Si 3N 4, where y>0; aluminum nitride (AlN) should be understood to encompass all possible stoichiometric and non-stoichiometric compositions of aluminum nitride that can be expressed by the general formula Al yN, including AlN, where y>0; titanium silicon nitride (TiSiN) should be understood to encompass all possible stoichiometric and non-stoichiometric compositions of titanium silicon nitride that can be expressed by the general formula Ti xSi yN, where x>0 and y>0; titanium aluminum nitride (TiAlN) should be understood to encompass all possible stoichiometric and non-stoichiometric compositions of titanium aluminum nitride that can be expressed by the general formula Ti xAl yN, where x>0 and y>0.

[0072] As described above, titanium nitride-based thin films play an important role in integrated circuit (IC) manufacturing. Although techniques such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) are already used in the IC industry to deposit TiN, there is an increasing demand for deposition methods to form TiN-based films with high conformability without significantly impairing electrical and / or physical properties (e.g., ternary or quaternary alloys containing Ti, N, and one or more additional metals including Si and / or Al).

[0073] Furthermore, while plasma-enhanced processes such as plasma-enhanced atomic layer deposition (PE-ALD) can effectively form conformal films on surfaces with relatively low aspect ratios, these processes may not be effective at depositing films within vias and cavities with relatively high aspect ratios. Without theoretical constraints, one possible reason for this is that, in some situations, the plasma may not be able to reach the deeper portions of high aspect ratio vias. In such cases, different portions of the via may be exposed to varying amounts of plasma, leading to undesirable structural effects due to non-uniform deposition, such as thicker films deposited near the via opening compared to deeper portions (sometimes referred to as sharpening or keyhole formation). For these reasons, thermally periodic vapor deposition, such as thermal ALD, may be more advantageous because these thermal processes are not dependent on the ability of the plasma to reach the portion of the surface it is depositing on.

[0074] However, while thermal ALD technology is suitable for forming relatively conformal TiN-based films on morphologies (especially those with relatively high aspect ratios, e.g., exceeding 1:1), the inventors have recognized that TiN-based films formed by thermal ALD may be inferior to those formed by PVD or CVD in certain aspects (e.g., film roughness and resistivity). In this regard, the inventors have found that some electrical and / or physical properties of TiN-based films grown by ALD can be affected by the growth mode. Specifically, the inventors have found that while it is desirable to grow TiN-based films in a two-dimensional layer-by-layer growth mode in ALD, this layer-by-layer growth mode may not be easily achieved in some situations. The inventors have further found that growing TiN-based films by ALD in a layer-by-layer growth mode presents specific challenges in IC manufacturing, where TiN-based films are formed on non-metallic surfaces (especially insulating surfaces, such as oxide and nitride surfaces) or semiconductor surfaces (such as doped and undoped silicon surfaces)). The inventors have recognized that the extent to which TiN-based films can be grown in a layer-by-layer growth mode can subsequently depend on the initial growth mode, which depends on the surface type and crystallinity, as described herein with reference to Figures 1A to 1D, without being subject to any theoretical constraints.

[0075] Figure 1A schematically illustrates the nucleation of a TiN-based layer, and Figures 1B to 1D illustrate different growth modes of the TiN-based layer on different surfaces. Referring to Figure 1A, once the precursor molecules 104 reach the surface of the substrate 100, they are substantially adsorbed onto that surface. Some of the adsorbed molecules 104 can diffuse along the surface of the substrate 100 until they reach an energy-favorable position for chemisorption. This surface diffusion is controlled, in particular, by the substrate temperature, the substrate material, and the kinetic energy of the adsorbed molecules. When the size of the nucleus formed by the chemisorbed molecules exceeds a certain size (sometimes called the "critical size") determined by the trade-off between volume free energy and surface energy, the nucleus can become energy-stable and begin to grow in size. Thus, the layer 108, with its stable nucleus formed, continues to grow by incorporating additional precursor molecules 104. Subsequent film growth can be classified according to different growth modes, as schematically illustrated in Figures 1B to 1D.

[0076] Figure 1B schematically illustrates the three-dimensional island growth mode (sometimes referred to as the Volmer–Weber growth mode) leading to the formation of layer 112 of three-dimensional islands. Without any theoretical constraints, this island growth mode can dominate when the net surface free energy associated with the three-dimensional islands is positive, indicating that the deposited atoms are more firmly bonded to each other compared to bonding to a substrate. It will be understood, for example, that the energenomics of ALD growth of TiN-based layers can favor the island growth mode when TiN-based metal layers are deposited on the surfaces of some semiconductors and / or insulating materials.

[0077] Figure 1C illustrates the layer-by-layer growth mode (sometimes referred to as the Frank-van der Merwe growth mode) that leads to the formation of a relatively smooth two-dimensional layer 116. Without any theoretical constraints, this layer-by-layer growth mode dominates when deposited atoms are more firmly bonded to the substrate than to each other, making it energy-efficient for stabilizing the two-dimensional layer 116. The layer-by-layer growth mode can be maintained as the bonding energy between layers continuously decreases from the bulk crystal value of the first monolayer to the TiN-dominated layer.

[0078] Although Figures 1B and 1C represent two different possible growth modes for TiN-based thin films, it will be understood that, in some cases, a growth mode intermediate between layer-by-layer and three-dimensional growth modes is possible. Figure 1D illustrates an example of an intermediate growth mode known as the Stranski-Krastanov (SK) growth mode. Without any theoretical constraints, SK growth can occur in thin film growth that begins in a layer-by-layer mode. When layer-by-layer growth becomes unfavorable after forming one or more monolayers, the island growth mode begins to dominate, resulting in a thin film structure 120 in which three-dimensional islands are formed on a two-dimensional initial layer. The SK growth mode can occur as a strain relaxation mechanism (strain-induced roughening).

[0079] Besides the interaction between the deposited material and the substrate, other factors such as substrate temperature, pressure, and deposition rate can significantly affect nucleation and early growth processes, which in turn affect the final nanostructure or microstructure of the resulting film. For example, deposition at relatively high substrate temperatures and / or lower deposition rates can promote the growth of relatively large grains, while relatively low substrate temperatures and higher deposition rates can favor the formation of smaller grains.

[0080] It has been found that when growing TiN-based thin films on various surfaces of interest in IC manufacturing (such as dielectric and semiconductor surfaces) using ALD, ALD growth can be initialized in a three-dimensional island growth mode or an SK growth mode. For example, in some cases, ALD growth of TiN-based thin films on substrates containing doped and undoped Si, SiO2, Si3N4, and other high-k or low-k materials can continue in either an island growth mode or an SK growth mode. The inventors have found that, partly due to the initial growth mode of island or SK growth, subsequent growth of TiN-based layers via ALD often results in undesirable film morphologies for various applications requiring ultrathin conformal diffusion barriers for high aspect ratio structures, as illustrated in Figure 2.

[0081] Figure 2 is a cross-sectional transmission electron micrograph of a TiN layer grown by thermal ALD on a morphology including a dielectric (Si3N4) surface. Following an initial film grown in a three-dimensional island or SK growth mode, TiN ALD growth is typically characterized by competitive growth of adjacent crystals with different orientations. In some cases, this results in V-shaped grains approaching the nucleation layer and ultimately forming a columnar morphology with a relatively high film thickness. As illustrated in Figure 2, the resulting film morphology includes faceted column tops that cause significant surface roughness and column boundaries with lower density relative to the grains. It will be understood that these column boundaries can have significantly poorer diffusion barrier properties relative to the grains themselves and can serve as pathways with minimal resistance for transporting unwanted contaminants through the TiN layer. Furthermore, due to the columnar morphology, a relatively thick TiN layer may be required to observe sufficient diffusion barrier properties. Therefore, the effective TiN barrier may be too thick for acceptable total contact or line conductivity, leaving little space for lower resistivity filler materials (such as W or Cu).

[0082] The inventors have discovered that when, for example, a thin film comprising TiSiN and / or TiAlN that may be at least partially amorphous is formed on a nonmetallic surface by a thermally periodic vapor deposition process (such as thermal ALD), three-dimensional or SK growth modes can be substantially suppressed and layer-by-layer growth modes can be promoted. This may be because, among other reasons, the nuclei can wet the nonmetallic surface with a relatively low contact angle when the TiN-dominant film has Si or Al added as alloying elements and / or contains an amorphous phase. The resulting film covers a relatively large area of ​​the nonmetallic surface with reduced island formation, for example, because film growth tends to be more advantageously carried out in a layer-by-layer growth mode on substrate surfaces where TiN-dominant films typically support three-dimensional island or SK growth modes in ALD, as described above. Therefore, unlike TiN layers grown directly on some non-metallic surfaces via ALD (which tends to support columnar growth as described above), according to the embodiments, thin films of TiSiN and / or TiAlN, comprising at least partially amorphous phases, formed on non-metallic surfaces tend to support a layer-by-layer growth mode, resulting in higher conformability and surface smoothness. Furthermore, the presence of the amorphous phase reduces grain boundaries, thereby suppressing the rapid diffusion paths of some elements (e.g., Cu or W). The presence of the amorphous phase, higher conformability, and / or surface smoothness subsequently enable a reduction in the thickness of the diffusion barrier. When formed to line high aspect ratio vias or trenches, the smaller thickness allows for relatively large openings to be subsequently filled with metal to form contact vias and / or reduce contact resistance.

[0083] Figure 3 schematically illustrates a cross-sectional view of a semiconductor structure 300 comprising a thin film 320 containing TiSiN and / or TiAlN, formed using methods according to the embodiments disclosed herein. The semiconductor thin film structure 300 includes a substrate 310, such as a semiconductor substrate. The substrate 310 may include a non-metallic surface (e.g., a dielectric and / or semiconductor surface) on which a thin film 320 comprising at least partially amorphous TiSiN and / or TiAlN is formed according to the methods described herein. The thin film 320 exhibits excellent diffusion barrier properties, along with excellent conformability, step coverage, and low surface roughness. These and other properties of the thin film can be advantageously tuned by controlling the crystallinity and / or uniformity of the nanoscale thin film (which can then be tuned by tuning the various procedural conditions described herein).

[0084] Although for clarity, the thin film including TiSiN and / or TiAlN is depicted in Figure 3 as formed on a planar substrate, the embodiments are not limited thereto. The benefits of the thin film including TiSiN and / or TiAlN can be particularly high when it is formed on a substrate with a morphology (e.g., having high (e.g., >1) aspect ratio vias and trenches and / or having a relatively high feature density) such that the surface area exposed to the precursor during periodic vapor deposition (e.g., ALD) is relatively large (e.g., more than twice the surface area of ​​the planar substrate).

[0085] In the context of high aspect ratio structures, one measure of conformality is referred to herein and in industry as stepped coverage. For example, a high aspect ratio structure can be a via, hole, trench, cavity, or similar structure. By way of illustrative example, Figure 4 schematically illustrates a semiconductor structure 400 having an exemplary high aspect ratio structure 416 formed therein, to illustrate some exemplary measures for defining and / or measuring the conformality of thin films formed on a high aspect ratio structure. The illustrated high aspect ratio structure 416 has inner surfaces that are lined with thin films 412 (e.g., including TiSiN and / or TiAlN films) of different thicknesses at different locations therein. As described herein, a high aspect ratio structure has an aspect ratio greater than 1, for example, defined as the ratio of the depth or height (H) of the opening region of the high aspect ratio structure 416 to its width (W). In the illustrated example, the high aspect ratio structure 416 is formed by forming vias through a dielectric layer 408 (e.g., an interlayer dielectric (ILD) layer) formed on the semiconductor material 404. In the illustrated example, the bottom surface of the high aspect ratio structure 416 exposes the underlying semiconductor substrate 404. Thin films 412 can be coated with different thicknesses on different surfaces of the high aspect ratio structure 416. As described herein, the step coverage can be defined as the ratio between the thickness of the film in the region below or at the bottom of the high aspect ratio structure and the thickness of the film in the region above or at the top of the high aspect ratio structure. The upper or top region can be a region of the high aspect ratio structure at a relatively shallow depth (e.g., 0 to 10% or 0 to 25% of H measured from the top of the opening). The lower or bottom region can be a region of the high aspect ratio structure at a relatively deep depth (e.g., 90% to 100% or 75% to 100% of H measured from the top of the opening). In some high aspect ratio structures, the step coverage can be defined or measured by the ratio of the thickness of the film 412A formed on the bottom surface of the high aspect ratio structure to the thickness of the film 412C formed on the top or top sidewall surface of the high aspect ratio structure. However, it will be understood that some high aspect ratio structures may not have a clearly defined bottom surface or may have a bottom surface with a small radius of curvature. In such structures, the step coverage can be defined or measured more consistently by the ratio of the thickness of the film 412B formed on the bottom or top sidewall surface of the high aspect ratio structure to the thickness of the film 412C formed on the top or top sidewall surface of the high aspect ratio structure. [include] [TiSiN] [and] [ / ] [or] [TiAlN] [Periodic vapor deposition of thin films]

[0086] Figure 5A illustrates a flowchart of a method 500 for forming a thin film comprising TiSiN and / or TiAlN according to an embodiment. Method 500 includes providing a substrate 510. The substrate may be a planar semiconductor substrate or a semiconductor substrate including a surface morphology such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to the surface area of ​​the unpatterned semiconductor substrate exceeds 2, as described herein. Surface morphologies resulting in a relatively large surface area may be a plurality of openings (such as trenches or vias) formed on the substrate, as described herein. These openings may include dielectric sidewall surfaces and an aspect ratio exceeding 5.

[0087] Furthermore, method 500 includes forming 520 a thin film, including titanium silicon nitride (TiSiN) or titanium aluminum nitride (TiAlN), which can be used as a diffusion barrier. This thin film is formed by exposing a semiconductor substrate to a plurality of vapor deposition cycles at a pressure greater than 1 Torr in a reaction chamber, wherein such vapor deposition cycles include exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.

[0088] As described herein and throughout the specification, it will be understood that a semiconductor substrate on which a thin film of TiSiN and / or TiAlN (e.g., a diffusion barrier) is formed can be implemented on various substrates, including (but not limited to) doped semiconductor substrates that can be formed from: group IV elemental materials (e.g., Si, Ge, C, or Sn) or alloys formed from group IV materials (e.g., SiGe, SiGeC, SiC, SiSn, SiSnC, GeSn, etc.); group III-V compound semiconductor materials (e.g., GaAs, GaN, InAs, etc.) or alloys formed from group III-V materials; group II-VI semiconductor materials (CdSe, CdS, ZnSe, etc.) or alloys formed from group II-VI materials.

[0089] According to some embodiments, the substrate may also be implemented as a semiconductor-on-insulator, such as a silicon-on-insulator (SOI) substrate. SOI substrates typically comprise silicon-insulator-silicon structures in which the various structures described above are isolated from the supporting substrate using an insulating layer such as a buried SiO₂ layer (BOX). Furthermore, it will be understood that the various structures described herein may be at least partially formed in an epitaxial layer formed in or near the surface region.

[0090] Referring again to Figure 5A, it will be understood that method 500 can be performed on a substrate that has been processed through a front-end process and may include various devices (e.g., transistors). Furthermore, the semiconductor substrate may include one or more of various structures pre-formed thereon, such as diffusion regions, isolation regions, electrodes, and metallization structures (to name a few, such as contacts and metallization lines), on which method 500 can be performed. Diffusion barriers including TiSiN and / or TiAlN can therefore be formed on various morphological structures including vias, cavities, holes, or trenches. Surfaces on which diffusion barriers including TiSiN and / or TiAlN can be formed according to embodiments include: metal surfaces, such as the surface of a metallized structure; semiconductor surfaces, such as doped or undoped Si surfaces; and / or dielectric surfaces, to name a few, such as interlayer dielectric (ILD) surfaces, mask or hard mask surfaces, or gate dielectric surfaces.

[0091] In some embodiments, when formed as a diffusion barrier, a thin film including TiSiN and / or TiAlN may be interposed between a dielectric layer (e.g., an interlayer dielectric (e.g., 408 in FIG. 4)) and a metallization structure formed by filling vias or trenches (e.g., 416 in FIG. 4), and / or between the semiconductor substrate 404 and the metallization structure formed by filling the vias or trenches, thereby (among other functionalities, such as electrical contacts) serving as a diffusion barrier between them. In these embodiments, the dielectric material may be any dielectric material used in integrated circuit fabrication, for example, silicon oxide, silicon nitride, high-k dielectrics, or low-k dielectrics. The metallization structure may include metallization lines, contact structures, or other conductive structures formed of metal or metallic materials for electrically connecting the underlying semiconductor material 404 (e.g., diffusion regions) to other portions of the fabricated integrated circuit device. Metallization structures can be formed from any suitable metal or metallic material, to name just a few, including: metals, including Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides, including TiN, TaN, WN, and TaCN; conductive metal silicides, including tantalum silicon, tungsten silicon, nickel silicon, cobalt silicon, and titanium silicon; and conductive metal oxides, including RuO2.

[0092] Referring again to Figure 5A, the method 500 for forming a thin film (e.g., a diffusion barrier) further includes forming 520 a thin film comprising TiSiN and / or TiAlN by exposing a semiconductor substrate in a reactor chamber to a plurality of vapor deposition cycles, which may be atomic layer deposition (ALD) cycles, wherein such vapor deposition cycles include exposure to one or more titanium (Ti) precursors, one or more nitrogen (N) precursors, and one or more silicon (Si) or aluminum (Al) precursors. At least one of the vapor deposition cycles may be performed in the reactor chamber at a pressure greater than about 1 Torr.

[0093] As described herein and throughout the specification, a reactor chamber refers to any reactor chamber suitably configured for periodic vapor deposition (which may be atomic layer deposition (ALD), e.g., thermal periodic vapor deposition or ALD) that contains a single wafer processing reactor chamber or a batch wafer processing reactor chamber. In a thermal periodic deposition reactor or ALD reactor, a substrate may be placed on a suitable substrate, such as a pedestal or a carrier boat. The substrate may be heated directly by conduction through a heated pedestal, or indirectly by radiation from a radiation source (such as a lamp) or by convection through heated chamber walls.

[0094] Typically, in periodic vapor deposition or ALD processes, reactants or precursors (e.g., oxidizing and reducing reactants) are alternately introduced into a reaction chamber in which a substrate is housed. This introduction of one or more reactants or precursors may be alternated with a scavenging or extraction process for removing excess reactants or precursors from the reaction chamber. Reactants may be introduced into the reaction chamber under conditions that expose surfaces that would otherwise hinder deposition diffusion to the reactants, thereby at least partially saturating the substrate surface with the precursors or reactants and / or reaction products of the reactants. Excess or residual precursors or reactants can then be scavenged and / or extracted from the reaction chamber. Extraction processes may be performed using a suitable vacuum pumping procedure, and scavenging steps may be performed by introducing a non-reactive or inert gas (e.g., nitrogen or a rare gas) into the reaction chamber. Other techniques exist for preventing the mixing of reactants in the gas phase.

[0095] Figure 5B is a flowchart illustrating a method for forming a diffusion barrier including TiSiN and / or TiAlN according to an embodiment, and Figures 5C and 5D are diagrams illustrating a method for forming a diffusion barrier including TiSiN and / or TiAlN according to an embodiment. Figure 5C illustrates a deposition stage including exposure to a precursor, and a cycle including exposure to the deposition stage. Figure 5D illustrates a periodic sequence of deposition stages as part of multiple cycles. Referring to Figures 5B to 5D, according to various embodiments, exposing a semiconductor substrate 520 (Figure 5A) to one or more vapor phase deposition cycles (which may be ALD cycles) includes exposing the substrate 525 to one or more first vapor phase deposition stages ("first deposition stages"), wherein at least one of the first deposition stages includes exposure to a Ti precursor and exposure to an N precursor. Furthermore, exposing the semiconductor substrate 520 (FIG. 5A) to one or more vapor deposition cycles (which may be ALD cycles) includes exposing the substrate 530 to one or more second vapor deposition stages (“second deposition stages”), wherein at least one of these second deposition stages includes exposure to a Si and / or Al precursor or a combination of exposure to a Si and / or Al precursor and further exposure to an N precursor. One or more first deposition stages and one or more second deposition stages may be combined to form a single cycle, which may then be repeated multiple times or multiple cycles. Different cycles may have the same or different numbers of first deposition stages and second deposition stages. The combination of exposing the substrate 525 to one or more first deposition stages and exposing 530 to one or more second deposition stages results in a diffusion barrier layer including a TiSiN and / or TiAlN layer or region. Exposing the substrate to one or more first deposition stages at 525 and exposing the substrate to one or more second deposition stages at 530 may subsequently include exposure to one or more of the respective precursors (such as in a pulse), as described below.

[0096] Referring again to Figures 5B to 5D, in various embodiments, exposing the substrate to one or more first deposition stages includes subjecting the substrate to one or more exposures to a Ti precursor and one or more exposures to an N precursor. Each exposure to the Ti precursor exposes the surface of the substrate, which is a diffusion barrier, to the Ti precursor, thereby substantially or partially saturating the surface with the Ti precursor. After exposing the substrate to the Ti precursor, excess or residual Ti precursor or its reaction products that are not retained adsorbed or chemisorbed on the substrate surface can be removed from the substrate surface, for example by pumping or purging the process chamber. Similarly, each exposure to the N precursor exposes the substrate, which is a diffusion barrier, to the N precursor, thereby substantially or partially saturating the surface with the N precursor. After exposing the substrate to the N precursor, excess or residual N precursor or its reaction products that have not been retained adsorbed, chemisorbed, or reacted with the substrate surface can be removed from the substrate surface, for example by pumping or purging the process chamber. Subjecting the substrate to one or more first deposition stages, including one or more exposures to the Ti precursor and one or more exposures to the N precursor, can locally form one or more monolayers or regions substantially formed of the deposited TiN.

[0097] In some embodiments, exposure to the Ti precursor in a given first deposition stage can be performed sequentially multiple times. Similarly, exposure to the N precursor in a given first deposition stage can be performed sequentially multiple times. Advantageously, in some situations, such as when there is substantial steric hindrance effect due to exposure to more reaction sites for adsorption or reaction of the respective precursors, exposing the substrate to the Ti and / or N precursors more than once can lead to a higher surface saturation level.

[0098] Referring again to Figures 5B to 5D, in various embodiments, exposing the substrate to one or more second deposition stages includes subjecting the substrate to one or more exposures to a Si precursor or an Al precursor. Each exposure to the Si and / or Al precursor exposes the surface of the substrate, which would otherwise impede deposition diffusion, to the Si and / or Al precursor, thereby substantially or partially saturating the surface with the Si and / or Al precursor. After exposing the substrate to the Si and / or Al precursor, excess or residual Si and / or Al precursors or their reaction products that are not retained adsorbed or chemisorbed on the substrate surface can be removed from the substrate surface, for example, by pumping or purging the process chamber. Subjecting the substrate to one or more second deposition stages, including one or more exposures to Si and / or Al precursors, can locally form one or more monolayers or regions substantially formed of deposited Si or Al.

[0099] In some embodiments, exposure to the Si and / or Al precursors in a given second deposition stage can be performed sequentially multiple times. Advantageously, in some situations, such as when there is substantial steric hindrance effect by exposing more reaction sites for adsorption or reaction of the respective precursors, exposing the substrate to the Si and / or Al precursors more than once can lead to a higher surface saturation level.

[0100] Referring again to Figures 5B to 5D, in some embodiments, exposing the substrate to 530 to each of one or more second deposition stages includes exposing the substrate to one or more Si and / or Al precursors and further exposing the substrate to one or more N precursors (which may be the same as or different from the N precursor of the first deposition stage). Each exposure to the Si and / or Al precursor exposes the surface of the substrate, which is a diffusion barrier, to the Si and / or Al precursor, thereby substantially or partially saturating the surface with the Si and / or Al precursor. After exposing the substrate to the Si and / or Al precursor, excess or residual Si and / or Al precursors or their reaction products that are not retained adsorbed or chemisorbed on the surface of the substrate can be removed from the substrate surface, for example by pumping or purging the process chamber. Each exposure to the N precursor exposes the surface of the substrate, which is a diffusion barrier, to the N precursor, thereby substantially or partially saturating the surface with the N precursor. Following one or more further exposures to the N precursor, excess or residual N precursor or its reaction products that have not reacted with the substrate surface can be removed from the substrate surface, for example by pumping or cleaning the process chamber. Subjecting the substrate to one or more second deposition stages, including one or more exposures to the Si precursor and one or more exposures to the N precursor, can locally form one or more monolayers or regions substantially formed of the deposited SiN or AlN.

[0101] In some embodiments, exposure to the Si precursor in a given second deposition stage can be performed sequentially multiple times. Similarly, further exposure to the N precursor can be performed sequentially multiple times. Advantageously, in some situations, such as when there is a substantial steric hindrance effect by exposing more reaction sites for adsorption of the respective precursors, exposing the substrate to the Si and / or Al and / or N precursors more than once can lead to higher surface saturation levels, as discussed herein.

[0102] It will be understood that, in various embodiments, based on various considerations including susceptibility to steric hindrance effects of precursors, the number of cycles, the frequency and number of repetitions of the first and second deposition stages, the frequency and number of repetitions of the first and second deposition stages, the frequency and number of repetitions of substrate exposure to Ti and N precursors during the first deposition stage, and the frequency and number of repetitions of substrate exposure to Si and / or Al precursors or Si and / or Al and N precursors during the second deposition stage can be varied to obtain the desired thickness, stoichiometry, and other properties of the resulting diffusion barrier layer including TiSiN and / or TiAlN as described herein.

[0103] Referring again to Figures 5B to 5D, depending on the circumstances or the desired film properties, it may be advantageous to initiate the deposition of a diffusion barrier including TiSiN and / or TiAlN by exposing the substrate to either the first or second deposition stage. For example, the inventors have found that, for instance, when the substrate surface includes a non-metallic surface (e.g., an insulating surface, such as the sidewalls of trenches or vias formed in an interlayer dielectric (ILD) layer; or a semiconductor surface, such as a Si diffusion region), it may be particularly advantageous to first expose the substrate to one or more second deposition stages (Si and / or Al precursors or N precursors) at 530, followed by exposing the substrate to one or more first deposition stages (Ti precursors or N precursors) at 525, to enhance the layer-by-layer growth pattern of the diffusion barrier layer, thereby improving conformability and reducing surface roughness.

[0104] However, the embodiments are not limited thereto, and in other embodiments, for example, when the substrate surface includes a metal surface (e.g., W, Al or Cu metal metallization), it may be more advantageous to first expose the substrate to one or more first deposition stages (Ti precursor or N precursor) at 525, and then expose the substrate to one or more second deposition stages (Si and / or Al precursor or N precursor) at 530, (for example) to reduce contact resistance while maintaining good conformability and surface roughness.

[0105] Referring to Figure 5D, in some cases, depending on the sequence described above, the sequence of the first and second deposition stages can result in a film with detectably rich regions or layers of TiN and Si and / or Al or SiN and / or AlN. However, in other cases, despite the dissimilar sequences of exposure to the first and second deposition stages, the resulting film can be a substantially uniform TiSiN and / or TiAlN film, as further described below.

[0106] According to various embodiments, non-limiting examples of Ti precursors for forming thin films (e.g., diffusion barrier layers or regions) include titanium tetrachloride (TiCl 4), tetradecyl (dimethylamino)titanium (TDMAT), or tetradecyl (diethylamino)titanium (TDEAT).

[0107] According to various embodiments, non-limiting examples of N precursors used to form thin films (e.g., diffusion barrier layers or regions) include ammonia (NH3), hydrazine (N2H4), or methylhydrazine (CH3(NH)NH2, "MMH"). As mentioned above, different N precursors may be used for the first deposition stage and the second deposition stage, and practically different precursors may be used for different cycles of the same stage.

[0108] According to various embodiments, non-limiting examples of inert gases used for purging include nitrogen (N2) or rare gases (such as Ar).

[0109] According to some embodiments, the Si precursor used to form the diffusion barrier layer may be a hydride precursor. Examples of such hydride precursors include silane (SiH4) and ethoxysilane (Si2H6). According to some other embodiments, the Si precursor used to form the diffusion barrier layer may be a chlorine-containing precursor, such as silica or chlorosilane. Examples include silica tetrachloride (SiCl4), monochloromethane (SiH3Cl, "MCS"), dichlorosilane (SiH2Cl2, "DCS"), trichlorosilane (SiHCl3), hexachloroethoxysilane (Si2Cl6, "HCDS"), and octachloroethoxysilane (Si3Cl8, "OCTS"). The inventors have discovered that silicon- and chlorine-containing Si precursors can be used to form diffusion barrier layers including TiSiN when a higher saturation level of the surface formed by the precursor is desired under various conditions due to the reduced steric hindrance relative to the organosilicon precursor.

[0110] According to some embodiments, the Al precursor used to form the diffusion barrier layer may be an organometallic precursor. Examples of such organometallic precursors include trimethylaluminum ("TMA"), triisobutylaluminum, and tris(dimethylamino)aluminum. According to some other embodiments, the Al precursor used to form the diffusion barrier layer may be a chlorine-containing Al precursor, such as AlCl3.

[0111] Without being constrained by any theory, the inventors have discovered that, compared to other Si or Al precursors, these Si and Al precursors, when introduced as the first non-nitrogen precursor, are particularly advantageous for promoting the layer-by-layer growth mode of TiSiN or TiAlN layers. This layer-by-layer growth mode is achieved by improving the wetting of the substrate surface through the core of the TiSiN or TiAlN layer during the early stages of growth, and this wetting can be characterized by a small contact angle between the core and the substrate surface. Due to the layer-by-layer growth mode, improved conformability and reduced surface roughness can be achieved, which is particularly advantageous for forming diffusion barriers by deposition in high aspect ratios with small dimensions. Furthermore, without being constrained by any theory, chlorine-containing Si and / or Al precursors can allow for more precise control of the composition in the growth direction by inhibiting or self-limiting adsorption.

[0112] According to embodiments, to achieve the various advantages disclosed herein (e.g., for use as an effective diffusion barrier), thin films including TiSiN and / or TiAlN may have a thickness not exceeding about 25 nm, 20 nm, 15 nm, 10 nm, 7 nm, 4 nm, 2 nm, 1 nm, or a value within or exceeding any of these equivalents. These thicknesses can be substantially lower than those of a TiN barrier having similar effectiveness as a diffusion barrier.

[0113] According to embodiments, in order to achieve the various advantages disclosed herein (e.g., for use as a diffusion barrier), thin films comprising TiSiN and / or TiAlN can be formed at substrate temperatures of 250 °C to 300 °C, 300 °C to 400 °C, 350 °C to 400 °C, 400 °C to 450 °C, 450 °C to 500 °C, 500 °C to 550 °C, 550 °C to 600 °C, 600 °C to 650 °C, or at temperatures within the range defined by any of these equivalents (e.g., about 400 °C).

[0114] According to embodiments, in order to achieve the various advantages disclosed herein (e.g., for use as an effective diffusion barrier), the exposure time or pulse duration of various precursors is in the range of about 0.1 seconds to 5 seconds, 5 seconds to 10 seconds, 10 seconds to 20 seconds, 20 seconds to 30 seconds, 30 seconds to 40 seconds, 40 seconds to 50 seconds, 50 seconds to 60 seconds, or a duration defined by any of these equivalents or longer.

[0115] In summary, forming a thin film comprising TiSiN and / or TiAlN (e.g., a diffusion barrier) involves exposing a substrate to one or more cycles comprising one or more first deposition stages and / or one or more second deposition stages. Each of the first deposition stages then includes one or more exposures to a Ti precursor, alternating with one or more exposures to an N precursor. According to some embodiments, each of the second deposition stages then includes one or more exposures to a Si or Al precursor. According to some other embodiments, each of the second deposition stages includes one or more exposures to a Si precursor and / or an Al precursor, alternating with one or more exposures to an N precursor. The resulting diffusion barrier layer comprises a TiSiN layer or region or a TiAlN layer or region. According to various embodiments, the frequency and number of exposures of the substrate to each of the Ti precursor, N precursor, and Si and / or Al precursor, as well as the frequency and number of exposures of the substrate to each of the cycle, the first deposition stage, and the second deposition stage, and the order of exposure can be customized to obtain the desired stoichiometry, thickness, and crystallinity, as described herein. [In areas with high surface area and] [ / ] [Deposition on a substrate with a high aspect ratio structure]

[0116] The inventors have discovered that when a substrate has a relatively high surface area (e.g., due to a relatively high area density of a high aspect ratio structure), film coating of the exposed surface using an ALD process formulation developed based on the characterization of films formed on a flat or unpatterned substrate or a substrate with a relatively low surface area, or a low area density of a high aspect ratio structure, can produce films with different properties at different portions of the exposed surface. For example, in a high aspect ratio structure with a relatively high area density of a high aspect ratio structure, the conformality or step coverage, as described above, can be significantly worse. Other properties that can also differ at different portions of the exposed surface, to name a few, include film stoichiometry, surface roughness, resistivity, and film density. Without any theoretical constraints, one reason for the low uniformity of properties could be the significantly increased exposed surface area compared to a flat substrate. Due to the increased exposed surface area, different portions of the exposed surface can receive different amounts of precursor flux, allowing different amounts of precursor to adhere to different portions of the exposed surface. By way of a simplified example, when hundreds of grains, each with a transistor on the order of 1x10¹⁰ or more, are formed on a 300 mm semiconductor substrate, and each transistor has one or more vias with a diameter of 10 nm to 100 nm and an aspect ratio of 1 to 100, the surface area exposed to the precursor during thin film deposition can exceed the surface area of ​​the corresponding unpatterned substrate by 10, 100, 1000, or even more times. Furthermore, the local deposition conditions at different portions of the exposed surface can be different. For example, the local pressure inside a deep trench or via can be different from, for example, lower, compared to the area outside the trench or via. In addition, under vacuum conditions, gas molecules collide more with the sidewalls of the channels or through holes, so the part above the deep channels or through holes can adsorb a higher amount of precursor molecules due to the higher flux.

[0117] Based on the embodiments described herein, the inventors have found that the deposition methods described herein are particularly advantageous for forming thin films including TiSiN and / or TiAlN with high uniformity across different portions of an exposed surface for various physical properties (to name a few, including conformality, step coverage, film stoichiometry, surface roughness, resistivity, and film density). Therefore, for one or more of these physical properties, thin films including TiSiN and / or TiAlN formed according to the deposition methods disclosed herein exhibit high uniformity at both local (e.g., within trenches or vias) and global (e.g., within the wafer) levels. Therefore, the deposition method according to the embodiments is particularly advantageous for forming thin films including TiSiN and / or TiAlN on a substrate, the substrate including a surface morphology such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate exceeds 2, 5, 10, 20, 50, 100, 200, 500, 1000 or has a ratio within or higher of any of these equivalent values.

[0118] Alternatively or additionally, the deposition method according to the embodiments is particularly advantageous for forming thin films on substrates comprising high aspect ratio structures having aperture widths less than 1 micrometer, 500 nm, 200 nm, 100 nm, 50 nm, 20 nm, or values ​​within the range defined by any of these equivalents; aspect ratios exceeding 5, 10, 20, 50, 100, 200, or values ​​within the range defined by any of these equivalents; and area density resulting in a surface area greater than that of a flat substrate as described above. Substrates having this morphology can be conformally coated with thin films comprising TiSiN and / or TiAlN according to the embodiments with a stepped coverage as defined above, the stepped coverage exceeding 50%, 60%, 70%, 80%, 90%, 95%, or having values ​​within the range defined by any of these equivalents or higher. As discussed above, the inventors have discovered that these results can be achieved by optimizing the process conditions for conformally coating substrates with relatively high area density and high aspect ratio structures, according to embodiments. The inventors have also discovered that these results can be achieved, in particular, by controlling (to name a few) the reaction chamber pressure or partial pressure of the precursor, the deposition rate, the temperature or pressure of the precursor introduced into the reaction chamber, the flow rate of the precursor, and the exposure time during substrate exposure.

[0119] The inventors have discovered that, according to embodiments, when coating a substrate with a relatively high area density and a high aspect ratio structure, a relatively high total pressure or partial pressure can lead to improvements in conformability and step coverage. Without being constrained by any theory, this improvement can be particularly associated with the effect of mitigating the effect of locally reduced partial pressure on precursors inside high aspect ratio vias or trenches. Therefore, according to the embodiment, referring again to Figures 5B and 5C, during the exposure of the substrate to one or more first deposition stages (Ti precursor and / or N precursor) at 525, and / or during the exposure of the substrate to one or more second deposition stages (Si and / or Al precursor and / or N precursor) at 530, the total pressure or partial pressure of any of the individual precursors may be 1.0 Torr to 3.0 Torr, 3.0 Torr to 5.0 Torr, 5.0 Torr to 7.0 Torr, 7.0 Torr to 9.0 Torr, 9.0 Torr to 11.0 Torr, 11.0 Torr to 13.0 Torr, 13.0 Torr to 15.0 Torr, or within the range defined by any of these equivalent values. In each of the exposures to the Ti precursor, N precursor, and / or Si and / or Al precursor, the respective precursor may constitute 1% to 2%, 2% to 5%, 5% to 10%, 10% to 20%, 20% to 50%, 50% to 100% of the total amount of gas molecules in the reaction chamber, or a percentage within the range defined by any of these equivalents. The inventors have discovered that, under certain conditions, when the total pressure or partial pressure exceeds these values, the step coverage may begin to degrade.

[0120] According to an embodiment, a relatively high total or partial pressure, along with the flow rates of the respective precursors and inert gases and the pumping power of the reaction chamber, is controlled during the exposure of the substrate to 525°C to one or more first deposition stages (Ti precursor and / or N precursor) and / or the exposure of the substrate to 530°C to one or more second deposition stages (Si and / or Al precursor and / or N precursor). This ensures that in each first and / or second deposition stage, the deposition rate is 0.20 Å / deposition stage to 0.30 Å / deposition stage, 0.30 Å / deposition stage to 0.40 Å / deposition stage, 0.40 Å / deposition stage to 0.50 Å / deposition stage, 0.50 Å / deposition stage to 0.60 Å / deposition stage, 0.60 Å / deposition stage to 0.70 Å / deposition stage, 0.60 Å / deposition stage to 0.70 Å / deposition stage, and 0.70 Å / deposition stage to 0.80 Å / deposition stage. The Å / deposition stage is relatively high, or is within a range defined by either of these equivalent values.

[0121] The inventors have discovered that, in order to achieve relatively high throughput while simultaneously delivering relatively high quantities of precursors to the reaction chamber for deposition at relatively high total or partial pressures, the flow rate of the precursors entering the reaction chamber should be significantly higher than the flow rates used in process conditions for forming thin films on flat substrates and / or substrates with low (e.g., <1) aspect ratio structures. This high flow rate can then be achieved by increasing one or both of the temperature or pressure of the precursors before they are introduced into the reaction chamber. For example, for precursors in liquid form under manufacturing conditions, the precursor flask can be heated to temperatures above room temperature, such as 30 °C to 60 °C, 60 °C to 80 °C, 80 °C to 100 °C, 100 °C to 120 °C, 120 °C to 150 °C, or temperatures within a range defined by any of these equivalents, to increase the vapor generation rate. The lower and upper bottle temperatures within these ranges can be determined, in part, based on the vapor pressure and decomposition temperature of the precursor. For example, TiCl₄ can be heated to approximately 60 °C to 80 °C. On the other hand, for precursors in gaseous form under manufacturing conditions, high flow rates can be achieved by increasing the gas line pressure to a value higher than that used when forming thin films on substrates with relatively low surface areas or flat substrates and / or substrates with low (e.g., <1) aspect ratio structures. It will be understood that the relatively high flow rates achieving the various advantages described herein can depend particularly on the pumping rate, exposure time, and reactor volume. To achieve suitable flow rates for depositing thin films on substrates with high surface area and / or high aspect ratio structures, the temperature and / or pressure of the precursors can be adjusted, among other parameters, so that the flow rates of the Ti, N, Si, and / or Al precursors can be, for example, 100 standard cubic centimeters per minute (sccm) to 1000 sccm, 1000 sccm to 2000 sccm, 2000 sccm to 5000 sccm, 5000 sccm to 10,000 sccm, 10,000 sccm to 15,000 sccm, 15,000 sccm to 20,000 sccm, or within or higher of any of these equivalent values. It will be understood that suitable flow rates can be particularly dependent on the reactor volume, and some of these flow rates are suitable for single-wafer reactors with a volume of approximately 1 to 2 liters.

[0122] Figures 6A to 6C illustrate experimental transmission electron microscopy (TEM) images of conformal TiSiN films with linings formed in high aspect ratio vias according to the deposition techniques described herein. These high aspect ratio vias have deposited silicon oxide surfaces. Figures 6A, 6B, and 6C are TEM images taken at the upper, middle, and lower portions of the TiSiN film formed in vias with an aspect ratio of approximately 40, respectively. In each of Figures 6A to 6C, the left image is a bright-field image of each portion of the high aspect ratio via, and the right image shows a selective area diffraction (SAD) pattern obtained from the film formed on each portion of the high aspect ratio via using an electron beam with a spot size equivalent to the thickness of the TiSiN film. Unlike polycrystalline TiN, which has a rough surface due to columnar growth as shown in Figure 2, the bright-field TEM images in Figures 6A to 6C show that the deposited TiSiN is smoother and more conformal. The inventors have discovered that these and other improvements can be partly attributed to the presence of at least some amorphous phases of TiSiN, which can coexist with some nanocrystalline phases of TiSiN, as indicated by SAD patterns. The TiSiN film is substantially amorphous and substantially conformal throughout the entire depth of the via, exhibiting good step height coverage (~60%). [control] [Nanoscale] [Of] [Thin Film Morphology]

[0123] Advantageously, thanks to the use of various procedural parameters described herein to control the adsorption of precursors at the sub-monolayer level, embodiments of the periodic vapor deposition process (which may be an ALD process) disclosed herein achieve control and improvement of the morphology and structure of films including TiSiN and / or TiAlN at the nanoscale. The controlled morphology and structure include crystallinity, uniformity, and surface roughness. Specifically, the inventors have discovered that nanoscale crystallinity and / or uniformity, as described herein, can be advantageously controlled in films including TiSiN and / or TiAlN by controlling various parameters of the exposure cycle.

[0124] According to various embodiments, when forming a thin film (e.g., a diffusion barrier layer) including TiSiN and / or TiAlN, in addition to the various parameters described above, the film morphology can also be controlled by a specific ratio of the number of times the substrate is exposed to the first deposition stage (including a combination of exposure to Ti precursor and N precursor) to the number of times the substrate is exposed to the second deposition stage (including exposure to Si and / or Al precursor or a combination of exposure to Si and / or Al precursor and N precursor). The ratio can be approximately 1:30 to 1:15, 1:15 to 1:6, 1:6 to 1:3, 1:3 to 1:2, 1:2 to 2:3, 2:3 to 5:6, 5:6 to 1:1, 1:1 to 6:5, 6:5 to 3:2, 3:2 to 2:1, 2:1 to 3:1, 3:1 to 6:1, 6:1 to 15:1, 15:1 to 30:1, or a ratio within a range defined by any of these equivalent values. For example, the ratio can be one of 2:3, 3:2, 5:4, 7:3, 7:5, 7:1, 10:1, and 15:1. Alternatively, the exposure to Ti precursors and Si and / or Al precursors can have these ratios. Under the combination of procedural conditions described herein for forming diffusion barriers including TiSiN and / or TiAlN, the ratio of exposure to the first deposition stage to exposure to the second deposition stage results in Si or Al being present in the diffusion barrier at an average concentration exceeding approximately 3%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or within a range defined by any of these equivalents, based on the total number of atoms in the diffusion barrier.

[0125] The inventors have discovered that by controlling the ratio of the number of times the substrate is exposed to the first deposition stage (or Ti precursor) to the number of times the substrate is exposed to the second deposition stage (or Si or Al precursor), the crystallinity of the resulting thin film including TiSiN and / or TiAlN can be continuously tuned, as illustrated in Figures 7A to 7C. Figures 7A to 7C show selected-area diffraction (SAD) patterns obtained from conformal thin films including TiSiN deposited on the sidewalls of high aspect ratio vias (similar to the thin films illustrated in Figures 6A to 6C, but with different crystallinities). Figures 7A to 7C respectively show SAD patterns of substantially completely amorphous TiSiN thin films, SAD patterns of partially amorphous and partially crystalline or nanocrystalline TiSiN thin films, and SAD patterns of substantially polycrystalline or nanocrystalline TiSiN thin films. It will be understood that the presence and qualitative degree of crystallinity of nano-domains or polycrystalline domains can be determined by the position and relative sharpness of diffracted spots and / or rings on the (111), (200), and (220) crystal planes of crystalline TiSiN indicated by warp indexing as shown in Figure 7C. For example, a SAD pattern mainly having diffusion rings can be associated with substantially amorphous TiSiN, while a SAD pattern mainly having spots can be associated with substantially polycrystalline TiSiN having a domain size equivalent to the selected region used to obtain the SAD pattern. SAD patterns of nanocrystalline and amorphous phases of TiSiN can have a mixture of both diffusion rings and spots. The inventors have found that the increased fraction of the amorphous phase can be attributed in particular to the increased smoothness, conformability, and step coverage of the TiSiN film.

[0126] Figure 8 shows a grazing-incident X-ray diffraction pattern of a blanket-type TiSiN layer formed on a substantially completely amorphous Si substrate according to an embodiment. The measured TiSiN layer is similar to the TiSiN layer imaged for the SAD patterns in Figures 7A and 6A to 6C. The lack of phase-dissimilar crystallization peaks attributable to the crystalline phases of the TiSiN layer indicates the substantially completely amorphous nature of the TiSiN layer.

[0127] As described herein, the relative crystallinity of films including TiSiN and / or TiAlN can be tunable to optimize various material properties (e.g., diffusion barrier properties). In some cases, lower crystallinity may be preferable (e.g.) for reducing grain boundaries. Reduced grain boundaries can inhibit the diffusion of specific elements through the film and improve smoothness. However, in other cases, higher crystallinity may be preferable (e.g.) for reducing the resistivity of the film. Figure 9 is a graph of experimentally measured resistivity varying according to the silicon content of the TiSiN film according to an embodiment. The graph illustrates that the resistivity of the TiSiN film can be tuned over a wide range of values ​​by tuning the relative Si content (atomic %) in the film, which in turn can be tuned by tuning the number of exposures to the Si precursor during periodic vapor deposition or ALD cycles. The inventors have found that while the resistivity of the TiSiN layer increases relatively slowly with respect to Si content at relatively low Si contents, it increases relatively rapidly with respect to Si content at relatively high Si contents. The inventors have discovered that, as verified by transmission electron microscopy experiments as described above, the relatively rapid increase in resistivity based on Si content generally coincides with the onset 910 of the amorphous phase appearance in TiSiN. It will be understood that this onset 910 and the resistivity can be particularly dependent on the deposition temperature and precursor used. As discussed above, to form at least a partially amorphous TiSiN layer, a Si content higher than about 10% may be required. While the resistivity may therefore increase, the total thickness can be reduced relative to a fully crystalline layer (such as a TiN layer).

[0128] Therefore, in situations where thin films possessing relatively high diffusion barrier properties and / or relatively low surface roughness are advantageous, the composition of the electrode layer can be advantageously tuned such that the thin film comprising TiSiN and / or TiAlN is at least partially amorphous. In these embodiments, the thin film may be substantially completely amorphous or comprise nanocrystalline regions surrounded by an amorphous matrix. For example, the electrode may comprise TiSi / TiAl, TiN, and TiAlN / TiSiN nanocrystals in an amorphous matrix comprising Ti, Al / Si, and N. In the illustrated embodiment, the initial 910 at approximately 1600 μΩ-cm corresponds to an average atomic concentration of approximately 10% Si. However, in other embodiments, depending on the deposition conditions and precursors used, the initial may correspond to an average Si concentration of approximately 10%, 15%, 20%, or 25%, or a value within a range defined by any of these equivalents. Alternatively, the start 910 corresponds to a ratio of 1:1 to 2:1, 2:1 to 3:1, 3:1 to 6:1, 6:1 to 15:1, 15:1 to 30:1, or a range defined by any of these equivalents, to the number of times the substrate is exposed to one or more first deposition stages (each including exposure to Si and / or Al precursors or a combination of exposure to Si and / or Al precursors and N precursors).

[0129] Tunable compositions comprising thin films of TiSiN and / or TiAlN having resistivity values ​​of <1000 μΩ-cm, 1000 μΩ-cm to 2000 μΩ-cm, 2000 μΩ-cm to 3000 μΩ-cm, 3000 μΩ-cm to 4000 μΩ-cm, 4000 μΩ-cm to 5000 μΩ-cm, 5000 μΩ-cm to 6000 μΩ-cm, 6000 μΩ-cm to 7000 μΩ-cm, 7000 μΩ-cm to 8000 μΩ-cm, 8000 μΩ-cm to 9000 μΩ-cm, 9000 μΩ-cm to 10000 μΩ-cm or greater than 10000 μΩ-cm, or within a range defined by any of these equivalent values.

[0130] In addition to crystallinity, the inventors have discovered that nanoscale uniformity can also be controlled by controlling the number of exposures to the first deposition stage and / or the number of exposures to the second deposition stage. In some cases, the sequence of the first and second deposition stages can be controlled to form a thin film having regions or layers rich in TiN and Si and / or Al or SiN and / or AlN, for example, a nano-layer comprising alternating TiN-rich regions or layers with Si-rich and / or Al-rich regions or layers or SiN / AlN-rich regions or layers. In other cases, despite dissimilar sequences of exposure to the first and second deposition stages, the resulting thin film can still be a substantially uniform TiSiN and / or TiAlN thin film, as described in further detail below. Exemplary embodiments are illustrated with reference to Figures 10A and 10B. Figure 10A illustrates a TEM image of a substantially uniform TiSiN layer, while Figure 10B illustrates a TEM image of a TiSiN layer in the form of a nano-layer comprising alternating TiN-rich regions or layers with SiN-rich regions or layers.

[0131] According to various embodiments, when forming a thin film comprising TiSiN and / or TiAlN (e.g., a diffusion barrier layer) to form a substantially uniform layer as shown in FIG10A, the number of back-to-back executions of the first deposition stage and / or the second deposition stage during film deposition at the temperatures disclosed above may be less than about 50, 30, 25, 20, 15, 10, 5, or values ​​within the range defined by any of these equivalents. When the number of back-to-back executions of the first deposition stage and / or the second deposition stage exceeds these equivalents, the thin film may comprise a nanolayer structure. It will be understood that the number of back-to-back executions of the first and / or second deposition stages for forming a substantially uniform or nanolayer structure may depend on various factors, including the temperature, pressure, and precursor used. For example, at relatively high temperatures, higher atomic diffusion mixing may favor a uniform composition, while at relatively low temperatures, lower atomic diffusion mixing may favor nanolayer formation.

[0132] The inventors have discovered that, advantageously, when forming thin films comprising TiSiN and / or TiAlN according to the embodiments disclosed herein, surface roughness can be reduced compared to other diffusion barrier materials (e.g., TiN or TiSiN) formed using other techniques (e.g., CVD or PVD). This reduced surface roughness is particularly advantageous when the surface on which the diffusion barrier is deposited includes a non-metallic surface (e.g., a dielectric surface and / or a semiconductor surface) exposed by openings such as vias or trenches, compared to other materials or techniques. During deposition, a diffusion barrier having the aforementioned thickness can have a root mean square (RMS) surface roughness of 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, and 5% of the average thickness of the diffusion barrier, or values ​​within a range defined by any of these equivalents, or lower. Alternatively, during deposition, the diffusion barrier having the aforementioned thickness may have a root mean square (RMS) surface roughness value of less than 0.5 nm, 0.4 nm, 0.3 nm, 0.2 nm, 0.1 nm, or within a range defined by any of these values, or even lower. The reduced RMS roughness can then improve the conformability of the diffusion barrier layer. [application]

[0133] Thin films comprising TiSiN or TiAlN formed using various procedural parameters according to the embodiments disclosed herein can be used in a variety of applications, particularly where the substrate includes a morphology with a relatively high surface area, a relatively high aspect ratio structure, and / or a non-metallic surface that can benefit from the various advantageous properties disclosed herein. Exemplary applications include lining the deposition of vias, holes, trenches, cavities, or similar structures having an aspect ratio (e.g., defined as the ratio of depth to top width) exceeding 1, 2, 5, 10, 20, 50, 100, 200, or within a range defined by any of these values.

[0134] Figure 11 illustrates an exemplary application in the background content of forming diffusion barriers for contact structures (e.g., source or drain contacts) formed on heavily doped active semiconductor substrate regions. A portion of a semiconductor device 1100 is illustrated, comprising material 1104, on which a dielectric layer 1108 (e.g., an interlayer dielectric (ILD) layer) of a dielectric material (such as silicon oxide or silicon nitride) is formed. For contacts formed to various regions of the substrate 1104 (including various doped regions, e.g., source and drain regions), vias or trenches may be formed through the dielectric layer 1108. These vias or trenches may expose various non-metallic surfaces, such as the exposed bottom surface of the substrate surface (e.g., a silicon substrate surface) and dielectric sidewalls. Subsequently, the bottom and side surfaces of the vias can be conformally coated with thin films comprising TiSiN and / or TiAlN in a manner similar to that shown in Figures 6A to 6C, according to the various embodiments described herein. The lined vias to form contact plugs 1116 can then be filled with a more conductive material (especially a metal or metal alloy, such as W, Al, or Cu). For example, the vias can be filled with tungsten using, for example, WF 6 via CVD.

[0135] For the various reasons described above, the barrier layer 1112 formed according to the embodiments can be advantageous. Furthermore, due to the conformal properties of the barrier layer 1112, the tendency for pinching off during subsequent metal filling processes can be substantially reduced. Additionally, as described above, the barrier layer 1112 can provide an effective barrier to material transport across it, for example, the outward diffusion of dopants (B, P) from the substrate 1104 and the inward diffusion of reactants, etchants, and metals (e.g., F, Cl, W, or Cu) from the contact plug formation process. The barrier effect can be enhanced by reduced surface roughness, increased step coverage, partially amorphous morphology (which may be partially nanocrystalline), and / or uniform / nano-layered morphology. These advantageous effects can be achieved with a lower thickness compared to TiN films. Furthermore, as described above, the layer-by-layer growth mode can reduce the overall contact resistance of the barrier layer 1112.

[0136] Other applications of thin films including TiSiN and / or TiAlN formed according to the embodiments disclosed herein include (to name only) various conductive structures formed in recessed substrates (e.g., buried electrodes or lines), electrodes (e.g., DRAM capacitor electrodes or gate electrodes), metallization barriers for higher metal layers (e.g., barriers in vias / trenches for Cu contacts / lines), high aspect ratio vertical rod electrodes, or through-holes and silicon vias (TSVs) for three-dimensional memory. [exist] [Si] [Including before precursor exposure] [Ti] [Surface Treatment] [TiSiN] [Film Deposition] []

[0137] The embodiments described herein address the need for improved diffusion barriers used in industry (e.g., TiN-based diffusion barriers as described above with respect to Figure 2). As described above, the low resistivity and high step coverage of films including TiSiN are desirable for many applications (e.g., for forming electrodes and / or diffusion barriers lined with high aspect ratio vias or trenches). As discussed above, the procedural conditions described above with respect to (e.g., Figures 5A to 5D) for conformally coating relatively high area density substrates with high aspect ratio structures can be optimized by controlling, in particular (to name a few) the reaction chamber pressure or precursor partial pressure, deposition rate, temperature or pressure of the precursor introduced into the reaction chamber, precursor flow rate, and exposure time.

[0138] In addition to the aforementioned improvements provided by TiSiN compared to other diffusion barrier materials (such as TiN), the inventors have discovered that TiSiN offers other advantages for advanced technology nodes. Figure 12 shows a cross-sectional transmission electron micrograph of an ultrathin TiN layer grown on a morphologically defined substrate by atomic layer deposition. The inventors have discovered that even when grown by atomic layer deposition, ultrathin (e.g., <5 nm) TiN layers can still discontinuously cover the underlying surface and exhibit discontinuities. These discontinuities can limit the effectiveness of TiN layers as diffusion barriers. In contrast, the inventors have discovered that when deposited under the specific deposition conditions described herein, TiSiN can provide continuous and uniform coverage even at ultrathin dimensions (e.g., <5 nm), which is particularly critical for applications of ultrathin diffusion barriers in advanced technology nodes. As described herein, the inventors have discovered alternative methods and / or further improvements to the various methods described above (e.g., with respect to Figures 5A to 5D) for increasing the stepped coverage and / or reducing the resistivity of TiSiN films. Specifically, in the alternative or further improved methods described herein, the semiconductor substrate is exposed to one or more first deposition stages that alternate with and do not overlap with one or more second deposition stages, wherein: exposing the semiconductor substrate to the one or more first deposition stages includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor; and exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor, followed by a silicon (Si) precursor, followed by the N precursor. That is, in the second deposition stages, the exposure of the Ti precursor precedes the exposure of the Si precursor, and the exposure of the Si precursor is followed by the exposure of the N precursor. This alternative method further reduces roughness and enhances layer-by-layer growth, allowing the TiSiN film to remain continuous even at ultra-thin (e.g., <5 nm) dimensions. Furthermore, the inventors have discovered that the method allows for more precise control of Ti incorporation even when one or more precursors cause surface undersaturation of the substrate during growth. Therefore, the inventors have found that the method allows for substantially reduced resistivity and greater stability of resistivity values.

[0139] Figure 13 is a flowchart illustrating a method for forming a TiSiN thin film, similar to the flowcharts described above with respect to Figures 5B to 5D. The illustrated method for depositing a TiSiN thin film includes exposing a semiconductor substrate to one or more (m) first deposition stages at position 525 and exposing a semiconductor substrate to one or more (n) second deposition stages at position 530. Each of the first deposition stages then includes a plurality of alternating exposures to a Ti precursor and an N precursor, and each of the second deposition stages then includes a plurality of alternating exposures to a Si precursor and an N precursor. Additional details of the method illustrated in Figure 13 have been described above with respect to Figures 5B to 5D, and will not be repeated here for the sake of brevity.

[0140] Figures 14 to 16 illustrate alternative or further improved methods for forming diffusion barriers including TiSiN, including further improvements in roughness and continuity at ultra-low thicknesses, and higher precision in controlling the Ti content, which allows for less variability in reducing resistivity.

[0141] Figure 14 is a flowchart illustrating a method for forming a diffusion barrier including TiSiN according to an embodiment. The method includes step 1402 of exposing a semiconductor substrate to one or more first deposition stages alternating with one or more second deposition stages. In this method, exposing the semiconductor substrate 1404 to one or more first deposition stages includes alternating exposure of the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. In this method, exposing the semiconductor substrate 1406 to one or more second deposition stages includes sequentially exposing the semiconductor substrate to a Ti precursor and a silicon (Si) precursor without intermediate exposure to an N precursor, followed by exposure of the semiconductor substrate to the N precursor.

[0142] Figure 15 is a flowchart illustrating a method for forming a diffusion barrier including TiSiN according to another embodiment. The method includes step 1502 of exposing a semiconductor substrate to one or more first deposition stages alternating with one or more second deposition stages. In this method, exposing the semiconductor substrate 1504 to one or more first deposition stages includes alternatingly exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. In this method, exposing the semiconductor substrate 1506 to one or more second deposition stages includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by an N precursor.

[0143] Figure 16 is a flowchart illustrating a method for forming a diffusion barrier comprising TiSiN according to another embodiment. The method includes step 1602 of exposing a semiconductor substrate to one or more first deposition stages alternating with one or more second deposition stages. In this method, exposing the semiconductor substrate 1604 to one or more first deposition stages includes alternating exposure of the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. In this method, exposing the semiconductor substrate 1606 to one or more second deposition stages includes exposing the semiconductor substrate to a Ti precursor for a Ti precursor exposure duration, followed by a silicon (Si) precursor for a Si precursor exposure duration, followed by an N precursor, wherein the ratio of the Si precursor exposure duration to the Ti precursor exposure duration is between 2 and 130.

[0144] Figure 17 is a flowchart illustrating a method for forming a TiSiN thin film according to an embodiment, illustrating a precursor exposure sequence compatible with any of the embodiments illustrated above with respect to Figures 14 to 16. Unlike the method described above with respect to Figure 13, in the second deposition stage, the Ti precursor is exposed before the Si precursor, which is then followed by the N precursor exposure. The illustrated method includes exposing a substrate to one or more (x) vapor deposition cycles 1720, each vapor deposition cycle 1720 including exposing the semiconductor substrate 1725 to one or more (m) first deposition stages and exposing the semiconductor substrate 1730 to one or more (n) second deposition stages. In the illustrated embodiment, the first and second deposition stages alternate and do not overlap in time. In the illustrated method, the sequence of exposing the semiconductor substrate to one or more first deposition stages 1725 can be substantially the same as that described above with respect to Figures 5B to 5D and Figure 13, in which the semiconductor substrate is exposed to one or more (m) first deposition stages 525. Specifically, exposing the semiconductor substrate to one or more first deposition stages 1725 includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor in a manner similar to that described above with respect to Figures 5B to 5D and Figure 13, the details of which are not repeated herein for the sake of brevity.

[0145] However, unlike the method described above with respect to Figure 13 (and Figures 5B to 5D), the method illustrated in Figure 17 further includes exposing the semiconductor substrate to a titanium (Ti) precursor in each of the second deposition stages. Specifically, exposing the semiconductor substrate to one or more second deposition stages includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, and then an N precursor.

[0146] Alternatively, exposing the semiconductor substrate 1730 may include sequentially exposing the semiconductor substrate to the Ti precursor and the Si precursor without intermediate exposure to the N precursor, and then exposing the semiconductor substrate to the N precursor. In the embodiment illustrated in FIG17, when the second deposition stage immediately follows the first deposition stage, exposing the semiconductor substrate 1725 to the first deposition stage includes exposing the semiconductor substrate to the N precursor as the final precursor and exposing the semiconductor substrate to the Ti precursor as the first precursor of the second deposition stage.

[0147] Although details are omitted for brevity in this document, the various process parameters used in the illustrated embodiment of Figure 17 are similar to those used in the methods described above with respect to Figures 13 and / or 5B to 5D, including the precursor, chamber pressure during deposition, and deposition temperature. Similar parameters are not repeated in this document for the sake of brevity.

[0148] The inventors have discovered that, for the various reasons stated above, exposing the Ti precursor before the Si precursor can be advantageous, as described herein. To enhance this advantageous effect, the Ti precursor exposure during the second deposition stage can be optimized relative to other exposures with respect to various parameters, including precursor flow rate and exposure duration.

[0149] To achieve a suitable flow rate for depositing TiSiN thin films on substrates with high surface area and / or high aspect ratio structures using a deposition process with Ti surface treatment prior to Si precursor exposure, the flow rates of both the Ti and Si precursors can be adjusted to less than 1000 standard cubic centimeters per minute (sccm), 800 sccm, 600 sccm, 400 sccm, 200 sccm, or values ​​within or higher of any of these equivalents. The flow rate of the N precursor can be adjusted to even higher values, for example, less than 10,000 standard cubic centimeters per minute (sccm), 8,000 sccm, 6,000 sccm, 4,000 sccm, 2,000 sccm, or values ​​within or higher of any of these equivalents. It will be understood that suitable flow rates may depend particularly on the reactor volume, and such flow rates are suitable for single-wafer reactors with a volume of approximately 1 to 2 liters. For a reactor comprising multiple processing stations, these flow rates can be adapted to each processing station.

[0150] Referring back to Figure 17, the inventors have found that exposing the semiconductor substrate to the Ti precursor during the second deposition stage is particularly effective when the exposure time of the Ti precursor during exposure 1730 is shorter than the exposure time of the Si precursor. Advantageously, in certain embodiments, the relatively short exposure time of the Ti precursor in the second deposition stage results in a remarkably large improvement in resistivity and / or step coverage. In various embodiments, the ratio of the exposure time of the semiconductor substrate to the Si precursor and the exposure time of the semiconductor substrate to the Ti precursor in the second deposition stage exceeds 0.05, 0.1, 0.5, 1, 2, 5, 10, 20, 50, 100, 130, 200, 240, or values ​​within the range defined by any of these equivalents. For example, in the embodiment illustrated in Figure 17, the Si precursor exposure time in the second deposition stage may be less than 120 seconds, 90 seconds, 60 seconds, 30 seconds, 10 seconds, 5 seconds, 3 seconds, 2 seconds, 1 second, 0.5 seconds, or 0.1 seconds, or a value within the range defined by any of these equivalent values, and the Ti exposure time in the second deposition stage may be less than 2 seconds, 1.5 seconds, 1.2 seconds, 1.0 seconds, 0.7 seconds, or 0.5 seconds, or a value within the range defined by any of these equivalent values.

[0151] Referring again to Figure 17, the inventors have further discovered that exposing the semiconductor substrate to the Ti precursor during the exposure phase from exposure 1730 to the second deposition stage is particularly effective when the exposure time of the Ti precursor during exposure 1730 to the second deposition stage is longer than the exposure time of the Ti precursor during exposure 1725 to the first deposition stage. Advantageously, in various embodiments, the ratio of the exposure time of the semiconductor substrate to the Ti precursor in the second deposition stage to the exposure time of the semiconductor substrate to the Ti precursor in the first deposition stage exceeds 0.5, 1, 3, 5, 10, 20, 30, 40, or values ​​within the range defined by any of these equivalents. For example, in the embodiment illustrated in Figure 17, the Ti precursor exposure time in the first deposition stage may be less than 1 second, 0.5 seconds, 0.2 seconds, 0.1 seconds, or 0.05 seconds, or a value within the range defined by any of these equivalents, while the Ti exposure time in the second deposition stage may be less than 2 seconds, 1.5 seconds, 1.2 seconds, 1.0 seconds, 0.7 seconds, or 0.5 seconds, or a value within the range defined by any of these equivalents.

[0152] Referring again to Figure 17, the inventors have further discovered that exposing the semiconductor substrate to the N precursor during the exposure phase from exposure 1730 to the second deposition stage is particularly effective when the exposure time of the N precursor during exposure 1730 to the second deposition stage is longer than the exposure time of the N precursor during exposure 1725 to the first deposition stage. Advantageously, in various embodiments, the ratio of the exposure time of the semiconductor substrate to the N precursor in the second deposition stage to the exposure time of the semiconductor substrate to the N precursor in the first deposition stage exceeds 1, 2, 5, 10, 20, 50, 100, 200, 500, 600, or a value within the range defined by any of these equivalents. For example, in the embodiment illustrated in Figure 17, the N precursor exposure time in the first deposition stage may be less than 1 second, 0.5 seconds, 0.2 seconds, 0.1 seconds, or a value within the range defined by any of these equivalents, while the N exposure time in the second deposition stage may be less than 60 seconds, 30 seconds, 10 seconds, 5 seconds, 2 seconds, 1 second, 0.5 seconds, 0.2 seconds, or a value within the range defined by any of these equivalents.

[0153] Referring again to Figure 17, for illustrative purposes only, the typical durations of the Ti precursor pulse / Ti precursor removal / N precursor pulse / N precursor removal in the first deposition stage can be 0.05 seconds to 1 second / 0.2 seconds to 1 second / 0.1 seconds to 1 second / 0.2 seconds to 1 second, respectively. In the second deposition stage, the typical durations of the Ti precursor pulse / Ti precursor removal / Si precursor pulse / Si precursor removal / N precursor pulse / N precursor removal can be 0.5 seconds to 2 seconds / 0.2 seconds to 1 second / 0.2 seconds to 120 seconds / 0.5 seconds to 5 seconds / 0.2 seconds to 120 seconds / 0.5 seconds to 5 seconds, respectively.

[0154] By controlling the various Ti precursor exposure conditions during the second deposition stage as described herein, the TiSiN thin film formed using the method according to the embodiments can have a resistivity at least 200 μΩ–cm, 500 μΩ–cm, 1000 μΩ–cm, 1500 μΩ–cm, or within the range defined by any of these equivalents, lower than that formed using the same method (except that exposing the semiconductor substrate to the Ti precursor as part of one or more second deposition stages). Therefore, the formed TiSiN thin film can have a resistivity lower than 2500 μΩ–cm, 2000 μΩ–cm, 1500 μΩ–cm, 1000 μΩ–cm, 500 μΩ–cm, or within the range defined by any of these equivalents.

[0155] In addition to the exposure time, the ratio (m / n) of the number of the first deposition stage (m) to the number of the second deposition stage (n) can also be adjusted to tune various properties of the obtained TiSiN thin film.

[0156] Figure 18A is a graph showing the experimentally measured Si content of TiSiN films deposited according to the method illustrated in Figure 17, where the Si content is shown as varying according to the ratio of the number of first deposition stages to the number of second deposition stages. As shown, the Si content in the deposited TiSiN films decreases with increasing m / n ratio. As shown, when the m / n ratio increases to approximately 7 or higher, the rate of decrease in Si content according to the m / n ratio unexpectedly decreases (showing the inflection point). This decrease is consistent with the resistivity trend (Figure 18C). In the illustrated experimental results, adjusting the m / n ratio to be greater than 7 is shown to be crucial for forming TiSiN films with low resistivity (e.g., below approximately 2000 μΩ–cm) corresponding to a Si content of 15% or less. Above 15% or more of Si content corresponding to an m / n ratio greater than approximately 7, the nanostructure of TiSiN becomes substantially amorphous, as shown in Figure 18B.

[0157] Figure 18B is a graph of experimentally measured grazing-incidence X-ray diffraction (XRD) spectra of TiSiN films deposited according to the method shown in Figure 17, where different curves correspond to TiSiN films with different ratios of the number of first deposition stages to the number of second deposition stages. As shown, the XRD peak intensities of the (111), (002), and (220) domains are observed to decrease with decreasing m / n ratio. As indicated by the impurity ratio, the amount of amorphous phase in the TiSiN film increases with decreasing m / n ratio.

[0158] Figure 18C is a graph showing the resistivity experimentally measured on a TiSiN thin film with equal Si content, as plotted in Figure 18A. As shown, the resistivity of the TiSiN film decreases with increasing m / n ratio. As presented and discussed above, the rate of increase in resistivity unexpectedly increases when the m / n ratio drops below 7. In the experimental results shown, adjusting the m / n ratio to be greater than 7 is crucial for forming TiSiN thin films with resistivity of 2000 μΩ–cm or lower. Below this ratio, in addition to high resistivity values, the variability in resistivity with small variations in Si content makes the process unsuitable for mass production.

[0159] The inventors have discovered that, particularly before the exposure of the Si precursor in the second deposition stage, the resulting TiSiN film can exhibit relatively small variability in its low resistivity, varying with exposure time, even when the exposure of one or more of the Ti, Si, and N precursors in the second deposition stage causes undersaturation of the substrate surface. Therefore, the variability of the TiSiN film during continuous operation is reduced, and its manufacturability is enhanced. This is illustrated below with respect to various precursors. Furthermore, since a long exposure time is not required during the second deposition stage, throughput can be increased. Therefore, according to embodiments, exposing the semiconductor substrate to one or more of the Ti, Si, and N precursors (e.g., illustrated in any of Figures 14 to 17) during one or more second deposition stages includes causing undersaturation of the main surface of the semiconductor substrate.

[0160] As described herein, precursor surface saturation refers to a condition in which increasing the exposure time of a particular precursor does not result in a substantial change in the surface saturation induced by the precursor. Conversely, undersaturation refers to a condition in which increasing the exposure time of a particular precursor does indeed result in a substantial change in the surface saturation induced by the precursor. Although surface saturation is difficult to measure absolutely, it can be inferred by measuring relevant electrical or physical parameters. For example, for a given parameter, if exposure over a duration is used to achieve a given value for the parameter, and if additional exposure over the same or longer duration does not change the value of the parameter by more than, for example, 10%, then the surface can be inferred to be substantially saturated.

[0161] Figures 19A and 19B are graphs showing the experimentally measured resistivity of TiSiN films as the exposure time of the Ti precursor (TiCl₄) during the second deposition stage of the deposition cycle illustrated in Figures 14 to 17 varies, with the exposure time for dichlorosilane (SiH₂Cl₂, "DCS"), the Si precursor, fixed at 60 seconds and 90 seconds, respectively. As shown, the resistivity of the TiSiN film decreases with increasing Ti precursor exposure time in the second deposition stage. It is evident that the TiSiN film deposited using the same procedure (except omitting Ti precursor exposure in the second deposition stage) exhibits substantially lower resistivity with a Ti precursor exposure time as short as 0.7 seconds in the second deposition stage. Although longer exposure times further reduce resistivity, a substantial reduction is achieved with a Ti precursor pulse duration as short as 0.7 seconds. As shown, in the second deposition stage without precursor Ti exposure (zero on the x-axis), exposure to DCS for 90 seconds increases the resistivity from approximately 2800 μΩ cm to approximately 3200 μΩ cm, a 10% increase, compared to 60 seconds of exposure to DCS. That is, it can be inferred that 60 seconds of DCS may not be sufficient to substantially saturate the surface. However, regardless of the DCS saturation level, exposure to the Ti precursor for a duration as short as 0.7 seconds was observed to be effective in substantially reducing resistivity. Thereafter, any further increase in resistivity with additional Ti precursor exposure time resulted in substantially smaller resistivity changes. As shown, the TiSiN film obtained with a Ti precursor exposure duration of 1.2 seconds in the second deposition stage exhibits a relatively small change in resistivity (e.g., approximately 10% or less) compared to the TiSiN film obtained with a Ti precursor exposure duration of 0.7 seconds in the second deposition stage. The results show that by inserting a relatively short Ti precursor before the Si precursor in the second deposition stage, two advantageous technical effects are obtained: a substantial reduction in resistivity and a substantial reduction in resistivity variability.

[0162] Figures 20A to 20C are cross-sectional transmission electron micrographs of high aspect ratio structures of TiSiN films with linings formed during the second deposition stage of a deposition cycle similar to that shown in Figure 17, using different Ti precursor (TiCl₄) exposure times. The micrographs in Figures 20A to 20C were obtained on a planar semiconductor substrate after lining a TiSiN film with an equivalent thickness of approximately 4 nm with a high aspect ratio structure of 57:1 (measured using the width of the opening at the top). The TiSiN films imaged in the micrographs of Figures 20A to 20C were formed using the method shown in Figures 14 to 17, where the Si precursor (dichlorosilane) exposure time was fixed at 90 seconds during the second deposition stage, and the Ti precursor exposure times were 0 seconds, 0.7 seconds, and 1.2 seconds, respectively. As can be seen, the step coverage measured in the photomicrographs from Figure 20A to Figure 20C is 83%, 85%, and 87%, respectively.

[0163] Figures 21A to 21C are graphs of experimentally measured resistivity varying with the exposure time of the Ti precursor (TiCl₄) during the second deposition stage of the deposition cycle illustrated in Figures 14 to 17, where the exposure time for chlorosilane (SiH₃Cl, "MCS"), one of the Si precursors, is fixed at 3.5 seconds, 30 seconds, and 90 seconds, respectively. As illustrated, a decrease in the resistivity of the TiSiN film can be observed as the exposure time of the Ti precursor in the second deposition stage increases. It is evident that the TiSiN film deposited using the same procedure (except omitting the Ti precursor exposure in the second deposition stage) exhibits substantially lower resistivity with a Ti precursor exposure time as short as 0.7 seconds in the second deposition stage. Although a longer exposure time further reduces the resistivity, a substantial reduction is achieved with a pulse duration as short as 0.7 seconds. Similar observations described above with respect to Figures 19A and 19B can be made here. As shown, in the second deposition stage without leading Ti exposure (zero on the x-axis), regardless of the MCS saturation level, it was observed that Ti precursor exposure for a duration as short as 0.7 seconds was effective in substantially reducing resistivity. Subsequently, resistivity changes with further increases in Ti precursor exposure time resulted in substantially smaller resistivity changes. As shown, TiSiN films obtained with a Ti precursor exposure duration of 1.2 seconds exhibited a relatively small change in resistivity (e.g., about 10% or less) compared to TiSiN films obtained with a Ti precursor exposure duration of 0.7 seconds in the second deposition stage. The results demonstrate that by inserting a relatively short Ti precursor before the Si precursor in the second deposition stage, two advantageous technical effects are achieved: a substantial reduction in resistivity and a substantial reduction in resistivity variability.

[0164] Figures 22A to 22C are cross-sectional transmission electron micrographs of high aspect ratio structures of TiSiN films with linings formed during the second deposition stage of a deposition cycle similar to that shown in Figure 17, using different Ti precursor (TiCl₄) exposure times. The micrographs in Figures 22A to 22C were obtained on a planar semiconductor substrate after lining a TiSiN film with an equivalent thickness of approximately 4 nm with a high aspect ratio structure of 57:1 (measured using the width of the opening at the top). The TiSiN films imaged in Figures 22A and 22B were formed using a method similar to that shown in Figures 14 to 17, where the Si precursor (chlorosilane) exposure time was fixed at 3.5 seconds during the second deposition stage, and the Ti exposure times were 0 seconds and 1.2 seconds, respectively. The TiSiN thin film imaged in Figure 22C was formed using a method similar to that shown in Figures 14 to 17, wherein in the second deposition stage, the Si precursor (chlorosilane) was exposed for 90 seconds, and the Ti was exposed for 1.2 seconds. As can be seen, the step coverage measured in the micrographs of Figures 22A to 22C is 86%, 93%, and 96%, respectively.

[0165] Figures 23A and 23B are graphs of experimentally measured resistivity varying with the exposure time of the Ti precursor (TiCl₄) during the second deposition stage of the deposition cycle shown in Figures 14 to 17, where the exposure time for trisilicon octachloride (Si₃Cl₈, "OTCS"), the Si precursor, is fixed at 5 seconds and 30 seconds, respectively. As shown, a decrease in the resistivity of the TiSiN film can be observed as the Ti precursor exposure time increases during the second deposition stage. It is evident that the TiSiN film deposited using the same procedure (except omitting the Ti precursor exposure in the second deposition stage) exhibits substantially lower resistivity with a Ti precursor exposure time as short as 1.2 seconds during the second deposition stage. A similar observation to that described above with respect to Figures 19A and 19B can be made here. As demonstrated, in the second deposition stage without leading Ti exposure (zero on the x-axis), regardless of the OTCS saturation level, exposure of the Ti precursor for a duration as short as 1.2 seconds was observed to be effective in substantially reducing resistivity. Similarly, by inserting a relatively short Ti precursor before the Si precursor in the second deposition stage, two advantageous technical effects are obtained: a substantial reduction in resistivity and a substantial reduction in resistivity variability.

[0166] Figures 24A and 24B are cross-sectional transmission electron micrographs of high aspect ratio structures of TiSiN films with linings formed during the second deposition stage of a deposition cycle similar to that shown in Figure 17, using different Ti precursor (TiCl₄) exposure times. The micrographs in Figures 24A and 24B were obtained on a planar semiconductor substrate after lining a TiSiN film with an equivalent thickness of approximately 4 nm with a high aspect ratio structure of 57:1 (measured using the width of the opening at the top). The TiSiN films imaged in Figures 24A and 24B were formed using a method similar to that shown in Figures 14 to 17, where the Si precursor (OTCS) exposure time was fixed at 5 seconds during the second deposition stage, while the Ti precursor exposure times were 0 seconds and 1.2 seconds, respectively. As can be seen, the step coverage measured in the micrographs of Figures 24A and 24B are 96% and 100%, respectively.

[0167] Advantageously, the transmission electron micrographs shown in Figures 20A to 20C, 22A to 22C, and 24A to 24B confirm that TiSiN significantly improves the smoothness of the ultrathin diffusion barrier compared to ALD TiN films (see, for example, Figure 12). In each of the transmission electron micrographs shown in Figures 20A to 20C, 22A to 22C, and 24A to 24B, the TiSiN film continuously covers the substrate surface with a thickness of less than 5 nm.

[0168] In the transmission electron micrographs shown in Figures 20A to 20C, 22A to 22C, and 24A to 24B, the aspect ratio of 57:1 has been measured as the ratio of the height to the width of the top opening. Figure 25A shows a full view of the ditch structure. It will be understood that the aspect ratio can be defined in various ways. For example, the ratio of the height to the width of the bottom opening is approximately 171:1. [TiN] [ / TiSiN] [Nano-layer diffusion barrier deposition] []

[0169] Referring back to the methods described above with respect to Figures 13 and 17, the inventors have discovered that the ratio (m / n) of the number of first deposition stages (m) to the number of second deposition stages (n) can be adjusted to form a substantially uniform film including TiSiN or a nanolayer including TiN and TiSiN as dissimilar layers.

[0170] Figure 26A is a flowchart illustrating a method for forming a nano-layered thin film according to some embodiments. As illustrated in Figure 26A, the method includes depositing a TiN film by exposing a semiconductor substrate to one or more (y1) first deposition stages, depositing a TiSiN film by exposing the semiconductor substrate to one or more (x) second deposition stages, and forming another TiN film by exposing the semiconductor substrate to one or more (y2) first deposition stages. In some embodiments, y1 and y2 are different. Figure 26B is a flowchart illustrating a method for forming a nano-layered thin film using a vapor deposition cycle similar to that illustrated in Figures 5B to 5D and Figure 13 according to some embodiments. Figure 26C is a flowchart illustrating a method for forming a nano-layered thin film using a vapor deposition cycle similar to that illustrated in Figures 14 to 17 according to some embodiments.

[0171] According to various embodiments, when forming a thin film (e.g., including a diffusion barrier layer of TiSiN) to form a substantially uniform layer, the number of back-to-back operations of the first deposition stage and / or the second deposition stage during deposition at the temperatures disclosed above may be less than about 50, 30, 25, 20, 15, 10, 5, or values ​​within the range defined by any of these equivalents. On the other hand, when the number of back-to-back operations of the first deposition stage and / or the second deposition stage exceeds these values, the thin film may include a nanolayer structure.

[0172] Figure 27A is a graph showing the resistivity experimentally measured on various nano-layer films deposited according to the methods illustrated in Figures 26A and 26C, according to some embodiments. The measured nano-layer films include a TiSiN film interposed between two TiN films. It can be seen that the resistivity can be tuned by independently adjusting the thickness of the upper and lower TiN films. Surprisingly, although the total combined thickness of the TiN films is the same in the three measured nano-layer films, the resistivity unexpectedly decreases when the lower TiN film is thinner than the upper TiN film. It will be understood that at least the various advantages described above regarding uniform TiSiN films have been observed in the nano-layers according to the embodiments.

[0173] Figure 27B is a graph of experimentally measured grazing incidence X-ray diffraction spectra of various nanolayered films deposited according to the methods illustrated in Figures 26A and 26C, based on some embodiments.

[0174] Figures 28A and 28B are cross-sectional transmission electron micrographs of a high aspect ratio structure of a self-contained nano-layered film with a liner according to some embodiments. It can be seen that the stepped coverage is comparable to that of a uniform TiSiN film. [Possesses superior mechanical properties, including high modulus and hardness] [TiSiN] [film] []

[0175] As described above, thin films including TiSiN are desirable for many applications, such as forming electrodes and / or diffusion barriers lined with high aspect ratio vias or trenches. As discussed above, the procedural conditions described above with respect to (for example) Figures 5A to 5D for conformally coating relatively high area density substrates with high aspect ratio structures can be optimized by controlling, in particular, the reaction chamber pressure or precursor partial pressure, deposition rate, temperature or pressure of the precursor introduced into the reaction chamber, precursor flow rate, and exposure time during deposition.

[0176] Beyond electrical and barrier properties, the diverse applications of TiSiN increasingly demand improved structural and mechanical properties of TiSiN thin films. For example, as the feature size of integrated circuit devices continues to shrink and / or the aspect ratio increases, the physical requirements for thin films used as diffusion barriers and / or electrodes continue to increase. Film thickness can also decrease with shrinking feature sizes, and films can be subjected to correspondingly higher levels of thermomechanical stress. While TiN is one of the dominant materials for many applications, structural failures of TiN in high aspect ratio structures are a major concern for the reliability and yield of integrated circuit devices. Failure modes (such as defects, bending, and warping) have been associated with insufficient physical properties of TiN films (such as hardness and elastic modulus). Therefore, with the increasing demand for complex three-dimensional structures, there is a need for alternative barrier materials with superior physical properties. To address these and other needs, this paper describes methods for forming and tuning TiSiN thin films with superior mechanical properties, and thin films formed using these methods.

[0177] As described herein, the inventors have discovered alternative methods and / or further improvements to the various methods described above for improving the mechanical and structural properties of TiSiN films, in addition to their electrical and structural properties. As described above, the inventors have discovered that even when grown by atomic layer deposition, ultrathin (e.g., <5 nm) TiN layers can still discontinuously cover the underlying surface and exhibit discontinuities. Besides limiting the effectiveness of the TiN layer as a diffusion barrier, these discontinuities can also severely impair the mechanical and structural properties of the TiN film.

[0178] Unlike TiN thin films, the inventors have discovered that TiSiN, when deposited under the specific deposition conditions described herein, can provide continuous and uniform coverage even at ultra-thin dimensions (e.g., < 5 nm), which is particularly critical for providing superior mechanical and structural properties for applications in ultra-thin diffusion barriers for advanced technology nodes. For example, in a manner similar to that described above with respect to Figures 14 to 17, a semiconductor substrate is exposed to one or more first deposition stages that alternate with and do not overlap with one or more second deposition stages, wherein: exposing the semiconductor substrate to the one or more first deposition stages includes alternating exposure of the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor; and exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor, followed by a silicon (Si) precursor, followed by an N precursor. That is, in the second deposition stages, the exposure of the Ti precursor precedes the exposure of the Si precursor, which is then followed by the exposure of the N precursor. The method further improves the continuity and structural properties of TiSiN films with improved mechanical integrity, even down to ultrathin (e.g., <5 nm) dimensions.

[0179] Figure 29 is a flowchart illustrating a method for forming a TiSiN thin film with improved mechanical and structural properties according to some embodiments. In these embodiments, the method includes forming a 2902 diffusion barrier comprising TiSiN by exposing a semiconductor substrate to one or more first deposition stages alternating with one or more second deposition stages. The diffusion barrier has: a modulus exceeding 290 GPa and a Si content exceeding 2.7 atomic%; or a hardness exceeding 20 GPa and a Si content exceeding 2.7 atomic%; or a crystalline texture such that the sum of the area at the (002) peak and the area at the (111) and (222) peaks of the grazing incidence X-ray diffraction spectrum of the diffusion barrier exceeds 0.4 and a Si content exceeding 2.7 atomic%; or a nanocrystalline structure having an average grain size of less than about 6.5 nm and a Si content exceeding 2.7%. Exposing the semiconductor substrate 2904 to one or more first deposition stages includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate 2906 to one or more second deposition stages includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by an N precursor.

[0180] Various embodiments of the method illustrated in Figure 29 may include the features described above with respect to Figures 5B to 5D and Figures 13 or 14 to 17, the details of which are not repeated herein for the sake of brevity. For example, according to an embodiment, the exposure time of each of the Ti precursor exposure time in the first deposition stage, the N precursor exposure time in the first deposition stage, and the N precursor exposure time in the second deposition stage may be less than 1.0 s, 0.8 s, 0.6 s, 0.4 s, 0.2 s, 0.1 s, or values ​​within the range defined by any of these equivalents. The thin film deposition system may be configured to introduce each precursor at its respective flow rate such that the surface of the substrate substantially reaches a saturation level during these exposure times, for example, a saturation level greater than 40%, 60%, 80%, or values ​​within the range defined by any of these equivalents. In one embodiment illustrated in Figure 17, a rapid removal step following exposure of the precursor may last for less than 1.0 seconds, 0.8 seconds, 0.6 seconds, 0.4 seconds, 0.2 seconds, 0.1 seconds, or within a range defined by any of these equivalent values.

[0181] Referring back to Figure 17, in another example, the inventors have found that exposing the semiconductor substrate to the Ti precursor during the exposure phase from exposure 1730 to the second deposition stage is particularly effective when the exposure time of the Ti precursor during exposure 1730 is the same as or shorter than the exposure time of the N precursor. In various embodiments, the ratio of the exposure time of the semiconductor substrate to the Ti precursor and the exposure time of the semiconductor substrate to the Si precursor during the second deposition stage is greater than 1, 0.2, 0.4, 0.6, 0.8, and 1.0, or values ​​within the range defined by any of these equivalents. For example, in the embodiment illustrated in Figure 17, the Si precursor exposure time in the second deposition stage may be less than 30 seconds, 15 seconds, 10 seconds, 5 seconds, 1 second, 0.5 seconds, or a value within the range defined by any of these equivalents, while the Ti exposure time in the second deposition stage may be 0 or less than 2 seconds, 1.5 seconds, 1.0 seconds, 0.5 seconds, 0.2 seconds, or a value within the range defined by any of these equivalents.

[0182] Referring back to Figure 17, for illustrative purposes only, in a specific example, the typical durations of the Ti precursor pulse / Ti precursor removal / N precursor pulse / N precursor removal in the first deposition stage can be 0.15 s / 0.53 s / 0.2 s / 0.32 s, respectively, while the typical durations of the Ti precursor pulse / Ti precursor removal / Si precursor pulse / Si precursor removal / N precursor pulse / N precursor removal in the second deposition stage can be 0 s to 1.0 s / 0.3 s / 1 s to 10 s / 0.5 s / 0.5 s / 0.5 s, respectively.

[0183] In addition to the exposure time, the ratio (m / n) of the number of first deposition stages (m) to the number of second deposition stages (n) can also be adjusted to tune various properties of the obtained TiSiN thin film. m / n can be greater than 5, 10, 20, 40, 60, 80 and 100.

[0184] Figure 30 is a graph illustrating the tunability of the Si content in TiSiN films according to embodiments, achieved by tuning the precursor exposure time and / or the ratio of the number of first deposition stages to the number of second deposition stages. The x-axis plots the m:n ratio, and the y-axis plots the Si content in the TiSiN film as measured by X-ray photoelectron spectroscopy (XPS). Three curves showing the decrease in Si content as the m / n ratio increases correspond to Si precursor exposure times of 1 second, 5 seconds, and 10 seconds for a fixed Ti precursor exposure time of 1 second. It can be seen that different combinations of m / n ratio and Si precursor exposure time produce TiSiN films with Si content ranging from approximately 2.7 atomic% to 9 atomic%, a range that has been particularly shown to be effective for providing superior mechanical properties.

[0185] The area under a specific peak in the grazing incidence X-ray diffraction spectrum can be monitored as an indicator of a specific structural performance parameter of the TiSiN film deposited according to the embodiments. Specifically, the inventors have discovered that the TiSiN film deposited according to the embodiments has a crystalline structure such that the ratio (R) of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks in the grazing incidence X-ray diffraction spectrum of the TiSiN film can be monitored as an indicator of a specific structural performance parameter of the TiSiN film. Without any theoretical constraints, the ratio R can be correlated with the preferential (002) texturing of the nanocrystalline domains of the TiSiN film. Figures 31A to 31I are experimentally measured grazing incidence X-ray diffraction (XRD) spectra of TiSiN films with different Si contents.

[0186] Figure 32 is a graph summarizing the XRD spectra shown in Figures 31A to 31I. The results of the ratio (R) for TiSiN films with different Si contents are summarized in Table 1 below. According to various embodiments, the ratio (R) of the area at the (002) peak to the sum of the areas at the (111) and (222) peaks for TiSiN films with a Si content of more than 2.7 atomic percent can exceed 0.4, 1.0, 2.0, 3.0, 4.0, 4.5, or have values ​​within the range defined by any of these equivalents. As illustrated, for TiSiN films with a Si content of about 7 atomic percent, the R ratio peaks at around 4.5 and then unexpectedly decreases. The inventors have found that higher values ​​of the R ratio can be associated with improved hardness and modulus, as described below. Table 1. X-ray peak area and ratio in TiSiN relative to Si content Si content Average crystallite size Area under

[0111] Area under

[0002] Area under

[0022] Area under

[0113] Area under

[0222] R =

[0002] / (

[0111] +

[0222] ) 2.7 63 1635 644 817 330 162 0.4 3.5 62 1224 745 483 348 228 0.5 3.8 60 907 912 411 350 278 0.8 4.5 59 245 1208 618 204 104 3.5 5.5 58 182 1388 656 233 170 4.0 5.8 58 159 1226 644 207 146 4.0 6.0 57 183 1411 744 213 143 4.3 6.8 56 117 987 559 163 104 4.5 9.0 54 108 1038 627 187 220 3.2

[0187] Figure 33 is a graph showing the estimated average nanocrystalline grain size varying with Si content calculated from measured grazing-incidence X-ray diffraction (XRD) spectra, as shown in Figures 31A to 31I. The average grain size was calculated using the broadened peaks of the XRD spectra using the Scherrer method known in this art. The TiSiN films have nanocrystalline structures with average grain sizes less than about 6.5 nm, 6.0 nm, 5.5 nm, 5.0 nm, or within a range defined by any of these equivalents. The inventors have discovered that for grain sizes greater than about 5.5 nm corresponding to about 7 atomic % Si, smaller grain sizes can be associated with improved hardness and modulus, as described below.

[0188] Figure 34 is a graph showing the variation of hardness values ​​based on the Si content measured on TiSiN films corresponding to the procedural conditions shown in Figure 30. Figure 35 is a graph showing the variation of modulus values ​​based on the Si content of TiSiN films corresponding to the procedural conditions shown in Figure 30. Hardness and modulus values ​​were measured using nanoindentation techniques. As shown, hardness and modulus values ​​are generally proportional to the R ratio (Figure 32) and follow the same general trend as the R ratio. As shown, the peak values ​​of hardness and modulus values ​​generally coincide with the peak value of the R ratio and reach a peak for TiSiN films with a Si content of approximately 7 atomic% and then unexpectedly decrease. In addition, hardness and modulus values ​​are generally inversely proportional to the grain size, down to approximately 5.5 nm, corresponding to approximately 7 atomic% Si.

[0189] Without any theoretical constraints, increased hardness and modulus can be associated with a grain boundary hardening effect, where increased Si content leads to smaller grain size and therefore higher grain boundary density. Grain boundaries can interact with each other to form a dense three-dimensional network of grain boundaries. Under these conditions, due to the three-dimensional network of grain boundaries, grain movement under external forces is greatly restricted, resulting in higher hardness and modulus values. However, as illustrated, this effect peaks near a Si content of 7 atomic percent, above which hardness and modulus actually decrease. Without any theoretical constraints, this can be attributed to an increased fraction of amorphous phase, which reduces the grain boundary hardening effect. Therefore, increasing the Si content to improve hardness and modulus values ​​can be effective up to a critical value of approximately 7 atomic percent. According to various embodiments, the TiSiN films of the embodiments have Si contents exceeding any of the values ​​listed in Table 1 to achieve the modulus and hardness disclosed herein. In certain embodiments, the Si content does not exceed 7%.

[0190] Figure 36 shows low- and high-resolution cross-sectional transmission electron micrographs of a high aspect ratio structure of a self-made TiSiN thin film with a liner according to an embodiment. The high aspect ratio structure is similar to that described above with respect to Figures 25A to 25B. According to the embodiment, the TiSiN thin film with high modulus and hardness as described herein also exhibits excellent uniformity and step coverage, with step coverage exceeding >85% when measured using cross-sectional TEM images of the high aspect ratio structure shown in Figure 36. As an example method for measuring step coverage, the distances indicated as (top surface of the top portion) TT, (left surface of the top portion) TS-L, (right surface of the top portion) TS-R, (left surface of the bottom portion) BS-L, and (right surface of the bottom portion) are measured by averaging multiple measurements using an image processing software program. For the specific high aspect ratio structure shown in Figure 36, the measurements are: TT = 12.87 nm, TS-L = 11.96 nm, TS-R = 11.81 nm, BS-L = 10.67 nm, BS-R = 11.11 nm. The stepped coverage is calculated as: SC = (BS-L + BS-R) / (TS-L + TS-R) = 21.78 nm / 23.77 nm = 92%. Alternatively, the stepped coverage can be calculated as: (BS-L + BS-R)² / (TT) = 10.89 / 12.87 nm / 23.77 nm = 85%.

[0191] According to the embodiments, the diffusion barrier of TiSiN deposited with high modulus and hardness can have a root mean square (RMS) surface roughness value of less than 0.4 nm, 0.3 nm, 0.2 nm, 0.1 nm, or a value within the range defined by any of these equivalents, or lower. The reduced RMS roughness can subsequently improve the conformality of the diffusion barrier layer. Figure 37A is an atomic force microscope image of the TiSiN thin film deposited according to the embodiments. The measured RMS roughness is 0.27 nm. Figure 37B is an atomic force microscope image of the TiN thin film as a comparative example. For TiN films with considerable thickness, the RMS roughness is substantially higher at 0.67 nm. [Additional Examples] [I] 1. A method for forming a diffusion barrier, the method comprising: Thin films comprising one or both of TiSiN and TiAlN are formed by exposing a semiconductor substrate to a plurality of vapor deposition cycles at a pressure greater than 1 Torr in a reaction chamber. These vapor deposition cycles include exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor. The semiconductor substrate includes a surface morphology in which the ratio of the surface area of ​​the semiconductor substrate exposed to the one or more vapor deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate exceeds 2. 2. The method of Example 1, wherein the surface morphology includes a plurality of trenches or through holes having an aspect ratio of more than 5. 3. The method of Example 2, wherein the number and size of the trenches or through holes are such that the ratio of the surface areas exceeds 20. 4. The method of Example 1, wherein forming the thin film includes exposing the semiconductor substrate to one or more vapor deposition cycles under a pressure of 3 to 10 Torr in the reaction chamber. 5. The method of Example 1, wherein one or more of the Ti precursor, the N precursor and the Si or Al precursor are liquids at room temperature and atmospheric pressure. 6. The method of Example 1, wherein exposing the semiconductor substrate to the one or more vapor deposition cycles includes: The semiconductor substrate is exposed to a plurality of first deposition stages, each of which includes exposure to the Ti precursor and exposure to the N precursor; and The semiconductor substrate is exposed to a plurality of second deposition stages, each of which includes exposure to one or both of the Si precursor or the Al precursor. 7. The method of Example 6, wherein at least one of the second deposition stages further includes further exposure to the N precursor. 8. The method of Example 6, wherein the ratio of the number of the first deposition stages to the number of the second deposition stages is such that the film is at least partially amorphous. 9. The method of Example 8, wherein the ratio of the number of the first deposition stages to the number of the second deposition stages is equal to or less than 15:1. 10. The method of Example 8, wherein the thin film comprises TiSiN having a silicon concentration of more than about 10 atomic percent. 11. The method of Example 6, wherein the number of the first deposition stages and the number of the second deposition stages are such that the film is substantially uniform in the depth direction. 12. The method of Example 11, wherein the number of the first deposition stages or the number of the second deposition stages does not exceed about 50 cycles. 13. The method of Example 1, wherein the thin film comprises TiSiN, and wherein the Si precursor system is selected from compounds of the group consisting of SiH4, Si2H6, SiH2Cl2, SiH3Cl, Si2Cl6 and Si3Cl8. 14. The method of Example 1, wherein the thin film comprises TiAlN, and wherein the Al precursor system is selected from compounds of the group consisting of trimethylaluminum, triisobutylaluminum and tri(dimethylamino)aluminum. 15. The method of Example 1, wherein the semiconductor substrate is exposed to the vapor deposition cycle at a substrate temperature of 450 °C to 650 °C. 16. A method for forming a diffusion barrier, comprising: A semiconductor substrate is provided, the semiconductor substrate including a plurality of openings formed thereon, wherein the openings include dielectric sidewall surfaces and an aspect ratio of more than 5; and By exposing the semiconductor substrate to a plurality of vapor deposition cycles, a diffusion barrier layer of at least partially amorphous material, including one or both of TiSiN and TiAlN, is applied to the surface of the openings, wherein the vapor deposition cycles include exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor. 17. The method of Example 16, wherein the aspect ratio of the openings exceeds 5. 18. The method of embodiment 17, wherein lining the surface of the openings includes conformally lining such that the ratio of the thickness of the diffusion barrier layer formed at 25% below the height of the openings to the thickness formed at 25% above the height of the openings exceeds 0.6. 19. The method of Example 16, wherein the number and size of the openings are such that the ratio of the surface area of ​​the semiconductor substrate exposed to the one or more vapor deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate exceeds 2. 20. The method of Example 16, wherein lining the surface of the opening includes exposing the semiconductor substrate to the vapor deposition cycle under a pressure of 3 to 10 Torr in the reaction chamber. 21. The method of Example 16, wherein the openings further include an exposed semiconductor bottom surface. 22. The method of Example 16, wherein exposing the semiconductor substrate to the vapor deposition cycles comprises: The semiconductor substrate is exposed to a plurality of first deposition stages, wherein the first deposition stages include exposure to the Ti precursor and exposure to the N precursor; and The semiconductor substrate is exposed to a plurality of second deposition stages, wherein the second deposition stages include exposure to one or both of the Si precursor or the Al precursor. 23. The method of Example 22, wherein the second deposition stage further includes further exposure to the N precursor. 24. The method of Example 22, wherein the ratio of the number of the first deposition stages to the number of the second deposition stages is such that the diffusion barrier layer is at least partially amorphous. 25. The method of Example 24, wherein the ratio of the number of the first deposition stages to the number of the second deposition stages is 2:3, 3:2, 5:4, 7:3, 7:5, 7:1, 10:1 or 15:1. 26. The method of Example 22, wherein the number of the first deposition stages and the number of the second deposition stages are such that the diffusion barrier layer is substantially uniform in the depth direction. 27. The method of Example 26, wherein the number of the first deposition stages or the number of the second deposition stages does not exceed about 50 cycles. 28. The method of Example 22, wherein the number of the first deposition stages and the number of the second deposition stages are such that the diffusion barrier layer has a nanolayer structure. 29. The method of Example 16, wherein the root mean square surface roughness of the diffusion barrier layer is less than about 5% based on the average thickness of the diffusion barrier layer. 30. The method of Example 16, wherein the diffusion barrier layer comprises TiSiN, and wherein the Si precursor system is selected from compounds of the group consisting of SiH4, Si2H6, SiH2Cl2, SiH3Cl, Si2Cl6 and Si3Cl8. 31. The method of Example 16, wherein the diffusion barrier layer comprises TiAlN, and wherein the Al precursor system is selected from compounds of the group consisting of trimethylaluminum, triisobutylaluminum and tri(dimethylamino)aluminum. 32. The method of Example 16, wherein the semiconductor substrate is exposed to the vapor deposition cycle at a substrate temperature of 450 °C to 650 °C. 33. A method for forming a thin film, the method comprising: Thin films comprising one or both of TiSiN and TiAlN are formed by exposing a semiconductor substrate to a plurality of vapor deposition cycles at a pressure greater than 5 Torr in a reaction chamber, wherein such vapor deposition cycles include exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor. 34. The method of Example 33, wherein the pressure in the reaction chamber is less than 10 Torr. 35. The method of Example 33, wherein the semiconductor substrate includes a surface morphology such that the ratio of the surface area of ​​the semiconductor substrate exposed to the one or more vapor deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate exceeds 2. 36. The method of Example 35, wherein the semiconductor substrate includes a plurality of trenches or vias formed thereon, wherein the trenches or vias include dielectric sidewall surfaces and an aspect ratio of more than 5. 37. The method of Example 33, wherein exposing the semiconductor substrate to the one or more vapor deposition cycles includes: The semiconductor substrate is exposed to a plurality of first deposition stages, wherein the first deposition stages include exposure to the Ti precursor and exposure to the N precursor; and The semiconductor substrate is exposed to a plurality of second deposition stages, wherein the second deposition stages include exposure to one or both of the Si precursor or the Al precursor. 38. The method of Example 37, wherein the second deposition stage further includes further exposure to the N precursor. 39. The method of Example 37, wherein the ratio of the number of the first deposition stages to the number of the second deposition stages is such that the film is at least partially amorphous. 40. The method of Example 39, wherein the ratio of the number of the first deposition stages to the number of the second deposition stages is equal to or less than 15:1. 41. The method of Example 37, wherein the number of the first deposition stages and the number of the second deposition stages are such that the film is substantially uniform in the depth direction. 42. The method of Example 41, wherein the number of the first deposition stages and the number of the second deposition stages do not exceed about 50 cycles. 43. The method of Example 33, wherein the thin film comprises TiSiN, and wherein the Si precursor system is selected from compounds of the group consisting of SiH4, Si2H6, SiH2Cl2, SiH3Cl, Si2Cl6 and Si3Cl8. 44. The method of Example 33, wherein the thin film comprises TiAlN, and wherein the Al precursor system is selected from compounds of the group consisting of trimethylaluminum, triisobutylaluminum and tri(dimethylamino)aluminum. 45. The method of Example 33, wherein the semiconductor substrate is exposed to the vapor deposition cycle at a substrate temperature of 450 °C to 650 °C. 46. ​​A semiconductor structure comprising: A semiconductor substrate, the semiconductor substrate including a plurality of trenches or vias formed thereon, wherein the trenches or vias include dielectric sidewall surfaces and an aspect ratio of more than 5; and A diffusion barrier layer comprising one or both of TiSiN or TiAlN conformally lining the surface of the trenches or vias, wherein the diffusion barrier layer is at least partially amorphous. 47. The semiconductor structure of Example 46, wherein the aspect ratio of the trenches or vias exceeds 5. 48. The semiconductor structure of embodiment 47, wherein the diffusion barrier layer is conformally lined to the surfaces such that the ratio of the thickness of the diffusion barrier layer formed at 25% below the height of the trenches or vias and at 25% above the height of the trenches or vias exceeds 0.6. 49. The semiconductor structure of Example 46, wherein the area density of the trenches or vias is such that the ratio of the surface area of ​​the diffusion barrier layer formed thereon to the surface area of ​​the corresponding unpatterned semiconductor substrate exceeds 2. 50. The semiconductor structure of Example 49, wherein the ratio of the surface areas exceeds 100. 51. The semiconductor structure of Example 46, wherein the diffusion barrier is substantially completely amorphous. 52. The semiconductor structure of Example 46, wherein the diffusion barrier layer is substantially uniform in the depth direction. 53. The semiconductor structure of Example 46, wherein the diffusion barrier layer has a nano-layer structure. 54. The semiconductor structure of Example 46, wherein the root mean square surface roughness of the diffusion barrier layer is less than about 5% based on the average thickness of the diffusion barrier layer. 55. The semiconductor structure of Example 46, wherein the diffusion barrier layer comprises TiSiN having a silicon concentration of more than about 10 atomic percent. 56. The semiconductor structure of Example 46, wherein the trenches or vias further include a semiconductor bottom surface. 57. The semiconductor structure of Example 46, wherein the trenches or vias are filled with tungsten or copper. 58. The semiconductor structure of Example 46, wherein the diffusion barrier has a thickness of about 1 nm to 10 nm. 59. The semiconductor structure of Example 46, wherein the trenches or vias have a width of about 10 nm to 1000 nm. 60. The semiconductor structure of Example 23, wherein the diffusion barrier layer has a resistivity of less than about 1600 μΩ-cm. [Additional Examples] [II] 1. A method for forming a diffusion barrier comprising TiSiN, the method comprising: This exposes the semiconductor substrate to one or more first deposition stages that alternate with one or more second deposition stages. The process of exposing the semiconductor substrate to the one or more first deposition stages includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor, and The process of exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor and the silicon (Si) precursor without intermediate exposure to the N precursor in between, and then exposing the semiconductor substrate to the N precursor. 2. A method for forming a diffusion barrier comprising TiSiN, the method comprising: This exposes the semiconductor substrate to one or more first deposition stages that alternate with one or more second deposition stages. The process of exposing the semiconductor substrate to the one or more first deposition stages includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor, and Exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor, then the silicon (Si) precursor, and then the N precursor. 3. A method for forming a diffusion barrier comprising TiSiN, the method comprising: This exposes the semiconductor substrate to one or more first deposition stages that alternate with one or more second deposition stages. The process of exposing the semiconductor substrate to one or more first deposition stages includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. The process of exposing the semiconductor substrate to the one or more second deposition stages includes exposing the semiconductor substrate to the Ti precursor for a Ti precursor exposure duration, followed by a silicon (Si) precursor for a Si precursor exposure duration, followed by the N precursor, and... The ratio of the exposure duration of the Si precursor to the exposure duration of the Ti precursor is between 2 and 130. 4. The method of any of the above embodiments, wherein the diffusion barrier formed by the method has a resistivity of 2000 μΩ–cm or lower. 5. The method of any of the above embodiments, wherein the diffusion barrier formed by the method has a resistivity that is at least 500 μΩ–cm lower than that formed by a method identical to the above, except that the semiconductor substrate is exposed to the Ti precursor as part of one or more second deposition stages. 6. The method of any of the above embodiments, wherein the semiconductor substrate includes an opening having an aspect ratio of more than 50, and wherein forming the diffusion barrier includes lining the surface of the opening such that the ratio of the thickness of the diffusion barrier formed at 25% below the height of the opening to the thickness formed at 25% above the height of the opening is greater than 0.9. 7. The method of any of the above embodiments, wherein exposing the semiconductor substrate to the one or more first deposition stages includes exposing the semiconductor substrate to the N precursor, which serves as the final precursor of the one or more first deposition stages. 8. The method of any of the above embodiments, wherein exposing the semiconductor substrate to the one or more second deposition stages includes exposing the semiconductor substrate to the Ti precursor, which serves as a first precursor of the one or more second deposition stages. 9. The method of any of the above embodiments, wherein the semiconductor substrate is exposed to the Ti precursor, which is the first precursor in the second deposition stage, immediately after the semiconductor substrate is exposed to the N precursor, which is the last precursor in the first deposition stage, without intermediate exposure to the N precursor. 10. The method of any of the above embodiments, wherein the ratio of the exposure time of the semiconductor substrate to the Si precursor and the exposure time of the semiconductor substrate to the Ti precursor in the second deposition stage exceeds 2. 11. The method of any of the above embodiments, wherein the ratio of the exposure time of the semiconductor substrate to the Si precursor and the exposure time of the semiconductor substrate to the Ti precursor in the second deposition stage is less than 130. 12. The method of any of the above embodiments, wherein the ratio of the exposure time of the semiconductor substrate to the Si precursor and the exposure time of the semiconductor substrate to the Ti precursor in the second deposition stage is between 2 and 130. 13. The method of any of the above embodiments, wherein the ratio of the exposure time of the semiconductor substrate to the Ti precursor in the second deposition stage and the exposure time of the semiconductor substrate to the Ti precursor in the first deposition stage is between 3 and 34. 14. The method of any of the above embodiments, wherein the ratio of the exposure time of the semiconductor substrate to the N precursor in the second deposition stage and the exposure time of the semiconductor substrate to the N precursor in the first deposition stage is between 5 and 50. 15. The method of any of the above embodiments, wherein the exposure time of the semiconductor substrate to the Si precursor exceeds 3 seconds, and the exposure time of the semiconductor substrate to the Ti precursor in the second deposition stage is less than 2 seconds. 16. The method of any of the above embodiments, wherein exposing the semiconductor substrate to the one or more first deposition stages and the one or more second deposition stages includes exposure in a reaction chamber at a pressure greater than 1 Torr. 17. The method of any of the above embodiments, wherein the semiconductor substrate includes a surface morphology such that the ratio of the surface area of ​​the semiconductor substrate exposed to the one or more first deposition stages and the one or more second deposition stages to the surface area of ​​the corresponding unpatterned semiconductor substrate exceeds 2. 18. The method of Example 17, wherein the surface morphology includes a plurality of trenches or through holes having an aspect ratio of more than 5. 19. The method of embodiment 17 or 18, wherein the number and size of the trenches or through holes are such that the ratio of the surface areas exceeds 20. 20. The method of any of the above embodiments, wherein exposing the semiconductor substrate to the one or more first deposition stages and the one or more second deposition stages includes exposure in the reaction chamber at a pressure of 3 to 10 Torr. 21. The method of any of the above embodiments, wherein the ratio of the number of the first deposition stages to the number of the second deposition stages is such that the diffusion barrier is at least partially amorphous. 22. The method of any of the above embodiments, wherein the ratio of the number of the first deposition stages to the number of the second deposition stages is greater than 3. 23. The method of any of the above embodiments, wherein the ratio of the number of the first deposition stages to the number of the second deposition stages is 3 to 60. 24. The method of any of the above embodiments, wherein the diffusion barrier comprises TiSiN having a silicon concentration of more than 5 atomic percent. 25. The method of any of the above embodiments, wherein the diffusion barrier comprises TiSiN having a silicon concentration of 5 atomic% to 30 atomic%. 26. The method of any of the above embodiments, wherein the Si precursor system is selected from compounds of the group consisting of SiH4, Si2H6, SiH2Cl2, SiH3Cl, Si2Cl6 and Si3Cl8. 27. The method of any of the above embodiments, wherein the Ti precursor comprises TiCl4. 28. The method of any of the above embodiments, wherein the N precursor system is NH3. 29. The method of any of the above embodiments, wherein exposing the semiconductor substrate to a vapor deposition cycle is performed at a substrate temperature of 400 °C to 600 °C. 30. The method of any of the above embodiments, wherein the number of the first deposition stages and the number of the second deposition stages are such that the diffusion barrier layer is substantially uniform in the depth direction. 31. The method of Example 30, wherein the number of the first deposition stages and the number of the second deposition stages do not exceed about 50. 32. The method of any of the above embodiments, wherein the number of the first deposition stages and the number of the second deposition stages are such that the diffusion barrier layer has a nanolayer structure including TiN layers alternating with TiSiN layers. 33. The method of Example 32, wherein the number of one or both of the first deposition stages and the second deposition stages exceeds about 50. 34. The method of Example 32 or 33, wherein the thickness of one or both of the TiN layers and the TiSiN layers exceeds 1.5 nm. 35. The method of any one of Examples 32 to 34, wherein the nanolayer comprises a TiSiN layer between TiN layers. 36. The method of any of the above embodiments, wherein the semiconductor substrate includes a plurality of openings formed thereon, wherein the openings include dielectric sidewall surfaces and an aspect ratio of more than 5; and wherein forming the diffusion barrier includes lining the surfaces of the openings. 37. The method of embodiment 36, wherein lining the surface of the openings includes conformally lining such that the ratio of the thickness of the diffusion barrier layer formed at 25% below the height of the openings to the thickness formed at 25% above the height of the openings exceeds 0.8. 38. The method of Example 37, wherein the Si precursor system is SiH2Cl2 and the ratio exceeds 83%. 39. The method of Example 37, wherein the Si precursor system is SiH 3Cl and the ratio exceeds 86%. 40. The method of Example 37, wherein the Si precursor system is Si 3Cl 8 and the ratio is greater than 86%. 41. The method of any one of Examples 38 to 40, wherein the aspect ratio exceeds 50. 42. The method of any of the above embodiments, wherein the number and size of the openings are such that the ratio of the surface area of ​​the semiconductor substrate exposed to the one or more vapor deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate exceeds 2. 43. The method of any of the above embodiments, wherein lining the surface of the opening comprises exposing the semiconductor substrate to the vapor deposition cycle under a pressure of 3 to 10 Torr in the reaction chamber. 44. The method of any of the above embodiments, wherein the openings further include an exposed semiconductor bottom surface. 45. The method of any of the above embodiments, wherein the one or more first deposition stages do not overlap with one or more second deposition stages. 46. ​​The method of any of the above embodiments, wherein exposing the semiconductor substrate to one or more of the Ti precursor, the Si precursor and the N precursor during the one or more second deposition stages includes undersaturating the surface of the semiconductor substrate. 47. The method of Example 42, wherein the diffusion barrier comprising TiSiN has a resistivity that is more than 10% higher than that of a reference diffusion barrier comprising TiSiN obtained by the same method except for undersaturation. 48. A nanolayer comprising TiN-rich regions or layers alternating with Si-rich and / or Al-rich regions or layers or SiN / AlN-rich regions or layers. [Additional Examples] [III] 1. A method for forming a diffusion barrier, the method comprising: A diffusion barrier, including TiSiN, with a modulus exceeding 290 GPa and a Si content exceeding 2.7 atomic percent is formed by exposing a semiconductor substrate to one or more first deposition stages alternating with one or more second deposition stages. The process of exposing the semiconductor substrate to the one or more first deposition stages includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor, and Exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor, then the silicon (Si) precursor, and then the N precursor. 2. A method for forming a diffusion barrier, the method comprising: A diffusion barrier, including TiSiN, with a hardness exceeding 20 GPa and a Si content exceeding 2.7 atomic percent, is formed by exposing a semiconductor substrate to one or more first deposition stages alternating with one or more second deposition stages. The process of exposing the semiconductor substrate to the one or more first deposition stages includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor, and Exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor, then the silicon (Si) precursor, and then the N precursor. 3. A method for forming a diffusion barrier, the method comprising: A diffusion barrier comprising TiSiN is formed by exposing a semiconductor substrate to one or more first deposition stages alternating with one or more second deposition stages. This diffusion barrier has a crystalline texture such that the sum of the area of ​​the diffusion barrier exhibited in the grazing incident X-ray diffraction spectrum at the (002) peak and the area at the (111) and (222) peaks exceeds 0.4, and a Si content exceeding 2.7 atomic percent. The process of exposing the semiconductor substrate to the one or more first deposition stages includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor, and Exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor, then the silicon (Si) precursor, and then the N precursor. 4. A method for forming a diffusion barrier, the method comprising: A diffusion barrier comprising TiSiN is formed by exposing a semiconductor substrate to one or more first deposition stages alternating with one or more second deposition stages. This diffusion barrier has a nanocrystalline structure with an average grain size of less than about 6.5 nm and a Si content exceeding 2.7%. The process of exposing the semiconductor substrate to the one or more first deposition stages includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor, and Exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor, then the silicon (Si) precursor, and then the N precursor. 5. The method of any of the above embodiments, wherein the diffusion barrier has a Si content of 2.7 atomic% to 9 atomic%. 6. The method of any of the above embodiments, wherein the diffusion barrier has a Si content of 2.7 atomic% to 7 atomic%. 7. The method of any of the above embodiments, wherein the diffusion barrier has a modulus of 290 GPa to 350 GPa. 8. The method of any of the above embodiments, wherein the diffusion barrier has a hardness of 20 GPa to 40 GPa. 9. The method of any of the above embodiments, wherein the diffusion barrier has a crystalline texture such that the area of ​​the grazing incident X-ray spectrum exhibited at the (002) peak is in a ratio of 0.4 to 4.5 to the sum of the areas at the (111) and (222) peaks. 10. The method of any of the above embodiments, wherein the diffusion barrier layer has a nanocrystalline structure having an average grain size of about 5.0 nm to 6.5 nm. 11. The method of any of the above embodiments, wherein exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor and the silicon (Si) precursor without intermediate exposure to the N precursor in between, and then exposing the semiconductor substrate to the N precursor. 12. The method of any of the above embodiments, wherein exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor as a first precursor, followed by a silicon (Si) precursor, and then to the N precursor as a final precursor. 13. The method of any of the above embodiments, wherein exposing the semiconductor substrate to the one or more second deposition stages includes exposing the semiconductor substrate to the Ti precursor for a Ti precursor exposure duration, then to the silicon (Si) precursor for a Si precursor exposure duration, then to the N precursor, and wherein the ratio of the Ti precursor exposure duration to the Si precursor exposure duration is 0 to 1. 14. The method of any of the above embodiments, wherein exposing the semiconductor substrate to the one or more second deposition stages includes exposing the semiconductor substrate to the Ti precursor for a Ti precursor exposure duration of 0 to 1 second, followed by exposing the silicon (Si) precursor for a Si precursor exposure duration of 1 to 10 seconds. 15. The method of any of the above embodiments, wherein the ratio of the number of the first deposition stages to the number of the second deposition stages is greater than 10. 16. The method of any of the above embodiments, wherein the ratio of the number of the first deposition stages to the number of the second deposition stages is 10 to 50. 17. The method of any of the above embodiments, wherein the semiconductor substrate includes an opening having an aspect ratio of more than 5, and wherein forming the diffusion barrier includes lining the surface of the opening such that the ratio of the thickness of the diffusion barrier formed at 25% below the height of the opening to the thickness formed at 25% above the height of the opening exceeds 0.80. 18. The method of any of the above embodiments, wherein exposing the semiconductor substrate to the one or more first deposition stages includes exposing the semiconductor substrate to the N precursor, which serves as the final precursor. 19. The method of any of the above embodiments, wherein exposing the semiconductor substrate to the one or more second deposition stages includes exposing the semiconductor substrate to the Ti precursor serving as the first precursor. 20. The method of any of the above embodiments, wherein the semiconductor substrate is exposed to the Ti precursor, which is the first precursor of the second deposition stage, immediately after the semiconductor substrate is exposed to the N precursor, which is the last precursor of the first deposition stage, without intermediate exposure to the N precursor. 21. The method of any of the above embodiments, wherein exposing the semiconductor substrate to the one or more first deposition stages and the one or more second deposition stages includes exposure in a reaction chamber at a pressure greater than 1 Torr. 22. The method of any of the above embodiments, wherein the semiconductor substrate includes a surface morphology such that the ratio of the surface area of ​​the semiconductor substrate exposed to the one or more first deposition stages and the one or more second deposition stages to the surface area of ​​the corresponding unpatterned semiconductor substrate exceeds 2. 23. The method of Example 22, wherein the surface morphology includes a plurality of trenches or through holes having an aspect ratio of more than 5. 24. The method of embodiment 22 or 23, wherein the number and size of the trenches or through holes are such that the ratio of the surface areas exceeds 20. 25. The method of any of the above embodiments, wherein exposing the semiconductor substrate to the one or more first deposition stages and the one or more second deposition stages includes exposure in the reaction chamber at a pressure of 3 to 10 Torr. 26. The method of any of the above embodiments, wherein the ratio of the number of the first deposition stages to the number of the second deposition stages is such that the diffusion barrier is at least partially amorphous. 27. The method of any of the above embodiments, wherein the Si precursor system is selected from compounds of the group consisting of SiH4, Si2H6, SiH2Cl2, SiH3Cl, Si2Cl6 and Si3Cl8. 28. The method of any of the above embodiments, wherein the Ti precursor comprises TiCl4. 29. The method of any of the above embodiments, wherein the N precursor system is NH3. 30. The method of any of the above embodiments, wherein exposing the semiconductor substrate to a vapor deposition cycle is performed at a substrate temperature of 400 °C to 600 °C. 31. The method of any of the above embodiments, wherein the number of the first deposition stages and the number of the second deposition stages are such that the diffusion barrier layer is substantially uniform in the depth direction. 32. The method of any of the above embodiments, wherein the semiconductor substrate includes a plurality of openings formed thereon, wherein the openings include dielectric sidewall surfaces and an aspect ratio of more than 5, and wherein forming the diffusion barrier includes lining the surfaces of the openings. 33. The method of embodiment 32, wherein lining the surfaces of the openings includes conformally lining such that the ratio of the thickness of the diffusion barrier layer formed at 25% below the height of the openings to the thickness formed at 25% above the height of the openings exceeds 0.8. 34. The method of embodiment 32 or 33, wherein the number and size of the openings are such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate exceeds 2. 35. The method of any one of Examples 32 to 34, wherein lining the surface of the opening comprises exposing the semiconductor substrate to the vapor deposition cycle under a pressure of 3 to 10 Torr in a reaction chamber. 36. The method of any one of Examples 32 to 35, wherein the openings further include an exposed semiconductor bottom surface. 37. A semiconductor structure comprising: A semiconductor substrate including a plurality of trenches or vias formed thereon, wherein the trenches or vias include dielectric sidewall surfaces and an aspect ratio of more than 5; and The diffusion barrier layer, including TiSiN, is conformally lined to the surface of the trenches or vias, wherein the diffusion barrier layer has a Si content of 2.7 atomic% to 9 atomic% and a modulus of 290 GPa to 350 GPa. 38. A semiconductor structure comprising: A semiconductor substrate including a plurality of trenches or vias formed thereon, wherein the trenches or vias include dielectric sidewall surfaces and an aspect ratio of more than 5; and The diffusion barrier layer, including TiSiN, is conformally lined to the surface of the trenches or vias, wherein the diffusion barrier layer has a Si content of 2.7 atomic% to 9 atomic% and a hardness of 20 GPa to 40 GPa. 39. A semiconductor structure comprising: A semiconductor substrate including a plurality of trenches or vias formed thereon, wherein the trenches or vias include dielectric sidewall surfaces and an aspect ratio of more than 5; and The diffusion barrier layer, including TiSiN, is conformally lined to the surface of the trenches or vias, wherein the diffusion barrier layer has a Si content of 2.7 atomic% to 9 atomic% and a crystalline texture such that the area of ​​the grazing incident X-ray spectrum at the (002) peak is 0.4 to 4.5 times the sum of the areas at the (111) and (222) peaks. 40. A semiconductor structure comprising: A semiconductor substrate including a plurality of trenches or vias formed thereon, wherein the trenches or vias include dielectric sidewall surfaces and an aspect ratio of more than 5; and The diffusion barrier layer, including TiSiN, is conformally lined to the surface of the trenches or vias, wherein the diffusion barrier layer has a Si content of 2.7 atomic% to 9 atomic% and a nanocrystalline structure with an average grain size of about 5.0 nm to 6.5 nm. 41. The semiconductor structure of any one of Examples 37 to 40, wherein the Si content is 2.7 atomic% to 7 atoms. 42. The semiconductor structure of any one of Examples 37 to 41, wherein the aspect ratio of the trenches or vias exceeds 10. 43. The semiconductor structure of any one of embodiments 37 to 42, wherein the diffusion barrier layer is conformally lined to the surfaces such that the ratio of the thickness of the diffusion barrier layer formed at 25% below the height of the trenches or vias to the thickness formed at 25% above the height of the trenches or vias exceeds 0.8. 44. The semiconductor structure of any one of Examples 37 to 43, wherein the area density of the trenches or vias is such that the ratio of the surface area of ​​the diffusion barrier layer formed thereon to the surface area of ​​the corresponding unpatterned semiconductor substrate exceeds 2. 45. The semiconductor structure of any one of Examples 37 to 44, wherein the ratio of the surface areas exceeds 100. 46. ​​The semiconductor structure of any one of Examples 37 to 45, wherein the root mean square surface roughness of the diffusion barrier layer is less than about 0.3 nm. 47. The semiconductor structure of any one of Examples 37 to 46, wherein the trenches or vias further include a semiconductor bottom surface. 48. The semiconductor structure of any one of Examples 37 to 47, wherein the trenches or vias are filled with tungsten or copper. 49. The semiconductor structure of any one of Examples 37 to 48, wherein the diffusion barrier has a thickness of about 1 nm to 10 nm. 50. A semiconductor structure as described in any of Examples 37 to 49, wherein the trenches or vias have a width of about 10 nm to 1000 nm. 51. The semiconductor structure of any one of Examples 37 to 50, wherein the diffusion barrier layer has a resistivity of less than about 1600 μΩ-cm.

[0192] Although the invention has been described herein with reference to specific embodiments, these embodiments are not intended to limit the invention and are set forth for illustrative purposes. Those skilled in the art will understand that modifications and improvements can be made without departing from the spirit and scope of the invention.

[0193] Simple modifications and improvements to the various embodiments disclosed herein are within the scope of this invention, and furthermore, the specific scope of this invention will be defined by the appended claims.

[0194] As will be understood from the foregoing, any feature of any embodiment may be combined with or replaced by any other feature of any other embodiment.

[0195] Unless otherwise clearly required by the background context, the terms "comprise / comprising," "include / including," and similar terms throughout the description and scope of the invention claim shall be interpreted as encompassing, the opposite of exclusive or exhaustive; that is, meaning "including but not limited to." As commonly used herein, the term "coupled" refers to two or more elements that can be directly connected or connected by one or more intermediate elements. Similarly, as commonly used herein, the term "connected" refers to two or more elements that can be directly connected or connected by one or more intermediate elements. Furthermore, the terms "in this document," "above," "below," and similar terms, when used in this application, shall refer to the entire application and not any particular part of it. Where the background context permits, the use of singular or plural terms in the [Implementation] section above may also include both singular and plural terms respectively. The word "or" in relation to a list of two or more items covers all of the following interpretations: any one of the items in the list, all the items in the list, and any combination of the items in the list.

[0196] Furthermore, unless otherwise expressly stated or otherwise understood within the context of its use, the conditional language used herein (especially terms such as "can / could," "might," "may," "e.g. / for example," "like," and the like) is generally intended to convey that certain embodiments include certain features, elements, and / or states that are not included in other embodiments. Therefore, this conditional language is not generally intended to imply that one or more embodiments require features, elements, and / or states in any given situation, or whether such features, elements, and / or states are included in or performed in any particular embodiment.

[0197] While certain embodiments have been described, these embodiments are merely illustrative and are not intended to limit the scope of the invention. In fact, the novel devices, methods, and systems described herein may be embodied in many other forms; furthermore, various omissions, substitutions, and changes may be made to the form of the methods and systems described herein without departing from the spirit of the invention. For example, while features are presented in a given configuration, alternative embodiments may perform similar functionality using different components and / or sensor morphologies, and some features may be deleted, moved, added, subdivided, combined, and / or modified. These features may be implemented in many different ways. Any suitable combination of elements and actions of the various embodiments described above may be combined to provide further embodiments. The various features and procedures described above may be implemented independently of each other or may be combined in various ways. All possible combinations and sub-combinations of the features of the invention are intended to fall within the scope of the invention.

[0198] 100:Substrate 104: Precursor molecule / Adsorbed molecule 108: Floor 112: Floor 116: Stable Two-Dimensional Layer 120: Thin Film Structure 300: Semiconductor Structure / Semiconductor Thin Film Structure 310:Substrate 320:Thin film 400: Semiconductor Structure 404: Semiconductor material / semiconductor substrate 408: Dielectric layer 412:Thin film 412A: Thin Film 412B: Thin Film 412C: Thin Film 416: High aspect ratio structure 500: Methods 510: Steps 520: Steps 525: Steps 530: Steps 910: Start 1100: Semiconductor Device 1104:Material / Substrate 1108: Dielectric layer 1112: Barrier Layer 1116: Contact plug 1402: Steps 1404: Steps 1406: Steps 1502: Steps 1504: Steps 1506: Steps 1602: Steps 1604: Steps 1606: Steps 1720: Vapor Deposition Cycle 1725: Steps 1730: Steps 2902: Steps 2904: Steps 2906: Steps

Claims

1. A method for forming a diffusion barrier comprising TiSiN, the method comprising: Exposing a semiconductor substrate to one or more first deposition stages that alternate with and do not overlap with one or more second deposition stages, wherein exposing the semiconductor substrate to the one or more first deposition stages includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor, and wherein exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor and a silicon (Si) precursor without intermediate exposure to the N precursor in between, and then exposing the semiconductor substrate to the N precursor.

2. The method of claim 1, wherein exposing the semiconductor substrate to the first deposition stages includes exposing the semiconductor substrate to the N precursor, which is the final precursor of each of the first deposition stages.

3. The method of claim 2, wherein exposing the semiconductor substrate to the second deposition stages includes exposing the semiconductor substrate to the Ti precursor, which serves as a first precursor for each of the second deposition stages.

4. The method of claim 3, wherein exposing the semiconductor substrate to the Ti precursor, which is a first precursor of each of the second deposition stages, immediately follows exposing the semiconductor substrate to the N precursor, which is the last precursor of the immediately preceding first deposition stage, without intermediate exposure to any other precursor.

5. The method of claim 4, wherein exposing the semiconductor substrate to one or more of the Ti precursor, the Si precursor and the N precursor during the one or more second deposition stages includes undersaturating the surface of the semiconductor substrate.

6. The method of claim 1, wherein the method is performed without plasma assistance.

7. The method of claim 6, wherein exposing the semiconductor substrate to the one or more first deposition stages and the one or more second deposition stages includes exposure in a reaction chamber at a pressure greater than 1 Torr.

8. The method of claim 1, wherein the ratio of the exposure time of the semiconductor substrate to the Si precursor and the exposure time of the semiconductor substrate to the Ti precursor in the second deposition stage is between 2 and 130.

9. The method of claim 1, wherein the ratio of the exposure time of the semiconductor substrate to the Ti precursor in the second deposition stage and the exposure time of the semiconductor substrate to the Ti precursor in the first deposition stage is between 3 and 34.

10. The method of claim 1, wherein the ratio of the exposure time of the semiconductor substrate to the N precursor in the second deposition stage and the exposure time of the semiconductor substrate to the N precursor in the first deposition stage is between 5 and 50.

11. A method for forming a diffusion barrier comprising TiSiN, the method comprising: Exposing a semiconductor substrate to one or more first deposition stages that alternate with and do not overlap with one or more second deposition stages, wherein exposing the semiconductor substrate to the one or more first deposition stages includes alternating exposure of the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor, and wherein exposing the semiconductor substrate to the one or more second deposition stages includes sequentially exposing the semiconductor substrate to the Ti precursor, followed by a silicon (Si) precursor, followed by the N precursor.

12. The method of claim 11, wherein the method is performed without plasma assistance.

13. The method of claim 12, wherein exposing the semiconductor substrate to the one or more first deposition stages and the one or more second deposition stages includes exposure in a reaction chamber at a pressure greater than 1 Torr.

14. The method of claim 11, wherein exposing the semiconductor substrate to the first deposition stages includes exposing the semiconductor substrate to the N precursor, which is the final precursor of each of the first deposition stages.

15. The method of claim 14, wherein exposing the semiconductor substrate to the second deposition stages includes exposing the semiconductor substrate to the Ti precursor, which serves as a first precursor for each of the second deposition stages.

16. The method of claim 15, wherein exposing the semiconductor substrate to the Ti precursor, which is a first precursor of each of the second deposition stages, immediately follows exposing the semiconductor substrate to the N precursor, which is the last precursor of the immediately preceding first deposition stage, without intermediate exposure to any other precursor.

17. The method of claim 16, wherein exposing the semiconductor substrate to one or more of the Ti precursor, the Si precursor and the N precursor during the one or more second deposition stages includes undersaturating the surface of the semiconductor substrate.

18. The method of claim 11, wherein the semiconductor substrate includes an opening having an aspect ratio of more than 50, and wherein forming the diffusion barrier includes lining the surface of the opening such that the ratio of the thickness of the diffusion barrier formed at 25% below the height of the opening to the thickness formed at 25% above the height of the opening is greater than 0.

9.

19. The method of claim 11, wherein the diffusion barrier formed using the method has a resistivity of 2000 μΩ–cm or lower.

20. The method of claim 11, wherein the diffusion barrier formed by the method has a resistivity that is at least 500 μΩ–cm lower than that formed by a method identical to that formed by means of the semiconductor substrate except that the semiconductor substrate is exposed to the Ti precursor as part of the one or more second deposition stages.

21. The method of claim 11, wherein in the second deposition stage, the exposure time of the semiconductor substrate to the Si precursor exceeds 3 seconds, and the exposure time of the semiconductor substrate to the Ti precursor is less than 2 seconds.

22. The method of claim 11, wherein exposing the semiconductor substrate to the one or more first deposition stages and the one or more second deposition stages includes exposure in a reaction chamber at a pressure greater than 1 Torr.

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