Write-once method for non-volatile memory

Abstract

A one-time write method for non-volatile memory is disclosed, suitable for a memory cell. A memory module is formed by sequentially connecting a bit line transistor, a word line transistor, a memory cell, and a source line transistor. The write method includes providing a write voltage and generating a write current flowing through the memory cell in response to the write voltage. The write voltage and current are each composed of multiple gradually increasing rising voltage signals and rising current signals, and each rising voltage and current signal is separated by a pause interval. By configuring these signals, the present invention writes to the memory module according to the aforementioned write voltage and current, thereby optimizing the reliability and write performance of the memory cell. At the same time, it can avoid problems such as excessive pressure or incomplete writing for different memory bits.

Description

Technical Field

[0001] This invention relates to a method for writing non-volatile memory, and more particularly to a one-time write method that can balance the reliability and write performance of memory cells, while optimizing the write performance of different memory bits during the write process. Prior Technology

[0002] Semiconductor memory refers to a semiconductor circuit that uses electricity to control semiconductors, enabling it to retain and store data. Compared to existing magnetic disks and optical disks, semiconductor memory has advantages such as faster data reading and writing speeds, higher recording density, lower power consumption, and vibration resistance. Therefore, in recent years it has successfully replaced traditional data storage devices and is widely used in electronic circuit systems and various electronic products.

[0003] Among the different types of semiconductor memory, those whose stored data is lost when the power supply is cut off are called "volatile memory," while those whose stored data is retained even when the power supply is cut off are called "non-volatile memory (NVM)." As is well known, NVM allows for multiple data write-in, read-out, and erase operations, and has advantages such as data retention during power outages, short data access times, and low power consumption. Therefore, in recent years, it has become a widely used memory component in personal computers and electronic devices.

[0004] Generally speaking, Random Access Memory (RAM) is an indispensable component because it allows for the free reading and writing of data. For example, it is used for long-term data storage. Non-volatile memory used in data storage devices can include flash memory, magnetoresistive RAM (MRAM), ferroelectric RAM, resistive RAM (RRAM), spin transfer torque RAM (STT-RAM), and various other types of RAM. With the development of current memory technology, these non-volatile RAMs offer advantages such as lower operating voltage, shorter write times, higher data retention, simpler structure, and smaller circuit area. Therefore, they are widely used and actively developed in the industry today and represent one of the most promising memory devices for future applications.

[0005] However, it is worth noting that even though resistive random access memory (RAM) or magnetoresistive random access memory (MRAM) have the aforementioned advantages, there are still problems to be overcome when writing data. For example, in the existing write process, the voltage across the memory cell changes during the write process. This change may cause the voltage across the memory cell to become too large, resulting in overstress and damage to the memory cell, thus affecting its reliability.

[0006] Furthermore, due to variations in memory cell manufacturing processes or other influencing factors, resistive memory cells are also classified into three different types based on their characteristics: fast bit, slow bit, and typical bit. Taking fast bit as an example, compared to other memory bits, fast bit is easier to write; that is, under the same writing conditions, fast bit can complete the write process much faster than typical bit. In other words, fast bit requires only a shorter write time to complete the write operation. In this situation, existing writing methods fail to adequately handle these fast-write memory bits. In other words, current methods only provide the same write time, allowing fast-write memory bits to undergo the same write time as regular memory bits. This results in fast-write memory bits being subjected to excessive stress; that is, after the write operation is complete, the fast-write memory bits continue to be subjected to extra write operations, leading to extra stress. Especially with the rapid development of semiconductor memory manufacturing technology, these problems will become increasingly serious if not properly addressed, significantly impacting and damaging the memory structure. Therefore, as the density of non-volatile memory continues to increase, improving the electrical performance and reliability of memory devices remains a key industry goal. Ensuring the reliability of non-volatile memory storage and achieving a balance between reliability and write efficiency is an important issue in this field.

[0007] Therefore, considering the numerous problems of the aforementioned prior art, the inventor, recognizing the potential for improvement in these deficiencies, and drawing upon years of experience in this field, has carefully observed and researched the subject, applying theoretical principles to propose a novel and effective invention that addresses these shortcomings. This invention discloses an improved memory writing method. This memory writing method not only balances the reliability and writing performance of memory cells but also optimizes the writing process for different memory bits. Based on the inventive efficacy of this invention, it has been proven to effectively solve many of the deficiencies of prior art. The specific architecture and implementation methods of this invention will be detailed below. Summary of the Invention

[0008] To address the problems existing in the prior art, one objective of this invention is to provide a one-time write method for non-volatile memory. By applying the write method disclosed in this invention, many long-standing problems of memory cells in the prior art can be solved. In addition, the problem of excessive pressure time for fast write of memory bits can also be significantly improved.

[0009] On the other hand, another objective of this invention is to optimize the writing process for different memory bits within a memory module, even during the writing process. For example, fast writing of memory bits avoids the problem of excessive pressure, standard writing of memory bits completes the writing process precisely, while slow writing of memory bits avoids the problem of underwrite. Based on the technical solution and inventive effects disclosed in this invention, it is certain that this represents a significant improvement over aspects that prior art patents or papers could not achieve or apply.

[0010] Another objective of this invention is to provide a writing method that achieves a balance between the reliability of non-volatile memory storage and its writing performance. The memory writing method disclosed in this invention can be applied not only to resistive RAM (RRAM) architectures but also to magnetoresistive RAM (MRAM) architectures to optimize existing writing methods. Furthermore, the memory writing method disclosed in this invention can be applied not only to common electronic component memory fields but also to various products that require random access to non-volatile memory cells, demonstrating the wide range of applications of this invention.

[0011] Therefore, based on achieving the aforementioned inventive objectives, this invention aims to provide a one-time write method for non-volatile memory, suitable for a memory module. The memory module includes a memory cell for storing data to be written, a source linear transistor, a word linear transistor, and a bit linear transistor. The bit linear transistor, word linear transistor, memory cell, and source linear transistor are sequentially connected in series to form the memory module, and the memory module is electrically coupled between a write voltage input terminal and a power supply terminal. The one-time write method disclosed in this invention mainly includes the following steps:

[0012] A write voltage is provided, which is input to the memory module via a write voltage input terminal, and the write voltage includes a plurality of gradually increasing rising voltage signals, with a pause interval between each rising voltage signal.

[0013] A write current flows through the memory cell in response to the write voltage, wherein the write current comprises a plurality of gradually increasing rising current signals, and each rising current signal is separated by a pause interval. According to an embodiment of the present invention, the gradually increasing rising voltage signals are composed of a plurality of pulse trains with gradually increasing voltage, and the gradually increasing rising current signals are composed of a plurality of pulse trains with gradually increasing current.

[0014] Subsequently, the memory module is written according to the stated write voltage and write current. The write voltage can be selectively input to the memory module through either the write voltage input terminal or the power supply terminal. The memory cell is a two-terminal element, such as a resistive memory cell, a magnetoresistive memory cell, or other non-volatile memory cells. The one-time write method disclosed in this invention effectively maintains the voltage across the two terminals of the memory cell within a predetermined range during the write process.

[0015] According to a first embodiment of the present invention, the waveform of the write voltage can be output as a ripple signal corresponding to the pause interval. Furthermore, the voltage level of the ripple signal is lower than the voltage level of each of the rising voltage signals. According to this first embodiment, the waveform of the write current also outputs as a ripple signal corresponding to the pause interval. Furthermore, the current level of the ripple signal is lower than the voltage level of each of the rising voltage signals.

[0016] According to a second embodiment of the present invention, the waveform of the write voltage can also be output as zero during the corresponding pause interval. Similarly, according to this second embodiment, the waveform of the write current can also be output as zero during the corresponding pause interval.

[0017] In summary, it is evident that the main purpose of this invention is to control the pause intervals between a plurality of gradually increasing rising voltage signals or a plurality of gradually increasing rising current signals, thereby maintaining the voltage across the memory cell within a predetermined range and optimizing it during the write operation. Furthermore, this invention also utilizes these rising voltage and rising current signals with pause intervals to avoid the ballooning effect commonly seen in conventional memory elements during writing.

[0018] In one embodiment, the bit-line transistor configured in this invention has its source connected to the drain of a word-line transistor, the drain of the bit-line transistor connected to the write voltage input terminal, and the gate of the bit-line transistor connected to a bit-line drive voltage. The source of the word-line transistor is connected to a first terminal of the memory cell, the gate of the word-line transistor is connected to a word-line drive voltage, the second terminal of the memory cell is connected to the drain of the source-line transistor, the gate of the source-line transistor is connected to a source-line drive voltage, and the source of the source-line transistor is connected to the power supply terminal. A self-stop write circuit is electrically connected to the drain of the bit-line transistor and is used to generate a stop signal to stop the continuous writing of the memory cell.

[0019] Specifically, the write method disclosed in this invention can further detect write voltage or write current, and when the write voltage reaches a preset threshold voltage value, or when the write current reaches a preset threshold current value, the write to the memory module is stopped by generating an abort signal, so as to optimize the write period of the memory cell.

[0020] According to one embodiment of the present invention, the write abort circuit includes: a write signal generator, a buffer, a threshold signal generator, and a comparator. The write signal generator generates a write reference signal, the threshold signal generator generates a threshold signal, the buffer has a positive input terminal, a negative input terminal, an output terminal, and an enable terminal, the positive input terminal of the buffer is connected to the write signal generator to receive the write reference signal, the negative input terminal of the buffer is connected to its output terminal to form negative feedback, and the enable terminal of the buffer receives the abort signal. The comparator has a positive input node, a negative input node, and an output node. In this embodiment, when the positive input node of the comparator is connected to the output terminal of the buffer and the write voltage input terminal and receives the write voltage, the write reference signal is a reference voltage signal that is preset according to the characteristics of the memory cell. Meanwhile, the threshold signal generated by the threshold signal generator provides a threshold voltage value. The negative input node of the comparator is connected to the threshold signal generator to receive the threshold signal (threshold voltage value). When the comparator compares the write voltage to the threshold signal (threshold voltage value), it generates a stop signal at its output node, making the stop signal a voltage signal corresponding to the write voltage, and shuts down the write buffer to stop the continuous writing of the memory cell.

[0021] In another alternative embodiment of the invention, the stop signal can also be generated through signal processing of the write current. Specifically, when the positive input node of the comparator is connected to the output of the buffer and the drain of the bit line transistor to receive the write current, the write reference signal is a reference current signal, which is preset according to the characteristics of the memory cell. Simultaneously, the threshold signal generated by the threshold signal generator provides a threshold current value. The negative input node of the comparator is connected to the threshold signal generator to receive the threshold signal (threshold current value). When the comparator compares the write current to be higher than the threshold signal (threshold current value), it generates a stop signal at its output node, making the stop signal a current signal corresponding to the write current, and shutting down the write buffer to stop continuous writing to the memory cell.

[0022] By using this self-stop write circuit and generating its stop signal, the present invention can control the automatic self-stop write process when the write voltage or write current reaches the threshold target (threshold voltage value or threshold current value), so as to properly protect and maintain the reliability of memory elements. Even for fast write memory bits, standard write memory bits, or slow write memory bits with different process conditions, the design can be optimized during their write process, and the good structure can be maintained. Excessive pressure can be avoided, and even the problem of insufficient pressure can be improved.

[0023] Furthermore, the write method disclosed in this invention can also preset a write time. When the preset write time is reached, the input write voltage and write current are stopped, thereby directly terminating the writing to the memory cell.

[0024] In summary, this invention is not limited to the exemplary examples disclosed above. Those skilled in the art can make appropriate modifications or variations to the technical solutions disclosed in this invention without departing from its spirit, but such modifications or variations should still fall within the scope of this invention. This invention is not limited to the transistor structures disclosed in these embodiments.

[0025] On the other hand, it is worth noting that the embodiments disclosed in this invention are illustrated using a resistive memory cell as an example, and their purpose is to enable those skilled in the art to fully understand the technical concept of this invention, rather than to limit the application of this invention. In other words, the writing method for memory cells and their modules disclosed in this invention can be applied to memory cell architectures that are not limited to resistive or magnetoresistive memory cell architectures, and can also be widely applied to memory cell architectures constructed from various other memory elements.

[0026] The following detailed description, with reference to specific embodiments and accompanying drawings, will make it easier to understand the purpose, technical content, features and effects of the present invention. Simple Explanation of the Diagram

[0027] Figure 1 is a partial circuit diagram of a conventional resistive memory write circuit. Figure 2 is a schematic diagram of the write current / resistance versus time in a conventional resistive memory write circuit as shown in Figure 1. Figure 3 is a schematic diagram of the write voltage versus time in a conventional resistive memory write circuit as shown in Figure 1. Figure 4 is a schematic diagram of a conventional resistive memory write circuit as shown in Figure 1, in which the problem of excessive pressure arises. Figure 5 is a flowchart of the steps of a one-time write method according to an embodiment of the present invention. Figure 6 is a schematic diagram of the circuit architecture of a non-volatile memory module using the write-once method of an embodiment of the present invention. Figure 7 is a schematic diagram of the write voltage and write current versus time in one embodiment of the present invention. Figure 8 is a schematic diagram of the write voltage and write current versus time according to another embodiment of the present invention. Figure 9 is a flowchart illustrating the steps of a method for self-termination of writing by setting a preset threshold voltage value, according to an embodiment of the present invention. Figure 10 is a flowchart illustrating the steps of another embodiment of the present invention to achieve self-stop writing by setting a preset threshold current value. Figure 11 is a flowchart illustrating the steps of terminating writing by setting a preset writing time according to an embodiment of the present invention. Implementation

[0028] The foregoing description of the present invention, along with the following embodiments, are used to demonstrate and explain the spirit and principles of the invention, and to provide a further explanation of the scope of the patent application. The features, implementation, and effects of the present invention are described in detail below with reference to the accompanying drawings.

[0029] In particular, preferred embodiments of the present invention are illustrated in the accompanying drawings, and in the drawings and description thereof, the same reference numerals are used as much as possible to refer to the same or similar elements.

[0030] First, please refer to Figure 1, which is a partial circuit diagram of a conventional resistive memory write circuit. As shown in Figure 1, the conventional resistive memory write circuit 100 mainly includes a resistive memory cell 10 connected in series with transistors 12, 14, and 16, and a write buffer 17. The resistive memory cell 10 is a two-terminal element, with its two ends electrically connected to the drain of transistor 12 and the source of transistor 14, respectively. The source of transistor 12 is connected to a low-voltage contact VSS, and the gate of transistor 12 is connected to a source line drive voltage VGS. The drain of transistor 14 is connected to the source of transistor 16, and the gate of transistor 14 is connected to a word line drive voltage VWL. Simultaneously, the drain of transistor 16 is electrically connected to the output of the write buffer 17, and the gate of transistor 16 is connected to a word line drive voltage VGB. Generally, the connection between resistive memory cell 10 and transistor 12 is a local source line. The connection between transistor 16 and transistor 14 is a local bit line. Meanwhile, the output of write buffer 17 is fed back to its negative input, and a write reference voltage Vref_w is input to the positive input of write buffer 17, thereby generating a write voltage Vwrite at its output. In one embodiment, the write reference voltage Vref_w can be provided via a reference voltage generator.

[0031] As shown in Figure 1, the write current Iwrite passes through a series circuit consisting of transistor 16, transistor 14, resistive memory cell 10, and transistor 12. In this case, the voltage across the resistive memory cell 10 is denoted as ΔVR, the voltage across the transistor 12 is denoted as ΔVts, and the voltage across the series circuit of transistors 14 and 16 is denoted as ΔVtb.

[0032] Next, please refer to Figures 2 and 3. Figures 2 and 3 are schematic diagrams illustrating the write current / resistance and write voltage versus time in the conventional resistive memory write circuit shown in Figure 1, respectively. Figure 2 shows that during the write process, the resistance value Rcell of the resistive memory cell 10 gradually increases over time, causing the write current Iwrite to decrease relatively over time. On the other hand, Figure 3 shows that during the write process, since the write voltage Vwrite remains approximately constant (approximately equivalent to the write reference voltage Vref_w), as the resistance value Rcell of the resistive memory cell 10 gradually increases, the voltage across the resistive memory cell 10, ΔVR, also increases. Conversely, this causes the voltage across transistor 12, ΔVts, and the voltage across transistors 14 and 16, ΔVtb, to gradually decrease. This voltage increase may eventually cause the voltage across the resistive memory cell 10, ΔVR, to exceed the withstand voltage of the resistive memory cell 10. In other words, such excessive pressure could damage the resistive memory cell 10, seriously affecting its reliability.

[0033] In addition, please refer to Figure 4. In the conventional resistive memory writing process, all resistive memory (including fast write memory bits, standard write memory bits, and slow write memory bits) operate under the same writing conditions, such as applying the same write voltage and write current, until the predetermined write time is reached. However, in this case, for fast write memory bits, because they can complete the write and reach their target resistance value faster than other general memory bits, fast write memory bits are usually subjected to "excessive time" of pressure when operating under the same writing conditions. This is the "excessive pressure" time after reaching the target resistance value, as shown in Figure 4. Therefore, such excessive pressure will also cause excessive pressure on fast write memory bits, leading to damage to the resistive memory cell structure and thus degrading its reliability.

[0034] On the other hand, if the write voltage and write current are reduced to accommodate the write conditions of fast memory bits, it may cause underwrite problems for slow memory bits. Therefore, in view of the numerous shortcomings mentioned above that can be improved, the applicant proposes an innovative write method, which is a one-time write method for non-volatile memory disclosed in this invention. Its aim is to successfully optimize the write period of different memory bits (including fast write memory bits, standard write memory bits, and slow write memory bits) in the memory cell through the write method disclosed in this invention.

[0035] According to the writing method disclosed in this invention, the flowchart of its steps is shown in Figure 5, including steps S501, S503, and S505. Hereinafter, to explain in detail the specific implementation of the writing method disclosed in this invention, please refer to the circuit diagram shown in Figure 6. This circuit can be used to implement the writing method disclosed in this invention. However, it is worth noting that this circuit structure is not limited to this invention; in other words, it is used to illustrate the main technical content and characteristics of this invention, and to enable those skilled in the art to understand, manufacture, and use this invention. However, it should be noted that this circuit structure is not intended to limit the scope of this invention. Therefore, any equivalent modifications or variations thereof according to the spirit of this invention, including the memory cells and their circuit composition used in the memory cell architecture, should still fall within the scope of this invention under equivalent variations. The writing method disclosed in this invention can also be implemented through other embodiments (circuit structures), which should also be covered within the scope of this invention, as stated above.

[0036] According to the non-volatile memory write-once method disclosed in this invention, it is suitable for a memory module. This invention is illustrated using the memory module architecture shown in Figure 6 as an example, but as stated above, this invention is not limited to this architecture. The memory module 600 includes a memory cell 60 for storing data to be written, a source transistor 62, a word transistor 64, and a bit transistor 66. The memory cell 60 is a two-terminal element; in this embodiment, a resistive memory cell is used as an example. The source of the bit transistor 66 is connected to the drain of the word transistor 64, the drain of the bit transistor 66 is connected to a write voltage input terminal VBL, and the gate of the bit transistor 66 is connected to a bit line drive voltage VGB. The source of the character line transistor 64 is connected to the first terminal of the memory cell 60, and the gate of the character line transistor 64 is connected to a character line drive voltage VWL. The second terminal of the memory cell 60 is connected to the drain of the source line transistor 62, the gate of the source line transistor 62 is connected to a source line drive voltage VGS, and the source of the source line transistor 62 is connected to a power supply terminal VSL. According to an embodiment of the present invention, the bit line transistor 66, the character line transistor 64, the memory cell 60, and the source line transistor 62 are sequentially connected in series to form the memory module 600, and the memory module 600 is electrically coupled between the write voltage input terminal VBL and the power supply terminal VSL.

[0037] The write method disclosed in this invention first provides a write voltage in step S501. According to one embodiment of the invention, the write voltage Vwrite can be input to the memory module 600 via the write voltage input terminal VBL. According to another embodiment of the invention, the write voltage Vwrite can also be input to the memory module 600 via the power supply terminal VSL. Figure 7 is a schematic diagram of the write voltage and write current versus time in one embodiment of the invention. As shown in the figure, the write voltage Vwrite is represented by a thinner solid line. The write voltage Vwrite includes a plurality of gradually increasing rising voltage signals Vin, and there is a pause interval T0 between each rising voltage signal Vin. In the embodiment shown in Figure 7, the waveform of the write voltage Vwrite outputs a ripple signal R0 at the corresponding pause interval T0, and the voltage level of the ripple signal R0 is lower than the voltage level of each rising voltage signal Vin.

[0038] In step S503, a write current Iwrite is generated corresponding to the write voltage Vwrite, flowing through the memory cell 60. Similarly, referring to the waveform diagram shown in Figure 7, the write current Iwrite is represented by a thicker, shorter dashed line. The write current Iwrite includes a plurality of gradually increasing rising current signals Iin, and each rising current signal Iin is separated by a pause interval T0. In the embodiment shown in Figure 7, the waveform of the write current Iwrite also outputs a ripple signal R0' at the corresponding pause interval T0, and the current level of the ripple signal R0' is lower than the current level of each rising current signal Iin.

[0039] In detail, these gradually increasing rising voltage signals Vin are composed of multiple pulse trains with gradually increasing voltage, and the gradually increasing rising current signals Iin are composed of multiple pulse trains with gradually increasing current. By designing a corresponding pause interval T0, through the unique write voltage and write current settings of this invention, as shown in step S505, this invention can write to the memory module 600 according to the write voltage Vwrite and write current Iwrite, and keep the voltage across the two ends of the memory cell 60 within a predetermined range during the writing process to achieve optimization.

[0040] Figure 8 is a schematic diagram of the write voltage Vwrite and write current Iwrite relative to time in another embodiment of the present invention. As shown in the figure, the waveforms of the write voltage Vwrite and write current Iwrite can also be designed to output zero (amplitude = 0) when corresponding to the pause interval T0, thus achieving the purpose of the present invention. One of the objectives of the present invention is to control the pause interval T0 formed between a plurality of gradually increasing rising voltage signals Vin or a plurality of gradually increasing rising current signals Iin by using these gradually increasing rising voltage signals Vin or rising current signals Iin. In this way, the ballooning effect commonly seen in conventional memory elements during writing can be avoided by using these several rising voltage signals Vin and rising current signals Iin with pause interval T0.

[0041] Furthermore, the write method disclosed in this invention further includes a self-terminate write function, as shown in Figure 9. This includes steps S92 and S94. In step S92, the invention detects the write voltage Vwrite; and in step S94, when the detected write voltage Vwrite reaches a preset threshold voltage value, writing to the memory module 600 is stopped to optimize the write period of the memory cell 60. However, the self-terminate write solution of this invention is not limited to detecting the write voltage Vwrite; it can also be implemented by detecting the write current Iwrite. As shown in Figure 10, steps S102 and S104 are included. First, the write current Iwrite is detected; and when the detected write current Iwrite reaches a preset threshold current value, writing to the memory module 600 is stopped to optimize the write period of the memory cell 60. The self-terminate write solution can be implemented using the self-terminate write circuit 68 shown in Figure 6.

[0042] In detail, please refer to the circuit shown in Figure 6. The self-stop write circuit 68 is electrically connected to the drain of the bit line transistor 66 and generates a stop signal TERMINATE. This invention can use the stop signal TERMINATE to stop the continuous writing of the memory cell 60. In one embodiment of this invention, the self-stop write circuit 68 may include (but is not limited to) a write signal generator 681, a buffer 682, a threshold signal generator 683, and a comparator 684. Write signal generator 681 generates a write reference signal REFW, threshold signal generator 683 generates a threshold signal THRESHOLD, and buffer 682 has a positive input, a negative input, an output, and an enable input. The positive input of buffer 682 is connected to write signal generator 681 to receive the write reference signal REFW, the negative input of buffer 682 is connected to its output to form negative feedback, and the enable input of buffer 682 receives the stop signal TERMINATE. Comparator 684 has a positive input node, a negative input node, and an output node. The positive input node of comparator 684 is connected to the output of buffer 682 and the write voltage input VBL. The negative input node of comparator 684 is connected to threshold signal generator 683 to receive the threshold signal THRESHOLD. In this embodiment, when the positive input node of comparator 684 is used to receive the write voltage Vwrite, its write reference signal REFW corresponds to a reference voltage signal. Generally, this reference voltage signal can be preset according to the characteristics of memory cell 60. In this case, the stop signal TERMINATE output by comparator 684 corresponds to the write voltage Vwrite as a voltage signal. At the same time, the threshold signal THRESHOLD generated by threshold signal generator 683 provides a threshold voltage value. Therefore, comparator 684 can compare the write voltage Vwrite with the threshold voltage value. When comparator 684 compares the write voltage Vwrite with the threshold voltage value, it generates the stop signal TERMINATE at its output node to close the write buffer 682 and stop the continuous writing of memory cell 60.

[0043] On the other hand, in an alternative embodiment of the present invention, as shown in the flowchart of Figure 10 above, the write current Iwrite can be detected instead of the write voltage Vwrite to achieve a self-stop writing solution. In this alternative embodiment, when the positive input node of comparator 684 is connected to the output of buffer 682 and the drain of bit line transistor 66, and the signal it receives is the write current Iwrite, the write reference signal REFW corresponds to a reference current signal. Generally, this reference current signal can also be preset according to the characteristics of memory cell 60. At the same time, the threshold signal THRESHOLD generated by threshold signal generator 683 provides a threshold current value, and the negative input node of comparator 684 is connected to threshold signal generator 683 to receive this threshold current value. Therefore, through these settings, the TERMINATE signal output by comparator 684 is a current signal corresponding to the write current Iwrite. Thus, when comparator 684 compares the write current Iwrite to be higher than the threshold current value, it generates the TERMINATE signal at its output node to turn off writing to the buffer 682 and stop the continuous writing to the memory unit 60.

[0044] Generally speaking, in any embodiment of the present invention, the write reference signal REFW and the threshold signal THRESHOLD can be preset according to the characteristics of different memory cells.

[0045] From the perspective of these technical solutions, the self-stop write circuit disclosed in this invention can enable the memory cell to self-stop the write process without additional detection and verification signals by setting the threshold signal THRESHOLD and generating the stop signal TERMINATE. Due to the different process conditions in semiconductor manufacturing, which cause characteristic differences in different memory cells, please refer to Figures 7 and 8 for the corresponding signal waveform diagrams of different memory bits (fast write memory bits, standard write memory bits, and slow write memory bits). As shown in the STN section of these figures, when the write voltage Vwrite or write current Iwrite exceeds the preset threshold voltage or threshold current value, the aforementioned stop signal TERMINATE is generated, causing the memory module to self-stop writing. This is the signal waveform where the voltage and current indicated by the STN section in these figures drop sharply and abruptly to zero. Therefore, whether it is the fast write memory bit FB, the standard write memory bit TB, or the slow write memory bit SB shown in Figures 7 and 8, the writing period can be optimized to achieve the purpose of this invention, avoiding 1. excessive and unnecessary pressure on the fast write memory bit FB, and 2. the possibility that the slow write memory bit SB may not be fully written (underwrite), while 3. ensuring that the standard write memory bit TB can be fully written.

[0046] In addition, please continue to refer to the flowchart in Figure 11 of this invention. According to another embodiment of this invention, the writing method disclosed in this invention can be further described as follows: First, a writing time (that is, the writing time Tmax shown in Figures 7 and 8) is preset. The purpose of this setting is that when the writing time Tmax preset by the user or system designer is reached, step S1103 can be executed, thereby directly stopping the input of the writing voltage Vwrite and the writing current Iwrite, so as to directly terminate the writing to the memory cell. In one embodiment of this invention, the writing time Tmax is set to, for example (but not limited to), 10~15 nanoseconds (ns).

[0047] As can be seen from the foregoing, the one-time write method disclosed in the embodiments of the present invention has been proven to achieve optimal performance even for different memory bits in a memory module during the write process. Furthermore, in order to simultaneously improve the ballooning effect commonly seen in conventional memory elements during writing, the present invention also designs the write voltage and write current as several rising voltage signals and rising current signals with pause intervals.

[0048] Furthermore, the memory cells used in the memory module disclosed in this invention are not limited to the aforementioned types of memory. According to the numerous different embodiments of this invention, the memory cells designed and used in this invention can also be implemented using resistive memory cells, magnetoresistive memory cells, or other non-volatile memory cells. In addition, those skilled in the art can make equivalent modifications and changes based on the inventive intent and spirit of this invention without departing from its spirit, making it widely applicable to various other memory cell architectures. This invention proposes an optimized writing method that balances the write performance and reliability of memory cells. In summary, it is evident that the technical solution claimed by the applicant in this case has excellent industrial applicability and competitiveness, and is not something that can be easily accomplished by those skilled in the art; therefore, it should meet the requirements for patentability.

[0049] Therefore, in view of the above, compared with the prior art, it is certain that the embodiments and methods disclosed in this invention can effectively solve the deficiencies still existing in the prior art. Furthermore, the one-time write method disclosed in this invention can not only be applied to common electronic memory components, but also widely applied to memory devices of various electronic circuit components in the semiconductor industry, integrated circuit industry, or power electronics. Clearly, the technical solution disclosed by the applicant has excellent industrial applicability and competitiveness. At the same time, the applicant has also verified through various experimental data and empirical data that the technical features, methods, and effects achieved by the present invention are significantly different from existing solutions, and cannot be easily accomplished by those skilled in the art; rather, it possesses progressiveness.

[0050] It should be noted, however, that this invention is not limited to the transistor structures or system design architectures used in the above embodiments. The several embodiments described above are illustrative examples using common memory types and their operating transistors, and are intended to enable those skilled in the art to fully understand the technical ideas disclosed in this invention. In other words, those skilled in the art can make equivalent modifications and changes based on the inventive intent and spirit of this invention without departing from its spirit, such as using other types or forms of transistors, or using various non-volatile memory elements to construct memory storage units. However, within such equivalent scope, they should still fall within the scope of this invention.

[0051] The embodiments described above are merely for illustrating the technical ideas and features of the present invention. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be used to limit the patent scope of the present invention. That is, all equivalent changes or modifications made in accordance with the spirit disclosed in the present invention should still be covered within the patent scope of the present invention.

[0052] 100: Resistive memory write circuit 10: Resistive memory cell 12: Transistor 14: Transistor 16: Transistor 17: Write buffer VSS: Low Voltage Contact VGS: Source line drive voltage VWL: Character line drive voltage VGB: Bit line drive voltage VBL: Write voltage input terminal VSL: Power Supply Vref_w: Write reference voltage Vwrite: Write voltage Iwrite: Write current Vin: Rising Voltage Signal Iin: Rising current signal T0: Pause Interval R0,R0': Ripple signal Rcell: Resistance value ΔVR, ΔVts, ΔVtb: Trans-pressure S501, S503, S505, S92, S94, S102, S104, S1101, S1103: Steps 600: Memory Module 60: Memory Unit 62: Source Linear Transistor 64: Character Linear Transistor 66-bit linear transistor 68: Self-abort write circuit 681: Write signal generator 682: Buffer 683: Threshold Signal Generator 684: Comparator TERMINATE: Abort signal REFW: Write reference signal THRESHOLD: Threshold Signal Tmax: Write time STN: Section FB: Fast Write Memory Bits TB: Standard Write Memory Bits SB: Slow write to memory bits

Claims

1. A one-time write method for a non-volatile memory, suitable for a memory module, the memory module comprising a memory cell for storing data to be written, a source line transistor, a word line transistor, and a bit line transistor, the bit line transistor, the word line transistor, the memory cell, and the source line transistor being sequentially connected in series to form the memory module, such that the memory module is electrically coupled between a write voltage input terminal and a power supply terminal, the one-time write method comprising the following steps: providing a write voltage, the write voltage being input to the memory module via the write voltage input terminal, and the write voltage comprising a plurality of gradually increasing rising voltage signals, each of the rising voltage signals having a pause interval; generating a write current flowing through the memory cell in response to the write voltage, the write current comprising a plurality of gradually increasing rising current signals, and each of the rising current signals being spaced apart by the pause interval, wherein... These gradually increasing rising current signals are composed of multiple pulse trains with gradually increasing current; and the memory module is written according to the write voltage and the write current, wherein the memory cell is a two-terminal element, such that the voltage across the two ends of the memory cell is kept within a predetermined range during the write, wherein a pause interval is formed between each of the rising voltage signals and each of the rising current signals written to the memory module, so that the memory module avoids a bulging effect, wherein the waveform of the write voltage and the waveform of the write current output a ripple signal when corresponding to the pause interval.

2. The one-time write method as described in request item 1 further includes: Preset a write time; And when the write time is reached, the input of the write voltage and the write current is stopped, thereby directly stopping the writing to the memory cell.

3. The one-time write method as described in request item 1, wherein, The voltage level of the ripple signal is lower than the voltage level of each of the rising voltage signals.

4. A one-time write method as described in request item 1, wherein, The waveform of the written voltage is zero when corresponding to the pause interval.

5. A one-time write method as described in request item 1, wherein, The write voltage can be selectively input to the memory module through the power supply terminal.

6. The one-time write method as described in request item 1 further includes: Detect the write voltage; And when the write voltage reaches a preset threshold voltage value, the writing to the memory module is stopped, so as to optimize the writing period of the memory cell.

7. A one-time write method as described in request item 1, wherein, The source of the bit line transistor is connected to the drain of the word line transistor, the drain of the bit line transistor is connected to the write voltage input terminal, the gate of the bit line transistor is connected to a bit line drive voltage, the source of the word line transistor is connected to the first terminal of the memory cell, the gate of the word line transistor is connected to a word line drive voltage, the second terminal of the memory cell is connected to the drain of the source line transistor, the gate of the source line transistor is connected to a source line drive voltage, and the source of the source line transistor is connected to the power supply terminal.

8. A one-time write method as described in request item 7, wherein, The memory module further includes a self-stop write circuit, which is electrically connected to the drain of the bit line transistor and generates a stop signal that stops the continuous writing of the memory cell.

9. A one-time write method as described in request item 8, wherein, The stop signal corresponds to a voltage signal that should be written.

10. A one-time write method as described in request item 8, wherein, The self-stop write circuitry includes: a write signal generator, a buffer, a threshold signal generator, and a comparator. The write signal generator generates a write reference signal, and the threshold signal generator generates a threshold signal. The buffer has a positive input, a negative input, an output, and a comparator. The positive input of the buffer is connected to the write signal generator to receive the write reference signal, and the negative input of the buffer is connected to its output to form negative feedback. The enable terminal receives the stop signal. The comparator has a positive input node, a negative input node, and an output node. The positive input node of the comparator is connected to the output terminal of the buffer and the write voltage input terminal to receive the write voltage. The negative input node of the comparator is connected to the threshold signal generator to receive the threshold signal. When the comparator compares the write voltage to be higher than the threshold signal, it generates the stop signal at its output node to turn off writing to the buffer and stop the continuous writing of the memory cell.

11. A one-time write method as described in request item 10, wherein, When the stop signal corresponds to a voltage signal that should be written, the threshold signal generated by the threshold signal generator provides a threshold voltage value.

12. A one-time write method as described in request item 1, wherein, The current level of the ripple signal is lower than the current level of each of the rising current signals.

13. The one-time write method as described in request item 1, wherein, The waveform of the write current is zero when the corresponding pause interval is applied.

14. The one-time write method as described in request item 1 further includes: Detect the write current; And when the write current reaches a preset threshold current value, the writing to the memory module is stopped, so as to optimize the writing period of the memory cell.

15. A one-time write method as described in request item 8, wherein, The stop signal corresponds to a current signal for the write current.

16. A one-time write method as described in request item 10, wherein, When the stop signal corresponds to a current signal for the write current, the threshold signal generated by the threshold signal generator provides a threshold current value.

17. A one-time write method as described in request item 1, wherein, These gradually increasing voltage signals consist of multiple pulse trains with gradually increasing voltage.

18. A one-time write method as described in request item 1, wherein, The memory cell in the memory module is a resistive memory cell, a magnetoresistive memory cell, or other non-volatile memory cell.

19. A one-time write method as described in request item 10, wherein, The write reference signal can be a reference voltage signal, which is preset according to the characteristics of the memory cell.

20. A one-time write method as described in request item 10, wherein, The write reference signal can be a reference current signal, which is preset according to the characteristics of the memory cell.

21. A one-time write method as described in request item 8, wherein, The self-stop write circuitry includes: a write signal generator, a buffer, a threshold signal generator, and a comparator. The write signal generator generates a write reference signal, and the threshold signal generator generates a threshold signal. The buffer has a positive input, a negative input, an output, and an enable input. The positive input of the buffer is connected to the write signal generator to receive the write reference signal. The negative input of the buffer is connected to its output to form negative feedback. The enable input of the buffer receives the stop signal. The comparator has a positive input node, a negative input node, and an output. The comparator's positive input node is connected to the output of the buffer and the drain of the bit-line transistor to receive the write current. The comparator's negative input node is connected to the threshold signal generator to receive the threshold signal. When the write reference signal is a reference current signal, the threshold signal is a threshold current value, causing the comparator's negative input node to be connected to the threshold signal generator to receive the threshold current value. When the comparator compares the write current to be higher than the threshold current value, it generates the stop signal at its output node to close the write to the buffer and stop the continuous writing to the memory cell.

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