Electronic-photonic processors and related packages

Abstract

This invention describes an electro-photonic package and related manufacturing methods. The package may include a plurality of photonic integrated circuits (PICs), each PIC including a photonic accelerator configured to perform matrix multiplication in an optical domain. The package may further include an application-specific integrated circuit (ASIC) configured to control at least one of the photonic accelerators. The package further includes an interposer. The plurality of PICs are coupled to a first side of the interposer, and the ASIC is coupled to a second side of the interposer opposite to the first side. A first thermally conductive member is in thermal contact with at least one of the PICs. The first thermally conductive member may include a heat sink. A second thermally conductive member is in thermal contact with the ASIC. The second thermally conductive member may include a cover. The first thermally conductive member faces the first side of the interposer, and the second thermally conductive member faces the second side of the interposer. In some embodiments, the interposer is partially on a substrate and partially on the PICs.

Description

Technical Field

[0001] Cross-reference to related applications

[0002] This application claims the benefits under patent law of U.S. Provisional Patent Application No. 63 / 192,519 entitled "OPTICAL COMPUTE NODE" filed on May 24, 2021, under Agent's No. L0858.70042US01, and U.S. Provisional Patent Application No. 63 / 191,278 entitled "OPTICAL COMPUTE NODE" filed on May 20, 2021, under Agent's No. L0858.70042US00, each of which is incorporated herein by reference in its entirety. Prior Technology

[0003] Deep learning, machine learning, latent variable models, neural networks, and other matrix-based differentiable programs are used to solve a variety of problems, including natural language processing and object recognition in images. Solving these problems with deep neural networks typically requires long processing times to perform the necessary computations. Known methods for accelerating deep learning algorithms have developed specialized hardware architectures. This is because conventional computer processors, such as central processing units (CPUs), which consist of circuits including billions of transistors that implement logic gates on bits of information represented by electrical signals, are designed for general-purpose computing and are therefore not optimized for the specific types of data movement and computation required by algorithms used in deep learning and other matrix-based differentiable programs. A known example of specialized hardware used in deep learning is a graphics processing unit (GPU) with a highly parallel architecture, which makes these GPUs more efficient than CPUs used for image processing and graphics rendering. Following its development for graphics processing, GPUs were found to be more efficient than CPUs used for other parallelizable algorithms, such as those used in neural networks and deep learning. This realization, and the increasing popularity of artificial intelligence and deep learning, has led to further research into new electronic circuit architectures that can further improve the speed of these computations.

[0004] Deep learning using neural networks conventionally requires two phases: a training phase and an evaluation phase (sometimes called "inference"). Before a deep learning algorithm can be meaningfully executed on a processor during the evaluation phase—for example, to classify image or speech samples—the neural network must first be trained. The training phase can be time-consuming and computationally intensive. Summary of the Invention

[0005] Some embodiments relate to an electro-photonic package comprising: a substrate having an opening defined through the substrate; an application-specific integrated circuit (ASIC) and a photonic integrated circuit (PIC), wherein a first chip between the ASIC and the PIC is disposed in the opening; an interposer layer, wherein the first chip is coupled to a first side of the interposer layer, and a second chip between the ASIC and the PIC is coupled to a second side of the interposer layer opposite to the first side; a heat sink disposed in the opening and in thermal contact with the first chip; and a thermally conductive cap in thermal contact with the second chip.

[0006] In some embodiments, the opening is defined from the top surface of the substrate to the bottom surface of the substrate.

[0007] In some embodiments, the first chip is the PIC and the second chip is the ASIC, such that the heat sink is in thermal contact with the PIC and the thermal cover is in thermal contact with the ASIC.

[0008] In some embodiments, the first wafer is at least partially disposed in the opening.

[0009] In some embodiments, the heat-conducting cover has an optical fiber channel defined through the heat-conducting cover.

[0010] In some embodiments, the optical fibers through the optical fiber channel are configured to be edge-coupled to the PIC.

[0011] In some embodiments, the substrate has a top surface and a bottom surface facing the interposer, wherein the electrophotonic package further includes land grid array (LGA) pads coupled to the bottom surface of the substrate.

[0012] In some embodiments, the interposer layer comprises a silicon interposer layer or an organic interposer layer.

[0013] In some embodiments, the PIC includes a photon accelerator configured to perform matrix multiplication in the optical domain, and the ASIC includes a digital controller configured to control the photon accelerator.

[0014] In some embodiments, the electrophotonic package does not contain a laser.

[0015] Some embodiments relate to an electrophotonic processor comprising a plurality of photonic integrated circuits (PICs), each PIC including a photonic accelerator configured to perform matrix multiplication in an optical domain; an application-specific integrated circuit (ASIC) configured to control at least one of the photonic accelerators; an interposer layer wherein the plurality of PICs are coupled to a first side of the interposer layer and the ASIC is coupled to a second side of the interposer layer opposite to the first side; a first thermally conductive member in thermal contact with at least one of the PICs; and a second thermally conductive member in thermal contact with the ASIC, wherein the first thermally conductive member faces the first side of the interposer layer and the second thermally conductive member faces the second side of the interposer layer.

[0016] In some embodiments, the electrophotonic processor further includes a substrate having an opening formed through the substrate, wherein the interposer is mounted on the substrate, and wherein the first thermally conductive member or the second thermally conductive member is disposed in the opening.

[0017] In some embodiments, the substrate has a top surface and a bottom surface facing the interposer, wherein the electrophotonic processor further includes land grid array (LGA) pads coupled to the bottom surface of the substrate.

[0018] In some embodiments, the second thermally conductive member is in contact with the substrate.

[0019] In some embodiments, the interposer layer comprises a silicon interposer layer or an organic interposer layer.

[0020] In some embodiments, the digital controller is configured to control the photon accelerators to perform matrix multiplication in parallel, block-by-block manner in the optical domain.

[0021] In some embodiments, the photon accelerators include photon multipliers configured to perform scalar multiplication in the optical domain.

[0022] In some embodiments, the photon accelerators include photon adders configured to perform scalar addition in the optical domain.

[0023] In some embodiments, the plurality of PICs, the ASIC, the interposer, the first thermally conductive member, and the second thermally conductive member form a package, wherein the electrophotonic processor further includes a laser disposed outside the package.

[0024] In some embodiments, the first thermally conductive member includes a conductive post.

[0025] Some embodiments relate to an electro-photonic package comprising a substrate; a photonic integrated circuit (PIC) supported by the substrate; an interposer partially disposed on the substrate and partially disposed on the PIC; a first set of connections coupling the interposer to the substrate and a second set of connections coupling the interposer to the PIC, wherein the first set of connections has a different size relative to the second set of connections; and an application-specific integrated circuit (ASIC) disposed on the interposer.

[0026] In some embodiments, the electrophotonic package further includes a thermally conductive cover that is in thermal contact with the ASIC.

[0027] In some embodiments, the first connection set is a ball grid array (BGA).

[0028] In some embodiments, the first set of connections is larger than the second set of connections.

[0029] In some embodiments, the substrate has an opening defined through the substrate, and the PIC is disposed in the opening.

[0030] Some embodiments relate to a method for manufacturing an electro-photonic package, the method comprising: obtaining a substrate, an application-specific integrated circuit (ASIC), a photonic integrated circuit (PIC), and an interposer; forming an interposer module by attaching the ASIC to a first side of the interposer and attaching the PIC to a second side of the interposer; attaching the interposer module to the substrate; placing a first thermally conductive member in thermal contact with the ASIC; and placing a second thermally conductive member in thermal contact with the PIC.

[0031] In some embodiments, the method further includes forming a first underfiller on the first side of the interlayer; flipping the interlayer; and, following the flipping, forming a second underfiller on the second side of the interlayer.

[0032] In some embodiments, placing the second thermally conductive member in thermal contact with the PIC includes inserting the second thermally conductive member through an opening formed in the substrate.

[0033] In some embodiments, the method further includes flipping the substrate such that placing the first thermally conductive member in thermal contact with the ASIC is performed before flipping the substrate, and placing the second thermally conductive member in thermal contact with the PIC is performed after flipping the substrate. Simple Explanation of the Diagram

[0034] Various forms and embodiments of this application will be described with reference to the following drawings. It should be understood that the drawings are not necessarily drawn to scale. Items appearing in multiple drawings are indicated by the same element symbols in the drawings in which these items appear.

[0035] Figure 1A illustrates representative matrix-vector multiplication according to some embodiments.

[0036] Figure 1B is a block diagram illustrating an electronic photonic processor configured to perform matrix-vector multiplication according to some embodiments.

[0037] Figure 1C is a block diagram illustrating a portion of a photon accelerator according to some embodiments of Figure 1B.

[0038] Figure 2A illustrates a representative matrix-vector multiplication performed block-by-block according to some embodiments.

[0039] Figure 2B is a block diagram of an electronic photonic processor configured to perform matrix-vector multiplication block by block according to some embodiments.

[0040] Figure 2C is a schematic diagram of an electrophotonic processor with an intermediary layer according to some embodiments.

[0041] Figure 3A is a first cross-sectional view of a package containing an electro-photonic processor according to some embodiments.

[0042] Figure 3B is a second cross-sectional view of a package containing an electro-photonic processor according to some embodiments.

[0043] Figure 3C is a top view of a package containing an electro-photonic processor according to some embodiments.

[0044] Figure 3D is a perspective view of a package containing an electrophotonic processor according to some embodiments.

[0045] Figure 4 is a cross-sectional view of a package mounted to a printed circuit board via a socket according to some embodiments.

[0046] Figure 5 is a first cross-sectional view of another package containing an electrophotonic processor according to some embodiments.

[0047] Figure 6 illustrates a flowchart of a process for manufacturing an electro-photonic package according to some embodiments. Implementation

[0048] I. Overview

[0049] The inventors have recognized and understand that photon accelerators are sensitive to temperature changes caused by heat generation in the photon accelerator itself or in the electronic circuitry controlling the photon accelerator. The inventors have developed a package designed to allow heat to diffuse in a manner that limits temperature changes.

[0050] The proper functioning of a photon accelerator heavily relies on its refractive index remaining relatively constant over time. The refractive index of a material—a dimensionless number describing how fast light travels through the material—is a critical parameter for the design of photonic circuits because it determines how light propagates within the material. This is because the propagation constants of modes defined in an optical waveguide are directly dependent on the refractive index. The ability to accurately control the refractive index of a material allows engineers to control, modulate, and redirect light, as well as perform other functions. The refractive index of a material can be varied by utilizing plasma dispersion effects (by altering the density of carriers in the material) and other effects. Therefore, the refractive index can be intentionally varied to achieve desired effects. However, undesirable changes in the refractive index can also occur, for example, due to heat. When a photon accelerator is exposed to heat generated by the accelerator itself or other wafers, the refractive index changes in unpredictable ways, thus altering the properties of the optical modes. This adversely affects the performance of the photon accelerator.

[0051] Although photon accelerators themselves generate heat, this heat is typically less than that generated by the digital controllers that control them. This is because electronic circuits are sensitive to parasitic capacitance, which causes power dissipation and thus heat generation via the Joule effect. Conversely, photonic circuits are inherently insensitive to parasitic capacitance. In one instance, the photon accelerator operates at 1 W and the digital controller controlling it operates at 100 W—thus generating significantly more heat.

[0052] Having understood that heat generated by a digital controller is a major disruptor to the proper functioning of a photon accelerator, the inventors have developed a package engineered to divert heat away from the photon accelerator. In some embodiments, for example, a package is provided comprising an interposer having a photonic integrated circuit (PIC) and an application-specific integrated circuit (ASIC) attached to the interposer. The PIC includes the photon accelerator, and the ASIC includes the digital controller. The PIC may be positioned on one side of the interposer (e.g., the bottom side) or on the opposite side (e.g., the top side), and the heat generated by the PIC is diverted away from the PIC, thereby limiting thermally induced changes in the refractive index.

[0053] The PIC also generates some heat. Although this heat is significantly less than that generated by the ASIC, it can still cause undesirable changes in the refractive index. Therefore, it is important that this heat also diffuses on the outside of the package. The packaging developed by the inventors allows the heat generated by the PIC to diffuse in the opposite direction to the heat generated by the ASIC. This can be accomplished, for example, by placing a heat-conducting component on the opposite side of the package. II. Electro-photon processor

[0054] This application relates to analog accelerators configured to execute neural networks. An accelerator is a microprocessor capable of accelerating certain types of workloads. Typically, workloads that can be accelerated are offloaded to high-performance accelerators, which are far more efficient at performing workloads such as artificial intelligence, machine vision, and deep learning. Accelerators are dedicated processors and are typically programmed to work in conjunction with general-purpose processors to perform tasks. Analog accelerators are accelerators that perform computations in an analog domain. Therefore, analog accelerators typically involve digital-to-analog conversion and analog-to-digital conversion that allow the analog accelerator to communicate with digital hardware.

[0055] Photonic accelerators are a specific type of analog accelerator in which computation is performed in the optical domain (using light). The inventors have recognized and understand that using optical signals (in lieu of or in combination with electrical signals) can overcome some of the problems of electronic computing. Optical signals travel at the speed of light. Therefore, the latency of optical signals has far fewer limitations compared to the propagation latency of electrical signals. Furthermore, virtually no power dissipation occurs by increasing the distance the optical signal travels, thus eliminating the need for new topologies and processor layouts that would be infeasible with the use of electrical signals. Therefore, photonic processors offer significantly better speed and efficiency performance than conventional electronic processors.

[0056] Some embodiments involve photonic accelerators designed to run machine learning algorithms or other types of data-intensive computation. Certain machine learning algorithms (e.g., support vector machines, artificial neural networks, and probabilistic graphical model learning) heavily rely on linear transformations over multidimensional arrays / tensors. The simplest linear transformation is matrix-vector multiplication, which, using known algorithms, has an order of magnitude O(N^2) complexity, where N is the dimension of a square matrix multiplied by a vector of the same size. General matrix-matrix (GEMM) operations are prevalent in software algorithms, including those used in graphics processing, artificial intelligence, neural networks, and deep learning.

[0057] Figure 1A illustrates a representation of matrix-vector multiplication according to some embodiments. Matrix-vector multiplication is an example of GEMM. Matrix W is referred to herein as a "weight matrix," "input matrix," or simply a "matrix," and individual elements of matrix W are referred to herein as "weights," "matrix values," or "matrix parameters." Vector X is referred to herein as an "input vector," and individual elements of vector X are referred to herein as "input values" or simply "inputs." Vector Y is referred to herein as an "output vector," and individual elements of vector Y are referred to herein as "output values" or simply "outputs." In this example, W is an NxN matrix, but embodiments of this application are not limited to a square matrix or any particular size. In the context of artificial neural networks, matrix W may be a weight matrix, or a submatrix of a weight tensor, or an activation (batch) matrix, or a submatrix of a (batch) activation tensor, and several possible instances. Similarly, for example, input vector X may be a vector of weight tensors or a vector of activation tensors.

[0058] The matrix-vector multiplication in Figure 1A can be decomposed into scalar multiplication and scalar addition. For example, the output value yi (where = 1, 2…N) can be calculated as a linear combination of the input values ​​x1, x2…xN. Obtaining yi involves performing scalar multiplication (e.g., Wi1 multiplied by x1, and Wi2 multiplied by x2) and scalar addition (e.g., Wi1x1 plus Wi2x2). In some embodiments, scalar multiplication, scalar addition, or both can be performed in the optical domain, as discussed in further detail below.

[0059] Figure 1B illustrates an electronic photonic processor 10 implemented using photonic circuitry according to some embodiments. The processor 10 can be configured to perform matrix multiplication (e.g., matrix-vector multiplication or matrix-matrix multiplication). The processor 10 includes a digital controller 100 and a photonic accelerator 150. The digital controller 100 operates in the digital domain, and the photonic accelerator 150 operates in the analog photonic domain.

[0060] The digital controller 100 includes a digital processor 102 and a memory 104. The photon accelerator 150 includes an optical encoder module 152, an optical computing module 154, and an optical receiver module 156. Digital-to-analog (DAC) modules 106 and 108 convert digital data to analog signals. Analog-to-digital (ADC) module 110 converts analog signals to digital values. Thus, the DAC / ADC modules provide an interface between the digital and analog domains. In this example, DAC module 106 generates N analog signals (one for each item of the input vector), DAC module 108 generates N x N analog signals (one for each item of the matrix), and ADC module 110 receives N analog signals (one for each item of the output vector). Although the matrix W is square in this example, it may be rectangular in some embodiments, such that the size of the output vector differs from the size of the input vector.

[0061] Processor 10 receives an input vector represented by groups of input bit strings as input from an external processor (e.g., CPU) and produces an output vector represented by groups of output bit strings. For example, if the input vector is an N-dimensional vector, it can be represented by N separate bit strings, each representing a different component of the vector. The input bit strings can be received as electrical signals from the external processor, and the output bit strings can be transmitted to the external processor as electrical signals. In some embodiments, digital processor 102 does not necessarily output an output bit string after each process iteration. Instead, digital processor 102 can use one or more output bit strings to determine a new stream of input bit strings to feed to the elements of processor 10. In some embodiments, the output bit strings themselves can be used as input bit strings for subsequent iterations of the process performed by processor 10. In other embodiments, multiple streams of output bit strings are combined in various ways to determine subsequent input bit strings. For example, one or more output bit strings can be summed together as part of the determination of subsequent input bit strings.

[0062] DAC module 106 is configured to convert digital data into analog signals. Optical encoder module 152 is configured to convert the analog signals into optically encoded information to be processed by optical computing module 154. The information may be encoded in the amplitude, phase, and / or frequency of the optical pulse. Therefore, optical encoder module 152 may include an optical amplitude modulator, an optical phase modulator, and / or an optical frequency modulator. In some embodiments, the optical signal represents the amplitude and phase of the optical pulse by the value and sign of the associated bit string. In some embodiments, the phase may be limited to a binary choice of zero phase shift or π phase shift representing positive and negative values, respectively. Embodiments are not limited to real input vector values. When encoding optical signals, complex vector components may be represented, for example, by using more than two phase values.

[0063] Optical encoder module 152 outputs N discrete optical pulses, which are transmitted to optical computing module 154. Each output of optical encoder module 152 is coupled one-to-one to an input of optical computing module 154. In some embodiments, optical encoder module 152 may be mounted on the same substrate as optical computing module 154 (e.g., optical encoder module 152 and optical computing module 154 are on the same wafer). In such embodiments, optical signals may be transmitted from optical encoder module 152 to optical computing module 154 in a waveguide such as a silicon photonic waveguide.

[0064] Optical computing module 154 performs multiplication of input vector X by matrix W. In some embodiments, optical computing module 154 includes a plurality of optical multipliers, each configured to perform scalar multiplication between terms of the input vector and terms of matrix W in the optical domain. Alternatively, optical computing module 154 may further include optical adders for adding the results of scalar multiplications together in the optical domain. Alternatively, the addition may be performed electrically. For example, optical receiver module 156 may generate a voltage resulting from the integration (over time) of the photocurrent received from the photodetector.

[0065] Optical computing module 154 outputs N discrete optical pulses, which are transmitted to optical receiver module 156. Each output of optical computing module 154 is coupled one-to-one to an input of optical receiver module 156. In some embodiments, optical computing module 154 may be mounted on the same substrate as optical receiver module 156 (e.g., optical computing module 154 and optical receiver module 156 are on the same wafer). In such embodiments, optical signals may be transmitted from optical computing module 154 to optical receiver module 156 in a silicon photonic waveguide. In other embodiments, optical computing module 154 may be mounted on a separate substrate relative to optical receiver module 156. In such embodiments, optical signals may be transmitted from photonic processor 103 to optical receiver module 156 using an optical dimension.

[0066] Optical receiver module 156 receives N optical pulses from optical computing module 154. Each of the optical pulses is then converted into an electrical analog signal. In some embodiments, the intensity and phase of each optical pulse are detected by a photodetector within the optical receiver module. The electrical signals representing those measurements are then converted into a digital domain using ADC module 110 and provided back to digital processor 102.

[0067] Digital processor 102 controls optical encoder module 152, optical computing module 154, and optical receiver module 156. Memory 104 can be used to store input and output bit strings and measurement results from optical receiver module 156. Memory 104 also stores executable instructions that, when executed by digital processor 102, control optical encoder module 152, optical computing module 154, and optical receiver module 156. Memory 104 may also include executable instructions that, based on a set of one or more output vectors determined by measurement, cause digital processor 102 to determine a new input vector to send to the optical encoder, which is measured by optical receiver module 156. In this way, digital processor 102 can control the iterative process of multiplying the input vector by multiple matrices by adjusting the settings of optical computing module 154 and feeding back detection information from optical receiver module 156 to optical encoder module 152. Therefore, the output vector transmitted by the processor 10 to the external processor can be the result of multiple matrix multiplications, rather than simply the result of a single matrix multiplication.

[0068] Figure 1C further illustrates in detail a portion of a photon accelerator 150 according to some embodiments. More specifically, Figure 1C illustrates the circuitry used to compute y1, the first term of the output vector Y. For simplicity, in this example, the input vector has only two terms, x1 and x2. However, the input vector can have any suitable size.

[0069] DAC module 106 includes DAC 206, DAC module 108 includes DAC 208, and ADC module 110 includes ADC 210. DAC 206 generates an electrical analog signal (e.g., voltage or current) based on the values ​​received by the DACs. For example, voltage Vx1 represents value x1, voltage Vx2 represents value x2, voltage VW11 represents value W11, and voltage VW12 represents value W12. Optical encoder module 152 includes optical encoder 252, optical computing module 154 includes optical multiplier 154 and optical adder 255, and optical receiver module 156 includes optical receiver 256.

[0070] Light source 402 generates light S0. Light source 402 can be implemented in any suitable manner. For example, light source 402 may include a laser, such as an edge-emitting laser of a vertical cavity surface emitting laser (VCSEL), examples of which are described in further detail below. In some embodiments, light source 402 may be configured to generate multiple light wavelengths, enabling optical processing utilizing wavelength division multiplexing (WDM), as described in further detail below. For example, light source 402 may include multiple laser resonators, each specifically sized to generate a different wavelength.

[0071] Optical encoder 252 encodes an input vector into a complex number of optical signals. For example, one optical encoder 252 encodes an input value x1 into an optical signal S(x1) and another optical encoder 252 encodes an input value x2 into an optical signal S(x2). The input values ​​x1 and x2 provided by digital processor 102 are signed digital numbers (e.g., with floating-point or fixed-point representation). The optical encoder modulates the light S0 based on the respective input voltage. For example, optical encoder 404 modulates the amplitude, phase, and / or frequency of the light to generate the optical signal S(x1), and optical encoder 406 modulates the amplitude, phase, and / or frequency of the light to generate the optical signal S(x2). The optical encoder can be implemented using any suitable optical modulator, including, for example, a light intensity modulator. Examples of such modulators include Mach-Zehnder (MZM), Franz-Keldysh (FKM), resonant modulators (e.g., ring-based or disk-based), nano-electro-electro-mechanical-system (NOEMS) modulators, etc.

[0072] Optical multipliers are designed to generate signals indicating the product between an input value and a matrix value. For example, one optical multiplier 254 generates a signal S(W11x1) indicating the product between an input value x1 and a matrix value A11, and another optical multiplier 254 generates a signal S(W12x2) indicating the product between an input value x2 and a matrix value W12. Examples of optical multipliers include Mach-Zehnder (MZM), Franz-Keldysh (FKM), resonant modulators (e.g., ring-based or disk-based), nano-electro-mechanical-system (NOEMS) modulators, etc. In one example, an optical multiplier can be implemented using a modulated detector. The modulated detector is a photodetector with the characteristic of being modulated using an input voltage. For example, a modulated detector can be a photodetector with a responsivity modulated by an input voltage. In this example, the input voltage (e.g., VW11) sets the responsivity of the photodetector. As a result, the output of the modulated detector depends not only on the amplitude of the input optical signal but also on the input voltage. If the modulated detector operates in its linear region, the output of the modulated detector depends on the product of the amplitudes of the input optical signal and the input voltage (thus achieving the desired multiplication function).

[0073] The optical adder 412 receives electronic analog signals S(W11x1) and S(W12x2) and light S0' (generated by light source 414), and generates an optical signal S(W11x1+W12x2) indicating the sum of W11x1 and W12x2.

[0074] Optical receiver 256 generates an electronic digital signal indicating W11x1 + W12x2 based on the optical signal S(W11x1 + W12x2). In some embodiments, optical receiver 256 includes a coherence detector and a transimpedance amplifier. The coherence detector generates an output indicating the phase difference between the waveguides of the interferometer. Because the phase difference is a function of W11x1 + W12x2, the output of the coherence detector also indicates that phase difference. The ADC converts the output of the coherence receiver to an output value y1 = W11x1 + W12x2. The output value y1 can be provided as input to digital processor 102, which can use the output value for further processing. III. Parallel Calculation

[0075] Some applications rely on computations involving large amounts of data. In some embodiments, photon accelerators operating in parallel can be used to process these applications. For example, a matrix to be multiplied by a vector can be decomposed into tiles. Figure 2A illustrates an example of how a matrix can be decomposed into tiles, with each tile processed by a different photon accelerator. In this way, multiple tiles can be processed in parallel. The diagram in Figure 2A depicts a matrix segmented into four tiles. In this example, performing matrix-vector multiplication involves 1) multiplying a first matrix tile by an input data vector to obtain a first output tile; 2) multiplying a second matrix tile by an input data vector to obtain a second output tile; 3) multiplying a third matrix tile by an input data vector to obtain a third output tile; and 4) multiplying a fourth matrix tile by an input data vector to obtain a fourth output tile. The output tiles together form the output vector. Each tile multiplication can be processed by a different photon accelerator. Although this example illustrates an 8x4 weighted matrix and a 4x1 input dataset, any possible size is possible.

[0076] Therefore, some embodiments relate to computing systems that include multiple photonic accelerators. One such example is illustrated in Figure 2B. The computing system shown here includes four photonic accelerators 150 and two digital controllers 100. In some embodiments, each photonic accelerator is formed as a separate chip—referred to herein as a photonic integrated circuit (PIC). Similarly, in some embodiments, each digital controller is formed as a separate chip—referred herein as an application-specific integrated circuit (ASIC). Thus, in some embodiments, the computing system includes multiple PICs and multiple ASICs.

[0077] The inventors have recognized the challenge of packaging multiple ASICs with multiple PICs. To reduce fixed assets, the inventors have understood that ASICs should be co-packaged with PICs in the same assembly. However, co-packaging presents challenges in terms of thermal extraction. PICs are particularly sensitive to temperature changes. The proper functioning of a PIC heavily depends on its refractive index remaining relatively constant over time (the refractive index of a material is temperature-dependent). Undesirable changes in the refractive index can cause the PIC's performance to deviate drastically from its expected performance. This occurs because the propagation constant associated with the optical mode is related to the refractive index of the material.

[0078] Therefore, it is extremely important that the heat generated inside the package be rapidly extracted to the outside of the package. This is not simple, because ASICs are power-hungry due to their digital nature and can therefore generate considerable levels of heat. In some embodiments, some ASICs of the type described herein use power levels up to 100 W. Additionally, the PIC itself generates heat, even though the PIC operates at significantly lower levels, such as 1 W.

[0079] The inventors have developed package designs that take into account efficient heat extraction from ASICs and PICs. The packages developed by the inventors are designed so that heat is extracted from both sides of the package. For example, heat generated by the ASIC can be extracted from the top side of the package and heat generated by the PIC can be extracted from the bottom side of the package, or vice versa. This scheme forces heat generated by the ASIC to travel preferentially away from the PIC, thus limiting changes in the refractive index.

[0080] Figure 2C illustrates a schematic diagram of a representative package design according to some embodiments. As shown, the package includes an interposer 370 (e.g., a silicon interposer or an organic interposer). An ASIC 300 is disposed on a first side of the interposer, and a PIC 350 is disposed on a second, opposite side of the interposer. Each ASIC 300 may be a chip including a digital controller 100, and each PIC 350 may be a chip including a photon accelerator 150. The interposer 370 includes conductive traces that place the PIC in communication with the ASIC. The use of an interposer is particularly useful in embodiments where the number of PICs (four in the example of Figure 2B) differs from the number of ASICs (two in the example of Figure 2B). In some embodiments, the interposer is a passive element because it includes conductive traces but does not include circuitry that requires electrical power to operate (e.g., transistors). In this way, the interposer can be manufactured inexpensively.

[0081] Thermally conductive component 250 is positioned in thermal contact with the ASIC on a first side of the interposer, and thermally conductive component 252 is positioned in thermal contact with the PIC on a second side of the interposer. The thermally conductive components can be made of any suitable thermally conductive material, including indium and silicone epoxy. Positioning an element in thermal contact with another element involves creating a thermal path between the two elements. This can be achieved in many ways, such as by positioning the elements in direct physical contact or via thermal interface material (TIM).

[0082] As shown, in the arrangement of Figure 2C, the heat generated by the ASIC is extracted from the top side of the package. In this way, the heat preferentially travels away from the PIC, thereby limiting the variation in refractive index. On the other hand, the heat generated by the PIC is extracted from the bottom side of the package. The arrows marked "heat" have different sizes to indicate that the heat generated by the ASIC is generally greater than the heat generated by the PIC. IV. Packaging

[0083] Figures 3A through 3D are schematic diagrams of a package implemented according to the principles depicted in Figure 2C. Figure 3A is a cross-sectional view taken in the yz plane, Figure 3B is a cross-sectional view taken in the xz plane, Figure 3C is a top view, and Figure 3D is a perspective view. Note that the figures are not drawn to scale. Package 360 ​​includes an interposer 370, an ASIC 300, a PIC 350, a substrate 364, a cover 362, and a heat sink 372, as well as other components. In this example, the package includes four PICs and two ASICs, but the package described herein is not limited to any particular number of chips.

[0084] The substrate 364 can be made of any suitable material, including organic and inorganic materials. For example, the substrate 364 can be made of a laminate of organic layers. A land grid array (LGA) pad can be defined on the bottom surface of the substrate, but other types of connections are also possible. The use of LGA pads allows the substrate to be mounted to a printed circuit board (PCB) via sockets. However, in other embodiments, the substrate can be directly mounted to the PCB using ball grid array (BGA) solder balls without sockets.

[0085] An opening 370 is formed through the entire thickness of substrate 364, thereby creating a channel from the top surface of the substrate to the bottom surface of the substrate. In some embodiments, a PIC or ASIC is disposed in the opening. (In some embodiments, there may be more than one opening, with each chip disposed in a separate opening). In the example of Figure 3A, the PIC is disposed in the opening. The chip can be attached to the substrate in any suitable manner, including by adhesive or by mechanically anchoring the chip to the substrate. In some embodiments, the top surface of PIC 350 is raised relative to the top surface of substrate 364, thereby allowing optical fiber connection to the side of the PIC (e.g., edge coupling). Fiber optic channels 366 are defined through cover 362. These channels allow fiber optic ribbons to pass through the insertion of the cover. Each ribbon may include multiple optical fibers assembled and edge-coupled to the PIC. Fiber optic trenches may be formed on the top surface of the substrate to accommodate the optical fibers.

[0086] Interposer 370 is partially located on the PIC and partially on the top surface of the substrate. Because the top surface of the PIC is slightly raised relative to the top surface of the substrate, the interposer may include two distinct sets of connections. A first set of connections electrically couples the interposer to the substrate. A second set of connections electrically couples the interposer to the PIC. To account for the fact that the surface of the substrate may be lower than the surface of the PIC, the connections in the first set may be larger (e.g., higher) than the connections in the second set. For example, the connections coupling the interposer to the substrate may form a ball grid array (BGA), and the connections coupling the interposer to the PIC may be solder bumps or Cu pillars. In one example, the first set of connections has a pitch of 400 μm, and the second set of connections has a pitch of 100 μm. Underfill fills the area between the interposer and the PIC. ASIC 300 is disposed on top of interposer 370. Bumps 382 place the ASIC in electrical communication with the interposer. The interposer then routes signals between the ASIC and the PIC.

[0087] Cover 362 encloses the chip inside the package. Cover 362 may be made of a high thermal conductivity material such as nickel-plated Cu or other high thermal conductivity materials such as SiC. Cover 362 may be located on the top surface of the substrate and may be in thermal contact with the top surface of the ASIC 300. For example, TIM 374 is disposed between the cover and the ASIC. Cover 362 acts as the thermally conductive member 250 of Figure 2C because it draws away heat generated by the ASIC from the top side of the package.

[0088] Heat sink 372 fills at least a portion of opening 372. Heat sink 372 may be a single piece or may include multiple dissimilar pieces. Heat sink 372 is in thermal contact with the bottom surface of PIC 350. For example, TIM 374 is disposed between the thermally conductive member and the PIC. Heat sink 372 acts as the thermally conductive member 252 of Figure 2C because it draws heat generated by the PIC from the bottom side of the package.

[0089] Figure 4 shows a side view of package 360 ​​mounted on PCB 400 via socket 402. Laser 410 is also mounted on the PCB. Optical fiber 412 passes through channel 366 and couples the laser light to the PIC. Laser 410 is located outside package 360. Therefore, in some embodiments, package 360 ​​does not contain a laser.

[0090] Figure 5 illustrates an alternative packaging implementation. This package is similar to the package in Figure 3A because it includes an interposer layer between the ASIC and the PIC, and because the cover overlies the chip and is in thermal contact with the ASIC. However, unlike the package in Figure 3A, in this package, the heat generated by the PIC is also drawn away from the top side of the package. A thermal path 500 places the PIC in thermal contact with the cover. The thermal path 500 may include conductive pillars (or vias) and conductive traces. In some embodiments, the PIC may have a TSV. In this way, electrical connections to the substrate are enabled, and the thermal path scheme is also permitted. V. to manufacture

[0091] Figure 6 is a flowchart of a method (600) for manufacturing an electro-photonic package according to some embodiments. In this figure, dashed squares represent optional manufacturing steps. It should be noted that, unless otherwise specified, manufacturing method 600 need not be performed in the order of the steps presented in Figure 6 (but some embodiments may be performed in that order). As described in detail below, in some embodiments, the manufacturing of the electro-photonic package may involve flip-chip technology.

[0092] At step 602, one or more ASICs are obtained. For example, the ASICs may be received from an ASIC manufacturing facility at a packaging facility. The ASICs may be obtained as individual wafers or as wafers. If the latter, the ASICs may be cut from the wafer, for example, using a saw blade or other suitable tool. Each ASIC may be pre-patterned (at the ASIC manufacturing facility) as a digital controller of the type described herein, such as digital controller 100. Patterning the ASICs may be performed prior to step 602.

[0093] At step 604, one or more PICs are obtained. For example, the PICs may be received from a PIC manufacturing facility at a packaging facility. As with ASICs, the PICs may be obtained as individual wafers or as wafers. If the latter, the PICs may be cut from the wafer, for example, using dicing techniques (e.g., stealth dicing). Each PIC may be pre-patterned (at the PIC manufacturing facility) as a photon accelerator of the type described herein, such as photon accelerator 150.

[0094] At step 606, an interposer is obtained. For example, the interposer may be received from an interposer manufacturing facility at a packaging facility. The interposer may be pre-patterned as described in conjunction with Figures 3A to 3D. At step 608, the interposer may be pre-dried.

[0095] At step 610, the ASIC may be attached to the interposer. This can be performed using pick-and-place techniques. In some embodiments, the attachment of the ASIC to the interposer may involve reflow and / or flux removal.

[0096] At step 612, the PIC may be attached to the interposer. This can be performed using pick-and-place techniques. In some embodiments, the attachment of the PIC to the interposer may involve reflow. The PIC may be attached to the opposite side of the interposer relative to the ASIC, as shown, for example, in Figure 3A. At step 614, the interposer module (comprising the interposer with the ASIC and PIC attached thereto) may undergo flux cleaning.

[0097] At step 616, an underfill is formed on the ASIC side of the interposer. The underfill is a curable dielectric material. At step 618, the interposer module is flipped. At step 620, the underfill is formed on the PIC side of the interposer. In other embodiments, steps 616 and 620 may be flipped such that the underfill is formed on the PIC side of the interposer before the interposer is flipped, and on the ASIC side of the interposer after the flipping step. At step 622, the underfill is cured. At step 624, solder paste stencils may be printed on one side of the interposer module, for example, the PIC side. Alternatively or additionally, solder paste printing may be performed on a BGA previously formed on one side of the interposer module, for example, the PIC side.

[0098] At step 626, a substrate is obtained. For example, the substrate may be received from a substrate manufacturing facility at a packaging facility. In some embodiments, at step 626, the substrate is etched to form an opening, as shown, for example, in Figure 3A (see opening 370). At step 628, a BGA is formed on the substrate such that when the interposer module is attached to the substrate, the BGA balls fall onto the BGA pads of step 624. At step 630, the substrate undergoes reflow. At step 632, the substrate undergoes flux removal. At step 634, the interposer module is attached to the substrate. This can be performed using pick-and-place techniques. In some embodiments, the attachment of the interposer module to the substrate may involve reflow.

[0099] Subsequently, the first thermally conductive member is positioned to make thermal contact with the ASIC and the second thermally conductive member is positioned to make thermal contact with the PIC. The thermally conductive members may be positioned on the opposite side of the interposer module. As an example, at step 638, a thermally conductive cover is mounted to the substrate such that the cover makes thermal contact (either directly or via the TIM) with the ASIC. At step 640, the package is flipped. At step 642, a heat sink is positioned to make thermal contact with the PIC. In some embodiments, the heat sink is inserted from the bottom side of the package through an opening defined in the substrate. In other embodiments, steps 638 and 642 may be flipped such that the cover is attached before the package is flipped and the heat sink is formed after the flipping step. Furthermore, in some embodiments, the PIC may be on the top side of the package and the ASIC may be on the bottom side of the package. In these embodiments, the cover contacts the PIC and the heat sink contacts the ASIC.

[0100] At step 644, the optical fiber is attached to the PIC. VI. Additional Notes

[0101] Therefore, having described several aspects and embodiments of the technology of this application, it will be understood that those skilled in the art will readily conceive of various changes, modifications, and improvements. Such changes, modifications, and improvements are intended to be within the spirit and scope of the technology described in this application. Therefore, it will be understood that the preceding embodiments are presented only by way of example, and that inventive embodiments may be practiced differently from the specific descriptions within the scope of the appended claims and their equivalents. Furthermore, any combination of two or more features, systems, articles, materials, and / or methods described herein, provided that such features, systems, articles, materials, and / or methods are not inconsistent with each other, is included within the scope of this disclosure.

[0102] Additionally, as described, some states may be embodied as one or more methods. Actions performed as part of a method can be ordered in any suitable manner. Thus, embodiments may be constructed in which actions are performed in a different order than those illustrated, which may include performing some actions simultaneously, although they are shown as sequential actions in the illustrative embodiments.

[0103] As defined herein, the definitions used should be understood as control dictionary definitions, definitions in incorporated documents, and / or the general meaning of the terms.

[0104] Unless clearly indicated to the contrary, the indefinite articles “a” and “an” as used herein and in the claims shall be understood to mean “at least one”.

[0105] As used herein and in the claims, the term "and / or" should be understood to mean "any one or both" of the elements so combined, that is, elements that are combined in some situations and separate in others.

[0106] As used herein and in the claims, the term "at least one" in relation to a list of one or more elements shall be understood to mean at least one element selected from any one or more elements in the list, but does not necessarily include at least one of each element specifically listed in the list, nor exclude any combination of elements in the list. This definition also allows for the optional presence of elements other than those specifically identified in the list of elements referred to by the term "at least one," whether related to or unrelated to those specifically identified elements.

[0107] The terms "approximately," "generally," and "about" may be used in some embodiments to mean within ±10% of the target value. The terms "approximately," "generally," and "about" may include the target value.

[0108] The use of ordinal terms such as "first," "second," and "third" in the claims does not imply any priority, preference, or order of action of one claim element over another, but is merely used as a marker to distinguish one claim element with a certain name from another claim element with the same name (if not using ordinal terms).

[0109] Furthermore, the wording and terminology used herein are for descriptive purposes and should not be considered limiting. The use of "including," "comprising," "having," "containing," "involving," and variations thereof in this document means to cover the items listed below and their equivalents, as well as additional items.

[0110] 10: Electron Photonic Processor 100: Digital Controller 102: Digital Processor 103: Photon Processor 104: Memory 106, 108: Digital-to-Analog Module / DAC Module 110: Analog Digital Module / ADC Module 150:Photon accelerator 152: Optical encoder module 154: Optical Computing Module 156: Optical Receiver Module 206,208,210:DAC 250: Thermal conductive component 252: Thermal conductive components 252: Optical Encoder 254: Light Multiplication Device 255: Light Adder 256: Optical Receiver 300: ASIC 350:PIC 360: Packaging 362: Cover 364:Substrate 366: Fibre Channel 370: Intermediary Layer 372: Heatsink / Opening 374: Thermal Interface Materials / TIM 382: Bump 400:PCB 402: Socket 402: Light source 404: Optical Encoder 406: Optical Encoder 410: Laser 412: Fiber optic cable 412: Light Adder 414: Light source 500: Hot Path 600: Method 602,604,606,608,610,612,614,616,618,620,622,624,626,628,630,632,634,636,638,642,644: Steps W: Matrix X: Vector Y: Vector

[0111] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An electro-photonic package comprising: a substrate having an opening defined through the substrate; an application-specific integrated circuit (ASIC) and a photonic integrated circuit (PIC), wherein a first chip between the ASIC and the PIC is disposed in the opening; an interposer layer, wherein the first chip is coupled to a first side of the interposer layer, and a second chip between the ASIC and the PIC is coupled to a second side of the interposer layer opposite to the first side; a heat sink disposed in the opening and in thermal contact with the first chip; and a thermally conductive cap in thermal contact with the second chip, wherein the thermally conductive cap has an optical fiber channel defined through the thermally conductive cap, wherein an optical fiber through the optical fiber channel is configured and edge-coupled to the PIC.

2. The electro-photonic package as claimed in claim 1, wherein the opening is defined from a top surface of one of the substrates to a bottom surface of one of the substrates.

3. The electro-photonic package as described in claim 1, wherein the first chip is the PIC and the second chip is the ASIC, such that the heat sink is in thermal contact with the PIC and the thermal cover is in thermal contact with the ASIC.

4. The electro-photonic package as described in claim 1, wherein the first wafer is at least partially disposed in the opening.

5. The electro-photonic package as claimed in claim 1, wherein the substrate has a top surface and a bottom surface facing the interposer, wherein the electro-photonic package further includes ground grid array (LGA) pads coupled to the bottom surface of the substrate.

6. The electro-photonic package as described in claim 1, wherein the interposer comprises a silicon interposer or an organic interposer.

7. The electro-photonic package as claimed in claim 1, wherein the PIC includes a photonic accelerator configured to perform matrix multiplication in an optical domain, and wherein the ASIC includes a digital controller configured to control the photonic accelerator.

8. The electro-photonic package as described in claim 1, wherein the electro-photonic package has no laser disposed therein.

9. An electrophotonic processor comprising: a plurality of photonic integrated circuits (PICs), each PIC including a photonic accelerator configured to perform matrix multiplication in an optical domain; an application-specific integrated circuit (ASIC) configured to control at least one of the photonic accelerators; an interposer layer wherein the plurality of PICs are coupled to a first side of the interposer layer and the ASIC is coupled to a second side of the interposer layer opposite to the first side; a first thermally conductive member in thermal contact with at least one of the PICs; and a second thermally conductive member in thermal contact with the ASIC, wherein the first thermally conductive member faces the first side of the interposer layer and the second thermally conductive member faces the second side of the interposer layer.

10. The electrophotonic processor of claim 9 further includes a substrate having an opening formed through the substrate, wherein the interposer is mounted on the substrate, and wherein the first thermally conductive member or the second thermally conductive member is disposed in the opening.

11. The electrophotonic processor of claim 10, wherein the substrate has a top surface and a bottom surface facing the interposer, wherein the electrophotonic processor further includes ground grid array (LGA) pads coupled to the bottom surface of the substrate.

12. The electrophotonic processor as claimed in claim 10, wherein the second thermally conductive member is in contact with the substrate.

13. The electrophotonic processor as claimed in claim 9, wherein the interposer comprises a silicon interposer or an organic interposer.

14. The electrophotonic processor as claimed in claim 9 further includes a digital controller configured to control the photonic accelerators to perform matrix multiplication in a block-by-block parallel manner in the optical domain.

15. The electro-photon processor as claimed in claim 9, wherein the photon accelerator includes photon multipliers configured to perform scalar multiplication in the optical domain.

16. The electrophoton processor as claimed in claim 9, wherein the photon accelerator includes photon adders configured to perform scalar addition in the optical domain.

17. The electro-photonic processor as claimed in claim 9, wherein the plurality of PICs, the ASIC, the interposer, the first thermally conductive member, and the second thermally conductive member form a package, and wherein the electro-photonic processor further includes a laser disposed outside the package.

18. The electrophotonic processor as claimed in claim 9, wherein the first thermally conductive member comprises a conductive post.

19. An electro-photonic package comprising: a substrate; a photonic integrated circuit (PIC) supported by the substrate; an interposer partially disposed on the substrate and partially disposed on the PIC; a first set of connections coupled to the interposer to the substrate and a second set of connections coupled to the interposer to the PIC, wherein the first set of connections has a different size relative to the second set of connections; and an application-specific integrated circuit (ASIC) disposed on the interposer.

20. The electro-photonic package as described in claim 19 further includes a thermally conductive cap that is in thermal contact with the ASIC.

21. The electro-photonic package as described in claim 19, wherein the first connection set is a ball grid array (BGA).

22. The electro-photonic package as described in claim 19, wherein the first connection set is greater than the second connection set.

23. The electro-photonic package as claimed in claim 19, wherein the substrate has an opening defined through the substrate, and wherein the PIC is disposed in the opening.

24. A method for manufacturing an electro-photonic package, the method comprising the steps of: obtaining a substrate, an application-specific integrated circuit (ASIC), a photonic integrated circuit (PIC), and an interposer; forming an interposer module by attaching the ASIC to a first side of the interposer and attaching the PIC to a second side of the interposer; attaching the interposer module to the substrate; placing a first thermally conductive member in thermal contact with the ASIC, wherein the first thermally conductive member has an optical fiber channel defined through the first thermally conductive member; placing a second thermally conductive member in thermal contact with the PIC; and edge-coupled the optical fiber to the PIC by passing an optical fiber through the optical fiber channel.

25. The method as described in claim 24 further comprises the steps of: forming a first underfiller on the first side of the interlayer; flipping the interlayer; and, following the flipping, forming a second underfiller on the second side of the interlayer.

26. The method as described in claim 24, wherein the step of placing the second thermally conductive member in thermal contact with the PIC comprises the step of inserting the second thermally conductive member through an opening formed in the substrate.

27. The method of claim 24 further comprises the steps of: flipping the substrate such that the step of placing the first thermally conductive member in thermal contact with the ASIC is performed before the step of flipping the substrate, and the step of placing the second thermally conductive member in thermal contact with the PIC is performed after the step of flipping the substrate.

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