Surface emitting laser, method for fabricating surface emitting laser

Abstract

A vertical-cavity surface-emitting laser includes an oxide substrate having a first surface and a second surface located on the opposite side of the first surface, the second surface including a curved surface; a semiconductor portion disposed on the first surface; a dielectric filter layer disposed between the semiconductor portion and the first surface, and having a reflectance spectrum to provide an optical window; a first dispersed Bragg reflector (DBR) mirror; and a second DBR mirror disposed on the curved surface of the second surface. The first DBR mirror, the semiconductor portion, the dielectric filter layer, the oxide substrate, and the second DBR mirror are arranged upwardly along a first axis to form an extended cavity. The semiconductor portion is disposed between the dielectric filter layer and the first DBR mirror, and includes a p-type III nitride region, an n-type III nitride region, and a III nitride active region located between the p-type and n-type III nitride regions.

Description

[Technical Field]

[0001] This disclosure relates to an extended cavity group III nitride vertical resonant cavity surface-emitting laser (VCSEL) and a method for manufacturing an extended cavity group III nitride VCSEL. [Previous Technology]

[0002] A surface-emitting laser is also known as a vertical cavity surface-emitting laser (VCSEL). A VCSEL includes a semiconductor active region disposed between an n-side semiconductor region and a p-side semiconductor region, and two distributed Bragg reflectors (DBRs) that act as highly reflective mirrors. The semiconductor active region, also known as the gain medium, is disposed between the two DBRs to form an optical cavity. Carriers, namely electrons and holes, are injected into the active region from the n-side and p-side regions, respectively, and these carriers recombine in the active region to generate light. Therefore, the generated light or electromagnetic radiation is reflected many times by these DBRs to travel in the optical cavity, thereby generating laser emission. One of the DBRs in a VCSEL is a low-reflectivity mirror used to emit laser light.

[0003] This application references multiple patent and non-patent publications, indicated throughout the specification by their citation numbers enclosed in brackets (i.e., []). A list of publications arranged according to their citation numbers is provided in the following "Non-patent Literature" or "Patent Literature" sections. [List of Citations] [Non-patent Literature]

[0004] [Non-Patent Literature 1] Appl. Phys. Express 12, 044004 (2019) [Non-Patent Literature 2] Sci. Rep. 8, 10350 (2018) [Non-Patent Literature 3] Applied Phys. Lett. 83, 2121 (2003) [Non-Patent Literature 4] Appl. Phys. Express 2008, 1, 121102. [Non-Patent Literature 5] Appl. Phys. Express 2012, 5, 092104 [Non-Patent Literature 6] Optics Express, 27, 24717 (2019) [Non-Patent Literature 7] Appl. Phys. Express, 13, 041003 (2020) [Non-Patent Literature 8] Appl. Phys. Express, 14,031002 (2021) [Non-Patent Literature 9] Applied Phys. Lett. 119, 142103 (2021) [Non-Patent Literature 10] Crystals, 11 (12) 1563, (2021) [Non-Patent Literature 11] MB Stern and TR Jay, “Dry etching for coherent refractive micro-lens arrays,” Opt. Eng. 33, 3547-3551 (1994) [Summary of the Invention]

[0005] [Technical Problem] When the length of the optical cavity defined by the two DBR mirrors in a VCSEL is increased, excessive diffraction loss occurs. Using curved mirrors or lenses in a VCSEL allows for a longer optical cavity. As shown in Non-Patent Documents 1 and 2, curved mirrors or lenses focus the electric field of the laser beam onto the gain medium to reduce diffraction loss from the longer optical cavity. High-efficiency operation can be achieved by aligning the cavity modes with the gain spectrum in the VCSEL. Using a very short cavity length in a VCSEL, such as one or two laser emission wavelengths, results in a large inter-mode spacing. Due to the larger spacing, it is less likely that at least one cavity mode will fall within the VCSEL's gain spectrum, thus reducing the VCSEL's yield and laser emission efficiency. Conversely, increasing the cavity length narrows the mode spacing. Due to the narrower spacing, it is very likely that at least one cavity mode will fall within the VCSEL's gain spectrum, thus improving the laser emission yield.

[0006] However, in VCSELs with long cavities, the challenge lies in the fact that all device layers, except for the active region, are fabricated using materials that are transparent to electromagnetic radiation propagating within the VCSEL. One of the DBR mirrors can be disposed on the curved back side of the group III nitride semiconductor host substrate, forming a lens structure. Accordingly, VCSELs with this structure do not require substrate removal, resulting in moderate losses within the cavity due to the group III nitride host substrate. This curved mirror method is proposed in Non-Patent Documents 1 and 2, still providing a cavity with a significant portion of the native host substrate, on which a lens structure is formed by etching to fabricate a curved n-side DBR mirror. This method is designed for homo-epitaxy gallium nitride (GaN). In addition, the doping concentration of the host substrate contained within the cavity must be low enough to account for losses such as pin absorption. Furthermore, the host substrate is first thinned to reduce optical absorption losses within the cavity. Thinning the substrate is a process that is more difficult to control in terms of thickness, and the substrate may be damaged because it must be thinned from an initial thickness of 300 to 400 micrometers to a target thickness of 10 to 30 micrometers to provide a VCSEL with the expected cavity length.

[0007] Otherwise, including a main substrate within the cavity could cause unintentional absorption loss of electromagnetic radiation per round trip, thus hindering the reduction of the laser lasing threshold. However, the authors of Non-Patent Document 3 describe the operation of a GaN-based VCSEL in an extended cavity scheme, which is fabricated by directly growing a GaN-based device on a low-absorption sapphire substrate. In this scheme, the lattice mismatch between the sapphire substrate and the device layer still limits the crystal quality of the device layer, and correspondingly, the lifespan and yield of such a device also become problematic.

[0008] Preferably, the absorption source is kept as thin as possible while maintaining stable laser operation, and the bottom mirror must be positioned to form a cavity with upper and lower mirrors that are close to each other, resulting in the removal of the native substrate. In hetero-epitaxy, a group III nitride device layer is grown on a heterogeneous substrate, such as sapphire or silicon. Since hetero-epitaxy of GaN on a sapphire substrate cannot enhance its crystal quality, as described in Non-Patent Document 4, the heterogeneous substrate of the group III nitride VCSEL device can be easily removed by chemical etching or laser lift-off (LLO). However, conventional LLO processes cannot be used for GaN homo-epitaxy. In other ways, the removal of the group III nitride device layer from the GaN homo-epitaxy structure is described in Non-Patent Document 5 and is still widely discussed in Non-Patent Documents 6 to 10.

[0009] The longer the cavity, the better the stability in terms of laser emission and thermal drift. Furthermore, extended cavity VCSEL designs can be achieved by carefully removing the VCSEL device layer from the native growth substrate or a heterogeneous substrate, followed by reconnecting lossless transparent oxide (TO) materials, such as zinc oxide (ZnO) and group III oxides, including aluminum oxide (Al₂O₃) and gallium oxide (Ga₂O₃). This design requires sub-nanometer-level surface preparation for both the TO substrate and the removed device layer, and can also cause potentially unwanted reflections due to the refractive index difference between the GaN / oxide interfaces formed by reconnection. If reflections degrade device performance, unwanted reflections can be suppressed by applying an anti-reflective coating to the interface. These procedures are time-consuming and can lead to additional costs and other problems.

[0010] Considering these drawbacks, the purpose of this disclosure is to provide a structure of a group III VCSEL with extended cavity features and a method for manufacturing a VCSEL with extended cavity features. Another purpose of this disclosure is to provide a single-step integration solution that eliminates the need for complex bonding and substrate removal steps in forming the extended cavity.

[0011] [Solution] This disclosure provides a VCSEL comprising: an oxide substrate having a first surface and a second surface located on the opposite side of the first surface, the second surface including a curved surface; a semiconductor portion disposed on the first surface of the oxide substrate; a dielectric filter layer disposed between the semiconductor portion and the first surface of the oxide substrate and having a reflection spectrum that provides an optical window; a first dispersed Bragg reflector (DBR) mirror, the semiconductor portion being disposed between the dielectric filter layer and the first DBR mirror; and a second DBR mirror disposed on the curved surface of the oxide substrate, the first DBR mirror, the semiconductor portion, the dielectric filter layer, the oxide substrate, and the second DBR mirror being arranged in a first axial direction to form an extended cavity. The semiconductor portion includes a p-type group III nitride region, a group III nitride region, and a group III nitride active region located between the p-type group III nitride region and the group III nitride region. The p-type group III nitride region, the group III nitride active region, and the group III nitride region are arranged along the first axis, and the group III nitride region includes an n-type group III nitride region.

[0012] This disclosure provides a method for manufacturing a vertical-cavity surface-emitting laser. The method includes: preparing an initial substrate, the initial substrate including an oxide substrate, a group III nitride template plug, and a dielectric filter layer. The oxide substrate has a first surface and a second surface located on the opposite side of the first surface of the oxide substrate. The dielectric filter layer and the group III nitride template plug are located on the first surface of the oxide substrate. The dielectric filter layer has a reflection spectrum, and the reflection spectrum provides an optical window; the method involves preparing an initial substrate including an oxide substrate, a group III nitride template plug, and a dielectric filter layer. A group III nitride region is grown using a template plug; after growing the group III nitride region, a semiconductor stack including an n-type group III nitride region, a group III nitride active region, and a p-type group III nitride region is grown; the second surface of the oxide substrate is processed to form an oxide substrate with a curved surface, the curved surface being disposed on the opposite side of the first surface of the oxide substrate; after growing the semiconductor stack, a first DBR stack is formed on the first surface of the oxide substrate; and a second DBR stack is formed on the curved surface of the oxide substrate. [Effects of this disclosure]

[0013] The above invention can provide a structure of a group III VCSEL with extended cavity features and a method for manufacturing a VCSEL with extended cavity features.

Implementation Method

[0015] As used herein, terms such as "first," "second," "third," "fourth," and "fifth" describe various elements, components, regions, layers, and / or parts, which should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Unless the context clearly indicates otherwise, the use of terms such as "first," "second," "third," "fourth," and "fifth" herein does not imply order or sequence.

[0016] Other features, aspects, and advantages of the subject matter of this specification will become apparent from the description, drawings, and claims. A schematic diagram illustrating the vertical cavity surface-emitting laser (VCSEL) disclosed herein and a method for manufacturing the VCSEL will be described in detail below with reference to the drawings. For ease of understanding, the same elements are represented by the same symbols in the drawings.

[0017] FIG1 is a schematic diagram showing the layer structure of a VCSEL according to one embodiment of the present disclosure. FIG2 is a top view showing a VCSEL according to one embodiment of the present disclosure. Specifically, FIG1 shows a cross section along section II of FIG2. FIG1 and FIG2 show a VCSEL 11, which is bonded to a sub-mount 10b by solder bumps 10a on the curved DBR side of the VCSEL 11. In portions (1), (2) and (3) of FIG1, the vertical axis represents reflectivity (R) and the horizontal axis represents wavelength (W).

[0018] The VCSEL 11 includes a first distributed Bragg reflector (DBR) mirror 13, a semiconductor portion 15, a dielectric filter layer 17, a second DBR mirror 19, and an oxide substrate 21. The dielectric filter layer 17 is disposed between the first DBR mirror 13 and the second DBR mirror 19. The oxide substrate 21 has a first surface 21a and a second surface 21b located on the opposite side of the first surface 21a, and the second surface 21b includes a curved surface 21c. The semiconductor portion 15 is disposed on the first surface 21a of the oxide substrate 21 and is located between the first DBR mirror 13 and the dielectric filter layer 17. The first DBR mirror 13, the semiconductor portion 15, the dielectric filter layer 17, the oxide substrate 21, and the second DBR mirror 19 are arranged along a first axis Ax1 to form an extended optical cavity CAV. The first DBR mirror 13 is disposed on the semiconductor portion 15, and the second DBR mirror 19 is disposed on the curved surface 21c of the oxide substrate 21. A dielectric filter layer 17 is disposed in an extended optical cavity CAV formed by a first DBR mirror 13 and a second DBR mirror 19, and has a reflective wavelength region and an optical window WIN defined by the reflective wavelength region, serving as a bandpass filter near wavelength λ0. The optical window WIN allows light beams to travel in the optical cavity CAV at the laser emission wavelength, while the reflective wavelength region can block light of wavelengths other than those of the optical window WIN.

[0019] The semiconductor portion 15 includes a p-type group III nitride region 23, a group III nitride active region 27, and a group III nitride region 29. The group III nitride region 29 includes an n-type group III nitride region 25. The group III nitride active region 27 is disposed between the p-type group III nitride region 23 and the group III nitride region 29 (n-type group III nitride region 25). The p-type group III nitride region 23, the group III nitride active region 27, and the group III nitride region 29 (n-type group III nitride region 25) are arranged along the first axial direction Ax1. In VCSEL 11, Group III nitrides can contain compounds of any nitrogen and Group III elements, such as aluminum, gallium, and indium. Specifically, these can be binary alloys, such as gallium nitride (GaN), aluminum nitride (AlN), and indium nitride (InN); ternary alloys, such as aluminum gallium nitride (GaAlN), aluminum indium nitride (InAlN), and indium gallium nitride (InGaN); and quaternary alloys, such as indium gallium aluminum nitride (InGaAlN). These alloys may contain any trace impurities. Group III nitrides can be doped with p-type dopants, such as magnesium, carbon, and beryllium, to form p-type regions, or with n-type dopants, such as silicon and tellurium, to form n-type regions. Group III nitrides can also be doped with both p-type and n-type dopants.

[0020] The oxide substrate 21 includes one or more oxide materials, specifically, one of aluminum oxide (e.g., Al₂O₃, with a band ratio of approximately 8.8 electron volts (eV)), zinc oxide (e.g., ZnO, with a band ratio of approximately 3.37 eV), or gallium oxide (e.g., Ga₂O₃, with a band ratio of approximately 4.6 to 4.7 eV). These oxide materials, such as aluminum oxide, zinc oxide, and gallium oxide, are transparent to visible, infrared, or ultraviolet wavelengths of light, allowing light to pass through the oxide substrate 21.

[0021] The VCSEL 11 further includes a Group III nitride template plug 18, which extends from the first surface 21a of the oxide substrate 21 to the semiconductor portion 15 within a via 17a included in the dielectric filter layer 17. The via 17a extends along a first axial direction Ax1. The Group III nitride template plug 18 has an embedded portion 18a (also shown in FIG. 3D) and a protrusion 18b (also shown in FIG. 3D). The embedded portion is located in the via 17a and is positioned to contact the first surface 21a of the oxide substrate 21. The protrusion protrudes into the semiconductor portion 15.

[0022] As shown in Figure 1, the curved surface 21c of the oxide substrate 21 has a center line CNT, and the group III nitride template plug 18 and the center line CNT of the curved surface 21c are misaligned with each other.

[0023] The dielectric filter layer 17 has a reflection spectrum R3 and is configured to provide an optical window WIN, as shown in part (2) of FIG1. ​​Referring to FIG1, the dielectric filter layer 17 includes, specifically, a plurality of dielectric layers 30 disposed on the oxide substrate 21, and the dielectric layers 30 are configured to form a Fabry-Perot filter that can provide a reflection spectrum R3 with an optical window WIN.

[0024] The first DBR mirror 13 has a reflection spectrum R1, as shown in part (1) of Figure 1. The second DBR mirror 19 has a reflection spectrum R2, as shown in part (3) of Figure 1. The reflection spectra R1 and R2 each have a reflection wavelength bandwidth including wavelength λ0.

[0025] The order of magnitude of the reflectance spectra R1, R2 and R3 is as follows: the reflectance values ​​of each of the reflectance spectra R1 and R2 are much greater than the reflectance value of the reflectance spectrum R3; and the reflectance value of the reflectance spectrum R2 can be greater than the reflectance value of the reflectance spectrum R1.

[0026] The group III nitride active region 27 has a quantum well structure to generate light with wavelengths at the first reflection spectrum R1, the second reflection spectrum R2, and the optical window WIN of the dielectric filter layer 17. The laser light can be emitted through, for example, a first DBR mirror 13 having a reflectivity lower than that of the second DBR mirror 19.

[0027] Specifically, the first DBR mirror 13 includes a first dielectric layer 13a and a second dielectric layer 13b, which are alternately disposed along the first axis Ax1 to serve as, for example, a top mirror. The second DBR mirror 19 includes a third dielectric layer 19a and a fourth dielectric layer 19b, which are alternately disposed along the first axis Ax1 to serve as, for example, a bottom mirror. The dielectric filter layer 17 extends between the semiconductor portion 15 and the first surface 21a of the oxide substrate 21.

[0028] In VCSEL 11, the length of the extended optical cavity CAV can be greater than 50 micrometers (> 50 micrometers). The curved surface 21c has a radius of curvature greater than 50 micrometers (> 50 micrometers).

[0029] In VCSEL 11, the first DBR mirror is planar, while the second DBR mirror is curved, and the distance between the first DBR mirror 13 and the second DBR mirror 19 can be 50 micrometers or more. The semiconductor portion 15 can have a thickness of about 0.5 micrometers or more.

[0030] The VCSEL 11 further includes a conductive layer 35 disposed on the semiconductor portion 15. The conductive layer 35 may include any one or both of a group III nitride semiconductor (such as n-type GaN) or a conductive inorganic material (such as indium tin oxide (ITO)). A portion of the conductive layer 35 is disposed between the first DBR mirror 13 and the semiconductor portion 15.

[0031] In the VCSEL 11, the semiconductor portion 15 has an aperture structure 39 to confine electrical carriers and laser beams. If desired, the semiconductor portion 15 may further include a tunneling structure on its uppermost layer, replacing or replacing the aperture structure 39. The tunneling structure alters the type of conductivity, i.e., from one electron or hole to the other. The tunneling structure can be either a tunneling junction or an embedded tunneling junction. A tunneling junction can utilize the aperture structure 39 to confine the carrier path, while an embedded tunneling junction may not require the aperture structure 39 to confine the carrier path.

[0032] Referring to Figures 1 and 2, the semiconductor portion 15 has a mesa structure 37. The mesa structure 37 includes a base region 37a and a mesa region 37b disposed on the base region 37a. The mesa region 37b also has a portion of a p-type group III nitride region 23, a group III nitride active region 27, and a portion of an n-type group III nitride region 25. The base region 37a includes the remaining portion of the n-type group III nitride region 25, and at the bottom of the mesa region 37b, the mesa region 37b is surrounded by the n-type group III nitride front 25a located at the top of the base region 37a.

[0033] The VCSEL 11 further includes a first electrode 31, such as an anode electrode, on the mesa region 37b, and a second electrode 33, such as a cathode electrode, on the outside of the mesa region 37b. In one embodiment of the VCSEL 11, the anode electrode is disposed in contact with the ITO or an extended semiconductor layer, while the cathode electrode is disposed in contact with the top surface 25a of the n-type III nitride region 25 of the base region 37a. The first electrode 31 is disposed on the semiconductor portion 15 outside the conductive layer 35 or the first DBR mirror 13, and may be in contact with the conductive layer 35 or the semiconductor portion 15. The cathode electrode 33 may be disposed on the n-type III nitride front surface 37c (25a) of the base region 37a outside the mesa region 37b.

[0034] In the VCSEL 11 including the conductive layer 31, the semiconductor portion 15 has a first surface 15a and a second surface 15b located on the opposite side of the first surface 15a. The dielectric filter layer 17 is disposed in contact with the first surface 15a of the semiconductor portion 15, and the conductive layer 35 is disposed in contact with the second surface 15b.

[0035] Referring to Figure 1, which shows an outline of VCSEL 11, VCSEL 11 has two highly reflective DBR mirrors 13 and 19, one of which is disposed on a curved surface of oxide substrate 21. Oxide substrate 21 separates the two DBR mirrors 13 and 19 from each other to allow the extended optical cavity to be integrated in a single step. According to the fabrication of VCSEL 11, the semiconductor portion 15 is grown along dielectric filter layer 17 from group III nitride template plug 18 by epitaxial lateral overgrowth (ELO) and the dielectric filter layer 17 may have a Fabry-Perot multilayer film, which allows for both a narrow bandpass and a large optical suppression region outside the narrow bandpass at the wavelength. The reflectivity of dielectric filter layer 17 is designed to be very small at laser wavelengths compared to the reflectivity of DBR mirrors 13 and 19.

[0036] The DBR mirrors 13 and 19, separated by the oxide substrate 21, form an extended cavity. The larger this cavity is, the smaller the spacing between the longitudinal modes of the extended cavity becomes. This very small spacing allows at least one of the longitudinal modes to easily fall within the narrow bandpass window WIN of the dielectric filter layer 17. Conversely, the DBR mirror 13 and the dielectric filter layer 17, separated by the semiconductor portion 15, may form a parasitic cavity. The shorter this cavity is, the larger the spacing between the longitudinal modes of the parasitic cavity becomes. This large spacing allows most or all of the longitudinal modes of the parasitic cavity to easily fall outside the narrow bandpass window WIN. All of the longitudinal modes of the parasitic cavity are very likely to fall outside the narrow bandpass window WIN. The narrow bandpass window of the dielectric filter layer 17, combined with the wider reflection wavelength range of the highly reflective DBR mirrors 13 and 19, demonstrates the extended optical cavity. The active region, i.e., the gain medium, can be aligned with DBR mirrors 13 and 19, thereby suppressing the field maximum of the wide-segmented longitudinal modes, which will be misaligned with the position of the gain medium. Although the VCSEL 11 includes multiple cavities, at least one single longitudinal mode of the extended cavity within the narrow bandpass window WIN is selected, and the light of the selected mode within the narrow bandpass window WIN can travel between the flat and curved mirrors within the extended cavity to emit light. Accordingly, a small mode spacing makes the alignment of the selected modes and gain spectrum less complex, and a long cavity also makes the alignment of the selected modes and gain medium less complex.

[0037] The VCSEL 11 has a curved mirror on an oxide substrate 21, and a dielectric filter layer 17 (such as a Fabry-Perot filter) is embedded between the flat and curved mirrors of the VCSEL 11. The curved mirror can reflect incident electromagnetic radiation back to the gain medium with a reflectivity of nearly 90% by refocusing, thereby providing an extended optical cavity for the VCSEL 11 with lower diffraction loss. In addition, the oxide substrate 21 is made of a transparent oxide (TO) material, including ZnO, Ga₂O₃, or Al₂O₃, and the transparent oxide material and the curved mirror can make the optical absorption within it negligible, thereby achieving lossless optical transmission within the substantial portion of the optical cavity of the VCSEL 11. The device structure disclosed herein can achieve a long cavity and better thermal performance within the VCSEL 11.

[0038] Referring to FIG. 1, the VCSEL 11 has a curved DBR mirror disposed on the back side of the substrate 21 as a bottom mirror. According to the manufacturing of the VCSEL 11, the curved DBR mirror is designed to be integrated into a simple manufacturing step, such as forming a patterned dielectric layer along the curved back side of the substrate 21, i.e., the DBR mirror 19. The VCSEL 11 also has a planar DBR mirror located on the front side of the substrate 21 as an upper mirror. According to the manufacturing of the VCSEL 11, the planar DBR mirror is designed to be integrated into a simple manufacturing step, such as forming a patterned dielectric layer along the plane of the semiconductor portion 15 as an upper mirror, i.e., the DBR mirror 13. The planar DBR mirror 13 and the curved DBR mirror 19 form an extended cavity with a dielectric filter layer 17 embedded therebetween. The dielectric filter layer 17 preferably includes an anti-reflective coating or a Fabry-Perot structure (containing dielectric material) to exhibit narrow bandpass characteristics near the desired wavelength. It also reflects light at optical wavelengths outside the bandpass wavelength. According to the manufacturing of VCSEL 11, the semiconductor portion 15, formed by epitaxial elongation lateral growth (ELO), grows from a template plug 18 that can be deposited and etched onto an oxide substrate 21. The semiconductor portion 15 includes a light-generating structure having a p-type III nitride region 23, an n-type III nitride region 25 (a group III nitride region 29), and an active III nitride region 27 between the p-type III nitride region 23 and the n-type III nitride region 25.

[0039] The dielectric filter layer 17 is preferably a Fabry-Perot structure, entirely composed of dielectric material. According to the fabrication of the VCSEL 11, the dielectric filter layer 17 can function as an ELO mask, allowing group III nitrides to be epitaxially extended from the group III nitride template plug 18 to avoid group III nitride deposition thereon, and function on the oxide substrate 21 as a support structure for group III nitrides grown via ELO. For the ELO deposition of group III nitrides in the semiconductor portion 15, a portion of the dielectric filter layer 17 is embedded. Therefore, the laminated filter layer 17 (with an ELO mask structure) is designed to provide a simple step-by-step integration of the thin semiconductor portion 15 on the TO substrate 21 without the need for substrate removal and bonding. This filter layer 17 has the optical characteristics of providing both a narrow bandpass (allowing laser emission in the main optical cavity mode) and a rejection band (preventing parasitic laser emission in one or more modes of the optical cavity).

[0040] The VCSEL 11 has a first DBR mirror 13 on the semiconductor portion 15, which extends over the filter layer 17. The first DBR mirror 13 has a first dielectric layer 13a and a second dielectric layer 13b alternately disposed along the first axis Ax1, and the material of the first dielectric layer 13a is different from that of the second dielectric layer 13b.

[0041] The VCSEL 11 has a second DBR mirror 19, which is separated from the first DBR mirror 13 by a semiconductor portion 15 and an oxide substrate 21. The second DBR mirror 19 includes a third dielectric layer 19a and a fourth dielectric layer 19b alternately disposed along the first axis Ax1, and the material of the third dielectric layer 19a is different from that of the fourth dielectric layer 19b.

[0042] The VCSEL 11 further includes an omnidirectional reflector (ODR) layer 40. The omnidirectional reflector layer 40 covers the semiconductor portion 15 and the dielectric filter layer 17 to reflect stray light of the laser emission wavelength outward, thereby preventing stray light from interfering with the laser emission within the cavity. The omnidirectional reflector layer 40 also functions as a passivation layer between the cathode 33 and the anode 31.

[0043] The cavity CAV has a total cavity length, which can be defined as the distance between the curved surface 21c and the substantially flat surface disposed in contact with the first DBR mirror 19. In one embodiment of the VCSEL 11, the distance between the curved surface 21c and the flat top surface 21a of the TO substrate 21 can be 50 to 1000 micrometers, serving as an extension cavity, and the thickness of the semiconductor portion 15 is approximately 0.5 to 4 micrometers, also serving as an extension cavity.

[0044] The semiconductor portion 15 has an aperture structure 39. The aperture structure 39 has a conductive aperture portion 39a and a low-conductivity portion 39b surrounding the conductive aperture portion 39a. The conductive aperture portion 39a provides an electrical path for the VCSEL 11 to be formed between the anode electrode 31 and the cathode electrode 33. Carriers (such as electrons and holes) flow through the electrical path and recombine in the group III nitride active region 27 to generate light, which is emitted from one of the DBR mirrors (e.g., the first DBR mirror 13). The conductive aperture portion 39a is configured to be laterally away from the stencil plug 18 to reduce optical interference that may be caused by the stencil plug 18. Preferably, the conductive aperture portion 39a is separated from the sidewall of the stencil plug 18 by at least about 3 micrometers, as measured along the dielectric filter layer 17. The extended cavity, whose main portion is composed of the oxide substrate 21, should be spatially designed so that the stencil plug 18 is located outside the main portion of the cone relative to the curved DBR mirror 19.

[0045] Referring to Figure 2, the Group III nitride template plug 18, the curved surface 21c, and the aperture structure 39 are indicated by dashed lines. In addition to the first axis Ax1, the second axis Ax2 and the third axis Ax3 are also indicated, and the three axes are perpendicular to each other. For example, the conductive aperture portion 39a is asymmetrically arranged relative to the linear template plug 18. This asymmetrical design facilitates the configuration of the anode and cathode electrodes on the front side and the curved DBR mirror 19 on the back side. The semiconductor portion 15 is grown outwards from the exposed sidewalls and top surface of the Group III nitride template plug 18 onto the dielectric filter layer. This formation allows the Group III nitride template plug 18 to connect the semiconductor portion 15 to the TO substrate 21, and the template plug 18 forms a Group III nitride thermal path, allowing the active region 27 to dissipate heat to the oxide substrate 21. This structure provides a thermal path for the VCSEL 11, ensuring that heat can be dissipated through the template plug 18 via the TO substrate 21 with better thermal conductivity.

[0046] The method for manufacturing a VCSEL according to this embodiment will be described below with reference to Figures 3A to 3R. Figures 3A to 3R are cross-sectional views showing the process steps in the manufacturing method, and the cross-section is along line II shown in Figure 2. To avoid repetition of the following description, the symbols already used in Figures 1 and 2 will be used in the following description. In the following description, Group III nitrides can be deposited by, for example, metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0047] Referring to FIG3A, an oxide wafer 41 for an oxide substrate 21 related to VCSEL 11 is prepared, which includes a transparent material such as ZnO, Ga2O3, Al2O3, and then a group III nitride film 43, such as gallium nitride (GaN), is deposited on the top surface of the oxide wafer 41.

[0048] Referring to FIG. 3B, a photoresist mask 45 is formed on a group III nitride film 43, and the group III nitride film 43 together with the mask 45 is etched to form one or more group III nitride template plugs 18, each group III nitride template plug 18 having a width "W" and a height "H". Each group III nitride template plug 18 comprises a single-crystal group III nitride with a very low defect density. For example, the group III nitride template plugs 18 may extend linearly along the top surface of the oxide wafer 41 and may be arranged parallel to each other at a spacing "P".

[0049] Referring to FIG. 3C, a dielectric multilayer film 47 is deposited on an oxide wafer 41 and on a group III nitride template plug 18. The dielectric multilayer film 47 has a thickness less than the height of the group III nitride template plug 18 and the thickness of the group III nitride film 43, and has a structure that can form a Fabry-Perot filter.

[0050] The dielectric multilayer film 47 of one embodiment of the Fabry-Perot structure has the following exemplary layer structure: "(HL)m2nH(LH)m", where "H" and "L" represent layers with high and low refractive indices, respectively, each having a quarter-wave optical thickness, and "m" and "n" are integers. Specifically, "(HL)m" represents the alternation of high-refractive-index layers and low-refractive-index layers m times; "2nH" represents the thickness of the high-refractive-index layer 2n times; and "(LH)m" represents the alternation of low-refractive-index layers and high-refractive-index layers m times. By designing the Fabry-Perot spectrum (R3) based on the refractive index and layer thickness of the dielectric material, a high-transmission optical window can be achieved at the central wavelength λ0, and high-reflection spectral regions can be achieved on both sides of the high-transmission optical window.

[0051] Referring to FIG. 3D, the dielectric filter layer 17 is fabricated by etching the dielectric multilayer film 47. During the etching process, a mask (not shown) can be used, which is formed on the dielectric multilayer film 47 and has openings in the group III nitride template plugs 18. Each group III nitride template plug 18 is located in the corresponding opening of the subsequently formed dielectric filter layer 17 and has a lower portion and an upper portion. The lower portion 18a of the group III nitride template plug 18 is embedded in the opening of the dielectric filter layer 17, while the upper portion 18b of the group III nitride template plug 18 protrudes from the top surface of the dielectric filter layer 17.

[0052] In the process of obtaining the intermediate product shown in FIG. 3D, an initial substrate 51 has been prepared, which has an oxide substrate as an oxide wafer 41, a group III nitride template plug 18, and a dielectric filter layer 17. The oxide wafer 41 has a first surface 41a and a second surface 41b located on the opposite side of the first surface 41a. The dielectric filter layer 17 and the group III nitride template plug 18 are disposed on the first surface 41a. The reflectance spectrum (R3) of the dielectric filter layer 17 extending along the first surface 41a is used to provide an optical window (WIN). Light travels through an extended optical cavity between the flat and curved DBR mirrors 13 and 19 to pass through the dielectric Fabry-Perot filter twice in each optical round trip. The dielectric filter layer 17 has a Fabry-Perot filter structure to provide a narrow bandpass and rejection bands on both sides of the narrow bandpass. Depending on the requirements, a dielectric multilayer film 47 can be deposited and then patterned to form periodically arranged strip openings on the first surface 41a of the oxide wafer 41, and group III nitrides can be selectively grown on the strip openings to form group III nitride template plugs 18.

[0053] Referring to FIG. 3E, after forming an initial substrate 51 comprising a dielectric filter layer 17 and a group III nitride template plug 18, group III nitride regions 52 are epitaxially grown from the group III nitride template plug 18 along the dielectric filter layer 17 onto the initial substrate 51. The group III nitride regions 52 are grown from the sides and top edges of the group III nitride template plug 18 by ELO to form wing-shaped group III nitride islands, and adjacent group III nitride regions 52 are isolated from each other. The group III nitride islands are formed from the template plug 18 by depositing group III nitride material by ELO, and dicing streets "D" are defined between adjacent group III nitride islands. The dicing street "D" also defines a single VCSEL portion, related to the VCSEL wafer. The group III nitride regions 52 may be partially or completely doped with n-type dopants and extend outward from the template plug 18.

[0054] Referring to FIG3F, depending on the requirements, before the semiconductor stack after growth, the group III nitride region 52 can be planarized by at least one of grinding or etching to form a group III nitride region 53 having a flat top surface 53a.

[0055] Referring to Figure 3G, after growing the group III nitride region 53, an epitaxial semiconductor stack 55 including a group III nitride device layer is grown. The group III nitride device layer has an n-type group III nitride region 25, a group III nitride active region 27, and a p-type group III nitride region 23. Specifically, the n-type group III nitride region 25, the group III nitride active region 27, and the p-type group III nitride region 23 are grown sequentially on the flat surface of the group III nitride region 53.

[0056] Specifically, the nitride region 25 may include GaN or AlN-based materials doped with n-type dopant, which can provide electrons to the group III nitride active region 27, while the p-type group III nitride region 23 may include GaN or AlN-based materials doped with p-type dopant, which can provide holes to the group III nitride active region 27. The group III nitride active region 27 may include GaN or AlN-based materials, such as GaN, InGaN, AlN, AlGaN, or AlInGaN. The group III nitride active region 27 may have a single-well layer or quantum well structure, such as a single quantum well (SQW) or multiple quantum wells (MQWs). Depending on the requirements, an embedded tunneling interface or tunneling interface layer may be grown after depositing the p-type group III nitride region 23.

[0057] Referring to FIG. 3H, after growing the semiconductor stack 55, the oxide wafer 41 is processed on the second side 41b to form a curved surface 41c and a newly fabricated back side 41d derived from the second side 41b. The second side 41b may be a polished surface if desired. Specifically, the curved surface 41c of the oxide wafer 41 serves as a microlens 45a. The curved surface 41c of the oxide wafer 41 has a central axis CNT, and as shown in FIG. 3H, the group III nitride template plug 18 and the central axis CNT of the curved surface 41c are not aligned with each other. The oxide wafer 41 (such as a sapphire wafer) is processed on its polished surface to fabricate the curved surface 41c, such as the microlens 45a and the back side 41d. The curved surface 41c can be positioned at a predefined, calibrated location so that the focal length of the microlens 45a can be used to determine the location of the aperture structure that confines the carriers. The aperture structure will be described in detail below.

[0058] Referring to Figures 3H to 3J, the curved surface 41c, which functions like a microlens, can be manufactured using a thermal reflow technique, as described in Non-Patent Document 11. Specifically, as shown in Figure 3I, a photoresist film can be formed on the back side of the oxide wafer 41, and a patterned photoresist 57, such as a photoresist microdisk 45a, can be formed using a standard lithography process. Next, as shown in Figure 3J, the patterned photoresist 57 is subjected to heat treatment at high temperature, for example using a hot plate. The high-temperature heat treatment deforms the patterned photoresist 57 into a lens shape, which can be used as a sacrificial photoresist mask 58. Further, as shown in Figure 3H, the lens-shaped photoresist 58 and the back side 41b of the oxide wafer 41 can be processed by reactive ion etching (RIE), thus transferring the shape of the lens-shaped photoresist 58 to the oxide wafer 41. Specifically, the oxide wafer 41 is thinned, while the curved surface 41c (such as the microlens 45a) is retained on the back side 41d of the thinned oxide wafer (hereinafter referred to as oxide substrate 42). Thinning the oxide wafer 41 allows for adjustment of the length of the extended optical cavity. Therefore, this process can not only form the curved surface 41c but also adjust the cavity length.

[0059] Referring to FIG3K, a photoresist film 59 is formed on the front surface of the oxide substrate 42 to cover the semiconductor stack 55 and the dielectric filter layer 17. Next, the curved surface 41c of the back surface 41d of the oxide substrate 42 is irradiated by an exposure light 60 through a photomask 56. The exposure light 60 passes through the curved surface 41c and is focused on a point, such as a portion of the photoresist film 59 covering the top surface of the semiconductor stack 55, thereby forming the exposed portion 59a of the photoresist film 59.

[0060] Referring to FIG. 3L, the development of the exposed photoresist film 59 forms a photoresist mask 61 with patterned openings 61a. Next, a film 63 is deposited on the photoresist mask 61 and within the patterned openings 61a, and the removal of the photoresist mask 61 leaves a mask 64 made of the film 63. The film 63 may be made of Ti / Au or a dielectric layer.

[0061] Referring to Figure 3M, the fabrication of the VCSEL 11 excluding the embedded tunneling interface requires the formation of an aperture structure 65. Specifically, a mask 64 is used for ion implantation to form the aperture structure 65. The formed aperture structure 65 includes an aperture region 65a and an isolation region 65b surrounding the aperture region 65a. The aperture structure 65 can be fabricated on the semiconductor stack 55 by implanting ions (such as hydrogen atoms, n-type dopant atoms, and / or p-type dopant atoms) onto the semiconductor stack 55 in conjunction with the mask 64. The aperture structure 65 has a semiconductor aperture region 65a (which forms an electrical path for carrier flow) and an isolation region 65b (which restricts light and carriers from entering the semiconductor aperture region 65a). After ion implantation, the mask 64 is removed.

[0062] On the other hand, the fabrication of the VCSEL 11 with embedded tunneling junctions in the semiconductor stack 55 requires patterning the tunneling layers that the semiconductor stack 55 may include, such as p++GaN and n++GaN. Specifically, the tunneling layers may be etched in conjunction with a mask 64 to form embedded tunneling junctions. After etching, the mask 64 is removed, and then group III nitride regrowth is performed to deposit a doped semiconductor layer covering the embedded tunneling junctions as a current dissipation layer.

[0063] Referring to FIG. 3N, after removing mask 64 in the fabrication of the VCSEL 11 excluding the embedded tunneling interface, a conductive layer 67 is deposited on the semiconductor stack 55 to cover the semiconductor aperture region 65a and the isolation region 65b. The conductive layer 67 may include a heavily doped group III nitride semiconductor layer (such as GaN or AlGaN) and / or an inorganic layer (such as indium tin oxide (ITO)) and is transparent to light from the group III nitride active region 27. For example, the conductive layer 67 may be deposited on the oxide substrate 42 without a mask.

[0064] Referring to FIG30, a mesa structure 69 is fabricated from the semiconductor stack 55. Specifically, photoresist is formed on an oxide substrate 42a to cover the semiconductor stack 55, and then patterned to form a photoresist mask 71. The photoresist mask 71 is used to expose the n-type GaN region of the underlying semiconductor stack 55 by etching, thereby forming a mesa structure 69 including a group III nitride active region 27 and a p-type group III nitride region 23. On the outside of the mesa structure 69, an etched surface 69a of the n-type group III nitride region is fabricated from the semiconductor stack 55.

[0065] Referring to Figures 3P and 3Q, after the mesa structure 69 is formed and the photoresist mask 71 remains on the oxide substrate 42, an omnidirectional reflector (ODR) layer 73 is formed by depositing an omnidirectional reflective film 73 on the oxide substrate 42 and the photoresist mask 71. Then, the photoresist mask 71 is removed, i.e., by stripping. As shown in Figure 3P, the formed ODR layer 73 covers the sides of the mesa structure 69 and the top of the dielectric filter layer 17, and has an opening at the top of the mesa structure 69. The ODR layer 73 acts as a reflector for stray light of the laser wavelength of the VCSEL 11, and also as a passivation layer between the anode and cathode electrodes formed in subsequent steps.

[0066] Referring again to Figure 3Q, after the ODR layer 73 is formed, the first r (DBR) stack 75 and the first electrode 77 are formed on the conductive layer 67 by peeling, and the second electrode 79 is formed on the etched surface 69a of the n-type III nitride region 25 located outside the mesa structure 69 by peeling.

[0067] Specifically, the first DBR stack 75 can be formed by peeling and aligned with the aperture structure 65 or embedded in the tunneling interface. A first electrode 77, such as an anode electrode, can be located outside the first DBR stack 75 and is disposed in contact with the conductive layer 67 or the regrown semiconductor layer. A second electrode 79, such as a cathode electrode, can be located outside the mesa structure 69 after the ODR layer 73 is patterned to form an opening in the ODR layer 73. The opening in the ODR layer 73 allows the second electrode 79 to be disposed in contact with the etched n-type group III nitride surface 69a of the group III nitride region 25.

[0068] Referring to FIG3R, a second DBR mirror area layer 81 is formed on the curved surface 41c of the oxide substrate 42. If required, the second DBR mirror area layer 81 is patterned to expose a portion of the back surface 41d of the oxide substrate 42, and then bonding material, such as solder balls, may be formed on the exposed back surface 41d of the oxide substrate 42.

[0069] These procedures complete the VCSEL, such as VCSEL 11. This structure allows the manufactured VCSEL 11 to be bonded to the base on the bent DBR side using solder bumps.

[0070] Figure 4A is a schematic diagram showing the wafer portion including the template plug 18, the curved surface 41c as a lens structure, and the aperture structure 65 within the mesa structure 69. Figure 4B is a plan view of two wafers on the oxide substrate 42 using the above-described manufacturing process.

[0071] In the above manufacturing method, the manufactured oxide substrate is separated into VCSEL wafers by a separation process (such as dicing and / or etching). It should be noted that the oxide substrate here has a mesa structure and a dicing pattern located between adjacent mesa structures. The dicing pattern of the manufactured product disclosed herein does not include semiconductor structures. An omnidirectional filter layer covers the top surface of the oxide substrate, except for the top of the mesa structure, and can be removed at the dicing pattern by photolithography and etching as needed. Since the second DBR layer can be patterned to be located on and around the curved surface 41c, no material covers the dicing pattern located on the back side of the oxide substrate.

[0072] In the manufactured VCSEL 11, the length of the extended optical cavity CAV can be greater than 50 micrometers (>50 micrometers). The curved surface 41c has a radius of curvature greater than 50 micrometers (>50 micrometers).

[0073] In VCSEL 11, the first DBR mirror 13 is planar, while the second DBR mirror 19 is curved, and the distance between the first DBR mirror 13 and the second DBR mirror 19 is 50 micrometers or more. The semiconductor portion 15 has a thickness of 0.5 micrometers or more.

[0074] In Figures 4A and 4B, the hemispherical circle 44 is used to represent a virtual sphere extending along the curved surface 41c. For example, when the radius of curvature R0 of the curved mirror 21c is about 100 micrometers, the hemispherical circle 44 has a diameter "DIA" of 200 micrometers on the top surface 21a.

[0075] The spacing between adjacent stencil plugs 18 is related to the fill rate, which represents the ratio of the total area of ​​the device portion on a single wafer to the top area of ​​the wafer. The dicing lines define the configuration of the wafer regions, each prepared for a single VCSEL device. The stencil plugs 18 can be periodically configured in one direction, either as long microstrip lines spanning the entire wafer, or as interrupted microstrip lines longitudinally within a single wafer dimension, or as interrupted stripes configured in a checkerboard pattern, and, depending on requirements, partially staggered at the endpoints to achieve growth advantages, i.e., reducing edge effects.

[0076] The configuration of the template plug 18 is related to the position of the cutting path. The semiconductor portion growing from the template plug cannot be made large due to the ELO, and the ELO of the semiconductor portion is terminated before reaching the adjacent one.

[0077] Preferably, the semiconductor portion should have a size wider than the size of the aperture portion of the aperture structure design, and smaller than the size of the period of the configuration of the template plug 18.

[0078] Preferably, the dicing path should exclude the group III nitride material being diced. Dicing of the oxide substrate can be performed in the dicing path by means of a dicing blade, laser scribing, and / or plasma etching. One advantage of not having group III nitride material in the dicing path is to avoid wasting semiconductor layers.

[0079] The conductive aperture portion of the aperture structure can be positioned near the edge of the wing-shaped semiconductor island that grows outward from the stencil plug via ELO. An advantage of this device is that it accommodates an electrical pad on the wafer surface, reducing potential crystal defects or irregularities that may exist near the stencil plug. Another advantage of this device is that it separates the aperture structure from the reference plane that extends vertically from the center of the stencil plug to the top surface of the oxide substrate, thereby eliminating optical losses.

[0080] Narrower dicing allows for the placement of more device components on a single wafer.

[0081] Figures 5 to 7 are schematic diagrams illustrating configuration embodiments of the device portions on a TO substrate. Referring to Figures 5 to 7, a general configuration of the device portions on a TO substrate is shown. The device portions are configured to form a two-dimensional array, and cleaving lines D are provided to define the array. In Figures 5 and 6, the hemispherical circles 44 are separated from each other. In Figure 7, the hemispherical circles 44 partially overlap, while the curved surfaces 21c are separated from each other. The boundaries of the device portions 46 are indicated by dashed lines.

[0082] Those skilled in the art to which this disclosure pertains can understand different variations of the above configuration, such as more commonly used and less commonly used versions of the configuration of the VCSEL device portion.

[0083] Figure 8 is a schematic diagram showing one embodiment of the VCSEL disclosed herein. The VCSEL 11 has a conductive layer 35 and an aperture structure 39 that confines carriers and laser beams. The conductive layer 35 forms an electrical path from the first electrode 31 (located adjacent to the first DBR mirror 13) to the conductive aperture portion 39a of the aperture structure 39 (located directly below the first DBR mirror 13 and aligned with the cavity).

[0084] The following describes an embodiment of a method for manufacturing a VCSEL 11, which includes a conductive layer that functions as a current dissipation layer.

[0085] The method includes the following steps. 1. Prepare the initial substrate. The initial substrate preparation includes forming GaN template plugs that are straight along a second axis Ax2 perpendicular to the first axis Ax1 on the TO wafer; and forming a dielectric Fabry-Perot filter structure on the entire TO wafer, with the sidewalls of the template plugs partially exposed and the top surface of the template plugs fully exposed; 2. Growing a non-deliberately doped GaN layer (n-GaN) along the top surface of the Fabry-Perot filter structure from the exposed GaN template plugs to form a semiconductor substrate region with a total width of approximately 30 to 50 micrometers along a third axis Ax3 perpendicular to the first and second axes Ax1 and Ax2 using ELO; 3. Planarizing the semiconductor substrate region to form a planarized n-GaN layer; 4. Growing semiconductor layers on the planarized n-GaN layer, including device layers, such as n-GaN for encapsulation and n-contacts, InGaN multiple quantum wells, AlGaN electron blocking layers, and p-GaN layers, and depending on requirements, p-GaN layers are also grown. 1. ++GaN layer; 2. Grind the back side of the TO wafer; 3. Transfer the photoresist pattern formed by reflow to the back side of the TO wafer using reactive ion etching to form a monolithic microlens; 4. Fabricate a photoresist mask from the photoresist film covering the device layer using back-side exposure, in which the monolithic microlens is used to focus the exposure light at a focal point located near the photoresist film; 5. Form a mask on the device layer using the photoresist mask; 6. Perform ion implantation using the mask to define the aperture structure; 7. Deposit transparent conductive oxide (TCO); 8. Fabricate a mesa structure within the semiconductor stack; 9. Deposit a passivation layer of omnidirectional reflector (ODR) material with an opening at the top of the mesa structure; 10. Deposit a dielectric dispersed Bragg reflector stack on the flat top of the device layer of the mesa structure; 11. Deposit electrode metal pads on the semiconductor stack including the mesa structure. 15. Deposit dielectric distributed Bragg reflectors onto the curved surface of the TO substrate; 16. Apply bonding material to the back side of the TO substrate; 17. Separate the manufactured TO wafer to form a VCSEL wafer; 18. Bond the VCSEL wafer to the substrate.

[0086] VCSEL chips can be used in user-defined applications, such as light sources, sensors, or both.

[0087] Figure 9 is a schematic diagram of another embodiment of the VCSEL disclosed herein. The VCSEL 11a has a tunneling junction structure 36 and an aperture structure 39. The tunneling junction structure 36 forms an electrical path from the first electrode 31 (located adjacent to the first DBR mirror 13) to the conductive aperture portion 39a (located directly below the first DBR mirror 13 and confining carriers and laser beams). The tunneling junction structure 36 includes a p++III group nitride layer 36a within the aperture structure 39 and an n++III group nitride layer 36b on the mesa structure 36, and the p++III group nitride layer 36a and the n++III group nitride layer 36a are in contact with each other to form a tunneling junction. The tunneling junction is embedded by an additional group III nitride layer 36c.

[0088] An embodiment of the process of manufacturing VCSEL 11a will be described below. VCSEL 11a includes a heavily doped n++ layer and an n-type semiconductor layer as a current dissipation layer. The n++ semiconductor layer is in contact with the uppermost p++ semiconductor layer to form a tunneling interface 36.

[0089] The method includes the following steps. 1. Prepare the initial substrate. The initial substrate preparation includes forming GaN template plugs that are straight along a second axis Ax2 perpendicular to a first axis Ax1 on a TO wafer; and forming a dielectric Fabry-Perot filter structure on the entire TO wafer, with the sidewalls of the template plugs partially exposed and the top surface of the template plugs fully exposed; 2. Growing a non-deliberately doped GaN layer (n-GaN) along the top surface of the Fabry-Perot filter structure from the exposed GaN template plugs to form a semiconductor substrate region with a total width of approximately 30 to 50 micrometers along a third axis Ax3 perpendicular to the first and second axes Ax1 and Ax2 by means of ELO; 3. Planarizing the semiconductor substrate region to form a planarized n-GaN layer; 4. Growing semiconductor layers on the planarized n-GaN layer, including device layers, such as n-GaN for encapsulation and n-contacts, InGaN multiple quantum wells, AlGaN electron blocking layers, p-GaN layers, and p-contact layers. 5. Grind the back side of the TO wafer; 6. Transfer the photoresist pattern formed by reflow to the back side of the TO wafer using reactive ion etching to form a monolithic microlens; 7. Fabricate a photoresist mask from the photoresist film covering the device layer using back-side exposure, with the monolithic microlens used to focus the exposure light at a focal point located near the photoresist film; 8. Form a mask on the device layer using the photoresist mask; 9. Perform ion implantation using the mask to define the aperture structure; 10. After forming the aperture structure, grow an n++ GaN layer to complete the tunneling interface, and deposit an n-GaN layer on top of the n++ GaN layer for contact and current distribution; 11. Fabricate a mesa structure from the semiconductor stack including the device layer and the tunneling interface; 12. Deposit a passivation layer of omnidirectional reflector (ODR) material, which has an opening on the top surface of the mesa structure to serve as a contact area. 13. Deposit dielectric dispersed Bragg reflectors onto the flat top of the device layer; 14. Deposit electrode metal pads onto the semiconductor stack including the mesa structure; 15. Deposit dielectric dispersed Bragg reflectors onto the curved surface of the TO substrate; 16. Apply bonding material to the back side of the TO wafer; 17. Separate the manufactured TO wafer to form a VCSEL wafer; 18. Bond the VCSEL wafer to the substrate.

[0090] VCSEL chips can be used in user-defined applications, such as light sources, sensors, or both.

[0091] Figure 10 is a schematic diagram of another embodiment of the VCSEL disclosed herein. The VCSEL 11b has an embedded tunneling interface structure 38 but no aperture structure 39. The embedded tunneling interface 38 is located directly below the first DBR mirror 13 to be aligned with the cavity and covers a current spreading layer to define the electrical path from the first electrode 31 (located adjacent to the first DBR mirror 13) to the embedded tunneling interface 38 (located directly below the first DBR mirror 13 and confining carriers and laser beams).

[0092] An embodiment of the process for manufacturing a VCSEL 11b will be described below. The VCSEL 11b includes an embedded tunneling junction 38 having heavily doped n++ and p++ semiconductor layers, and an n-type semiconductor layer covering the embedded tunneling junction 38 and serving as a current dissipation layer. The embedded tunneling junction structure 38 includes a patterned p++ group III nitride layer 38a and a patterned n++ group III nitride layer 38b, which are disposed on a mesa structure 37. The p++ group III nitride layer 38a and the n++ group III nitride layer 38b are in contact with each other to form a tunneling interface and are buried by an additional group III nitride layer 38c. The additional group III nitride layer 38c is grown on the mesa structure 37 to form a substantially flat top surface. The first electrode 31 is disposed in contact with the group III nitride layer 38c, and the first DBR mirror 13 is disposed on top of the group III nitride layer 38c.

[0093] The method includes the following steps. 1. Prepare the initial substrate. The initial substrate preparation includes forming GaN template plugs that are straight along a second axis Ax2 perpendicular to a first axis Ax1 on a TO wafer; and forming a dielectric Fabry-Perot filter structure on the entire TO wafer, with the sidewalls of the template plugs partially exposed and the top surface of the template plugs fully exposed; 2. Growing a non-deliberately doped GaN layer (n-GaN) along the top surface of the Fabry-Perot filter structure from the exposed GaN template plugs to form a semiconductor substrate region with a total width of approximately 30 to 50 micrometers along a third axis Ax3 perpendicular to the first and second axes Ax1 and Ax2 by means of ELO; 3. Planarizing the semiconductor substrate region to form a planarized n-GaN layer; 4. Growing semiconductor layers on the planarized n-GaN layer, including device layers, such as n-GaN for encapsulation and n-contacts, InGaN multiple quantum wells, AlGaN electron blocking layers, p-GaN layers, and p-contact layers. 5. Grind the back side of the TO wafer; 6. Transfer the photoresist pattern formed by reflow to the back side of the TO wafer using reactive ion etching to form a monolithic microlens; 7. Grow an n++ GaN layer on the p++ GaN layer to complete the tunneling interface; 8. Fabricate a photoresist mask from the photoresist film covering the device layer using back-side exposure, with the monolithic microlens used to focus the exposure light at a focal point located near the photoresist film; 9. Pattern the tunneling interface using the photoresist mask to complete the embedded tunneling interface on the device layer; 10. After forming the embedded tunneling interface, deposit an n-GaN layer covering the embedded tunneling interface to form a planarized n-GaN top surface; 11. Fabricate a mesa structure from the semiconductor stack; 12. Deposit a passivation layer of omnidirectional reflector (ODR) material, which has openings on the top surface of the mesa structure to serve as contact areas. 13. Deposit dielectric dispersed Bragg reflectors onto the flat top of the device layer; 14. Deposit electrode metal pads onto the semiconductor stack including the mesa structure; 15. Deposit dielectric dispersed Bragg reflectors onto the curved surface of the TO substrate; 16. Apply bonding material to the back side of the TO wafer; 17. Separate the manufactured TO wafer to form a VCSEL wafer; 18. Bond the VCSEL wafer to the substrate.

[0094] VCSEL chips can be used in user-defined applications, such as light sources, sensors, or both.

[0095] Furthermore, the manufacturing of semiconductor wafers in the background art naturally includes growing an epitaxial layer on a wafer; and both a dicing layer and a wafer. The area used for dicing and wafer standardization may require at least 10% of the wafer's processing area.

[0096] There may be three ways to manufacture semiconductor wafers, such as extended cavity VCSELs.

[0097] Method 1 First, the entire device layer is epitaxially grown on a planar GaN substrate. After growth, the GaN substrate is thinned by grinding its back side, and then a curved surface for optical cavities (such as microlenses) is formed on the ground back side.

[0098] Method 2 First, the entire device layer is epitaxially grown on a planar GaN substrate. After growth, the GaN substrate is removed to form a device stack containing the device layer, and then the device stack is bonded to an external substrate having a curved surface for an optical cavity (such as a microlens) on its back side.

[0099] Method 3. Method 3 includes the manufacturing process according to this disclosure. Compared to Methods 1 and 2, integrating the extended cavity in Method 3 is a simple step process that does not require substrate removal and thinning. Drill tracks can be configured between semiconductor portions. The manufacturing process according to this disclosure allows for various configurations of device portions, such as high stacking density of device portions on the wafer.

[0100] Example

[0101] A transparent oxide (TO) substrate material microlens is integrated with the device layer on the TO substrate. The device layer is also grown on the TO substrate. The TO substrate material may include ZnO, Ga₂O₃, Al₂O₃, and other materials that are transparent to infrared, visible light, near-ultraviolet, and / or deep ultraviolet wavelengths. The VCSEL device disclosed herein has a cavity dominated primarily by a low-absorption TO substrate. This allows the fabrication of VCSEL devices using large-size TO wafers, such as sapphire wafers larger than 6 inches, and enables the production of more devices from a single process.

[0102] For TO wafers with group III nitride template plugs, the height of the group III nitride template plugs can range from 1 micrometer to 10 micrometers. The crystal quality of the group III nitride layer used for the template plugs increases with its thickness. Increasing the thickness of the group III nitride layer can terminate the threading dislocation within it, which originates from lattice mismatch at the substrate interface. Furthermore, a larger thickness can provide a Fabry-Perot filter structure with a dielectric filter layer thickness, which is helpful in characterization and forming a very narrow bandpass and a better suppression region on the outer side of the bandpass. A thicker Fabry-Perot filter is embedded in the lower sidewall portion of the template plug, which can accommodate most defects.

[0103] For example, the stencil plug can be a strip parallel to the <11-20> axis of a hexagonal group III nitride (such as GaN). In forming the stencil plug, etching a group III nitride film having a (0001)-polarity orientation can provide (11-22) sidewalls to the subsequently formed stencil plug strip. This sidewall orientation can enhance subsequent lateral growth. Depending on requirements, the group III nitride stencil plug sidewalls can have another direction that enhances lateral growth. Alternatively, the stencil plug can have a desired direction that enhances the growth of the group III nitride layer along the dielectric filter layer.

[0104] Fabry-Perot Filter / Anti-reflection: The Fabry-Perot filter structure is used in designs desired for narrow bandpass filters. The Fabry-Perot filter provides a narrow bandpass and suppression regions on both sides of the bandpass. The Fabry-Perot filter can be housed within a single laser cavity and includes a central spacer with a thickness typically half the laser wavelength, and two identical reflective mirrors, similar to the DBR mirror structure, sandwiching the central spacer.

[0105] A typical all-dielectric structure is as follows: "Substrate 1 / (HL)m / 2nH / (LH)m / Substrate 2". Substrate 1 and substrate 2 can be GaN layer and TO substrate, respectively, i.e., sapphire. "H" and "L" represent layers with high and low refractive indices and their quarter-wavelength thicknesses, respectively, while "m" and "n" are integers. The thickness of the overall structure is typically in the range of 1 to 2 micrometers or more for an operating wavelength of 450 nm. Optimized Fabry-Perot structures can allow for very narrow bandpasses, such as an optical window "WIN" around the central operating wavelength "λ0", and can have a thickness of more than 2 micrometers. "WIN" can be further narrowed by increasing the dielectric layer and fine-tuning the thickness of each layer. Fabry-Perot structures can have a surface roughness of less than 1 nanometer, and preferably, the roughness can be 0.1 to 1 nm at the root mean square (RMS). The dielectric layer of a Fabry-Perot structure can be deposited by sputtering, atomic layer deposition, ion beam deposition, or other methods. A Fabry-Perot filter comprises two reflectors and a high-index material center layer. Each of the two reflectors consists of alternating deposits of high and low refractive index materials, such as SiO₂ and HfO₂, each with a quarter-wavelength thickness. The high-index material center layer, with a thickness of half the central operating wavelength, is disposed between the reflectors.

[0106] Epitaxially grown group III nitride template plugs disposed on a TO substrate can be formed into strips, and the lower sidewalls of the template plugs are embedded with Fabry-Perot filter structures, which are made entirely of dielectric materials (such as SiO2, Ta2O5, HfO5, or other similar materials), and the top surface of the template plugs has fewer defects. Preferably, the thickness of the plugs is designed to achieve a Fabry-Perot filter with a very narrow bandpass distribution "WIN". The sidewalls of the plugs are exposed by about 1 or 2 micrometers, and the top surface width of the plugs is about 1 to 10 micrometers. These strips are arranged in a period of 50 to 200 micrometers. These strips may have a length matching or longer than the length of the device portion. Polar template plugs have a top surface orientation of c-plane (0001), and the strips of the template plugs are oriented along the <11-20> axis. On the other hand, the non-polar template plug has a top surface orientation of either the a-face (11-20) or the m-face (1100), and correspondingly, the strip of the template plug can be oriented along the <0001> axis. Furthermore, the semi-polar template plug has a top surface orientation of either the (20-21) face or the (20-2-1) face, and correspondingly, the strip of the template plug can be oriented in a direction parallel to [-1014] or [10-14]. Other directions can also be used corresponding to the orientation of the strip.

[0107] A TO wafer system with partially exposed sidewall template plugs is loaded into an MOCVD reactor to grow group III nitride islands. In some embodiments, the growth pressure ranges from 50 to 760 Torr, with a preferred range of 100 to 300 Torr to provide island-shaped group III nitride semiconductor layers with a larger width; the growth temperature ranges from 900 to 1200°C; the group V / group III ratio ranges from 10 to 30,000; the TMG flow rate ranges from 2 to 20 standard cubic centimeters per minute (sccm); the NH3 flow rate ranges from 0.1 to 10 standard liters per minute (slm); and only hydrogen, or both hydrogen and nitrogen, are used as carrier gases. The growth conditions for group III nitride islands can be optimized to obtain a smooth surface. Finally, the group III nitride layer, such as GaN layer 25, is grown by ELO to complete the islands, so that GaN layer 25 has a thickness of about 1 to 10 micrometers and a width of 50 micrometers, and the grown group III nitride islands are spaced about 15 micrometers apart.

[0108] A TO wafer with partially exposed sidewalls has a group III nitride interface (exposed stencil plug) and a dielectric interface (Fabry-Perot filter layer) on its top, and the ratio of these two interfaces is referred to as the "fill factor". In the reactor, group III nitrides can be deposited on the group III nitride interface but cannot be deposited on the dielectric interface, which is expressed as the "fill factor". In the TO wafer disclosed herein, the fill factor is less than 1. Deposition with a fill factor deviating from 1 may result in a large accumulation of group III nitride atoms at the edges of the growth surface within the reactor due to the large number of group III nitride atoms. This occurs near the boundary between the growth and non-growth interfaces, and therefore, a thicker GaN layer may be formed at the edges of the group III nitride islands compared to the central region.

[0109] Due to the large number of group III nitride atoms, the group III nitride islands grown from each template plug may have concave tops. To obtain a planar device layer, the group III nitride islands are initially grown to a thickness of 5 to 10 micrometers, and then planarized by grinding or etching to form a group III nitride substrate with a flat top. On this flat top, a device layer comprising p-GaN, n-GaN, InGaN, and AlGaN layers is grown. Specifically, since the overall thickness of the device layer, including n-GaN, MQW, and p-GaN, and / or tunneling interface layers, may not exceed 700 nm, the edge growth caused by the large number of group III nitride atoms during regrowth is negligible.

[0110] A group III nitride-based semiconductor layer and a tunneling junction or embedded tunneling junction layer are regrown on a polished surface of a group III nitride substrate. The semiconductor stack and semiconductor portion 15 each include a semiconductor device layer of a group III nitride compound, which may include In, Al, and / or B, as well as dopants or impurities such as Mg, Si, Zn, O, C, and H. The group III nitride-based semiconductor device layer typically comprises more than three layers, including an n-type layer, an undoped layer, and a p-type layer. Specifically, the device layer includes gallium nitride-based materials such as GaN layers, AlGaN layers, InGaN layers, and AlGaInN layers. For example, the epitaxial growth of these device layers is performed in an MOCVD or MBE reactor. The device region includes a thick n-GaN layer, multiple quantum wells (e.g., a 3 nm thick MQW and a 7 nm thick barrier), a 10 nm thick p-AlGaN electronic barrier layer (EBL), a 100 nm thick p-GaN layer, and a 10 nm thick p++GaN layer.

[0111] When ITO is used as the current distribution layer, the topmost device layer can be p++GaN. Conversely, an additional 10 nm thick n++GaN layer is deposited on top of the p++GaN to serve as a tunneling structure. For designs with embedded tunneling interfaces and tunneling interfaces, a 50 nm thick n-GaN layer as the current distribution layer is deposited on top of the additional n++GaN layer.

[0112] Specifically, in the tunneling interface design, the growth of the semiconductor stack stops after the growth of the p++GaN layer, followed by ion implantation to form the aperture structure, and then the n++GaN layer and the n-type GaN layer are deposited on the aperture structure.

[0113] Specifically, in the embedded tunneling junction design, the growth of the semiconductor stack stops after the n++GaN layer is grown on top of the p++GaN layer. Then, the n++GaN and p++GaN layers are patterned to form a patterned tunneling junction, after which an n-type GaN layer is deposited on the patterned tunneling junction. Re-growth can be performed using either MOCVD or MBE (molecular beam epitaxy) reactors. Using MBE instead of MOCVD eliminates hydrogen re-passivation of p-GaN during tunneling junction re-growth.

[0114] On the other hand, the design described in this disclosure may include processing island-shaped group III nitride device layers. To restore hydrogen repassivation, activation of p-type gallium nitride-based materials (such as p-GaN) can be achieved through lateral diffusion, and the p-GaN layer embedded in the tunneling junction or current spreading layer (n-GaN) can be activated. Accordingly, the design of a specific device layer can be selected using MBE or MOCVD based on manufacturing parameters such as cost or yield.

[0115] The formation of microlenses Monolithic microlenses are used in the aperture manufacturing process, especially monolithic lenses on the back side, which can focus the exposure light to the position of the aperture structure through the lens effect of the curved surface. The curved surface is used to form a curved second DBR mirror in VCSEL products.

[0116] The TO substrate can be a double-sided polished substrate, and correspondingly, the microlens pattern on the back surface is positioned so that the final position and shape of the lens can be usefully and correctly aligned with the position of the aperture portion on the top surface of the semiconductor portion. The monolithic microlens is manufactured by photoresist (PR) reflow and dry etching processes. For example, the double-sided polished sapphire substrate can be a (0001)-oriented 2-in wafer, and larger diameter wafers can also be used if feasible. Specifically, an array of circular PR disks is patterned on the back side of the polished sapphire substrate using standard photolithography. After reaching the phase transition temperature of PR, the PR pattern begins to reflow to form a convex shape with the thickest center of each pattern. The convex shape is then transferred to the sapphire substrate, for example using an inductively coupled plasma (ICP) system. Optimized etching conditions can achieve a surface roughness of less than 1 nanometer, and preferably, the etched surface of the sapphire can have a surface roughness between 0.1 nm and 0.5 nm to avoid optical scattering and related optical losses.

[0117] Ion Implantation: Ion implantation is used to create electronic and optical apertures in the GaN substrate by damaging the outer side of the aperture, and the damaged GaN-based material no longer has electrical conductivity. This method maintains a flat top surface and creates a very slight index guiding between the aperture region and the damaged region. The damaged region can have a higher absorption value than the unimplanted material in the aperture region; however, it will have increased optical loss within the cavity. Heavy ions, such as aluminum (Al), boron (B), and others, can be used in the ion implantation process. The basic concept of ion implantation is to create conductive apertures.

[0118] After ion implantation, the transparent conductive layer can be deposited on the device layer, or, for the regrowth of group III nitrides at the tunneling junction, can be performed on the device layer with or without ion implantation. ITO can be used as a commonly used transparent current dispersing layer. Including ITO in the VCSEL may result in additional absorption, but this absorption can be reduced by lowering the intensity of electromagnetic waves near the ITO layer. Alternatively, tunneling junctions can also be used to disperse current and reduce light absorption.

[0119] Tunneling Junction: The tunneling junction method allows hole carriers to be implanted into the active layer of the device via an n-type semiconductor. Because the junction between the highly doped n-type region and the highly doped p-type region allows electrons to tunnel from the valence band of the p-type region to the conduction band of the n-type region under reverse bias, this causes a change in the morphology of the conductive carriers. Since the tunneling probability is exponentially related to the tunneling distance, a highly doped region (~10¹⁹ / cm³ or higher) is preferred to create a thin depletion width for efficient operation. After forming the aperture structure through ion implantation, an n++ / n-GaN layer (10 / 50 nm thick) is epitaxially grown on the top p++GaN layer of the device layer to form the tunneling junction and current distribution layer.

[0120] Embedded tunneling junctions can function not only as carrier state alterers but also as current apertures. They are formed by growing a planar tunneling junction with a highly doped p++ / n++ layer (10 / 10 nm thick). A mask is formed on the highly doped junction layer at the desired aperture location using a microlens on the TO substrate. The highly doped junction layer is then etched through the mask. The embedded tunneling junction is not necessarily combined with a current aperture (formed by ion implantation) but can be combined with a current aperture as needed.

[0121] The DBR mirror disclosed herein comprises alternating dielectric layers bonded together to form a reflective mirror, and is disposed at the top and bottom of a VCSEL to form an optical cavity. The dielectric DBR mirror may, for example, comprise a dielectric quarter-wavelength thick SiO₂ / Ta₂O₅ layer. The pair number is related to its reflectivity, and the reflectivity of the DBR mirror on the p-side of the VCSEL may be less than that of a curved surface to improve light emission.

[0122] Omnidirectional Reflector (ODR) The ODR is located outside the optical cavity and reflects light leaking from the travel path. The ODR is also located between the anode and cathode electrodes and serves to protect and / or passivate the device layer from possible contamination and direct contact.

[0123] Metal pads, such as gold (Au), aluminum (Al), nickel (Ni), platinum (Pd), titanium (Ti), indium (In), and others, can be used as materials for metal pads in the manufacture of VCSELs. The metal layer can be formed by sputtering, vapor deposition, or electroplating.

[0124] Application

[0125] With the increase in cloud computing and streaming services, data centers have increased demands for data communication hardware (such as side-emitting lasers and VCSELs) to provide server data transmission within the data center. In most data communications, VCSELs operate at infrared (IR) wavelengths. The Group III nitride VCSELs according to the above embodiments can be used for data communications related to data centers.

[0126] GaN-based light sources, such as LEDs, have already brought about a significant transformation in residential and automotive lighting. The integration of light sources with communication services is highly anticipated in future smart cities and smart infrastructure. VCSELs may be a better alternative to LEDs and edge-emitting laser diodes. The procedures developed in the above embodiments can be used to manufacture VCSEL cells applicable to light source applications.

[0127] Visible light communication laser beams can be used for data transmission and communication applications through Li-Fi (Light-to-Earth) technology. With the rapid increase in IoT devices, the demand for data transmission continues to expand. The RF spectrum is gradually becoming saturated, and new frequencies need to keep pace with the ever-increasing demand. Using GaN-based VCSELs in existing LED architectures is simpler than replacing them with side-emitting lasers. The Group III nitride VCSELs according to the above embodiments can be used for visible light communication.

[0128] Near-eye displays: Near-eye displays represent the next mainstream wave in consumer electronics and form the basis for virtual reality (VR) and augmented reality (AR) technologies. Currently, microLEDs are the most common choice for displays; however, even with the limited progress in VCSEL research, VCSELs may still be incorporated into microdisplays and near-eye displays. VCSELs offer relatively low light power, which is beneficial for eye safety, and relatively low divergence and circular symmetry, which reduce the number of additional optical components, thus enabling device miniaturization. 2D array integration of VCSELs is simpler than that of edge-emitting lasers. The Group III nitride VCSELs according to the above embodiments can be used in these applications.

[0129] The advantages of the above embodiments are as follows: Using a VCSEL cavity defined by two reflecting mirrors allows for a sufficiently long cavity without excessive diffraction loss, and the addition of a Fabry-Perot filter reduces the risk to single-mode operation; Better thermal management is achieved due to the sufficiently long cavity and / or the electrical contact configuration on the group III nitride layer; Improved thermal efficiency is achieved through GaN template plugs connected to the TO substrate, resulting in better thermal conductivity; Low-cost, large-size template substrates, such as GaN on Sapphire, are used; Waste of semiconductor layers is minimized by using island-shaped group III nitrides; Substrate removal and bonding processes are eliminated in the manufacturing process, thus improving manufacturing parameters; and the use of ELO technology unlocks the use of external substrates in VCSEL fabrication. The above embodiments provide significant improvements in efficiency, reduced manufacturing costs, and elimination of complex processes. The above embodiments propose integrating a Fabry-Perot filter into the VCSEL, which allows for lateral epitaxial growth, improving the crystal quality of the device layer. Using a template TO material substrate with a structure similar to GaN / sapphire allows the device layer to be grown on an epitaxially extended growth wing, which typically provides defect-free or low-defect properties, thus achieving high crystal quality.

[0130] Viewpoint 1: A VCSEL comprising: an oxide substrate having a first surface and a second surface located on the opposite side of the first surface, the second surface including a curved surface; a semiconductor portion disposed on the first surface of the oxide substrate; a dielectric filter layer disposed between the semiconductor portion and the first surface of the oxide substrate, and having a reflection spectrum, the reflection spectrum providing an optical window; a first dispersed Bragg reflector (DBR) mirror, the semiconductor portion being disposed between the dielectric filter layer and the first DBR mirror; and a second DBR mirror disposed on the curved surface of the oxide substrate, the first DBR mirror, The semiconductor portion, the dielectric filter layer, the oxide substrate, and the second DBR mirror are arranged in a first axial direction to form an extended cavity. The semiconductor portion includes a p-type group III nitride region, a group III nitride region, and a group III nitride active region located between the p-type group III nitride region and the group III nitride region. The p-type group III nitride region, the group III nitride active region, and the group III nitride region are arranged in the first axial direction, and the group III nitride region includes an n-type group III nitride region.

[0131] Viewpoint 2 As described in Viewpoint 1, the vertical resonant cavity surface-emitting laser has a via extending in the first axial direction, and the vertical resonant cavity surface-emitting laser further includes: a group III nitride template plug disposed in the via and extending from the oxide substrate into the semiconductor portion within the via.

[0132] Viewpoint 3: As described in viewpoint 2, the vertical resonant cavity surface-emitting laser includes an embedded portion within the via and a protrusion extending to the semiconductor portion, and the embedded portion of the group III nitride template plug is disposed in contact with the first surface of the oxide substrate.

[0133] Viewpoint 4: A vertical resonant cavity surface-emitting laser as described in any of Viewpoints 1 to 3, wherein the curved surface of the oxide substrate has a centerline, and the group III nitride template plug is misaligned with the centerline of the curved surface.

[0134] Viewpoint 5: A vertical resonant cavity surface-emitting laser as described in any of Viewpoints 1 to 3, wherein the length of the extended cavity is greater than 50 micrometers.

[0135] Viewpoint 6: A vertical resonant cavity surface-emitting laser as described in any of Viewpoints 1 to 3, wherein the curved surface has a radius of curvature greater than 50 micrometers.

[0136] Viewpoint 7 The vertical resonant cavity surface-emitting laser described in any of Viewpoints 1 to 3, wherein the second dispersed Bragg reflector mirror is curved, the first dispersed Bragg reflector mirror is planar, and the distance between the first dispersed Bragg reflector mirror and the second dispersed Bragg reflector mirror is 50 micrometers or more.

[0137] Viewpoint 8: A vertical cavity surface-emitting laser as described in any of views 1 to 3, wherein the semiconductor portion includes a mesa structure, the mesa structure includes a base region and a mesa region disposed in the base region, and the vertical cavity surface-emitting laser further includes: a conductive layer disposed in the semiconductor portion, a portion of the conductive layer being disposed between the first dispersed Bragg reflector mirror and the semiconductor portion; a first electrode disposed in the conductive layer and located outside the first dispersed Bragg reflector mirror, the first electrode being disposed in contact with the conductive layer; and a second electrode disposed on one side of the base region of the mesa structure.

[0138] Viewpoint 9 As described in viewpoint 8, the vertical resonant cavity surface-emitting laser has a first surface and a second surface located on the opposite side of the first surface of the semiconductor portion, the dielectric filter layer is disposed on the first surface of the semiconductor portion, and the conductive layer is disposed on the second surface of the semiconductor portion.

[0139] Viewpoint 10 A vertical resonant cavity surface-emitting laser as described in any of Viewpoints 1 to 3, wherein the semiconductor portion includes an aperture structure, the aperture structure including an aperture region extending in the first axis and an isolation region surrounding the aperture region, and the first dispersed Bragg reflector mirror, the aperture region and the second dispersed Bragg reflector mirror are arranged along an axis not passing through the group III nitride template plug.

[0140] Viewpoint 11 As described in any of Viewpoints 1 to 3, the total thickness of the semiconductor portion is approximately 0.5 micrometers or more.

[0141] Viewpoint 12 A vertical resonant cavity surface-emitting laser as described in any of Viewpoints 1 to 3, wherein the dielectric filter layer includes a Fabry-Perot filter that provides the reflected spectrum to the optical window.

[0142] Viewpoint 13 The vertical resonant cavity surface-emitting laser as described in any of Viewpoints 1 to 3, wherein the oxide substrate includes one of aluminum oxide, zinc oxide, or gallium oxide.

[0143] Viewpoint 14 The vertical resonant cavity surface-emitting laser described in any of Viewpoints 1 to 3, wherein the reflectivity of the first dispersed Bragg reflector mirror is lower than the reflectivity of the second dispersed Bragg reflector mirror.

[0144] Viewpoint 15 A vertical resonant cavity surface-emitting laser as described in any of Viewpoints 1 to 3, wherein the group III nitride active region contains a quantum well structure that generates light having wavelengths in the first reflection spectrum of the first dispersed Bragg reflector mirror, in the second reflection spectrum of the second dispersed Bragg reflector mirror, and in the optical window of the dielectric filter layer.

[0145] Viewpoint 16 A method for manufacturing a vertical-cavity surface-emitting laser, the method comprising: preparing an initial substrate, the initial substrate including an oxide substrate, a group III nitride template plug, and a dielectric filter layer, the oxide substrate having a first surface and a second surface located on the opposite side of the first surface of the oxide substrate, the dielectric filter layer and the group III nitride template plug being located on the first surface of the oxide substrate, the dielectric filter layer having a reflectance spectrum, and the reflectance spectrum providing an optical window; growing a group III nitride template plug located on the dielectric filter layer. Group III nitride regions; after growing the group III nitride regions, a semiconductor stack including n-type group III nitride regions, group III nitride active regions, and p-type group III nitride regions is grown; the second surface of the oxide substrate is processed to form an oxide substrate with a curved surface disposed on the opposite side of the first surface of the oxide substrate; after growing the semiconductor stack, a first dispersed Bragg reflector stack is formed on the first surface of the oxide substrate; and a second dispersed Bragg reflector stack is formed on the curved surface of the oxide substrate.

[0146] Viewpoint 17 The method described in viewpoint 16 further includes: planarizing the group III nitride region by at least one of grinding or etching before growing the semiconductor stack.

[0147] Viewpoint 18 The method described in viewpoint 16 or 17 further includes: depositing a conductive layer on the first surface of the oxide substrate after growing the semiconductor stack and before forming the first distributed Bragg reflector stack; and forming a first electrode on the conductive layer.

[0148] Viewpoint 19 The method described in viewpoint 16 or 17 further includes: forming an etched surface of the n-type III nitride region by etching a mesa structure from the semiconductor stack to form the mesa structure including the III nitride active region.

[0149] Viewpoint 20 The method described in viewpoint 19 further includes: forming a second electrode on the etched surface of the n-type III nitride region located outside the mesa structure.

[0150] Viewpoint 21 The method described in viewpoint 16 or 17, wherein the semiconductor stack further includes one of a tunneling interface or an embedded tunneling interface.

[0151] Viewpoint 22 The method described in viewpoint 16 or 17, wherein the oxide substrate comprises one of aluminum oxide, zinc oxide, or gallium oxide.

[0152] Viewpoint 23 The method described in viewpoint 16 or 17, wherein preparing the initial substrate comprises: depositing a group III nitride layer on the first surface of the oxide substrate; patterning the group III nitride layer to form the group III nitride template plug; depositing a plurality of dielectric layers to cover the first surface of the oxide substrate and the group III nitride template plug; and processing the dielectric layers to form the dielectric filter layer such that the group III nitride template plug is located within a via of the dielectric filter layer, and the group III nitride template plug has a height greater than the thickness of the dielectric filter layer.

[0153] Viewpoint 24 The method described in viewpoint 23, wherein the dielectric layers are grown to form a Fabry-Perot filter to provide the reflection spectrum to the optical window.

[0154] Viewpoint 25 The method described in viewpoint 16 or 17, wherein the group III nitride region is grown from the group III nitride template plug by epitaxial lateral elongation growth to form a group III nitride island.

[0155] Viewpoint 26 The method described in viewpoint 25, wherein the group III nitride island extends outward from the group III nitride template plug along the top surface of the dielectric filter layer, and the roughness of the top surface of the dielectric filter layer is less than 1 nanometer.

[0156] Viewpoint 27 The method described in viewpoint 16 or 17, wherein the group III nitride active region is grown to form a quantum well structure to generate light having wavelengths in the first reflection spectrum of the first dispersed Bragg reflector stack, in the second reflection spectrum of the second dispersed Bragg reflector stack, and in the optical window of the dielectric filter layer.

[0157] Viewpoint 28 The method described in viewpoint 16 or 17, wherein processing the second surface of the oxide substrate to form an oxide substrate comprises: forming a patterned photoresist layer on the second surface of the oxide substrate, heat-treating the patterned photoresist layer to form a protruding photoresist region, and transferring the shape of the protruding photoresist region to the oxide substrate by etching the protruding photoresist region and the oxide substrate to form the curved surface, wherein etching of the protruding photoresist region and the oxide substrate is stopped to satisfy the following condition: after forming the first dispersed Bragg reflector stack and the second dispersed Bragg reflector stack, the distance between the second dispersed Bragg reflector stack and the first dispersed Bragg reflector stack is 50 micrometers or more.

[0158] Viewpoint 29 The method described in viewpoint 16 or 17, wherein the curved surface has a radius of curvature greater than 50 micrometers.

[0159] Viewpoint 30 The method described in viewpoint 16 or 17 further includes: forming a photoresist film on the first surface of the oxide substrate after growing the semiconductor stack and before forming the conductive layer; irradiating the photoresist film through the curved surface of the oxide substrate to create a patterned mask from the photoresist film; and performing ion implantation using the patterned mask to form an aperture structure including an aperture region and an isolation region surrounding the aperture region.

[0160] Unless otherwise defined herein, the terms "substantially" and "approximately" are used to describe and narrate small changes. When used in connection with an event or situation, the term may include the exact moment the event or situation occurred, or the point to which the event or situation occurred. For example, when used in connection with a numerical value, the term may include a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.

[0161] The components of several embodiments have been summarized above to enable those skilled in the art to better understand the concepts of the embodiments disclosed herein. Those skilled in the art should understand that the embodiments disclosed herein can be used as a basis to design or modify other processes and structures to achieve the same purpose and / or benefits as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and other options can be made therein without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0014] [Figure 1] is a cross-sectional schematic diagram showing an extended cavity VCSEL including a two-mirror and Fabry-Perot filter according to one embodiment of the present disclosure. [Figure 2] is a top view schematic diagram showing a VCSEL according to one embodiment of the present disclosure. [Figure 3A] is a schematic diagram showing the manufacturing process steps of an extended cavity VCSEL according to one embodiment of the present disclosure. [Figure 3B] is a schematic diagram showing the manufacturing process steps of a VCSEL manufacturing method according to one embodiment of the present disclosure. [Figure 3C] is a schematic diagram showing the manufacturing process steps of a VCSEL manufacturing method according to one embodiment of the present disclosure. [Figure 3D] is a schematic diagram showing the manufacturing process steps of a VCSEL manufacturing method according to one embodiment of the present disclosure. [Figure 3E] is a schematic diagram showing the manufacturing process steps of a VCSEL manufacturing method according to one embodiment of the present disclosure. [Figure 3F] is a schematic diagram showing the manufacturing process steps of a VCSEL manufacturing method according to one embodiment of the present disclosure. [Figure 3G] is a schematic diagram showing the manufacturing process steps of a VCSEL manufacturing method according to one embodiment of the present disclosure. [Figure 3H] is a schematic diagram illustrating the process steps of a VCSEL manufacturing method according to an embodiment of this disclosure. [Figure 3I] is a schematic diagram illustrating the process steps of a VCSEL manufacturing method according to an embodiment of this disclosure. [Figure 3J] is a schematic diagram illustrating the process steps of a VCSEL manufacturing method according to an embodiment of this disclosure. [Figure 3K] is a schematic diagram illustrating the process steps of a VCSEL manufacturing method according to an embodiment of this disclosure. [Figure 3L] is a schematic diagram illustrating the process steps of a VCSEL manufacturing method according to an embodiment of this disclosure. [Figure 3M] is a schematic diagram illustrating the process steps of a VCSEL manufacturing method according to an embodiment of this disclosure. [Figure 3N] is a schematic diagram illustrating the process steps of a VCSEL manufacturing method according to an embodiment of this disclosure. [Figure 3O] is a schematic diagram illustrating the process steps of a VCSEL manufacturing method according to an embodiment of this disclosure. [Figure 3P] is a schematic diagram illustrating the process steps of a VCSEL manufacturing method according to an embodiment of this disclosure. [Figure 3Q] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to one embodiment of the present disclosure. [Figure 3R] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to one embodiment of the present disclosure. [Figure 4A] is a perspective view showing the main components of a VCSEL product manufactured according to the manufacturing method according to one embodiment of the present disclosure. [Figure 4A] is a top view showing the main components of a VCSEL product according to one embodiment of the present disclosure. [Figure 5] is a top view showing one configuration of the device portion of the VCSEL product in the VCSEL manufacturing method according to one embodiment of the present disclosure. [Figure 6] is a top view showing another configuration of the device portion of the VCSEL product in the VCSEL manufacturing method according to one embodiment of the present disclosure.[Figure 7] is a top view showing another configuration of the apparatus portion of the VCSEL product in the VCSEL manufacturing method according to an embodiment of the present disclosure. [Figure 8] is a cross-sectional view showing an example apparatus structure of the VCSEL according to an embodiment of the present disclosure. [Figure 9] is a cross-sectional view showing an example apparatus structure of the VCSEL according to an embodiment of the present disclosure. [Figure 10] is a cross-sectional view showing an example apparatus structure of the VCSEL according to an embodiment of the present disclosure.

Claims

1. A vertical cavity surface-emitting laser, comprising: an oxide substrate having a first surface and a second surface located on the opposite side of the first surface, the second surface including a curved surface; a semiconductor portion disposed on the first surface of the oxide substrate; a dielectric filter layer disposed between the semiconductor portion and the first surface of the oxide substrate, and having a reflection spectrum, the reflection spectrum providing an optical window; a first dispersed Bragg reflector mirror, the semiconductor portion disposed between the dielectric filter layer and the first dispersed Bragg reflector mirror; and a second dispersed Bragg reflector mirror disposed on the curved surface of the oxide substrate, the first dispersed Bragg reflector mirror, the semiconductor portion, the dielectric filter layer, the oxide substrate, and the second dispersed Bragg reflector mirror being arranged upwardly along a first axis to form an extended cavity. The semiconductor portion includes a p-type group III nitride region, a group III nitride region, and a group III nitride active region located between the p-type group III nitride region and the group III nitride region. The p-type group III nitride region, the group III nitride active region, and the group III nitride region are arranged along the first axial direction, and the group III nitride region includes an n-type group III nitride region. The dielectric filter layer has a via extending along the first axial direction. The vertical resonant cavity surface-emitting laser further includes a group III nitride template plug disposed in the via and extending from the oxide substrate into the semiconductor portion within the via.

2. The vertical cavity surface-emitting laser as claimed in claim 1, wherein the group III nitride template plug includes an embedded portion within the via and a protrusion extending to the semiconductor portion, and the embedded portion of the group III nitride template plug is disposed in contact with the first surface of the oxide substrate.

3. The vertical resonant cavity surface-emitting laser as described in any one of claims 1 to 2, wherein the curved surface of the oxide substrate has a centerline, and the group III nitride template plug is misaligned with the centerline of the curved surface.

4. The vertical resonant cavity surface-emitting laser as described in any one of claims 1 to 2, wherein the length of the extended cavity is greater than 50 micrometers.

5. The vertical resonant cavity surface-emitting laser as described in any one of claims 1 to 2, wherein the curved surface has a radius of curvature greater than 50 micrometers.

6. The vertical resonant cavity surface-emitting laser as described in any one of claims 1 to 2, wherein the second dispersed Bragg reflector mirror is curved, the first dispersed Bragg reflector mirror is planar, and the distance between the first dispersed Bragg reflector mirror and the second dispersed Bragg reflector mirror is 50 micrometers or more.

7. A vertical cavity surface-emitting laser as claimed in any one of claims 1 to 2, wherein the semiconductor portion includes a mesa structure, the mesa structure including a base region and a mesa region disposed in the base region, the vertical cavity surface-emitting laser further comprising: a conductive layer disposed in the semiconductor portion, a portion of the conductive layer being disposed between the first dispersed Bragg reflector mirror and the semiconductor portion; a first electrode disposed in the conductive layer and located outside the first dispersed Bragg reflector mirror, the first electrode being in contact with the conductive layer; and a second electrode disposed on one side of the base region of the mesa structure.

8. The vertical cavity surface-emitting laser as claimed in claim 7, wherein the semiconductor portion has a first surface and a second surface located on the opposite side of the first surface of the semiconductor portion, the dielectric filter layer is disposed on the first surface of the semiconductor portion, and the conductive layer is disposed on the second surface of the semiconductor portion.

9. A vertical resonant cavity surface-emitting laser as claimed in any one of claims 1 to 2, wherein the semiconductor portion includes an aperture structure comprising an aperture region extending along the first axial direction and an isolation region surrounding the aperture region, and the first dispersed Bragg reflector mirror, the aperture region, and the second dispersed Bragg reflector mirror are configured along an axis not passing through the group III nitride template plug.

10. The vertical cavity surface-emitting laser as described in any one of claims 1 to 2, wherein the total thickness of the semiconductor portion is about 0.5 micrometers or more.

11. The vertical resonant cavity surface-emitting laser as claimed in any one of claims 1 to 2, wherein the dielectric filter layer includes a Fabry-Perot filter that provides the reflected spectrum to the optical window.

12. The vertical cavity surface-emitting laser as claimed in any one of claims 1 to 2, wherein the oxide substrate comprises one of aluminum oxide, zinc oxide, or gallium oxide.

13. The vertical resonant cavity surface-emitting laser as described in any one of claims 1 to 2, wherein the reflectivity of the first dispersed Bragg reflector mirror is lower than the reflectivity of the second dispersed Bragg reflector mirror.

14. The vertical resonant cavity surface-emitting laser as claimed in any one of claims 1 to 2, wherein the group III nitride active region comprises a quantum well structure that generates light having wavelengths in a first reflection spectrum of the first dispersed Bragg reflector mirror, in a second reflection spectrum of the second dispersed Bragg reflector mirror, and in the optical window of the dielectric filter layer.

15. A method for manufacturing a vertical-cavity surface-emitting laser, the method comprising: preparing an initial substrate, the initial substrate including an oxide substrate, a group III nitride template plug, and a dielectric filter layer, the oxide substrate having a first surface and a second surface located on the opposite side of the first surface of the oxide substrate, the dielectric filter layer and the group III nitride template plug being located on the first surface of the oxide substrate, the dielectric filter layer having a reflectance spectrum, and the reflectance spectrum providing an optical window; growing a group III nitride region from the group III nitride template plug located on the dielectric filter layer; after growing the group III nitride region, growing a semiconductor stack including an n-type group III nitride region, a group III nitride active region, and a p-type group III nitride region; processing the second surface of the oxide substrate to form an oxide substrate having a curved surface, the curved surface being disposed on the opposite side of the first surface of the oxide substrate; After the semiconductor layer is grown, a first dispersed Bragg reflector layer is formed on the first surface of the oxide substrate; and a second dispersed Bragg reflector layer is formed on the curved surface of the oxide substrate.

16. The method of claim 15 further comprises: planarizing the group III nitride region by at least one of grinding or etching prior to growing the semiconductor stack.

17. The method of claim 15 or 16 further comprises: depositing a conductive layer on the first surface of the oxide substrate after growing the semiconductor stack and before forming the first distributed Bragg reflector stack; and forming a first electrode on the conductive layer.

18. The method of claim 15 or 16 further comprises: forming a mesa structure from the semiconductor stack by etching to form an etched surface of the n-type III nitride region, the mesa structure including the III nitride active region.

19. The method of claim 18 further comprises: forming a second electrode on the etched surface of the n-type III nitride region located outside the mesa structure.

20. The method of claim 15 or 16, wherein the semiconductor stack further includes one of a tunneling interface or an embedded tunneling interface.

21. The method of claim 15 or 16, wherein the oxide substrate comprises one of aluminum oxide, zinc oxide, or gallium oxide.

22. The method of claim 15 or 16, wherein preparing the initial substrate comprises: depositing a group III nitride layer on the first surface of the oxide substrate; patterning the group III nitride layer to form the group III nitride template plug; depositing a plurality of dielectric layers to cover the first surface of the oxide substrate and the group III nitride template plug; and processing the dielectric layers to form the dielectric filter layer such that the group III nitride template plug is located within a via of the dielectric filter layer, and the group III nitride template plug has a height greater than the thickness of the dielectric filter layer.

23. The method of claim 22, wherein the dielectric layers are grown to form a Fabry-Perot filter to provide the reflection spectrum to the optical window.

24. The method of claim 15 or 16, wherein the group III nitride region is grown from the group III nitride template plug by epitaxial lateral elongation growth to form a group III nitride island.

25. The method of claim 24, wherein the group III nitride island extends outward from the group III nitride template plug along the top surface of the dielectric filter layer, and the roughness of the top surface of the dielectric filter layer is less than 1 nanometer.

26. The method of claim 15 or 16, wherein the group III nitride active region is grown to form a quantum well structure to generate light having wavelengths in a first reflection spectrum of the first dispersed Bragg reflector stack, in a second reflection spectrum of the second dispersed Bragg reflector stack, and in the optical window of the dielectric filter layer.

27. The method of claim 15 or 16, wherein processing the second surface of the oxide substrate to form an oxide substrate comprises: forming a patterned photoresist layer on the second surface of the oxide substrate, thermally processing the patterned photoresist layer to form a protruding photoresist region, and transferring the shape of the protruding photoresist region to the oxide substrate by etching the protruding photoresist region and the oxide substrate to form the curved surface, wherein... Etching of the protruding photoresist region and oxide substrate is stopped to satisfy the following condition: after the formation of the first dispersed Bragg reflector stack and the second dispersed Bragg reflector stack, the distance between the second dispersed Bragg reflector stack and the first dispersed Bragg reflector stack is 50 micrometers or more.

28. The method as claimed in claim 15 or 16, wherein the curved surface has a radius of curvature greater than 50 micrometers.

29. The method of claim 15 or 16 further comprises: forming a photoresist film on the first surface of the oxide substrate after growing the semiconductor stack and before forming the conductive layer; irradiating the photoresist film through the curved surface of the oxide substrate to form a patterned mask from the photoresist film; and performing ion implantation using the patterned mask to form an aperture structure including an aperture region and an isolation region surrounding the aperture region.

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