Systems and methods for sleep clock edge-based global counter synchronization in a chiplet system

Abstract

Various embodiments include methods and systems for providing global counter synchronization based on a sleep clock edge in a multi-chip system. A system-on-a-chip (SoC) may include: a first chip including a first chip global counter subsystem; and a second chip including a second chip global counter subsystem. The SoC may also include an interface bus communicatively coupling the first and second chips; and a power management integrated circuit (PMIC) configured to provide a sleep clock to the first and second chips. The first chip may be configured to send a global counter synchronization pulse trigger to the second chip across the interface bus. The second chip may be configured to, in response to receiving the global counter synchronization pulse trigger, load a global counter synchronization value into the second chip global counter subsystem at the sleep clock synchronization edge of the sleep clock.

Description

[Technical Field]

[0001] This disclosure relates to a system and method for global counter synchronization based on sleep clock edge in a chip system. [Previous Technology]

[0002] To accommodate the increasing complexity and capabilities of integrated circuits used in various computing and communication devices, computing chips are increasingly being implemented in a segmented manner. For example, processing devices and large integrated circuits may include multiple "chiplets" that can work together to perform joint tasks and programs. As processing speeds increase, synchronizing these programs becomes increasingly difficult. As processing speeds increase, the chances of errors occurring and vulnerabilities for malicious attacks may also increase. Therefore, there is a growing need to synchronize chips within a multi-chiplet system to better isolate and identify any such errors that may occur on one or all chips within the multi-chiplet system. [Summary of the Invention]

[0003] Various states include methods and apparatus for providing global counter synchronization within a multi-core system using the rising edge of a sleep clock. In various states, the master core can be configured to send a global counter synchronization pulse trigger across an interface bus to the slave core, and in response, the slave core can be configured to load a global counter synchronization value into the slave core's global counter subsystem at the sleep clock synchronization edge of the sleep clock.

[0004] Some configurations may include: a first chip including a first chip global counter subsystem; a second chip including a second chip global counter subsystem; an interface bus communicatively coupling the first chip and the second chip; and a power management integrated circuit (PMIC) configured to provide a sleep clock to the first chip and the second chip, wherein: the first chip is configured to send a global counter synchronization pulse trigger to the second chip across the interface bus; and the second chip is configured to, in response to receiving the global counter synchronization pulse trigger, load a global counter synchronization value into the second chip global counter subsystem at a sleep clock synchronization edge of the sleep clock.

[0005] In some configurations, the first chip may also be configured to: read a first chip global counter value from the first chip global counter subsystem; generate a global counter synchronization value based on the first chip global counter value; and send the global counter synchronization value to the second chip across the interface bus; and the second chip may also be configured to store the global counter synchronization value in a preload register, wherein the global counter synchronization value is loaded from the preload register into the second chip global counter subsystem.

[0006] In some configurations, the global counter value of the first chip may be read from the global counter subsystem of the first chip at the rising edge of the sleep clock. In some configurations, the first chip may also be configured to determine the sleep clock synchronization edge of the sleep clock, wherein the sleep clock synchronization edge is the rising edge of the sleep clock. In some configurations, the first chip may also be configured to send the global counter synchronization pulse trigger to the second chip one sleep clock cycle before the sleep clock synchronization edge of the sleep clock. In some configurations, the first chip may also be configured to send the global counter synchronization pulse trigger to the second chip at a delay between the sleep clock synchronization edge and one sleep clock cycle before the sleep clock synchronization edge.

[0007] In some configurations, the first chip may also be configured to send a reset assertion to the second chip; and the second chip may also be configured to respond to the reset assertion by sending a global counter synchronization request to the first chip across the interface bus, wherein the first chip is configured to respond to receiving the global counter synchronization request from the second chip by sending a global counter synchronization pulse trigger across the interface bus to the second chip.

[0008] In some configurations, the second chip can also be configured to: disable global counter pause in the global counter subsystem of the second chip, wherein disabling global counter pause restart counts the second chip global counter in the global counter subsystem of the second chip; and enable global counter synchronization path in the global counter subsystem of the second chip, wherein enabling global counter synchronization path allows the first chip global counter subsystem to communicate with the second chip global counter subsystem.

[0009] In some configurations, the first chip can also be configured to disable global counter pause in the first chip global counter subsystem and the second chip global counter subsystem, wherein disabling global counter pause restarts counting of the first chip global counter in the first chip global counter subsystem and restarts counting of the second chip global counter in the second chip global counter subsystem; and the second chip can also be configured to enable global counter synchronization path in the second chip global counter subsystem, wherein enabling global counter synchronization path allows the first chip global counter subsystem and the second chip global counter subsystem to communicate.

[0010] In some configurations, the sleep clock offset between the first chip and the second chip may be equal to or less than two crystal oscillator clock cycles, wherein the sleep clock may be distributed to the first chip and the second chip in a star configuration. In some configurations, the interface bus may be a system power management interface (SPMI) bus.

[0011] Some configurations may also include: a third chip, which includes a third chip global counter subsystem, wherein the interface bus communicatively couples the first chip and the third chip; and wherein: the first chip may also be configured to send the global counter synchronization pulse trigger to the third chip across the interface bus; and the third chip may be configured to, in response to receiving the global counter synchronization pulse trigger, load the global counter synchronization value into the third chip global counter subsystem at the sleep clock synchronization edge of the sleep clock.

[0012] A further embodiment may include a method for global counter synchronization within a multi-core system. This method may include: providing a sleep clock to a first core and a second core via a PMIC; sending a global counter synchronization pulse trigger from the first core to the second core; and, in response to the second core receiving the global counter synchronization pulse trigger, loading a global counter synchronization value into the second core's global counter subsystem at the sleep clock synchronization edge of the sleep clock.

[0013] Some states may also include: reading the global counter value of a first chip from the global counter subsystem of the first chip via the first chip; generating the global counter synchronization value based on the global counter value of the first chip via the first chip; sending the global counter synchronization value from the first chip to the second chip; and storing the global counter synchronization value in a preload register of the second chip, wherein the global counter synchronization value is loaded into the global counter subsystem of the second chip from the preload register. In some states, the global counter value of the first chip may be read from the global counter subsystem of the first chip at the rising edge of the sleep clock.

[0014] Some states may also include: determining the sleep clock synchronization edge of the sleep clock via the first chip, wherein the sleep clock synchronization edge is the rising edge of the sleep clock. Some states may also include: sending the global counter synchronization pulse trigger from the first chip to the second chip in a sleep clock cycle preceding the sleep clock synchronization edge of the sleep clock. Some states may also include: sending the global counter synchronization pulse trigger from the first chip to the second chip at a delay between the sleep clock synchronization edge and a sleep clock cycle preceding the sleep clock synchronization edge.

[0015] Some states may also include: sending a reset assertion from the first chip to the second chip; and in response to the reset assertion, sending a global counter synchronization request from the second chip to the first chip, wherein sending the global counter synchronization pulse trigger from the first chip to the second chip is performed in response to the first chip receiving the global counter synchronization request from the second chip.

[0016] Some states may also include: disabling global counter pause in the global counter subsystem of the second core via the second core, wherein disabling global counter pause restarts counting of the second core global counter in the second core global counter subsystem; and enabling global counter synchronization path in the global counter subsystem of the second core via the second core, wherein enabling global counter synchronization path allows the first core global counter subsystem to communicate with the second core global counter subsystem.

[0017] Some states may also include: disabling global counter pause in the first core global counter subsystem and the second core global counter subsystem via the first core, wherein disabling the global counter pause restarts counting of the first core global counter in the first core global counter subsystem and restarts counting of the second core global counter in the second core global counter subsystem; and enabling global counter synchronization path in the second core global counter subsystem via the second core, wherein enabling the global counter synchronization path allows the first core global counter subsystem to communicate with the second core global counter subsystem.

[0018] A further embodiment may include a SoC, comprising: a first chip including a first chip global counter subsystem; a second chip including a second chip global counter subsystem; a unit for providing a sleep clock to the first chip and the second chip; a unit for sending a global counter synchronization pulse trigger from the first chip to the second chip; and a unit for loading a global counter synchronization value into the second chip global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to the second chip receiving the global counter synchronization pulse trigger.

[0019] Some configurations may also include: a unit for reading the global counter value of the first chip from the first chip global counter subsystem; a unit for generating the global counter synchronization value based on the first chip global counter value; a unit for sending the global counter synchronization value from the first chip to the second chip; and a unit for storing the global counter synchronization value in a preload register of the second chip, wherein the global counter synchronization value is loaded into the global counter subsystem of the second chip from the preload register.

[0020] In some states, the first chip global counter value is read from the first chip global counter subsystem at the rising edge of the sleep clock. Some states may also include: a unit for determining the sleep clock synchronization edge of the sleep clock, wherein the sleep clock synchronization edge is the rising edge of the sleep clock. Some states may also include: a unit for sending the global counter synchronization pulse trigger from the first chip to the second chip in a sleep clock cycle preceding the sleep clock synchronization edge of the sleep clock. Some states may also include: a unit for sending the global counter synchronization pulse trigger from the first chip to the second chip at a delay between the sleep clock synchronization edge and a sleep clock cycle preceding the sleep clock synchronization edge.

[0021] Some states may also include: a unit for sending a reset assertion from the first chip to the second chip; and a unit for sending a global counter synchronization request from the second chip to the first chip in response to the reset assertion, wherein the unit for sending the global counter synchronization pulse trigger from the first chip to the second chip is in response to the first chip receiving the global counter synchronization request from the second chip. Some states may also include: a unit for disabling global counter pause in the global counter subsystem of the second chip, wherein disabling global counter pause restart counts the global counter in the global counter subsystem of the second chip; and a unit for enabling a global counter synchronization path in the global counter subsystem of the second chip, wherein enabling the global counter synchronization path allows the global counter subsystem of the first chip to communicate with the global counter subsystem of the second chip.

[0022] Some configurations may also include: a unit for disabling the global counter pause in the first chip global counter subsystem and the second chip global counter subsystem, wherein disabling the global counter pause restarts the counting of the first chip global counter in the first chip global counter subsystem and restarts the counting of the second chip global counter in the second chip global counter subsystem; and a unit for enabling the global counter synchronization path in the second chip global counter subsystem, wherein enabling the global counter synchronization path allows the first chip global counter subsystem to communicate with the second chip global counter subsystem.

[0023] A further embodiment includes a method for global counter synchronization implemented by a first chip in a multi-chip system, comprising: receiving a sleep clock from a PMIC; and sending a global counter synchronization pulse trigger to a second chip, wherein the global counter synchronization pulse trigger is configured to cause the second chip to load a global counter synchronization value into a second chip global counter subsystem at a sleep clock synchronization edge of the sleep clock. Some embodiments may also include: reading a first chip global counter value from the first chip global counter subsystem; generating a global counter synchronization value based on the first chip global counter value; and sending the global counter synchronization value to the second chip.

[0024] A further embodiment includes a SoC comprising: a first chip including a first chip global counter subsystem; a second chip including a second chip global counter subsystem; an interface bus communicatively coupling the first chip and the second chip; and a PMIC configured to provide a sleep clock to the first chip and the second chip, wherein the first chip is configured to: receive the sleep clock from the PMIC; and send a global counter synchronization pulse trigger to the second chip, wherein the global counter synchronization pulse trigger is configured to cause the second chip to load a global counter synchronization value into the second chip global counter subsystem at a sleep clock synchronization edge of the sleep clock. In some embodiments, the first chip may also be configured to: read a first chip global counter value from the first chip global counter subsystem; generate the global counter synchronization value based on the first chip global counter value; and send the global counter synchronization value to the second chip.

Implementation Method

[0041] Various embodiments will be described in detail with reference to the accompanying drawings. Wherever possible, the same element symbols will be used throughout the drawings to represent the same or similar parts. References to specific examples and implementations are for illustrative purposes and are not intended to limit the scope of the claims.

[0042] Various embodiments provide hardware-based global counter synchronization solutions within a multi-chip system utilizing a sleep clock-edge-based global counter synchronization method. These embodiments can be implemented in a system-on-a-chip (SoC) or similar system comprising multiple chips, each chip including a chip-level global counter subsystem. These chips are coupled to an interface bus and a power management integrated circuit (PMIC) configured to provide a sleep clock to a first chip and a second chip. The first chip can send a global counter synchronization pulse trigger across the interface bus to the second chip, and in response, the second chip can load a global counter synchronization value into its second chip global counter subsystem at the sleep clock synchronization edge of the sleep clock.

[0043] The terms "System-on-a-Chip" and SoC are used herein to represent a single integrated circuit (IC) chip containing multiple resources or processors integrated on a single substrate. A single SoC may contain circuitry for digital, analog, mixed-signal, and radio frequency functions. A single SoC may also include any number of general-purpose or special-purpose processors (digital signal processors, modem processors, video processors, etc.), memory blocks (such as ROM, RAM, flash memory, etc.), and resources (such as timers, voltage regulators, oscillators, etc.). SoC may also include software for controlling the integrated resources and processors, as well as software for controlling peripheral devices.

[0044] The term "System-in-Package" (SIP) is used herein to refer to a single module or package that contains multiple resources, computing units, cores, or processors on two or more IC wafers, substrates, or SoCs. For example, a SIP may include a single substrate on which multiple IC wafers or semiconductor dies are stacked in a vertical configuration. Similarly, a SIP may include one or more multi-chip modules (MCMs) on which multiple ICs or semiconductor dies are packaged into a unified substrate. A SIP may also include multiple independent SoCs coupled together via high-speed communication circuitry and tightly packaged, such as on a single motherboard or in a single wireless device. The proximity of the SoCs facilitates high-speed communication and the sharing of memory and resources.

[0045] The term "functional block" is used herein to represent an encapsulation of one or more electronic circuit components that can be used to perform various functions. In various embodiments, a functional block may include components that can be used to perform functions related to secure timer synchronization between the functional block and one or more external components. A functional block may include various hardware, software, and / or firmware for implementing various embodiments. For example, a functional block may be or include a SoC, SIP, NOC, and various subsystems. A functional block may include various timing components, memory registers, logic gate bus interfaces, multiplexers, and other electronic components for implementing secure timer synchronization in various embodiments.

[0046] As used herein, the term "chip" is used to represent a sub-processing unit or sub-processing device (such as a SoC) within a processing system. A chip can be an integrated circuit block designed to work with other similar chips within a processing system to execute various programs. A chip can be a separate die operating independently of other dies within a larger processing system (such as a SoC), or it can be a separate die operating in conjunction with other dies within a larger processing system. A chip can include one or more processing cores to cooperate with other cores of associated chips within the system to execute system programs. A chip can include input / output (I / O) functions to transfer system data with other chips and / or other system devices (such as memory, power controllers, I / O controllers, and / or interfaces). A chip can act as and can be referred to as a functional block that performs processing operations within a system (such as a SoC).

[0047] Computing devices and systems are increasingly being implemented in a segmented manner. With technological advancements and faster processing speeds, multi-core systems constantly demand increased throughput and scalability. As processing speeds increase, synchronizing these programs becomes increasingly difficult. Furthermore, the chances of errors occurring and vulnerabilities exploited for malicious attacks also increase with processing speeds. Therefore, there is a growing need for core synchronization. Reducing latency both during synchronization and when executing debugging programs based on timestamps derived from synchronization programs within a multi-core system allows for better isolation and identification of any such errors that may occur on one or more cores working together in a multi-core system.

[0048] In a multi-chip system, a master chip or chip can be used to control, regulate, or otherwise indicate any number of associated slave chips or chips that are electrically communicating with the master chip. The master chip can share at least one clock signal with the slave chips, such that the shared clock signal can be derived from the same source (e.g., a PMIC crystal oscillator). For debugging purposes, it is helpful to correctly timestamp any errors occurring within any chip in a multi-chip system, ensuring minimal deviation between timestamped events in one chip that may be associated with other timestamped events in another chip. If clock synchronization between chips is too off or out of sync, the timestamps used for any timestamped event (including recorded hardware and / or software errors) may not be correctly associated with corresponding timestamped events recorded between other chips, and may therefore be useless for accurately identifying errors, malicious attacks, or for initiating corrective procedures. Therefore, clock synchronization between chips in a multi-chip system is important for basic system operation.

[0049] In a multi-core system, clock misalignment or loss of synchronization can be caused by a variety of reasons. During system startup, the master core may be out of sync with any slave core and may require clock or global counter synchronization. Specifically, the master core may reset slave cores in an interleaved manner during system boot, causing each slave core clock and / or global counter to be misaligned with each additional slave core clock.

[0050] As another example, each chip uses its local global counter time base for functional and debug tracing. Whenever a chip is reset, the global counter of either the master or slave chip is reset. Therefore, the master chip may experience a system failure, and the PMIC can provide a reset signal, message, or assertion to the master chip. Consequently, the global counter of a reset master chip may become out of sync with the global counter of a slave chip.

[0051] Similarly, the slave chip may experience a system failure, and the master chip can provide a reset assertion to the slave chip. Therefore, a reset slave chip global counter may be out of sync with the master chip global counter and other slave chip global counters.

[0052] As another example of global counter out-of-synchronization, during Cross Trigger Interface (CTI) operation and communication, the global counters of the master chip and any slave chips may be paused. A CTI trigger may pause the global counter of a slave chip, causing that slave chip's global counter to freeze and become misaligned with the global counters still running in other chips. In the case of a CTI trigger pausing the master chip's global counter, the same CTI pause trigger also stops the global counters in all slave chips. Therefore, all chips will need to be resynchronized.

[0053] The lack of low-latency global counter synchronization can lead to various system performance issues, such as during debugging. Multi-chip systems (such as those implementing CoreSight CTI) require a common time base to track timestamps collected and aggregated from all associated system chips. Global counter synchronization is also critical for the proper operation of multi-chip systems, such as chip-to-chip or device-to-device operations and communications that require precise timestamped message passing. Software-based synchronization solutions can also be affected by synchronization accuracy. In multi-chip systems, global counter synchronization faster than the microsecond (µs) scale may be desirable to achieve accurate isochronisms across all associated chips, as microseconds are critical time intervals when chip processors operate at GHz rates. Due to chip-to-chip latency and interrupt latency, software-based global counter synchronization is on the order of µs. Therefore, hardware-based global counter synchronization solutions can be used to improve global counter synchronization latency.

[0054] Various embodiments provide a hardware-based global counter synchronization solution within a multi-core system. A multi-core system may include a master core and one or more slave cores. A sleep clock (e.g., 32 kHz) derived from an active clock (e.g., 19.2 MHz) may be distributed to each core within the multi-core system. The master core may utilize the rising edge of the sleep clock to: (i) read the master core global counter, (ii) determine which future rising edge of the sleep clock should be used to synchronize with any slave core, (iii) determine a global counter synchronization value based on the read master core global counter value, (iv) send the global counter synchronization value to one or more slave cores, and (v) broadcast a global counter synchronization pulse trigger such that any unsynchronized slave core latches the global counter synchronization value into the global counter subsystem of its local storage area within each slave core.

[0055] In some embodiments, the master and slave chips can utilize the System Power Management Interface (SPMI) slave interface or function block to generate entities to support chip-to-chip communication. The master chip can configure the SPMI slave interface or CTI interface to transmit global counter synchronization pulse triggers to any unsynchronized slave chip. Slave chip global counter synchronization requests and master chip synchronization responses can be transmitted via SPMI or any other entity interface.

[0056] In some embodiments, multi-core global counter synchronization can be performed using global counter synchronization based on the sleep clock edge during the boot sequence. For example, at boot time, the master core can reset any connected slave cores to prepare them for synchronization, such that each core is unsynchronized at system boot time. In some embodiments, multi-core global counter synchronization can be performed using global counter synchronization based on the sleep clock edge when a slave core's global counter is paused. For example, a single slave core may be paused and therefore unsynchronized with the master core, while other slave cores may still be synchronized with the master core. The unsynchronized slave core can disable pause triggering and request global counter synchronization with the master core, while other cores remain unaffected. In some embodiments, multi-core global counter synchronization can be performed using global counter synchronization based on the sleep clock edge when the master core's global counter is paused.

[0057] FIG1 is a component block diagram illustrating an example multi-chip system circuit 100 suitable for implementing any of the various embodiments. Any number of chips, greater than or equal to two chips, can be used to implement the various embodiments. The example multi-chip system 100 shown includes four chips 110a, 110b, 110c, and 110d located within a single system package or system-in-package (SIP) 104, and a PMIC controller 102. The multi-chip system 100 may also include an interface bus 106 (e.g., SPMI, inter-integrated circuit (I2C) bus). As another example, six chips may be implemented within SIP 104, with one chip operating as a first (i.e., primary / master) chip and the remaining five chips operating as second (i.e., auxiliary / slave / secondary) chips. In some embodiments, the PMIC controller 102 may be located within SIP 104.

[0058] In various embodiments, one of cores 110a, 110b, 110c, and 110d may be configured as a master core, while the remaining cores may be configured as slave cores. For example, core 110a may be configured as a master core, while cores 110b, 110c, and 110d may be configured as slave cores. Unless otherwise specified, the following examples and embodiments are described using non-limiting examples of core 110a configured as a master core and cores 110b, 110c, and 110d configured as slave cores. Master core 110a is shown to have additional components (e.g., SPMI master interface 112, master timer 114, multiplexers 131, 133) compared to slave cores 110b, 110c, and 110d. However, since each of the cores 110a, 110b, 110c, and 110d can be configured as a main core, each of the cores 110b, 110c, and 110d can also include the components shown in the main core 110a.

[0059] For ease of description, the operation of various embodiments may be described herein using non-limiting examples of two-core systems, including a first core (e.g., 110a) configured to act as a primary / master core and a second core (e.g., 110b) configured to act as an auxiliary / subordinate / slave core. However, the description referring to the first and second cores without referring to other cores is not intended to be limiting, as operation between the two cores represents operation between any number of cores.

[0060] In some embodiments, one or more of chips 110a, 110b, 110c, and 110d may operate collectively as the central processing unit (CPU) of the multi-chip system 100, which executes instructions by performing arithmetic, logic, control, and input / output (I / O) operations specified by instructions from software applications. In some embodiments, one or more of chips 110a, 110b, 110c, and 110d may operate as a dedicated processing unit. Each chip 110a, 110b, 110c, and 110d may include one or more cores, and each core may perform operations independently of other cores within the same chip and cores within other chips. Furthermore, any or all of chips 110a, 110b, 110c, and 110d may be included as part of a processor cluster architecture, such as a synchronous processor cluster architecture, an asynchronous or heterogeneous processor cluster architecture, etc.

[0061] Chips 110a, 110b, 110c, and 110d may include various additional system components, resources, and custom circuitry for managing sensor data, analog-to-digital conversion, wireless data transmission, and for performing other specialized operations, such as decoding data packets and processing encoded audio and video signals for rendering in a web browser. For example, the system components and resources of chips 110a, 110b, 110c, and 110d may include power amplifiers, voltage regulators, oscillators, phase-locked loops, peripheral bridges, data controllers, memory controllers, system controllers, access ports, timers, and other similar components for supporting processors and software clients executing within SIP 104 and processors and software clients executing outside SIP 104 but communicating electrically with the SIP (e.g., PMIC controller 102) within the multi-chip system 100. System components and resources, and / or custom circuitry, may also include circuitry for interfacing with peripheral devices such as cameras, electronic displays, wireless communication devices, external memory chips, etc. Chips 110a, 110b, 110c, and 110d may each include input / output modules for communicating with resources outside the SIP, such as clock sources or PMIC controller 102. Resources outside the SIP may be shared by two or more of chips 110a, 110b, 110c, and 110d.

[0062] Chips 110a, 110b, 110c, and 110d may include memory devices 122a, 122b, 122c, and 122d (labeled "memory"), which may be volatile or non-volatile memory and are configured to store data and processor-executable code for access by one or more processing cores 120a, 120b, 120c, and 120d (labeled "Proc") of each respective chip 110a, 110b, 110c, and 110d. In addition to memory devices 122a, 122b, 122c, and 122d, the multi-chip system 100 may also include one or more additional memory devices (not shown) located inside or outside the SIP 104, which may be configured for various purposes. One or more memory devices, including memory devices 122a, 122b, 122c, and 122d, may include volatile memory, such as random access memory (RAM), main memory, or cache memory. These memory devices may be configured to temporarily store a limited amount of data received from a data sensor or subsystem, data requested from non-volatile memory and / or processor-executable code instructions (loaded from non-volatile memory into the memory device in anticipation of future access based on various factors), and / or intermediate processing data and / or processor-executable code instructions generated by chips 110a, 110b, 110c, and 110d and temporarily stored for future fast access without being stored in non-volatile memory. The memory devices 122a, 122b, 122c, and 122d of the multi-core system 100 can be configured to at least temporarily store data and processor-executable code loaded into the memory devices 122a, 122b, 122c, and 122d in each core 110a, 110b, 110c, and 110d for access by one or more of the processing cores 120a, 120b, 120c, and 120d. The data or processor-executable code loaded into the memory devices 122a, 122b, 122c, and 122d in each core 110a, 110b, 110c, and 110d may be loaded in response to functions performed by the processing cores 120a, 120b, 120c, and 120d.

[0063] In some embodiments, processing cores 120a, 120b, 120c, and 120d can perform operations related to various subsystems and / or functional blocks within the virtual space established within cores 110a, 110b, 110c, and 110d. For example, processing cores 120a, 120b, 120c, and 120d can perform operations related to timer subsystems 124a, 124b, 124c, and 124d, global counter subsystems 126a, 126b, 126c, and 126d, and SPMI from functional blocks 130a, 130b, 130c, and 130d.

[0064] Chips 110a, 110b, 110c, and 110d may each include timer subsystems 124a, 124b, 124c, and 124d (labeled as timer SS). Timer subsystems 124a, 124b, 124c, and 124d may be used to adjust, control, and retain local global counters for clock synchronization between chips 110a, 110b, 110c, and 110d. In some embodiments, the global counter may be a 56-bit global counter value. Timer subsystems 124a, 124b, 124c, and 124d may include global counter subsystems 126a, 126b, 126c, and 126d (labeled as GC SS), which may be loaded with global counter values ​​for clock synchronization between chips 110a, 110b, 110c, and 110d. In some embodiments, the global counter may also be referred to as a system counter.

[0065] The PMIC controller 102 can control, distribute, or otherwise adjust clock signals used for synchronizing chips 110a, 110b, 110c, and 110d. Chips 110a, 110b, 110c, and 110d can receive various clock signals from the PMIC controller 102. For example, the PMIC controller 102 can store or otherwise receive reference clock signals for synchronization purposes from external components (e.g., crystal oscillators) for chips 110a, 110b, 110c, and 110d. The reference clock signal may include a clock signal corresponding to an active mode, a sleep mode, or any other predefined mode with a preset frequency. For example, the PMIC controller 102 can send a 19.2 MHz clock corresponding to an active mode to chips 110a, 110b, 110c, and 110d. In addition, the PMIC controller 102 can send a 32 kHz clock or sleep clock 108 corresponding to the sleep mode / low power mode to chips 110a, 110b, 110c, and 110d. Other clock frequencies can be used. The sleep clock 108 is always available for chips 110a, 110b, 110c, and 110d.

[0066] In various implementations, a crystal oscillator (CXO) (not shown) can generate an active clock signal (e.g., 19.2 MHz) distributed from a common clock source PMIC controller 102. A sleep clock 108 (e.g., 32 kHz) can be derived from the CXO active clock and can always be used for each of the chips 110a, 110b, 110c, 110d. For example, for synchronization purposes, the sleep clock 108 can be distributed from the PMIC controller 102 to timer subsystems 124a, 124b, 124c, 124d. When the CXO active clock is available, the global counter of the multi-chip system 100 can be incremented by 1, and when the clock source is switched to the sleep clock 108, it can be incremented by 586. The sleep clock 108 and the CXO active clock can have any integer or non-integer relationship, as long as the clocks originate from the same crystal.

[0067] In some embodiments, the sleep clock 108 offset between chips 110a, 110b, 110c, and 110d can be less than one CXO clock cycle (e.g., 52.08 ns for a 32 kHz sleep clock). In some embodiments, the offset can be less than or equal to two CXO clock cycles. The sleep clock 108 can be supplied to chips 110a, 110b, 110c, and 110d by a PMIC and can be input at a ball grid array (BGA) pin of a package (e.g., SIP 104) and subsequently distributed to all chips 110a, 110b, 110c, and 110d within the package (e.g., SIP 104). The sleep clock 108 routing can be connected in a star configuration among chips 110a, 110b, 110c, and 110d. In some embodiments, the insertion delay of the sleep clock 108 within each core 110a, 110b, 110c, 110d can be balanced to keep program-to-program variations less than 52 nanoseconds (ns).

[0068] Interface bus 106 may be a broadcast interface, in which data communication messages can be broadcast simultaneously to multiple hardware components. For example, interface bus 106 may be an SPMI bus, which allows PMIC controller 102 and chips 110a, 110b, 110c, 110d to communicate via "telegraph" or broadcast message passing technology. For example, PMIC controller 102 may broadcast clock synchronization messages across interface bus 106 so that chips 110a, 110b, 110c, 110d perform clock synchronization actions simultaneously or nearly simultaneously (i.e., subject to hardware communication path delay limitations). As another example, master chip 110a may include SPMI master interface 112 to broadcast clock synchronization messages to PMIC controller 102 and chips 110b, 110c, 110d. Master chip 110a can simultaneously synchronize slave chips 110b, 110c, and 110d in parallel via interface bus 106, which is implemented as an SPMI bus or other type of broadcast communication interface. In some embodiments, master chip 110a can synchronize slave chips 110b, 110c, and 110d individually. In some embodiments, if configured when implementing a broadcast interface such as SPMI, or if limited by interface bus 106 being a sequential interface rather than a parallel broadcast interface, master chip 110a can synchronize slave chips 110b, 110c, and 110d sequentially. Synchronization requests from slave chips 110b, 110c, and 110d, including a 56-bit global counter value, and synchronization responses from master chip 110a can be transmitted via interface bus 106 (e.g., SPMI) or any other physical interface.

[0069] Chips 110a, 110b, 110c, and 110d can be physically generated using SPMI from function blocks 130a, 130b, 130c, and 130d, respectively. SPMI from function blocks 130a, 130b, 130c, and 130d can support circuit-to-circuit (C2C) communication in the early stages of pre-boot loading. The main chip 110a software (i.e., the Master Bootloader (PBL) / Support Bootloader (SBL)) can configure SPMI from function blocks 130a, 130b, 130c, and 130d to transmit synchronization signals, pulses, or triggers. Synchronization triggers can be transmitted to each SPMI from function block 130a, 130b, 130c, and 130d within a sleep clock cycle (e.g., 30.5 µs (1 / 32 kHz)) to ensure the identification and use of the correct synchronization clock edge. The timer subsystem 124a of the main chip 110a may include a main timer 114. The main timer 114 can initiate a synchronization pulse trigger, which can be relayed from SPMI from function block 130a to SPMI from function blocks 130b, 130c, and 130d.

[0070] One or more processing cores 120a, 120b, 120c, 120d may include general purpose input / output (GPIO) pins or internal hardwired communication interfaces, which can be used to receive and send data messages to and from the PMIC controller 102, and to receive and send data messages between other core communication interfaces and / or GPIO pins. For example, CTI 130 may include one or more data paths connecting the GPIO pins of cores 110a, 110b, 110c, 110d, which can allow cores 110a, 110b, 110c, 110d to send and receive data communication and / or synchronization messages between each of cores 110a, 110b, 110c, 110d. CTI 136 can be used to send a CTI trigger signal to the master core 110a to pause the master core global counter stored in the master core global counter subsystem 126a. CTI 136 can be used to send CTI trigger signals to slave cores 110b, 110c, and 110d to pause the slave core global counters stored in global counter subsystems 126b, 126c, and 126d, respectively.

[0071] The main chip 110a software (i.e., the main bootloader (PBL) / auxiliary bootloader (SBL)) can configure the CTI 136 for transmitting synchronization pulses. Synchronization pulses can be transmitted to each timer subsystem 124a, 124b, 124c, 124d within a sleep clock cycle (e.g., 30.5 µs (1 / 32 kHz)) to ensure the correct synchronization clock edge is identified and used.

[0072] For example, master chip 110a can initiate a synchronization select signal (marked "sync sel") to switch between synchronization methods. In some embodiments, PMIC controller 102 can switch the state of the synchronization select signal. Initiating the synchronization select signal can allow the multi-chip system 100 to switch from an SPMI-based broadcast synchronization method implementing interface bus 106 to a GPIO-based synchronization method implementing CTI 136. In the SPMI-based broadcast synchronization method, various synchronization requests and responses can be transmitted across interface bus 106 between master chip SPMI slave function block 130a and slave chip SPMI slave function blocks 130b, 130c, 130d. SPMI can relay global counter values ​​received from interface bus 106 via function blocks 130a, 130b, 130c, and 130d through corresponding multiplexers 134a, 134b, 134c, and 134d (i.e., during system boot or system resynchronization) to latch global counter values ​​into corresponding global counter subsystems 126a, 126b, 126c, and 126d. A start synchronization select signal can switch the data path of the multiplexers (e.g., multiplexers 131, 132a-d, 133, and 134a-d). The master timer 114 can initiate a synchronization pulse trigger (i.e., as CTI trig out 0) on CTI 136 (i.e., via multiple GPIO pins) through multiplexers 133 and 131. The synchronization pulse trigger from the master timer 114 can be propagated via multiplexers 132a, 132b, 132c, and 132d (i.e., as CTI trig in 0) and subsequently further propagated via multiplexers 134a, 134b, 134c, and 134d and latched into each global counter subsystem 126a, 126b, 126c, and 126d. When the global counter synchronization mode is not selected (i.e., the synchronization selection signal ("sync sel") is 0 or low), multiplexers 134a, 134b, 134c, and 134d can output CTI trig0 for debugging purposes.

[0073] Figures 2-4 are message flow diagrams 200, 300, and 400 illustrating operations and chip-to-chip and intra-chip communications for global counter synchronization based on a sleep clock edge in a multi-chip system according to some embodiments. The operations and communications for global counter synchronization based on a sleep clock edge in a multi-chip system shown in Figures 2-4 can be implemented using at least two chips (e.g., chips 110a, 110b, 110c, 110d) and a PMIC (e.g., PMIC controller 102) communicatively connected via an interface bus (e.g., interface bus 106). Some of the operations or communications shown in Figures 2-4 may not be performed in all embodiments, and the operations and communications may be performed in a different order than in the examples shown in Figures 2-4.

[0074] Referring to Figures 1-4, a master chip 110a, having a master chip processor 120a and a master chip global counter subsystem 126a, can communicate with a slave chip 110b, having a slave chip processor 120b and a slave chip global counter subsystem 126b. The master chip processor 120a can perform local communication with the master chip global counter subsystem 126a within the master chip 110a. The slave chip processor 120b can perform local communication with the slave chip global counter subsystem 126b within the slave chip 110b. The master chip processor 120a and the master chip global counter subsystem 126a can communicate with the slave chip processor 120b and the slave chip global counter subsystem 126b via an interface bus 106 (which may be an SPMI bus). Interface bus 106 can be used to send and receive various global counter synchronization messages between master chip processor 120a, master chip global counter subsystem 126a, slave chip processor 120b and slave chip global counter subsystem 126b to synchronize the global counter based on the edge of sleep clock 108.

[0075] Figures 2-4 illustrate various scenarios for resynchronizing global counters within any of the cores 110a, 110b, 110c, and 110d. For ease of illustration, the operation of two cores (e.g., cores 110a and 110b) and the communication between them are illustrated. However, the same operation performed by or in conjunction with core 110b can be performed simultaneously or in conjunction with additional cores (e.g., 110c and 110d) that are in electrical communication with master core 110a. For example, communication 214 can be simultaneously sent from master core global counter subsystem 126a to slave core global counter subsystems 126b, 126c, and 126d. As another example, communication 220 can be simultaneously sent from master core processor 120a to slave core global counter subsystems 126b, 126c, and 126d.

[0076] Figure 2 is a message flow diagram illustrating the operation of global counter synchronization based on sleep clock edge in a multi-core system during a boot sequence, according to some embodiments, as well as core-to-core and intra-core communication.

[0077] During a cold boot (i.e., system power-on) or a hot boot (i.e., system reset via software), the master chip 110a may become out of sync with the slave chip 110b. For example, the master chip 110a may be reset before the slave chip 110b, and then an instruction may be given to the slave chip 110b to prevent the slave chip 110a from being reset. The global counter maintained by the master chip global counter subsystem 126a may become out of sync with the global counter of the slave chip global counter subsystem 126b because the global counter values ​​of the master chip 110a and the slave chip 110b are enabled independently. The following procedure provides for resynchronizing the global counters of the master chip 110a and the slave chip 110b.

[0078] During cold boot or hot boot, the main chip 110a exits the reset, and the main chip global counter subsystem 126a begins to increment according to the clock provided by the PMIC controller 102 (e.g., a 19.2 MHz active clock).

[0079] In communication 202, the master chip processor 120a can generate a reset assertion and send it to the slave chip processor 120b. The reset assertion can be sent by the master chip processor 120a across a dedicated channel (such as a set of dedicated GPIO pins) to the slave chip processor 120b. The reset assertion can instruct the slave chip processor 120b to exit the reset (i.e., enter the PBL stage). After the master chip processor has entered the SBL stage, the master chip processor 120a can send a reset assertion to the slave chip processor 120b. The SBL stage is an operational stage in which dynamic random access memory (DRAM) is used to execute programs executed by the chip processors (e.g., master chip processor 120a, slave chip processor 120b), and the DRAM can be physically separated from the chip including the chip processors (e.g., DRAM located outside the SoC including master chip processor 120a and slave chip processor 120b). In some embodiments, when the master processor 120a is in the PBL stage and before entering the SBL stage, the master processor 120a may send a reset assertion to the slave processor 120b. The PBL stage is an operational stage in which a program executed by a processor (e.g., master processor 120a, slave processor 120b) is performed using read-only memory (ROM). The ROM may be physically located on a wafer or package including the processors (e.g., a ROM within a SoC including master processor 120a and slave processor 120b). After the master processor 120a has entered the PBL stage, the slave processor 120b may receive a reset assertion from the master processor 120a. The reset assertion received by the slave processor 120b from the master processor 120a may trigger the slave processor 120b to enter the PBL stage. At this time, the global counter in the slave global counter subsystem 126b is not synchronized with the global timer in the master global counter subsystem 126a.

[0080] In communication 204, the slave processor 120b can generate a global counter synchronization request and send it to the master processor 120a. The slave processor 120b can send the global counter synchronization request to the master processor 120a after entering the PBL phase. In some embodiments, the global counter synchronization request can be sent as an SPMI telegram or broadcast across interface bus 106.

[0081] In some embodiments, the master chip processor 120a may continuously poll the interface bus 106 in response to any SPMI telegram or broadcast sent from the chip processor 120b. In some embodiments, communications 206 and / or 208 may be performed in response to the master chip processor 120a detecting an SPMI telegram or broadcast from the chip processor 120b requesting a global counter synchronization procedure.

[0082] In communication 206, the main chip processor 120a may send commands or instructions to the main chip global counter subsystem 126a, or otherwise configure the main chip global counter subsystem 126a to enable periodic global counter reads performed by the main chip global counter subsystem 126a. In some embodiments, the main chip processor 120a may set bits or registers within (or in memory associated with) the main chip global counter subsystem 126a to enable periodic global counter reads performed by the main chip global counter subsystem 126a. Enabling periodic reads of the local global counter within the main chip global counter subsystem 126a allows the main chip global counter subsystem 126a to read its local global counter on each rising edge of the sleep clock 108 (e.g., 32 kHz).

[0083] In communication 208, the main chip processor 120a may send a command or instruction to the main chip global counter subsystem 126a, or otherwise configure the main chip global counter subsystem to read the latest global counter value stored in the main chip global counter subsystem 126a. In some embodiments, the main chip processor 120a may set bits or registers within the main chip global counter subsystem 126a (or in memory associated with the main chip global counter subsystem 126a) to read the latest global counter value stored in the main chip global counter subsystem 126a. In response to receiving a command or instruction from the main chip processor 120a, the main chip global counter subsystem 126a may make the local global counter corresponding to the latest rising edge of the sleep clock 108 available to the main chip processor 120a (e.g., in a register space or memory accessible by the main chip processor 120a). Therefore, the main chip processor 120a can read the latest local global counter determined by reading the periodic global counter enabled in communication 206, or take a snapshot of it.

[0084] In operation 209, the master chip processor 120a may determine the next sleep clock synchronization edge, which may be used for synchronization with the slave chip global counter subsystem 126b. In some embodiments, the next sleep clock synchronization edge that may be used for synchronization with the slave chip global counter subsystem 126b may be the first sleep clock rising edge of the master chip sleep clock that occurs after the slave chip 110b completes the PBL phase and enters the SBL phase.

[0085] In communication 210, the main chip processor 120a can configure a time comparator (e.g., main timer 114) within the main chip global counter subsystem 126a. The time comparator can be configured to prepare to trigger a global counter synchronization pulse at a future rising edge of the sleep clock, as determined via the sleep clock synchronization edge determined in operation 209.

[0086] In communication 212, the master chip processor 120a can send a global counter synchronization value (e.g., as an SPMI broadcast message) to the slave chip global counter subsystem 126b via interface bus 106. The slave chip global counter subsystem 126b can store the global counter synchronization value in a preload register in preparation for loading the global counter synchronization value into the local global counter stored and used by the slave chip global counter subsystem 126b.

[0087] In communication 214, the master chip global counter subsystem 126a can send a global counter synchronization pulse trigger (i.e., a synchronization message) to the slave chip global counter subsystem 126b. Subsequently, the slave chip global counter subsystem 126b can latch the global counter synchronization value stored in the preload register in communication 212 to synchronize the local global counter in the slave chip global counter subsystem 126b with the local global counter in the master chip global counter subsystem 126a.

[0088] In communication 216, the slave processor 120b may poll the slave global counter subsystem 126b to determine whether synchronization has been completed. For example, the slave processor 120b may poll the synchronization status register of the slave global counter subsystem 126b to determine whether a bit or register has changed to indicate that the synchronization procedure has been completed.

[0089] Communication 218-224 can be used for global counter synchronization debugging.

[0090] In communication 218, the main chip processor 120a can configure a time comparator (e.g., main timer 114) within the main chip global counter subsystem 126a. The time comparator can be configured to prepare to trigger a global counter synchronization pulse trigger at the rising edge of a future sleep clock. The time comparator can be configured to trigger the global counter synchronization pulse trigger in a manner similar to that described in communication 210 above.

[0091] In communication 220, the master chip processor 120a may send a message to the slave chip global counter subsystem 126b or otherwise instruct (i.e., set a register value) to disable the global counter synchronization path. Disabling the global counter synchronization path may include disabling the SPMI slave function block 130b, so that it may no longer be able to send and receive SPMI broadcast messages across interface bus 106. In some embodiments, disabling the global counter synchronization path may also suspend the global counter of the slave chip 110b.

[0092] In communication 222, the master chip global counter subsystem 126a can send a global counter synchronization pulse trigger (i.e., a synchronization message) to the slave chip global counter subsystem 126b. Subsequently, the slave chip global counter subsystem 126b can latch the global counter synchronization value stored in the preload register in communication 212, so that the local global counter in the slave chip global counter subsystem 126b is synchronized with the local global counter in the master chip global counter subsystem 126a. Communication 222 can be performed in a manner similar to communication 214 as described above.

[0093] In communication 224, the master chip processor 120a can read the global counter synchronization value stored in the slave chip global counter subsystem 126b. The master chip processor 120a can compare the global synchronization value determined in communication 218 with the global synchronization value stored in the preload register of the slave chip global counter subsystem 126b to determine whether these values ​​match. If the global synchronization value determined in communication 218 matches the global synchronization value stored in the preload register of the slave chip global counter subsystem 126b, the master chip processor 120a can determine that the synchronization procedure in communication 216 has been successfully completed.

[0094] The operation and communication described with reference to FIG2 can also be used during a slave chip system failure event. Any slave chip 110b, 110c, or 110d may fail during SBL or normal operation. When a slave chip system fails, the slave chip global counter enabled by PBL and stored by the slave chip global counter subsystem may become out of sync with the master chip global counter stored by the master chip global counter subsystem 126a. The master chip 110a may choose to reset any of the slave chips 110b, 110c, or 110d that have failed individually, without resynchronizing any slave chips 110b, 110c, or 110d that have not yet failed.

[0095] The operation and communication described with reference to FIG2 can also be used during a primary chip system failure event. The multi-chip system 100 can be operated to perform global counter synchronization as if the primary chip 110a and the slave chips 110b, 110c, and 110d were cold-booted.

[0096] Figure 3 is a message flow diagram illustrating, according to some embodiments, the operation of global counter synchronization based on sleep clock edge in a multi-core system when the global counter is paused from the core, as well as core-to-core communication and intra-core communication.

[0097] A CTI trigger can pause the global counter in the native storage area of ​​any of the slave chips 110b, 110c, and 110d. A CTI trigger can be used to pause the global counter in the native storage area (i.e., in the corresponding slave chip global counter subsystems 126b, 126c, and 126d) for debugging purposes, such as determining the timestamp at a specific error event. When the global counter in the native storage area of ​​any of the slave chips 110b, 110c, and 110d is paused by a CTI trigger, the global counter value may become out of sync with the global counter in the native storage area of ​​the master chip 110a within the master chip global counter subsystem 126a. The following procedure provides for resynchronizing the global counters of the master chip 110a and slave chip 110b after the slave chip global counter is paused.

[0098] In communication 301, the slave processor 120b can send a message to the slave global counter subsystem 126b or otherwise instruct (i.e., set a register value) to disable the global counter pause, which may be referred to as a CTI-triggered pause. Disabling the global counter pause allows the global counter stored in the slave global counter subsystem 126b to resume counting. However, due to the duration of the CTI pause, the slave global counter may become out of sync with the master global counter.

[0099] In communication 303, the slave processor 120b may send a message to or otherwise instruct (i.e., set a register value) the slave global counter subsystem 126b to enable the global counter synchronization path. Enabling the global counter synchronization path may include initiating the SPMI slave function block 130b, which may be able to send and receive SPMI broadcast messages across interface bus 106.

[0100] Once slave chip 110b is reconfigured to begin global counter synchronization, and the global counter in the local storage area is running, operations and communications 204-216 can be performed as described with reference to FIG2 to synchronize the slave global counter stored in slave chip global counter subsystem 126b with the master global counter stored in master chip global counter subsystem 126a. Furthermore, any debugging procedures can be performed according to communications 218-224 as described with reference to FIG2.

[0101] Figure 4 is a message flow diagram illustrating, according to some embodiments, the operation of global counter synchronization based on sleep clock edge in a multi-core system when the master core global counter is paused, as well as core-to-core communication and intra-core communication.

[0102] A CTI trigger can pause the global counter in the local storage area of ​​the master chip 110a. A CTI trigger can be used to pause the local storage area (i.e., in the master chip global counter subsystem 126a) for debugging purposes, such as determining the timestamp at a specific error event. When the global counter in the local storage area of ​​the master chip 110a is paused by a CTI trigger, the global counter value may become out of sync with all global counters in the local storage area of ​​the slave chips 110b, 110c, and 110d within the slave chip global counter subsystems 126b, 126c, and 126d. For example, when the master chip global counter is paused by a CTI trigger, the same CTI trigger is transmitted to the slave chip global counter via the CTI network to simultaneously pause the slave chip global timer. The master chip can send a non-pause CTI trigger (insertion request).

[0103] Therefore, in addition to slave cores 110b, 110c, and 110d, the multi-core system can also reinitialize master core 110a to resynchronize the global counter values ​​of all local storage areas. The following procedure provides the resynchronization of the global counters of master core 110a and slave core 110b after the master core global counter is paused.

[0104] In communication 401, the master chip processor 120a can send a message to the slave chip global counter subsystem 126b or otherwise instruct (i.e., set a register value) the slave chip global counter subsystem 126b to disable the global counter pause, which may be referred to as a CTI-triggered pause. Disabling the global counter pause allows the global counter stored in the slave chip global counter subsystem 126b to resume counting. However, due to the duration of the CTI pause, the slave chip global counter may become out of sync with the master chip global counter.

[0105] In communication 402, the master chip processor 120a can send a message to the master chip global counter subsystem 126a or otherwise instruct (i.e., set a register value) the master chip global counter subsystem 126a to disable the global counter pause, which may be referred to as a CTI-triggered pause. Disabling the global counter pause allows the global counter stored in the master chip global counter subsystem 126a to resume counting. However, due to the duration of the CTI pause, the master chip global counter may become out of sync with the slave chip global counter.

[0106] In some embodiments, communications 401 and 402 may be a single interrupt request sent from the master chip processor 120a. For example, a master chip CTI non-pause trigger may send an interrupt request to the master chip global counter subsystem 126a, which may be the same trigger sent to the slave chip processor 120b via the CTI network as an interrupt request A53 for the slave chip.

[0107] In communication 403, the slave processor 120b may send a message to or otherwise instruct (i.e., set a register value) the slave global counter subsystem 126b to enable the global counter synchronization path. Enabling the global counter synchronization path may include initiating SPMI slave function block 130b, which may be able to send and receive SPMI broadcast messages across interface bus 106.

[0108] Once the master chip 110a and slave chip 110b are reconfigured to begin global counter synchronization, and the global counter in the local storage area is running, operations and communications 204-216 can be performed as described with reference to FIG2 to synchronize the slave global counter stored in the slave chip global counter subsystem 126b with the master global counter stored in the master chip global counter subsystem 126a. Furthermore, any debugging procedures can be performed according to communications 218-224 as described with reference to FIG2.

[0109] Figure 5 is a timing diagram illustrating a timing flow 500 for global counter synchronization pulse triggering in a multi-core system according to some embodiments. Referring to Figures 1-5, the timing of some communications in the communications described with reference to Figures 2-4 is illustrated.

[0110] At event 502, the time comparator (e.g., master timer 114) of the master chip global counter subsystem 126a can initiate a global counter synchronization pulse trigger. If the interface bus 106 is capable of parallel communication, such as when the interface bus 106 can be configured as an SPMI broadcast bus, the time comparator can trigger the global counter synchronization pulse trigger as a global counter synchronization enable message. If the interface bus 106 is not capable of parallel communication, the time comparator can trigger the global counter synchronization pulse trigger via a serial data path (e.g., a dedicated GPIO pin between the master chip 110a and the slave chip 110b) as a global counter synchronization enable message. The global counter synchronization pulse trigger can instruct the slave chip 110b to load the global counter synchronization value (e.g., stored in the slave chip 110b's preload register; "N", as described below with reference to FIG6) onto the slave chip global counter at the next rising edge of the sleep clock.

[0111] At event 504, slave chip 110b can respond to receiving a global counter synchronization pulse trigger by loading the global counter synchronization value (e.g., stored in the preload register of slave chip 110b; "N", as described below with reference to FIG. 6) onto the slave chip global counter at the rising edge of the sleep clock (e.g., sleep clock synchronization edge "n", as described below with reference to FIG. 6). After slave chip 110b loads the global counter synchronization value into the slave chip global counter subsystem 126b, the global counter synchronization pulse trigger can be de-asserted by the time comparator. For example, with SPMI enabled on the interface bus 106, the global counter synchronization pulse trigger, which can transmit telegram or broadcast messages to all slave chips 110b, 110c, and 110d simultaneously, can be disabled after the rising edge identified at event 504 but before the subsequent rising edge of the sleep clock.

[0112] In some embodiments where parallel communication is not possible on their intermediate plane buses (e.g., a dedicated GPIO pin of master chip 110a is used to communicate with slave chips 110b, 110c, and 110d respectively), the rising edge of the sleep clock 505 (e.g., the rising edge "n-1" of the sleep clock as described with reference to FIG. 6 below) can be aligned with the global counter synchronization pulse trigger at 502. If the rising edge of the sleep clock 505 is synchronized with the global counter synchronization pulse trigger, the time comparator can send the global counter synchronization pulse one sleep clock cycle earlier than the expected sleep clock cycle at event 504, thus causing the slave chip global counter to be one sleep clock cycle earlier than the master chip global counter.

[0113] To avoid premature global counter synchronization pulse triggering caused by synchronization between the sleep clock and the global counter synchronization pulse trigger, the main chip 110a may introduce a delay after the rising edge 505 of the sleep clock to ensure that the global counter synchronization pulse triggering occurs after the rising edge 505 of the sleep clock. This delay may be from multiple CXO cycles from the rising edge 505 of the sleep clock.

[0114] Figure 6 is a timing diagram illustrating a timing flow 600 for global counter synchronization based on a sleep clock edge in a multi-chip configuration according to some embodiments. Referring to Figures 1-6, various signals within the timing diagram are illustrated, including signals observed from the perspective of the master chip 110a, such as the chip RESIN_N (i.e., a reset assertion provided by the PMIC controller 102 to the master chip 110a and redistributed from the master chip 110a to the slave chip 110b across a set of dedicated GPIO pins), master chip processor operation, master chip global counter (i.e., such as that stored in the master chip global counter subsystem 126a), master chip sleep clock (e.g., 32 kHz), slave chip SPMI message (i.e., a message observed by the master chip 110a via interface bus 106), and master chip SPMI message (i.e., a message broadcast by the master chip 110a via interface bus 106). The diagram illustrates additional signals from the perspective of chip 110b, such as the chip preload register, VIO int (i.e., global sync pulse trigger), sync status, chip sleep clock (e.g., 32 kHz), active clock (e.g., 19.2 MHz), chip global counter (i.e., as stored in chip global counter subsystem 126b), and chip processor operation.

[0115] At event 602, slave processor 120b may exit the reset process in response to receiving a reset assertion from master processor 120a. Master processor 120a may generate a reset assertion and send it to slave processor 120b. After master processor 120a has entered the PBL stage, master processor 120a may send a reset assertion to slave processor 120b. After master processor 120a has entered the PBL stage, slave processor 120b may receive a reset assertion from master processor 120a. In some embodiments, master processor 120a may send a reset assertion to slave processor 120b after master processor 120a has entered the SBL stage. The reset assertion (e.g., RESIN_N) may be sent by master processor 120a to slave processor 120b across a dedicated channel (such as a set of dedicated GPIO pins). A reset assertion received by slave processor 120b from master processor 120a can trigger slave processor 120b to enter the PBL phase. At this time, the global counter in slave global counter subsystem 126b is out of sync with the global timer in master global counter subsystem 126a. Slave processor 110b can remain in the PBL phase at least until the rising edge of the master sleep clock (e.g., designated as "n") occurs, after which slave global counter subsystem 126b can synchronize with master global counter subsystem 126a. Event 602 can be executed in a manner similar to communication 202 as described with reference to FIG. 2.

[0116] At event 604a, slave processor 120b may generate a global counter synchronization request and send it to master processor 120a. Slave processor 120b may send the global counter synchronization request to master processor 120a after entering the PBL phase. In some embodiments, the global counter synchronization request may be sent as an SPMI telegram or broadcast across interface bus 106. The global counter synchronization request generated by slave processor 120b or otherwise configured may include a unique slave identifier (USID) and / or a group slave identifier (GSID).

[0117] At event 604b, the master chip processor 120a may detect or otherwise receive a global counter synchronization request sent by the slave chip processor 120b during event 604a. In some embodiments, the master chip processor 120a may continuously poll the interface bus 106 in response to any SPMI telegram or broadcast sent by the slave chip processor 120b. Events 604a and 604b may be performed in a manner similar to communication 204 as described with reference to FIG2.

[0118] In some embodiments, event 606 may be executed in response to the main chip processor 120a detecting an SPMI telegram or broadcast from the chip processor 120b requesting a global counter synchronization procedure.

[0119] At event 606, the main chip processor 120a may send a command or instruction to the main chip global counter subsystem 126a, or otherwise configure the main chip global counter subsystem to enable periodic global counter reads performed by the main chip global counter subsystem 126a. In some embodiments, the main chip processor 120a may set bits or registers within the main chip global counter subsystem 126a (or in memory associated with the main chip global counter subsystem 126a) to enable periodic global counter reads performed by the main chip global counter subsystem 126a. Enabling periodic reads of the local global counter within the main chip global counter subsystem 126a allows the main chip global counter subsystem 126a to read its local global counter at each rising edge of the main chip sleep clock (e.g., 32 kHz).

[0120] The main processor 120a may also send commands or instructions to the main processor global counter subsystem 126a, or otherwise configure the main processor global counter subsystem to read the latest global counter value stored in the main processor global counter subsystem 126a. In some embodiments, the main processor 120a may set bits or registers within the main processor global counter subsystem 126a (or in memory associated with the main processor global counter subsystem 126a) to read the latest global counter value stored in the main processor global counter subsystem 126a. In response to receiving a command or instruction from the main processor 120a, the main processor global counter subsystem 126a may make its local global counter corresponding to the latest rising edge of the sleep clock 108 of the main processor 120a available to the main processor 120a (e.g., in a register space or memory accessible by the main processor 120a). Therefore, the main chip processor 120a can read the latest local global counter, as determined by the periodic global counter read enabled at event 606, or take a snapshot of it. Event 606 can be executed in a manner similar to communications 206 and 208 as described with reference to FIG2.

[0121] At event 610, the master chip processor 120a may determine the next sleep clock synchronization edge, which may be used for synchronization with the slave chip global counter subsystem 126b. In some embodiments, the next sleep clock synchronization edge (e.g., the master chip sleep clock rising edge "n") that may be used for synchronization with the slave chip global counter subsystem 126b may be the first sleep clock rising edge of the master chip sleep clock that occurs after the slave chip 110b completes the PBL phase and enters the SBL phase (i.e., after the slave PBL wait time expires).

[0122] The main chip processor 120a may be configured with a time comparator (e.g., main timer 114) within the main chip global counter subsystem 126a. The time comparator may be configured to prepare to trigger a synchronization pulse at the rising edge "n-1" of the main chip sleep clock. The time comparator may be configured together with the main chip sleep clock such that the time comparator can track the time exhibited by the main chip sleep clock at the rising edge (e.g., at each global counter read / snapshot).

[0123] In some embodiments, the sleep clock synchronization edge may be determined by the duration of the global counter synchronization mechanism. The duration of the global counter synchronization mechanism may be a duration determined in software based at least on the interface bus 106 delay (e.g., 8B global counter value and 2B synchronization message) between the master chip 110a and slave chips 110b, 110c, 110d and the software delay of the master chip 110a (e.g., via the master chip 110a and / or PMIC controller 102), the master chip 110a software delay being used for (i) reading the current global counter value and sending the value via the interface bus 106, and (ii) configuring a time comparator (e.g., master timer 114) for global counter synchronization pulse triggering via the interface bus 106 (e.g., SPMI or CTI).

[0124] The main chip processor 120a can configure and / or generate an SPMI timestamp message including a global counter synchronization value, which is then sent across interface bus 106. The main chip processor can determine or otherwise generate a global counter synchronization value "N" based on the last read or the latest main chip global counter value "K". The global counter synchronization value "N" can be equal to the last read main chip global counter "K" plus the next sleep clock synchronization edge "n" multiplied by the main chip sleep clock period. For example, N = K + (n * (1 / 32 kHz)). Event 610 can be executed in a manner similar to communications 209, 210 and 218 as described with reference to FIG2.

[0125] At event 612, the master chip processor 120a can send or broadcast the global counter synchronization value "N" as a master chip SPMI message via interface bus 106 to the slave chip global counter subsystem 126b. The slave chip global counter subsystem 126b can store the global counter synchronization value "N" in a preload register in preparation for loading the global counter synchronization value into the local global counter stored and used by the slave chip global counter subsystem 126b. As the global counter synchronization value "N" is preloaded into the slave chip global counter subsystem 126b, the slave chip global counter subsystem 126b may be waiting to synchronize with the master chip global counter subsystem 126a. Event 612 can be performed in a manner similar to communication 212 as described with reference to FIG2.

[0126] At event 614, the master chip global counter subsystem 126a may send or broadcast a global counter synchronization pulse trigger (i.e., an SPMI synchronization trigger message) to the slave chip global counter subsystem 126b. The global counter synchronization pulse trigger may be broadcast to the slave chip global counter subsystem 126b as a master chip SPMI message via interface bus 106. The master chip processor 120a may broadcast the global counter synchronization pulse trigger at a time one master chip sleep clock cycle (i.e., n-1) before the sleep clock synchronization edge "n", which is determined during event 610 for synchronization with the slave chip global counter subsystem 126b.

[0127] The main chip processor 120a may broadcast a global counter synchronization pulse trigger at a timer value equal to the main chip global counter value or the configured timer value K2. In some embodiments, the global counter synchronization pulse trigger may be initiated by a time comparator (e.g., the main timer 114). Previously, in event 610, the time comparator may have been configured with the main chip sleep clock such that the time comparator can track the time at the rising edge of the main chip sleep time (e.g., at each global counter read / snapshot). Using the time comparator, the main chip processor 120a may read or take a snapshot of the main chip global counter value at the rising edge "n-1" of the main chip sleep clock. When the time comparator value recorded at the rising edge "n-1" of the main chip sleep clock matches the configured value K2, the main chip processor 120a may broadcast a global counter synchronization pulse trigger. The global counter value of the main chip can be equal to (n-1) times the sleep clock cycle (e.g., K2 = (n-1)(1 / 32 kHz)).

[0128] The global counter sync pulse trigger can arrive at the slave chip global counter subsystem 126b before the next rising edge "n" of the master chip's sleep clock. The time between the rising edge "n-1" and the sleep clock sync edge "n" can be 586 crystal oscillator (XO) clock cycles, which can be referred to as the maximum SPMI message arrival delay, or the time during which the global counter sync pulse trigger must arrive at the slave chip global counter subsystem 126b. The time between the rising edge "n-1" when the global counter sync pulse trigger is broadcast and the time when the slave chip global counter subsystem 126b receives the global counter sync pulse trigger (i.e., the rising edge (sync trig) of VIO int) can be referred to as the SPMI message arrival delay. The SPMI message arrival delay may be a time delay limited by the hardware communication path. The SPMI message arrival delay may be less than the maximum SPMI message arrival delay.

[0129] After receiving a global counter synchronization pulse, such as one indicated by a rising edge (sync trig) of VIO int, from the slave global counter subsystem 126b, the slave global counter subsystem 126b can be prepared to synchronize with the master global counter subsystem 126a at the sleep clock synchronization edge "n". At the sleep clock synchronization edge "n", the global counter synchronization value "N" stored in the slave preload register can be loaded or latched into the slave global counter stored by the slave global counter subsystem 126b. The global counter synchronization value "N" can be loaded into the slave global counter at the rising edge of the slave sleep clock, which is considered to be the same sleep clock synchronization edge "n" of the master sleep clock. The rising edge of the slave sleep clock into which the global counter synchronization value "N" can be loaded into the slave global counter subsystem 126b may deviate from the sleep clock synchronization edge "n". The deviation between the master core sleep clock and the slave core sleep clock at the sleep clock synchronization edge "n" can be a time difference of 1 or 2 XO clock cycles. Event 614 can be executed in a manner similar to communication 214 as described with reference to Figure 2.

[0130] At event 616, slave processor 120b may poll slave global counter subsystem 126b to determine whether synchronization has been completed. Slave processor 120b may poll the synchronization status register (e.g., "sync status") of slave global counter subsystem 126b to determine whether a bit or register has been changed to indicate that the synchronization procedure has been completed. After slave processor 120b determines that synchronization between master global counter subsystem 126a and slave global counter subsystem 126b is complete, master processor 120a and slave processor 120b may continue with normal procedures, including debugging procedures. Therefore, slave processor 120b can transition from the PBL stage to the SBL stage upon completion of global counter synchronization. Once synchronization is complete, the assertion VIO int(sync trig) can be canceled before the next rising edge "n+1" of the sleep clock.

[0131] For ease of illustration and description, Figure 6 illustrates timing signals between two cores (e.g., cores 110a and 110b). However, the same timing signals and events occurring in, executed by, or in conjunction with core 110b can be executed simultaneously by additional cores (e.g., 110c and 110d) that are electrically communicating with master core 110a, as shown in Figure 1. For example, at event 612, the preload register of slave core 110d can be loaded with the value "N". As another example, at event 614, master core 110a can broadcast a global synchronization pulse trigger across the SPMI bus to simultaneously reach all three slave cores 110b, 110c, and 110d.

[0132] FIG7 is a flowchart illustrating an embodiment of a method 700 for global counter synchronization based on a sleep clock edge in a multi-core system according to various embodiments. Referring to FIG1-7, method 700 can be implemented in a processor (e.g., processing cores 120a, 120b, 120c, 120d) configured to perform the operations of the method. In some embodiments, the processor (e.g., processing cores 120a, 120b, 120c, 120d) can be configured to perform the operations via processor-executable instructions stored in a non-transitory processor-readable medium (e.g., memory devices 122a, 122b, 122c, and 122d). The unit for performing each operation of method 700 can be a processor of the multi-core system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0133] In block 702, the PMIC can provide a sleep clock to the first and second chips. The SoC (e.g., a multi-chip system 100) may include a first chip (e.g., a master chip 110a) which includes a first chip global counter subsystem (e.g., a master chip global counter subsystem 126a). The SoC may include a second chip (e.g., a slave chip 110b) which includes a second chip global counter subsystem (e.g., a slave chip global counter subsystem 126b). The SoC may also include an interface bus (e.g., an interface bus 106) that can communicatively couple the first and second chips. The SoC may include a PMIC (e.g., a PMIC controller 102) which can be configured to provide a sleep clock (e.g., a sleep clock 108) to the first and second chips in a star configuration. The first and second chips can be configured to receive the sleep clock from the PMIC. In some embodiments, the sleep clock offset between the first and second chips may be equal to or less than two crystal oscillator clock cycles.

[0134] In some embodiments, the SoC may include a third chip (e.g., slave chip 110c, 110d) which includes a third chip global counter subsystem (e.g., slave chip global counter subsystem 126c, 126d). An interface bus can communicatively couple the first chip and the third chip. The first chip may also be configured to send a global counter synchronization pulse trigger to the third chip across the interface bus. The third chip may be configured to, in response to receiving a global counter synchronization pulse trigger, load a global counter synchronization value into the third chip global counter subsystem at the sleep clock synchronization edge of the sleep clock.

[0135] The program in block 702 can be executed as shown in Figure 1. The unit used to execute the operation in block 702 may include the processor of the multi-core system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0136] In block 704, a global counter synchronization pulse trigger can be sent from the first chip to the second chip. The first chip can be configured to send the global counter synchronization pulse trigger across an interface bus to the second chip. For example, the first chip can send the global counter synchronization pulse trigger as a broadcast or telegraph message across an interface bus for SPMI. As another example, the first chip can send the global counter synchronization pulse trigger via a series of dedicated GPIO pins that communicatively connect the first chip to the second chip. The global counter synchronization pulse trigger can be configured by the first chip to cause the second chip to load the global counter synchronization value (e.g., "N") into the second chip's global counter subsystem at the sleep clock synchronization edge (e.g., "n") of the sleep clock.

[0137] In some embodiments, the first chip may be configured to send a global counter synchronization pulse trigger to the second chip one sleep clock cycle before the sleep clock synchronization edge of the sleep clock. In some embodiments, the first chip may be configured to send a global counter synchronization pulse trigger to the second chip at a delay between the sleep clock synchronization edge and one sleep clock cycle before the sleep clock synchronization edge.

[0138] The program in block 704 can be executed as described with reference to communication 214 in FIG2-4, event 614 in FIG5 and FIG6. The unit used to perform the operation in block 704 may include the processor of the multi-core system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0139] In block 706, in response to the second core receiving a global counter synchronization pulse trigger, the global counter synchronization value can be loaded into the second core global counter subsystem at the sleep clock synchronization edge of the sleep clock. As described with reference to block 704, in response to receiving a global counter synchronization pulse trigger, the second core can be configured to load or latch the global counter synchronization value (e.g., "N") into the second core global counter subsystem at the sleep clock synchronization edge (e.g., "n") of the sleep clock. The program in block 706 can be executed as described with reference to communication 214 in Figures 2-4 and event 614 in Figures 5 and 6. The unit for performing the operation in block 704 may include the processor of the multi-core system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0140] The order of operations performed in blocks 702-706 is merely illustrative, and in some embodiments, the operations of blocks 702-706 may be performed in any order and partially simultaneously. In some embodiments, method 700 may be performed by the processor of the device independently of the external memory device but in conjunction with the external memory device. For example, method 700 may be implemented as a software module executing within the processor of the SoC or in dedicated hardware within the SoC, which issues commands to establish secure memory channels and access the memory of the external memory device, and is otherwise configured to take actions and store data as described.

[0141] FIG8A is a flowchart illustrating an embodiment of method 800a for global counter synchronization based on a sleep clock edge in a multi-core system. Method 800a may be implemented as part of method 700 in some embodiments. Referring to FIG1-8A, method 800a may be implemented in a processor (e.g., processing cores 120a, 120b, 120c, 120d) configured to perform the operations of the method. In some embodiments, the processor (e.g., processing cores 120a, 120b, 120c, 120d) may be configured to perform the operations via processor-executable instructions stored in a non-transitory processor-readable medium (e.g., memory devices 122a, 122b, 122c, and 122d). The unit for performing each operation of method 800a may be a processor of the multi-core system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0142] In block 802, the first core can read the first core global counter value from the first core global counter subsystem. The first core (e.g., master core 110a) can be configured to read or otherwise receive the first core global counter value from the first core global counter subsystem (e.g., master core global counter subsystem 126a). In some embodiments, the first core global counter value can be read from the first core global counter subsystem at the rising edge of the sleep clock. The program in block 802 can be executed as described with reference to communication 208 in FIG2-4 and event 606 in FIG6. The unit for performing the operations in block 802 may include the processor of the multi-core system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0143] In block 804, a global counter synchronization value can be generated by the first core based on the first core global counter value. The first core (e.g., master core 110a) can be configured to generate a global counter synchronization value (e.g., N") based on the first core global counter value previously read as described in reference block 802. The program in block 804 can be executed as described in reference to event 610 of FIG6. The unit for performing the operations in block 804 may include the processor of the multi-core system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0144] In block 806, a global counter synchronization value can be sent from a first core to a second core. The first core (e.g., master core 110a) can be configured to send a global counter synchronization value (e.g., "N") to a second core (e.g., slave core 110b). For example, the first core can send the global counter synchronization value as a broadcast or telegraph message across an interface bus for SPMI. As another example, the first core can send the global counter synchronization value via a series of dedicated GPIO pins that connect the first core to the second core. The program in block 806 can be executed as described with reference to communication 212 in Figures 2-4 and event 612 in Figure 6. The unit used to perform the operations in block 806 may include a processor of the multi-core system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0145] In block 808, the global counter synchronization value can be stored in a preload register of the second core. The second core (e.g., from core 110b) can be configured to store the global counter synchronization value (e.g., "N") in the preload register, wherein the global counter synchronization value can be loaded from the preload register into the second core global counter subsystem (e.g., from core global counter subsystem 126b). The program in block 808 can be executed as described with reference to communication 212 in FIG2-4 and event 612 in FIG6. The multicore system 100 can continue to execute the operation of block 702 of method 700 (FIG. 7) as described. The unit for performing the operation in block 808 may include the processor of the multicore system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0146] The order of operations performed in blocks 802-808 is merely illustrative, and in some embodiments, the operations of blocks 802-808 may be performed in any order and partially simultaneously. In some embodiments, method 800a may be performed by the processor of the device independently of the external memory device but in conjunction with the external memory device. For example, method 800a may be implemented as a software module executing within the processor of the SoC or in dedicated hardware within the SoC, which issues commands to establish secure memory channels and access the memory of the external memory device, and is otherwise configured to take actions and store data as described.

[0147] FIG8B is a flowchart illustrating an embodiment of method 800b for global counter synchronization based on a sleep clock edge in a multi-core system. Method 800b may be implemented as part of method 700 in some embodiments. Referring to FIG1-8B, method 800b may be implemented in a processor (e.g., processing cores 120a, 120b, 120c, 120d) configured to perform the operations of the method. In some embodiments, the processor (e.g., processing cores 120a, 120b, 120c, 120d) may be configured to perform the operations via processor-executable instructions stored in a non-transitory processor-readable medium (e.g., memory devices 122a, 122b, 122c, and 122d).

[0148] In block 810, the first core can determine the sleep clock synchronization edge of the sleep clock. The first core (e.g., main core 110a) can be configured to determine the sleep clock synchronization edge (e.g., "n") of the sleep clock (e.g., sleep clock 108), wherein the sleep clock synchronization edge can be the rising edge of the sleep clock. The program in block 810 can be executed as described with reference to operation 209 of FIG. 2-4 and event 610 of FIG. 6. The unit for performing the operation in block 810 may include the processor of the multi-core system 100, such as processing cores 120a, 120b, 120c, 120d, etc. The multi-core system 100 can continue to execute the operation of block 702 of method 700 (FIG. 7) as described.

[0149] In some embodiments, method 800b may be executed by the device's processor independently of, but in conjunction with, the external memory device. For example, method 800b may be implemented as a software module executing within the processor of the SoC or in dedicated hardware within the SoC, which issues commands to establish a secure memory channel and access the memory of the external memory device, and is otherwise configured to take actions and store data as described.

[0150] Figure 8C is a flowchart illustrating an embodiment of method 800c for global counter synchronization based on a sleep clock edge in a multi-core system. Method 800c may be implemented as part of method 700 in some embodiments. Referring to Figures 1-8C, method 800c may be implemented in a processor (e.g., processing cores 120a, 120b, 120c, 120d) configured to perform the operations of the method. In some embodiments, the processor (e.g., processing cores 120a, 120b, 120c, 120d) may be configured to perform the operations via processor-executable instructions stored in a non-transitory processor-readable medium (e.g., memory devices 122a, 122b, 122c, and 122d).

[0151] In block 812, the first chip can send a reset assertion to the second chip. The first chip (e.g., master chip 110a) can be configured to send a reset assertion to the second chip (e.g., slave chip 110b) across a hardwired dedicated channel. For example, the first chip can send the reset assertion via a series of dedicated GPIO pins that communicatively connect the first chip to the second chip. The reset assertion received by the slave chip can trigger the slave chip to enter the PBL stage. The program in block 812 can be executed as described with reference to communication 202 in FIG2 and event 602 in FIG6. The unit for performing the operations in block 812 may include the processor of the multi-chip system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0152] In block 814, the second chip can respond to a reset assertion to send a global counter synchronization request to the first chip. The second chip (e.g., slave chip 110b) can be configured to respond to receiving a reset assertion from the first chip to send a global counter synchronization request to the first chip (e.g., master chip 110a), as described with reference to block 812. For example, the second chip can send the global counter synchronization request as a broadcast or telegraph message across an interface bus for SPMI. As another example, the second chip can send the global counter synchronization request via a series of dedicated GPIO pins that communicatively connect the first chip to the second chip. The multi-chip system 100 can continue to perform the operation of block 702 of method 700 (FIG. 7) as described. For example, the first chip can be configured to respond to receiving a global counter synchronization request from the second chip by sending a global counter synchronization pulse trigger across an interface bus to the second chip. The program in block 814 can be executed as described with reference to communication 204 in FIG2 and events 604a and 604b in FIG6. The unit for performing the operation in block 814 may include the processor of the multi-core system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0153] In some embodiments, method 800c may be executed by the device's processor independently of, but in conjunction with, the external memory device. For example, method 800c may be implemented as a software module executing within the processor of the SoC or in dedicated hardware within the SoC, which issues commands to establish a secure memory channel and access the memory of the external memory device, and is otherwise configured to take actions and store data, as described.

[0154] FIG8D is a flowchart illustrating an embodiment of method 800d for global counter synchronization based on a sleep clock edge in a multi-core system. Method 800d may be implemented as part of method 700 in some embodiments. Referring to FIG1-8D, method 800d may be implemented in a processor (e.g., processing cores 120a, 120b, 120c, 120d) configured to perform the operations of the method. In some embodiments, the processor (e.g., processing cores 120a, 120b, 120c, 120d) may be configured to perform the operations via processor-executable instructions stored in a non-transitory processor-readable medium (e.g., memory devices 122a, 122b, 122c, and 122d).

[0155] In block 816, the second core can disable global counter pause within the second core global counter subsystem. The second core (e.g., from core 110b) can be configured to disable global counter pause within the second core global counter subsystem (e.g., from core global counter subsystem 126b). Global counter pause can be CTI pause triggered. Disabling global counter pause can restart counting the second core global counter within the second core global counter subsystem. The program in block 816 can be executed as described with reference to communication 301 in FIG3. The unit for performing the operations in block 816 may include the processor of the multi-core system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0156] In block 818, the second core can enable the global counter synchronization path within the second core global counter subsystem. The second core (e.g., slave core 110b) can be configured to enable the global counter synchronization path within the second core global counter subsystem (e.g., slave core global counter subsystem 126b). Enabling the global counter synchronization path allows the first core global counter subsystem (e.g., master core global counter subsystem 126a) to communicate with the second core global counter subsystem. The multi-core system 100 can continue to perform the operation of block 702 of method 700 (FIG. 7) as described. The program in block 818 can be executed as described with reference to communication 303 in FIG. 3. The unit for performing the operation in block 818 may include the processor of the multi-core system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0157] The order of operations performed in blocks 816 and 818 is merely illustrative, and in some embodiments, the operations of blocks 816-818 may be performed in any order and partially simultaneously. In some embodiments, method 800d may be performed by the device's processor independently of, but in conjunction with, the external memory device. For example, method 800d may be implemented as a software module executing within the processor of the SoC or in dedicated hardware within the SoC, which issues commands to establish secure memory channels and access the memory of the external memory device, and is otherwise configured to take actions and store data as described.

[0158] Figure 8E is a flowchart illustrating an embodiment of method 800e for global counter synchronization based on a sleep clock edge in a multi-core system. Method 800e may be implemented as part of method 700 in some embodiments. Referring to Figures 1-8E, method 800e may be implemented in a processor (e.g., processing cores 120a, 120b, 120c, 120d) configured to perform the operations of the method. In some embodiments, the processor (e.g., processing cores 120a, 120b, 120c, 120d) may be configured to perform the operations via processor-executable instructions stored in a non-transitory processor-readable medium (e.g., memory devices 122a, 122b, 122c, and 122d).

[0159] In block 820, the first kernel can disable global counter pauses within the first kernel global counter subsystem and the second kernel global counter subsystem. The first kernel (e.g., master kernel 110a) can disable global counter pauses within the first kernel global counter subsystem (e.g., master kernel global counter subsystem 126a) and the second kernel global counter subsystem (e.g., slave kernel global counter subsystem 126b). Global counter pauses can be CTI pause triggers. Disabling global counter pauses can restart counting the first kernel global counter within the first kernel global counter subsystem and can restart counting the second kernel global counter within the second kernel global counter subsystem. The program in block 820 can be executed as described with reference to communications 401 and 402 in FIG4. The unit for performing the operations in block 820 may include processors of the multi-kernel system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0160] In block 822, the second core can enable the global counter synchronization path within the second core global counter subsystem. The second core (e.g., slave core 110b) can be configured to enable the global counter synchronization path within the second core global counter subsystem (e.g., slave core global counter subsystem 126b). Enabling the global counter synchronization path allows the first core global counter subsystem (e.g., master core global counter subsystem 126a) to communicate with the second core global counter subsystem. The multicore system 100 can continue to perform the operation of block 702 as described in method 700 (FIG. 7). The program in block 822 can be executed as described with reference to communication 403 in FIG. 4. The unit for performing the operation in block 822 may include the processor of the multicore system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0161] The order of operations performed in blocks 820 and 822 is merely illustrative, and in some embodiments, the operations of blocks 820-822 may be performed in any order and partially simultaneously. In some embodiments, method 800e may be performed by the device's processor independently of, but in conjunction with, the external memory device. For example, method 800e may be implemented as a software module executing within the processor of the SoC or in dedicated hardware within the SoC, which issues commands to establish secure memory channels and access the memory of the external memory device, and is otherwise configured to take actions and store data as described.

[0162] FIG9 is a component block diagram of an example wireless device in the form of a smartphone 900 suitable for implementing some embodiments. The smartphone 900 may include a first processing device, such as a multi-chip system 100 coupled to a second processing device (such as SoC 918). The multi-chip system 100 and SoC 918 may be SoCs with 5G capability. The multi-chip system 100 and SoC 918 may be coupled to internal memory 906, 916, a display 912, and a speaker 914. In addition, the smartphone 900 may include an antenna 904 for transmitting and receiving electromagnetic radiation that can be connected to a wireless data link, or a cellular transceiver 908 coupled to one or more processors in the multi-chip system 100 and SoC 918. The smartphone 900 also typically includes a menu selection button or rocker switch 920 for receiving user input.

[0163] A typical smartphone 900 also includes a voice codec (CODEC) circuit 910, which digitizes the sound received from the microphone into data packets suitable for wireless transmission and decodes the received voice data packets to generate an analog signal, which is provided to the speaker to produce sound. Furthermore, one or more processors in the multi-chip system 100 and SoC 918, the wireless transceiver 908, and the CODEC 910 may include digital signal processor (DSP) circuitry (not shown separately).

[0164] The processor of the smartphone 900 can be any programmable microprocessor, microcomputer, or one or more multiprocessor chips, which can be configured by processor-executable instructions to perform various functions, including the functions implemented herein. In some mobile devices, multiple processors may be provided, such as a processor within the multi-chip system 100 dedicated to wireless communication functions, and a processor within the SoC 918 dedicated to performing other applications. Typically, software applications can be stored in memories 906, 916 before being accessed and loaded into the processor. The processor may include internal memory sufficient to store application software instructions.

[0165] Various embodiments (including, but not limited to, the embodiments described above with reference to FIG1-8E) can be implemented in a wide variety of computing systems including the laptop computer 1000, an example of which is illustrated in FIG10. Referring to FIG1-10, the laptop computer may include a touchpad touch surface 1017 that acts as a pointing device for the computer and can therefore receive drag, scroll, and flick gestures similar to those implemented on computing devices equipped with touchscreen displays and described above. The laptop computer 1000 will typically include a processor 1002 coupled to volatile memory 1012 and a disk drive 1013 containing large-capacity non-volatile memory (such as flash memory). Additionally, the computer 1000 may have one or more antennas 1008 for transmitting and receiving electromagnetic radiation that can be connected to a wireless data link and / or a cellular telephone transceiver 1016 coupled to the processor 1002. Computer 1000 may also include a floppy disk drive 1014 and a compact optical disc (CD) drive 1015 coupled to processor 1002. Laptop 1000 may include a touchpad 1017, a keyboard 1018, and a display 1019, all of which are coupled to processor 1002. Other configurations of the computing device may include a computer mouse or trackball coupled to the processor (e.g., via Universal Serial Bus (USB) input), which, as is known, may also be used in combination with various embodiments.

[0166] Various embodiments (including, but not limited to, those described above with reference to FIG1-8E) can also be implemented in fixed computing systems (such as any of the various commercially available servers). Referring to FIG1-11, an example server 1100 is illustrated in FIG11. Such a server 1100 typically includes one or more multi-core processor assemblies 1101 coupled to volatile memory 1102 and mass non-volatile memory (such as disk drives 1104). As shown in FIG11, a server 1100 can be added by inserting a multi-core processor assembly 1101 into a rack of the assembly. The server 1100 may also include a floppy disk drive, CD-ROM, or DVD-ROM drive 1106 coupled to the processor 1101. Server 1100 may also include a network access port 1103 coupled to multi-core processor assembly 1101, which is used to establish a network interface connection with network 1105, such as a local area network, Internet, public switched telephone network and / or cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, LTE or any other type of cellular data network) coupled to other broadcast system computers and servers.

[0167] Implementation examples are described in the following paragraphs. Implementation examples described according to the example methods also include: example methods implemented in circuitry and a processor, the processor being configured with processor-executable instructions to perform the operations of the example methods; example methods implemented in units for performing the functions of such methods; and example methods implemented in a non-transitory processor-readable storage medium having processor-executable instructions stored thereon, the processor-executable instructions being configured to cause a chip processor to perform the operations of the example methods.

[0168] Example 1: A system-on-a-chip (SoC) includes: a first chip including a first chip global counter subsystem; a second chip including a second chip global counter subsystem; an interface bus communicatively coupling the first chip and the second chip; and a power management integrated circuit (PMIC) configured to provide a sleep clock to the first chip and the second chip, wherein: the first chip is configured to send a global counter synchronization pulse trigger to the second chip across the interface bus; and the second chip is configured to load a global counter synchronization value into the second chip global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

[0169] Example 2, according to the SoC of Example 1, wherein: the first chip is also configured to: read the first chip global counter value from the first chip global counter subsystem; generate the global counter synchronization value based on the first chip global counter value; send the global counter synchronization value to the second chip across the interface bus; and the second chip is also configured to store the global counter synchronization value in a preload register, wherein the global counter synchronization value is loaded from the preload register into the second chip global counter subsystem.

[0170] Example 3: According to the SoC of Example 2, the first chip global counter value is read from the first chip global counter subsystem at the rising edge of the sleep clock.

[0171] Example 4: The SoC according to any one of Examples 1-3, wherein the first chip is also configured to determine the sleep clock synchronization edge of the sleep clock, wherein the sleep clock synchronization edge is the rising edge of the sleep clock.

[0172] Example 5: The SoC according to any one of Examples 1-4, wherein the first chip is also configured to send the global counter synchronization pulse trigger to the second chip one sleep clock cycle before the sleep clock synchronization edge of the sleep clock.

[0173] Example 6: The SoC according to any one of Examples 1-5, wherein the first chip is also configured to send the global counter synchronization pulse trigger to the second chip at a time delay between the sleep clock synchronization edge and a sleep clock cycle preceding the sleep clock synchronization edge.

[0174] Example 7: The SoC according to any one of Examples 1-6, wherein: the first chip is also configured to send a reset assertion to the second chip; and the second chip is also configured to, in response to the reset assertion, send a global counter synchronization request to the first chip across the interface bus, wherein the first chip is configured to, in response to receiving the global counter synchronization request from the second chip, send the global counter synchronization pulse trigger across the interface bus to the second chip.

[0175] Example 8: The SoC according to any one of Examples 1-7, wherein the second chip is also configured to: disable global counter pause in the global counter subsystem of the second chip, wherein disabling global counter pause restart counts the second chip global counter in the global counter subsystem of the second chip; and enable global counter synchronization path in the global counter subsystem of the second chip, wherein enabling global counter synchronization path allows the first chip global counter subsystem to communicate with the second chip global counter subsystem.

[0176] Example 9: The SoC according to any one of Examples 1-8, wherein: the first chip is also configured to disable global counter pause in the first chip global counter subsystem and the second chip global counter subsystem, wherein disabling global counter pause restarts counting of the first chip global counter in the first chip global counter subsystem and restarts counting of the second chip global counter in the second chip global counter subsystem; and the second chip is also configured to enable global counter synchronization path in the second chip global counter subsystem, wherein enabling global counter synchronization path allows the first chip global counter subsystem to communicate with the second chip global counter subsystem.

[0177] Example 10: The SoC according to any one of Examples 1-9, wherein the sleep clock deviation between the first chip and the second chip is equal to or less than two crystal oscillator clock cycles, and wherein the sleep clock is distributed to the first chip and the second chip in a star configuration.

[0178] Example 11: The SoC according to any one of Examples 1-10 also includes: a third chip, which includes a third chip global counter subsystem, wherein the interface bus communicatively couples the first chip and the third chip, and wherein: the first chip is also configured to send the global counter synchronization pulse trigger to the third chip across the interface bus; and the third chip is configured to, in response to receiving the global counter synchronization pulse trigger, load the global counter synchronization value into the third chip global counter subsystem at the sleep clock synchronization edge of the sleep clock.

[0179] Example 12: The SoC according to any one of Examples 1-11, wherein the interface bus is an SPMI bus.

[0180] Example 13: A method for global counter synchronization in a multi-core system, comprising: providing a sleep clock to a first core and a second core via a power management integrated circuit (PMIC); sending a global counter synchronization pulse trigger from the first core to the second core; and, in response to the second core receiving the global counter synchronization pulse trigger, loading a global counter synchronization value into the global counter subsystem of the second core at the sleep clock synchronization edge of the sleep clock.

[0181] Example 14, the method according to Example 13 also includes: reading the global counter value of the first chip from the global counter subsystem of the first chip via the first chip; generating the global counter synchronization value based on the global counter value of the first chip via the first chip; sending the global counter synchronization value from the first chip to the second chip; and storing the global counter synchronization value in the preload register of the second chip, wherein the global counter synchronization value is loaded into the global counter subsystem of the second chip from the preload register.

[0182] Example 15: According to the method of Example 14, wherein the first chip global counter value is read from the first chip global counter subsystem at the rising edge of the sleep clock.

[0183] Example 16, the method according to any one of Examples 13-15, also includes: determining the sleep clock synchronization edge of the sleep clock via the first chip, wherein the sleep clock synchronization edge is the rising edge of the sleep clock.

[0184] Example 17, the method according to any one of Examples 13-16, also includes: sending the global counter synchronization pulse trigger from the first core to the second core one sleep clock cycle before the sleep clock synchronization edge of the sleep clock.

[0185] Example 18, the method according to any one of Examples 13-17, also includes: sending the global counter synchronization pulse trigger from the first chip to the second chip at a time delay between the sleep clock synchronization edge and a sleep clock cycle preceding the sleep clock synchronization edge.

[0186] Example 19, the method according to any one of Examples 13-18, also includes: sending a reset assertion from the first chip to the second chip; and in response to the reset assertion, sending a global counter synchronization request from the second chip to the first chip, wherein sending the global counter synchronization pulse trigger from the first chip to the second chip is in response to the first chip receiving the global counter synchronization request from the second chip.

[0187] Example 20: The method according to any one of Examples 13-19 also includes: disabling global counter pause in the global counter subsystem of the second core via the second core, wherein disabling global counter pause restart counting of the second core global counter in the second core global counter subsystem; and enabling global counter synchronization path in the global counter subsystem of the second core via the second core, wherein enabling global counter synchronization path allows the first core global counter subsystem to communicate with the second core global counter subsystem.

[0188] Example 21: The method according to any one of Examples 13-20 also includes: disabling the global counter pause in the first chip global counter subsystem and the second chip global counter subsystem via the first chip, wherein disabling the global counter pause restarts counting the first chip global counter in the first chip global counter subsystem and restarts counting the second chip global counter in the second chip global counter subsystem; and enabling the global counter synchronization path in the second chip global counter subsystem via the second chip, wherein enabling the global counter synchronization path allows the first chip global counter subsystem to communicate with the second chip global counter subsystem.

[0189] Example 22: A method for global counter synchronization implemented by a first chip in a multi-chip system, comprising: receiving a sleep clock from a power management integrated circuit (PMIC); and sending a global counter synchronization pulse trigger to a second chip, wherein the global counter synchronization pulse trigger is configured to cause the second chip to load a global counter synchronization value into the second chip global counter subsystem at the sleep clock synchronization edge of the sleep clock.

[0190] Example 32, the method according to Example 22 also includes: reading the global counter value of the first chip from the global counter subsystem of the first chip; generating the global counter synchronization value based on the global counter value of the first chip; and sending the global counter synchronization value to the second chip.

[0191] The various embodiments shown and described are provided merely as examples to illustrate the various features of the claimed item. However, the features shown and described with respect to any given embodiment are not necessarily limited to the associated embodiment and can be used or combined with other embodiments shown and described. Furthermore, the claimed item is not intended to be limited to any one of the example embodiments.

[0192] As used in this case, the terms "part," "module," "system," etc. are intended to include computer-related entities, such as, but not limited to, hardware, firmware, combinations of hardware and software, software, or software in execution configured to perform a specific operation or function. For example, a part may be, but is not limited to being: a program running on a processor, a processor, an object, an executable, a running thread, a program, or a computer. By way of explanation, both applications in the execution of wireless equipment and both wireless equipment may be referred to as components. One or more parts may be located in the thread of a program or execution, and the parts may be located on one processor or core or distributed between two or more processors or cores. In addition, these parts can be executed from various non-temporary computer-readable media on which various instructions or data structures are stored. Parts may communicate by means of local or remote procedures, function or program dialing, electronic signals, data packets, memory read / write, and other known communication methods related to a network, computer, processor, or program.

[0193] A variety of different cellular and mobile communication services and standards are available or expected in the future, all of which can be implemented and benefit from various implementations. Such services and standards include services such as the 3rd Generation Partner Program (3GPP), Long Term Evolution (LTE) Systems, 3rd Generation Wireless Mobile Communications Technology (3G), 4th Generation Wireless Mobile Communications Technology (4G), 5th Generation Wireless Mobile Communications Technology (5G), Mobile Communications Global Systems (GSM), General Mobile Telecommunications Systems (UMTS), 3GSM, Universal Packet Radio Services (GPRS), CDMAdma Multitasking Systems, etc A1020™), Enhanced GSM Evolutionary Data Rate (EDGE), Advanced Mobile Phone System (AMPS), Digital AMPS (IS-136 / TDMA), Evolved Data Optimization (EV-DO), Digitally Enhanced Powerless Wire Telecommunications (DECT), Global Interoperability Microwave Accessibility (WiMAX), Wireless Area Network (WLAN), Wi-Fi Protection Integrated Access I and WPAII (WPA) Network (Digital Enhanced I and II). Each of these technologies involves, for example, the sending and receiving of voice, data, signal transmission, or content messages. It should be understood that any reference to terms or technical details relating to a separate telecommunications standard or technology is for illustrative purposes only and is not intended to limit the scope of the claim to a particular communication system or technology unless specifically stated in the language in which the patent is being applied for.

[0194] The various implementations shown and described are provided merely as examples to illustrate the various features of the requested item. However, the features shown and described with respect to any given implementation are not necessarily limited to the associated implementation and can be used or combined with other implementations shown and described. Furthermore, the requested item is not intended to be limited to any particular instance implementation. For example, one or more operations of the methods disclosed herein may replace or be combined with one or more operations of the methods disclosed herein.

[0195] The foregoing method description and flowchart are provided as illustrative examples only and are not intended to require or imply that the blocks in the various embodiments must be executed in the provided order. As will be appreciated by those skilled in the art to which this invention pertains, the order of the blocks in the foregoing embodiments may be executed in any order. Words such as "then," "following," "next," etc., are not intended to restrict the order of the blocks; these words are only used to guide the reader throughout the description of the method. Furthermore, any reference to singular request elements, such as the use of the articles "a," "an," or "the," should not be construed as limiting the element to the singular.

[0196] The various illustrative logic blocks, modules, circuits, and algorithm blocks described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functions of the various illustrative components, blocks, modules, circuits, and blocks have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art to which this invention pertains can implement the described functionality in alternative ways for each specific application; however, such implementation decisions should not be construed as causing a departure from the scope of the various embodiments.

[0197] Hardware for implementing the various illustrative logic, logic blocks, modules, and circuits described herein can be implemented or executed using a general-purpose single-chip or multi-chip processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, individual gate or transistor logic, individual hardware component, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor or any general processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. In some implementations, specific programs and methods can be executed by a circuit system specific to a given function.

[0198] In one or more embodiments, the described functions can be implemented using hardware, digital electronic circuits, computer software, firmware (including the structures disclosed in this specification and their equivalents), or any combination thereof. Implementation of the subject matter described in this specification can also be implemented as one or more computer programs encoded on a computer storage medium for execution by or control of the operation of a data processing device, i.e., one or more modules of computer program instructions.

[0199] The computer program code or "program code" used to execute on a programmable processor to implement the operations of the various embodiments may be written in a high-level programming language such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic, Structured Query Language (e.g., Transact-SQL), Perl, or in various other programming languages. The program code or program stored on a computer-readable storage medium, as used in this case, may represent machine language code (such as object code) in a format understandable to the processor.

[0200] In various embodiments, the described functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, such functions may be stored as one or more instructions or code on a non-transitory computer-readable medium or a non-transitory processor-readable medium. The operation of the methods or algorithms disclosed herein may be embodied in a processor-executable software module, which may reside on a non-transitory computer-readable or processor-readable storage medium. A non-transitory computer-readable or processor-readable storage medium may be any storage medium accessible by a computer or processor. By way of example and not limitation, such non-transitory computer-readable or processor-readable media may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessible by a computer. As used herein, magnetic disks and optical disks include CDs, laser discs, optical discs, DVDs, floppy disks, and Blu-ray discs, where magnetic disks typically copy data magnetically, while optical discs use lasers to copy data optically. Combinations of the above are also included within the scope of non-transitory computer-readable and processor-readable media. Furthermore, the operation of a method or algorithm may reside as code and / or instructions, or any combination or set thereof, on non-transitory processor-readable and / or computer-readable media, which may be incorporated into a computer program product.

[0201] Various modifications to the implementations described herein will be readily apparent to those skilled in the art to which this invention pertains, and the general principles defined herein may be applied to other implementations without departing from the spirit or scope of this invention. Therefore, the claim is not intended to be limited to the implementations shown herein, but rather to be given the broadest scope consistent with the content of this invention, the principles disclosed herein, and the novel features.

[0202] Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, individual features described in the context of a single implementation may also be implemented individually or in any suitable combination of subgroups in multiple implementations. Furthermore, although features may be described above as taking action in certain combinations, and even originally claimed in this manner, in some cases, one or more features from the claimed combination may be removed from that combination, and the claimed combination may involve combinations of subgroups or variations thereof.

[0203] Similarly, although operations are illustrated in a specific order in the figures, this should not be construed as requiring that such operations be performed in the specific order shown or in sequential order, or that all of the illustrated operations be performed to achieve the desired result. Furthermore, the figures may schematically illustrate one or more example programs in the form of flowcharts. However, other operations not illustrated may be incorporated into the schematically illustrated example programs. For example, one or more additional operations may be performed before, after, simultaneously with, or between any of the illustrated operations. In some cases, multiplexing and parallel processing may be advantageous. Furthermore, the separation of the various system components in the above implementation should not be construed as requiring such separation in the entire implementation, and it should be understood that the described program components and systems can generally be integrated together in a single software product or encapsulated in multiple software products. Additionally, other implementations fall within the scope of the following requests. In some cases, the actions described in the requests may be performed in different sequences and still achieve the desired result.

[0204] The above description of the disclosed embodiments is provided so that any person skilled in the art to which this invention pertains can implement or use the embodiments herein. Various modifications to these embodiments will be apparent to those skilled in the art to which this invention pertains, and the overall principles defined herein can be applied to other embodiments without departing from the scope of the embodiments. Therefore, the various embodiments are not intended to be limited to the embodiments shown herein, but are given the widest scope consistent with the following claims and the principles and novel features disclosed herein. [Simplified Explanation of the Diagram]

[0025] The accompanying drawings, which are incorporated herein and form part of this specification, illustrate exemplary embodiments and, together with the overall description provided above and the detailed description provided below, serve to explain the features of the various embodiments.

[0026] FIG1 is a component block diagram illustrating an example of a multi-core system circuit suitable for implementing various embodiments.

[0027] Figure 2 is a message flow diagram illustrating the operation and chip-to-chip communication of global counter synchronization based on sleep clock edge within a multi-chip system according to some embodiments.

[0028] Figure 3 is a message flow diagram of operation and chip-to-chip communication in a multi-chip system according to some embodiments for synchronizing the global counter based on the sleep clock edge in the multi-chip system when the global counter from the chip is paused.

[0029] Figure 4 is a message flow diagram of operation and chip-to-chip communication in a multi-chip system according to some embodiments for synchronizing the global counter based on the sleep clock edge in the multi-chip system when the global counter of the master chip is paused.

[0030] Figure 5 is a timing diagram illustrating the timing flow of global counter synchronization pulse triggering in a multi-core system according to some embodiments.

[0031] Figure 6 is a timing diagram illustrating the timing flow of global counter synchronization based on sleep clock edge in a multi-core system according to some embodiments.

[0032] Figure 7 is a flowchart illustrating an embodiment method 700 for global counter synchronization based on sleep clock edge in a multi-core system according to various embodiments.

[0033] Figure 8A is a flowchart illustrating an embodiment of method 800a of global counter synchronization based on sleep clock edge in a multi-core system. Method 800a may be implemented as part of method 700 in some embodiments.

[0034] Figure 8B is a flowchart illustrating an embodiment of method 800b for global counter synchronization based on the sleep clock edge in a multi-core system. Method 800b may be implemented as part of method 700 in some embodiments.

[0035] Figure 8C is a flowchart illustrating an embodiment of method 800c for global counter synchronization based on the sleep clock edge in a multi-core system. Method 800c may be implemented as part of method 700 in some embodiments.

[0036] Figure 8D is a flowchart illustrating an embodiment of method 800d for global counter synchronization based on sleep clock edge in a multi-core system. Method 800d may be implemented as part of method 700 in some embodiments.

[0037] Figure 8E is a flowchart illustrating an embodiment of method 800e for global counter synchronization based on sleep clock edge in a multi-core system. Method 800e may be implemented as part of method 700 in some embodiments.

[0038] FIG9 is a component block diagram of an example wireless device having the form of a smartphone 1100 suitable for implementing various embodiments.

[0039] Figure 10 is a block diagram of components of an example computing device suitable for use with various embodiments.

[0040] Figure 11 is a block diagram of components of an example server suitable for use with various embodiments. [Biomaterial Storage]

[0206] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A system-on-a-chip (SoC), comprising: A first chip including a first chip global counter subsystem; a second chip including a second chip global counter subsystem; an interface bus communicatively coupling the first chip and the second chip; and a power management integrated circuit (PMIC) configured to provide a sleep clock to the first chip and the second chip, wherein: the first chip is configured to send a global counter synchronization pulse trigger across the interface bus to the second chip one sleep clock cycle before a sleep clock synchronization edge of the sleep clock; and the second chip is configured to, in response to receiving the global counter synchronization pulse trigger, load a global counter synchronization value into the second chip global counter subsystem at the sleep clock synchronization edge of the sleep clock.

2. According to the on-chip system of request item 1, wherein: The first chip is also configured to: read a first chip global counter value from the first chip global counter subsystem; generate a global counter synchronization value based on the first chip global counter value; send the global counter synchronization value to the second chip across the interface bus; and the second chip is also configured to store the global counter synchronization value in a preload register, wherein the global counter synchronization value is loaded from the preload register into the second chip global counter subsystem.

3. The system-on-a-chip according to request item 2, wherein the first chip global counter value is read from the first chip global counter subsystem at a rising edge of the sleep clock.

4. The system-on-a-chip according to request item 1, wherein the first chip is also configured to determine the sleep clock synchronization edge of the sleep clock, wherein the sleep clock synchronization edge is a rising edge of the sleep clock.

5. The system-on-a-chip according to request item 1, wherein the first chip is also configured to send the global counter synchronization pulse trigger to the second chip at a delay time between the sleep clock synchronization edge and a sleep clock cycle preceding the sleep clock synchronization edge.

6. According to the system-on-a-chip in request item 1, wherein: The first chip is also configured to send a reset assertion to the second chip; and the second chip is also configured to respond to the reset assertion by sending a global counter synchronization request to the first chip across the interface bus, wherein the first chip is configured to respond to receiving the global counter synchronization request from the second chip by sending a global counter synchronization pulse trigger across the interface bus to the second chip.

7. The system-on-a-chip according to request item 1, wherein the second chip is also configured to: disable a global counter pause within the global counter subsystem of the second chip, wherein disabling the global counter pause restart to count a second chip global counter within the global counter subsystem of the second chip; and enable a global counter synchronization path within the global counter subsystem of the second chip, wherein enabling the global counter synchronization path allows the first chip global counter subsystem to communicate with the second chip global counter subsystem.

8. According to the system-on-a-chip in request item 1, wherein: The first chip is also configured to disable a global counter pause within the first chip global counter subsystem and the second chip global counter subsystem, wherein disabling the global counter pause restarts counting of a first chip global counter within the first chip global counter subsystem and restarts counting of a second chip global counter within the second chip global counter subsystem; and the second chip is also configured to enable a global counter synchronization path within the second chip global counter subsystem, wherein enabling the global counter synchronization path allows communication between the first chip global counter subsystem and the second chip global counter subsystem.

9. The system-on-a-chip according to claim 1, wherein a sleep clock offset between the first chip and the second chip is equal to or less than two crystal oscillator clock cycles, and wherein the sleep clock is distributed to the first chip and the second chip in a star configuration.

10. The on-chip system according to request item 1 also includes: A third chip includes a third chip global counter subsystem, wherein the interface bus communicatively couples the first chip and the third chip, wherein: the first chip is also configured to send the global counter synchronization pulse trigger to the third chip across the interface bus; and the third chip is configured to, in response to receiving the global counter synchronization pulse trigger, load the global counter synchronization value into the third chip global counter subsystem at the sleep clock synchronization edge of the sleep clock.

11. The system-on-a-chip according to request item 1, wherein the interface bus is a system power management interface (SPMI) bus.

12. A method for global counter synchronization in a multi-chip system, comprising the steps of: providing a sleep clock to a first chip and a second chip via a power management integrated circuit (PMIC); sending a global counter synchronization pulse trigger from the first chip to the second chip at a delay time between a sleep clock synchronization edge and a sleep clock cycle preceding the sleep clock synchronization edge; and in response to the second chip receiving the global counter synchronization pulse trigger, loading a global counter synchronization value into a second chip global counter subsystem at the sleep clock synchronization edge of the sleep clock.

13. The method according to claim 12 also includes the following steps: reading a first-core global counter value from a first-core global counter subsystem via the first core; generating a global counter synchronization value based on the first-core global counter value via the first core; sending the global counter synchronization value from the first core to the second core; and storing the global counter synchronization value in a preload register of the second core, wherein the global counter synchronization value is loaded into the second core global counter subsystem from the preload register.

14. The method of claim 13, wherein the first chip global counter value is read from the first chip global counter subsystem at a rising edge of the sleep clock.

15. The method according to claim 12 also includes the following steps: determining the sleep clock synchronization edge of the sleep clock via the first chip, wherein the sleep clock synchronization edge is a rising edge of the sleep clock.

16. The method according to claim 12 also includes the following steps: sending the global counter synchronization pulse trigger from the first chip to the second chip one sleep clock cycle before the sleep clock synchronization edge of the sleep clock.

17. The method according to request item 12 also includes the following steps: sending a reset assertion from the first chip to the second chip; and in response to the reset assertion, sending a global counter synchronization request from the second chip to the first chip, wherein sending the global counter synchronization pulse trigger from the first chip to the second chip is in response to the first chip receiving the global counter synchronization request from the second chip.

18. The method according to claim 12 also includes the following steps: disabling a global counter pause within the global counter subsystem of the second chip via the second chip, wherein disabling the global counter pause restarts counting of a second chip global counter within the global counter subsystem of the second chip; and enabling a global counter synchronization path within the global counter subsystem of the second chip via the second chip, wherein enabling the global counter synchronization path allows a first chip global counter subsystem to communicate with the second chip global counter subsystem.

19. The method according to claim 12 also includes the following steps: disabling a global counter pause in a first-core global counter subsystem and a global counter pause in the second-core global counter subsystem via the first core, wherein disabling the global counter pause restarts counting of a first-core global counter in the first-core global counter subsystem and restarts counting of a second-core global counter in the second-core global counter subsystem; and enabling a global counter synchronization path in the second-core global counter subsystem via the second core, wherein enabling the global counter synchronization path allows communication between the first-core global counter subsystem and the second-core global counter subsystem.

20. A system-on-a-chip (SoC), comprising: A first chip, including a first chip global counter subsystem; a second chip, including a second chip global counter subsystem; a unit for providing a sleep clock to the first chip and the second chip; a unit for sending a global counter synchronization pulse trigger from the first chip to the second chip at a delay time between a sleep clock synchronization edge and a sleep clock cycle preceding the sleep clock synchronization edge; and a unit for loading a global counter synchronization value into the second chip global counter subsystem at the sleep clock synchronization edge of the sleep clock in response to the second chip receiving the global counter synchronization pulse trigger.

21. The system-on-a-chip according to request item 20 also includes: A unit for reading a first-core global counter value from the first-core global counter subsystem; a unit for generating a global counter synchronization value based on the first-core global counter value; a unit for sending the global counter synchronization value from the first core to the second core; and a unit for storing the global counter synchronization value in a preload register of the second core, wherein the global counter synchronization value is loaded into the second core global counter subsystem from the preload register.

22. The system-on-a-chip according to request item 21, wherein the first chip global counter value is read from the first chip global counter subsystem at a rising edge of the sleep clock.

23. The system-on-a-chip according to request item 20 also includes: A unit for determining the sleep clock synchronization edge of the sleep clock, wherein the sleep clock synchronization edge is a rising edge of the sleep clock.

24. The system-on-a-chip according to request item 20 also includes: A unit for sending the global counter synchronization pulse from the first chip to the second chip at a delay between the sleep clock synchronization edge and a sleep clock cycle preceding the sleep clock synchronization edge.

25. The system-on-a-chip according to claim 20 also includes: A unit for sending a reset assertion from the first chip to the second chip; and a unit for sending a global counter synchronization request from the second chip to the first chip in response to the reset assertion, wherein the unit for sending the global counter synchronization pulse trigger from the first chip to the second chip is in response to the first chip receiving the global counter synchronization request from the second chip.

26. The system-on-a-chip according to request item 20 also includes: The unit is used to disable the pause of a global counter within the second chip global counter subsystem, wherein disabling the global counter pause restarts the counting of a second chip global counter within the second chip global counter subsystem; and the unit is used to enable a global counter synchronization path within the second chip global counter subsystem, wherein enabling the global counter synchronization path allows the first chip global counter subsystem to communicate with the second chip global counter subsystem.

27. The system-on-a-chip according to claim 20 also includes: The unit is used to disable the pause of a global counter in the first and second chip global counter subsystems, wherein disabling the global counter pause restarts the counting of a first chip global counter in the first chip global counter subsystem and restarts the counting of a second chip global counter in the second chip global counter subsystem; and the unit is used to enable a global counter synchronization path in the second chip global counter subsystem, wherein enabling the global counter synchronization path allows the first and second chip global counter subsystems to communicate.

28. A method for synchronizing a global counter implemented by a first chip in a multi-chip system, comprising the steps of: receiving a sleep clock from a power management integrated circuit (PMIC); and sending a global counter synchronization pulse trigger to a second chip one sleep clock cycle prior to a sleep clock synchronization edge of the sleep clock, wherein the global counter synchronization pulse trigger is configured to cause the second chip to load a global counter synchronization value into a second chip global counter subsystem at the sleep clock synchronization edge of the sleep clock.

29. The method according to claim 28 also includes the following steps: reading a first chip global counter value from a first chip global counter subsystem; generating a global counter synchronization value based on the first chip global counter value; and sending the global counter synchronization value to the second chip.

30. A system-on-a-chip (SoC), comprising: A first chip including a first chip global counter subsystem; a second chip including a second chip global counter subsystem; an interface bus communicatively coupling the first chip and the second chip; and a power management integrated circuit (PMIC) configured to provide a sleep clock to the first chip and the second chip, wherein the first chip is configured to: receive a sleep clock from the PMIC; and, one sleep clock cycle prior to a sleep clock synchronization edge of the sleep clock, send a global counter synchronization pulse trigger to the second chip, the global counter synchronization pulse trigger being configured to cause the second chip to load a global counter synchronization value into a second chip global counter subsystem at a sleep clock synchronization edge of the sleep clock.

31. The system-on-a-chip according to request item 30, wherein the first chip is also configured to: read a first chip global counter value from a first chip global counter subsystem; generate a global counter synchronization value based on the first chip global counter value; and send the global counter synchronization value to the second chip.

Images