Active filters and gyrators including cascaded inverters

Abstract

One aspect relates to a filter or first cyclotron comprising a first set of cascaded inverters and a first set of one or more passive devices coupled to the first set of cascaded inverters. Another aspect relates to a method comprising applying an input signal to an input of a first cascaded inverter in a set of cascaded inverters coupled to a set of one or more passive devices, and receiving an output signal from the set of cascaded inverters, the output signal being a filtered version of the input signal. Yet another aspect relates to a transceiver comprising a filter and a mixer coupled to the filter, the filter having a first set of cascaded inverters and a first set of one or more passive devices coupled to the first set of cascaded inverters.

Description

Technical Field

[0001] This patent application claims priority to pending U.S. Provisional Application No. 17 / 400,991, filed August 12, 2021, which is assigned to the assignee of this patent application and is hereby expressly incorporated herein by reference, as fully set forth below and for all applicable purposes.

[0002] The various aspects of this disclosure generally relate to filters and oscillators used in devices that communicate using wireless signals. Prior Technology

[0003] Active filters and gyrators in devices communicating with wireless signals typically employ operational amplifiers coupled to one or more passive components, such as capacitors, resistors, and inductors. Operational amplifiers are generally complex devices. For example, an operational amplifier may include input pairs of differential field-effect transistors (FETs), one or more current sources coupled between the sources of the differential FET pair and ground (or a negative voltage rail), passive and / or active output impedance components, a current mirror for controlling the current through the differential FET pair, a common-mode voltage control circuitry, and other circuitry depending on gain and / or other requirements. Therefore, operational amplifiers typically have a relatively large circuit or integrated circuit (IC) footprint, consume significant power, and may have relatively narrow bandwidth characteristics. Summary of the Invention

[0004] The following is a simplified summary of one or more implementations to provide a basic understanding of such implementations. This summary is not a comprehensive overview of all anticipated implementations, nor is it intended to identify key or fundamental elements of all implementations, nor to define the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed descriptions that follow.

[0005] One aspect of this disclosure relates to an apparatus. The apparatus includes a filter or a first rotator, the filter or the first rotator comprising: a first set of cascaded inverters; and a first set of one or more passive devices coupled to the first set of cascaded inverters.

[0006] Another aspect of this disclosure relates to a method. The method includes applying an input signal to an input of a first cascade inverter in a group of cascade inverters coupled to a group of one or more passive devices; and receiving an output signal from the group of cascade inverters, the output signal being a filtered version of the input signal.

[0007] Another aspect of this disclosure relates to a transceiver. The transceiver includes a filter and a mixer coupled to the filter, the filter including a first set of cascaded inverters and a first set of one or more passive devices coupled to the first set of cascaded inverters.

[0008] To achieve the foregoing and related objectives, one or more implementations include the features fully described below and specifically pointed out in the claims. The following description and figures illustrate certain illustrative aspects of one or more implementations in detail. However, these aspects indicate only a few of the various ways in which the principles of various implementations can be adopted, and the description of implementations is intended to include all such aspects and their equivalents. Simple Explanation of the Diagram

[0009] Figures 1A and 1B respectively show schematic diagrams of a set of example cascaded inverters and corresponding example operational amplifiers according to one aspect of this disclosure.

[0010] Figures 2A and 2B respectively show schematic diagrams of an example Rauch filter with a set of cascaded inverters and a corresponding example Rauch filter with an operational amplifier according to another aspect of this disclosure.

[0011] Figures 3A and 3B respectively show schematic diagrams of an example Tow-Thomas double second-order filter with a group of cascaded inverters according to another aspect of the present disclosure and a corresponding example Tow-Thomas double second-order filter with an operational amplifier.

[0012] Figures 4A and 4B respectively show schematic diagrams of an example Sallen-Key filter with a set of cascaded inverters and a corresponding example Sallen-Key filter with an operational amplifier according to another aspect of the present disclosure.

[0013] Figures 5A and 5B respectively show schematic diagrams of an example rotary transformer having a set of cascaded inverters and corresponding example shunt inductors according to another aspect of this disclosure.

[0014] Figures 6A and 6B respectively show schematic diagrams of another example rotary transformer according to another aspect of the present disclosure, having a set of cascaded inverters and corresponding example shunt inductors and resistors.

[0015] Figures 7A-7B show schematic diagrams of an example baseband filter with a group of cascaded inverters according to another aspect of this disclosure, and alternative details of the inductor of the baseband filter.

[0016] Figure 8 shows a block diagram of an example receiver according to another aspect of this disclosure.

[0017] Figure 9 shows a schematic diagram of an example power supply voltage generator for a set of cascaded inverters according to another aspect of this disclosure.

[0018] Figure 10 shows a schematic diagram of an example transmitter according to another aspect of this disclosure.

[0019] Figure 11 shows a schematic diagram of another example transmitter according to another aspect of this disclosure.

[0020] Figure 12 shows a flowchart of an example method for filtering a signal according to another aspect of this disclosure.

[0021] Figure 13 shows a block diagram of an example pseudo-differential filter according to another aspect of this disclosure.

[0022] Figure 14 shows a block diagram of an example wireless communication device according to another aspect of this disclosure. Implementation

[0023] The detailed descriptions that follow, illustrated with reference to the accompanying drawings, are intended as descriptions of various configurations and not as representations of the only configuration in which the concepts described herein can be practiced. The detailed descriptions include specific details intended to provide a thorough understanding of the various concepts. However, it will be clear to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid confusion with such concepts.

[0024] Baseband (BB) filters are typically used at the output of a mixer in a receiver. The mixer receives a radio frequency (RF) signal that has previously been received by at least one antenna (e.g., an antenna array) and amplified by a low-noise amplifier (LNA). The mixer mixes the RF signal with a local oscillator (LO) signal to generate a mixed signal. The mixed signal includes the received signal of interest ("target received signal") and unwanted signals. Unwanted signals may include, for example, high-frequency components of the mixed signal, external interference signals (sometimes called RF jammers or blockers) located near or within the passband of the target received signal, or leakage of transmission signals from related transmitters located near or within the passband of the target received signal. A mixer can down-convert an RF signal to a signal at (or near) the baseband frequency, or it can down-convert an RF signal to an intermediate frequency (IF) signal, and an additional mixer can down-convert an IF signal to a signal at (or near) the baseband frequency.

[0025] A combination of a baseband (BB) filter and an analog-to-digital converter (ADC), followed by an anti-aliasing filter, has been used to essentially filter out unwanted signals in the receiver. The BB filter removes some of the unwanted signals. ADCs typically operate at sampling rates significantly higher than the Nyquist rate to provide a clear frequency separation between image signals, and anti-aliasing filters can filter out most of the image and unwanted signals from the frequency band of the target received signal. However, the high sampling rate causes the ADC to consume considerable power to spread the frequency of the image signal to allow the BB filter and anti-aliasing filter to effectively eliminate unwanted signals.

[0026] FinFETs (especially those 14 nanometers (nm) or smaller) can provide highly efficient transduction gain (gm) that can be used in filters and gyrators. More specifically, a cascaded set of inverters implemented using FinFETs and tightly controlled by complementary metal-oxide-semiconductor (CMOS) processes can provide sufficient wideband transduction gain (gm) for use in filters and gyrators. In some examples, the FinFETs or transistors of the inverter can be biased near the transition region of their voltage transfer characteristic (VTC), and the inverter's output voltage can be essentially a linear function of its input voltage.

[0027] Some examples of inverters will be discussed below. However, other inverters can be implemented besides those illustrated and / or described (and / or using other process technologies and / or nodes besides those explicitly listed). For example, active load, passive load, and / or tuned load inverters can be used. In some examples, bias can be used to stabilize one or more of the inverters. For example, bias can be used with a DC feedback loop to stabilize the operation of at least one inverter. In some examples, bias may cause the in-to-out gain to be limited and kept in a well-controlled region. Furthermore, cascaded inverters can allow the total gain to increase to a desired value or range. In some examples, coupling a resistor between the output of one stage and the input of another stage (e.g., between the output of the inverter forming the output of the gyroscope equivalent circuit (described below) and the input of the inverter forming the input of the gyroscope equivalent circuit) can stabilize the DC node of the output inverter. In some examples, the circuit described with respect to Figure 9 can be used to control the inverter gain, for example, by making the inverter's transconductance gain (gm) inversely proportional to its associated resistance (as will be described in more detail below). Furthermore, other bias schemes and / or loops (e.g., DC feedback loops) can be used.

[0028] Therefore, the operational amplifiers typically used in active filters and gyrators can be replaced with a set of cascaded inverters to achieve the desired filter frequency response provided by the filter or the impedance reversal provided by the gyrator, as discussed in more detail herein. Filters can also employ gyrators to perform their filtering operation.

[0029] Although the filter (and cyclotron) examples discussed above have been described with reference to (baseband) receiver applications, it should be understood that the filters and cyclotrons described herein can be used in other applications, including transmitter applications.

[0030] Figure 1A illustrates a schematic diagram of a set of example cascaded inverters 100 according to one aspect of this disclosure. The set of cascaded inverters 100 may include an input inverter 110-1 configured to receive an input signal Si, which may be the output signal of a downconverter mixer in a receiver application, or the input signal of an upconverter mixer in a transmitter application. The set of cascaded inverters 100 may also include one or more intermediate inverters 110-2 to 110-N-1 between the input inverter 110-1 and the output inverter 110-N. It should be understood that the set of cascaded inverters 100 does not necessarily need to include intermediate inverters, as is the case with a pair of cascaded inverters. In such an embodiment, the set of cascaded inverters 100 includes two inverters. In other embodiments, the set of cascaded inverters 100 includes three inverters, as shown, or more than three inverters. As shown in the figure, the inverters are connected in series, where the output of the input inverter 110-1 is coupled to the input of the next inverter, the output of the next inverter is coupled to the input of the following inverter, and so on, until the output inverter 110-N.

[0031] As further discussed herein, for filtering and / or gyroscope applications, one or more other passive components (which may include, for example, one or more reactances and / or other passive components) may be coupled to the cascaded inverter group 100. In this respect, based on the application in which the cascaded inverter group 100 is employed, the output inverter 110-N may be configured to generate an output signal So, which may be a filtered version of the input signal Si. For example, to implement a Rauch filter, the filter may include at least one feedback capacitor and at least one resistor coupled to the cascaded inverter group 100. To implement a Tow-Thomas dual second-order filter, the filter may include multiple cascaded inverter groups, each including at least one feedback capacitor, at least one feedback resistor, or both. To implement a Sallen-Key filter, the filter may include at least one capacitor and at least one resistor coupled to the cascaded inverter group. To implement a gyroscope, the gyroscope may include at least one capacitor and / or at least one resistor coupled to the cascaded inverter group. This group of cascaded inverters can be used to implement more complex filters, which can be used in receiver and / or transmitter applications.

[0032] Figure 1B illustrates a schematic diagram of an example operational amplifier 150 according to another aspect of this disclosure. Operational amplifier 150 can be used in filter and gyroscope applications. As an example, an input signal Si can be applied to a first input terminal of operational amplifier 150 (e.g., a negative input terminal or a positive input terminal as shown). Operational amplifier 150 includes a second input terminal (e.g., a positive input terminal or a negative input terminal as shown), which is typically coupled to a voltage rail, such as ground (or a specific reference voltage) in many filter applications. Similar to this group of cascaded inverters 100, one or more additional components can be coupled to operational amplifier 150 to implement a specific filter or gyroscope application.

[0033] In filtering and gyroscope applications, operational amplifier 150 can be used as a transconductance gain (gm) component for active filter or gyroscope applications. In this regard, operational amplifier 150 includes an output terminal configured to generate an output signal So, which can be a filtered version of the input signal Si. As discussed in more detail below, the cascaded inverter group 100 can also be used as a transconductance gain (gm) component for active filter or gyroscope applications. Therefore, the cascaded inverter group 100 can replace operational amplifier 150 in filter or gyroscope applications. Using the cascaded inverter group 100 in filter or gyroscope applications offers several advantages over operational amplifier 150.

[0034] As previously described, operational amplifier 150 is typically a complex transistor-level circuit. For example, operational amplifier 150 may include a differential FET pair, one or more current sources or receivers coupled between the sources of the differential FET pair and ground (or a negative voltage rail), passive and / or active output impedance components, a current mirror for controlling the current through the differential FET pair, and / or a common-mode voltage control circuit system, and other circuit systems depending on gain and / or other requirements. In contrast, the cascaded inverter group may be a set of CMOS FINFETs, which significantly reduces complexity, requires less circuitry or integrated circuit (IC) space, consumes significantly less power, and can have a wider bandwidth. In some embodiments, the cascaded inverter group may be single-ended, having both single-ended inputs and single-ended outputs, wherein single-ended signals are transmitted between the inverters in the group. In some embodiments, the power supply coupled to the inverters may be lower than the power supply required by the operational amplifier. In some embodiments, the power supply coupled to the inverters is approximately 0.8V. The following describes several filter and gyroscope applications that use a set of cascaded inverters as transconductance (GM) components in filter and gyroscope applications.

[0035] Figure 2A shows a schematic diagram of an example Rauch filter 200 according to another aspect of this disclosure. The Rauch filter can be a low-pass filter, which, compared to other filters, is less sensitive to component variations. Compared to a single-pole filter, a Rauch filter can include a zero-pole and a complex pole to provide a steeper roll-off.

[0036] In this example, Rauch filter 200 includes a set of cascaded inverters 210-1 to 210-3 (e.g., three (3) in this example, but other numbers of cascaded inverters may be configured). Rauch filter 200 also includes a first resistor R1 coupled between the input (node) of Rauch filter 200 (where the input signal Si can be received) and the input of the first cascaded inverter 210-1 in the set. Rauch filter 200 may also include a feedback capacitor C connected between the output of the last cascaded inverter 210-3 in the set and the input of the first cascaded inverter 210-1. In addition, Rauch filter 200 may include a feedback resistor R2 connected between the output of the last cascaded inverter 210-3 and the input (node) of Rauch filter 200. Therefore, the first terminal of the first resistor R1 can be directly connected to the feedback resistor R2 (and the input of the Rauch filter 200), and the second terminal of the first resistor R1 can be directly connected to the feedback capacitor C (and connected to the input of the first cascaded inverter 210-1).

[0037] The output of the final inverter 210-3 is configured to generate an output signal So based on the filter frequency response of the Rauch filter 200, which is a filtered version of the input signal Si. The filter frequency response of the Rauch filter 200 depends on the resistances of the input and feedback resistors R1 and R2, and the capacitance of the feedback capacitor C. The Rauch filter 200 can also be used as a transimpedance amplifier (TIA). In this case, the input signal Si can be the input current, and the output signal So can be the output voltage. Additionally, in this example, the number of cascaded inverters in the group is three (3), which is an odd number (this can also be characterized as the number of cascaded inverters between the first and last cascaded inverters being odd). In this case, the feedback provided by the feedback capacitor C and the feedback resistor R2 is negative feedback due to the cascaded inverting operation.

[0038] Figure 2B shows a schematic diagram of an example Rauch filter 250 according to another aspect of this disclosure. In this example, the Rauch filter 250 is implemented using an operational amplifier 260. The Rauch filter 250 includes an input resistor R1 connected between the input (node) of the Rauch filter 250 (where the input signal Si is received) and the negative input terminal of the operational amplifier 260. The Rauch filter 250 includes a feedback capacitor C connected between the output of the operational amplifier 260 and the negative input. Furthermore, the Rauch filter 250 also includes a feedback resistor R2 connected between the output of the operational amplifier 260 and the input (node) of the Rauch filter 250. Although resistors R1 and R2 and capacitor C are identified as the same in both filters 200 and 250, it should be understood that the resistances of resistors R1 and R2 and the capacitance of capacitor C may differ in both filters 200 and 250. This will apply to all other comparisons between inverter-based filters and operational amplifier-based filters, as further described herein. As described above, compared to operational amplifier 260, the cascaded inverters 210-1 to 210-3 can be significantly less complex, requiring less circuitry or IC footprint, consuming significantly less power, and having a wider bandwidth.

[0039] Figure 3A illustrates a schematic diagram of an example Tow-Thomas dual second-order filter 300 according to another aspect of this disclosure. The Tow-Thomas dual second-order filter 300 can be configured as a low-pass filter (LPF) and / or a band-pass filter (BPF). The Tow-Thomas dual second-order filter 300 may include a first output and a second output, the first input being configured to generate a first output signal associated with a band-pass filtered input signal, and the second input being configured to generate a second output signal associated with a low-pass filtered input signal.

[0040] More specifically, the Tow-Thomas dual second-order filter 300 includes a first filter stage 310, which includes an input resistor R0, a first set of cascaded inverters 312-1 to 312-3, a feedback capacitor C1, and a feedback resistor R1, both of which are connected in parallel between the output of the last cascaded inverter 312-3 and the input of the first cascaded inverter 312-1. The input resistor R0 is coupled between the input of the Tow-Thomas dual second-order filter 300 (where the input signal Si is received) and the input of the first cascaded inverter 312-1. The output of the last cascaded inverter 312-3 is configured to generate a first output signal So1, which can be correlated with the input signal Si filtered by the first filter stage 310. The first filter stage 310 can be configured to apply a bandpass filter (BPF) frequency response to the input signal Si based on the resistance and capacitance of resistors R0 and R1 and capacitor C1 to generate a first output signal So1.

[0041] In this example, the Tow-Thomas dual second-order filter 300 includes a second filter stage 320, which includes an input resistor R2, a second set of cascaded inverters 322-1 to 322-3, and a feedback capacitor C2. The input resistor R2 is coupled between the output of the first filter stage 310 and the input of the first cascaded inverter 322-1 of the second filter stage 320. Therefore, the second filter stage 320 is configured to receive an output signal So1 from the first filter stage 310 at its input. The feedback capacitor C2 is connected between the output of the final cascaded inverter 322-3 and the input of the first cascaded inverter 322-1. The second filter stage 320 is configured to filter the output signal So1 of the first filter stage 310 based on the resistance of the input resistor R2 and the capacitance of the feedback capacitor C2 to generate an intermediate signal or a second output signal So2. In other words, the signal So2 can be applied to another device outside the Tow-Thomas dual second-order filter 300, in which case it is the second output signal; or, the signal So2 can be not applied to another device, in which case it is simply used as an intermediate signal of the Tow-Thomas dual second-order filter 300.

[0042] Furthermore, according to this example, the Tow-Thomas dual second-order filter 300 includes a third filter stage 330, which includes an input resistor R3, a third set of cascaded inverters 332-1 to 332-3, and a feedback resistor R4. The input resistor R3 is coupled between the output of the second filter stage 320 and the input of the first cascaded inverter 332-1 of the third filter stage 330. Therefore, the third filter stage 330 is configured to receive an output signal So2 from the second filter stage 320 at its input. The feedback resistor R4 is connected between the output of the last cascaded inverter 332-3 and the input of the first cascaded inverter 332-1. The third filter stage 330 is configured to filter the output signal So2 of the second filter stage 320 according to the resistance of the input resistor R3 and the feedback resistor R4 to generate either a second output signal or a third output signal So3. Cascaded filter stages 310, 320, and 330 can be configured to apply a low-pass filter (LPF) frequency response to the input signal Si based on the resistance of resistors R0 to R4 and the capacitance of capacitors C1 to C2 to generate a second output signal and / or a third output signal So3. A feedback resistor R5 is connected between the output of the final cascaded inverter 332-3 of the Tow-Thomas dual second-order filter 300 and the input of the first cascaded inverter 312-1.

[0043] Figure 3B shows a schematic diagram of an example Tow-Thomas dual second-order filter 350 according to another aspect of the present disclosure. In this example, the Tow-Thomas dual second-order filter 350 includes three (3) cascaded filter stages 360, 370 and 380, which include operational amplifiers 365, 375 and 385 with resistors R0-R5 and capacitors C1-C2, as shown. As discussed, compared to the three (3) operational amplifiers 365, 375 and 385 of the Tow-Thomas dual second-order filter 350, the complexity of the first group of cascaded inverters 312-1 to 312-3, the second group of cascaded inverters 322-1 to 322-3 and the third group of cascaded inverters 332-1 to 332-3 can be significantly reduced, requiring less circuitry or IC space, consuming significantly less power and having a wider bandwidth.

[0044] Figure 4A shows a schematic diagram of an example Sallen-Key filter 400 according to another aspect of this disclosure. The Sallen-Key filter 400 can be used to implement second-order active filter operation. Specifically, the Sallen-Key filter 400 includes a first input resistor R1, a second input resistor R2, an input capacitor C1, a set of cascaded inverters 410-1 to 410-4, a feedback capacitor C2, and a voltage divider including resistors R3 and R4. The first resistor R1 and the second resistor R2 are connected in series between the input (node) of the Sallen-Key filter 400 (where the input signal Si is received) and the input of the first cascaded inverter 410-1 in the set. The input capacitor C1 can be connected between node n1 (between resistors R1 and R2) and a voltage rail (e.g., ground). The feedback capacitor C2 is connected between the output of the last cascaded inverter 410-4 in the set and node n1. Resistors R3 and R4 are connected in series between the output of the last cascaded inverter 410-4 and the voltage rail (e.g., ground). Node n2 between resistors R3 and R4 is coupled to the output of the first inverter 410-1 in the group.

[0045] The output of the final cascaded inverter 410-4 is configured to generate an output signal So, which is related to an input signal Si that is filtered according to the filter frequency response of the Sallen-Key filter 400, which depends on the resistance of resistors R1-R4 and the capacitance of capacitors C1 and C2. Since the Sallen-Key filter 400 involves positive feedback via capacitor C2, the number of cascaded inverters in this group is four (4), but it can be another even number (or it can be characterized as the number of cascaded inverters between the first cascaded inverter and the final cascaded inverter being even or zero (0)). For stability purposes, the coupling of node n2 to the output of the first cascaded inverter 410-1 involves negative feedback because it spans an odd number (e.g., three (3)) of cascaded inverters 410-2 to 410-4.

[0046] In some respects, a cascaded inverter group includes a configuration in which two inverters in the group are directly connected together, and no other components are connected between them or to the node between them. For example, this configuration is shown in Figure 4A, where the output of inverter 410-2 is directly connected to the input of inverter 410-3. No other components are connected between inverters 410-2 and 410-3, nor are any other components connected to the node or connection between these inverters. Instead, the node between inverters 410-1 and 410-2 is connected to other components (e.g., resistors R3 and R4).

[0047] Figure 4B shows a schematic diagram of an example Sallen-Key filter 450 according to another aspect of this disclosure. In this example, the Sallen-Key filter 450 includes an operational amplifier 460, which includes input resistors R1 and R2, an input capacitor C1, a feedback capacitor C2, and a voltage divider including resistors R3 and R4, as shown in Figure 4B. As discussed, compared to the operational amplifier 460 of the Sallen-Key filter 450, the complexity of this group of cascaded inverters 410-1 to 410-4 can be significantly lower, requiring less circuitry or IC space, potentially consuming significantly less power, and can have a wider bandwidth.

[0048] Figure 5A illustrates a schematic diagram of an example gyroscope 500 according to another aspect of this disclosure. A gyroscope can be used to reverse the impedance of one or more passive devices. For example, a gyroscope can be used to reverse the impedance of a capacitor to produce the impedance of an inductor. Conversely, a gyroscope can be used to reverse the impedance of an inductor to produce the impedance of a capacitor. In this example, gyroscope 500 is configured to more generally reverse the impedance of a capacitor to produce the impedance of an inductor more generally. Because inductors are generally more difficult to implement in an IC and / or consume additional space, gyroscope 500 can be used in filters to implement inductors as needed to achieve the desired frequency response of the filter.

[0049] The gyroscope 500 includes a set of cascaded inverters 512-1 to 512-3, a shunt capacitor C, and a conductive feedback path 514 (e.g., substantially zero (0) or negligible resistance) connecting the output of the last cascaded inverter 512-3 to the input of the first cascaded inverter 512-1. The capacitor C is connected between the output of the first cascaded inverter 512-1 and a voltage rail (e.g., ground). A signal can be applied to the input of the gyroscope 500, for example, at the input of the first cascaded inverter 512-1. Due to impedance reversal, the input sees the impedance of the shunt inductor L 550, as shown in Figure 5B.

[0050] Figure 6A illustrates a schematic diagram of another example gyroscope 600 according to another aspect of this disclosure. Gyroscope 600 can be configured to implement the impedance of a resistive-loaded inductor. As further discussed herein, an inductor connected in series with a capacitor between the signal node and a voltage rail (e.g., ground) can be used to generate a relatively narrow frequency notch in the filter's frequency response. A resistive-loaded inductor connected in series with a capacitor between the signal node and a voltage rail (e.g., ground) can be used to generate a wider frequency notch in the filter's frequency response, where the width is related to the resistance of the resistor.

[0051] The gyrator 600 includes a set of cascaded inverters 612-1 to 612-3, a capacitor C, a resistor R, and a conductive feedback path 614 (e.g., essentially zero (0) or negligible resistance) connecting the output of the last cascaded inverter 612-3 to the input of the first cascaded inverter 612-1. The capacitor C and resistor are coupled in series between the output of the first cascaded inverter 612-1 and a voltage rail (e.g., ground). A signal can be applied to the input of the gyrator 600, for example, at the input of the first cascaded inverter 612-1. Due to impedance reversal, the input sees the impedance of the resistive load shunt inductor L 650, as shown in Figure 6B.

[0052] Figure 7A illustrates a schematic diagram of an example filter 700 according to another aspect of this disclosure. The filter 700 can be used for fundamental frequency (BB) filtering or for other applications. The filter 700 includes a first filter stage 710 cascaded with a second filter stage 720. An input signal Si, which may be an input current, is applied to the input of the first filter stage 710. As discussed in more detail herein, the first filter stage 710 performs a specific filtering operation on the input signal Si. The second filter stage 720 can be configured as a Rauch filter (as previously discussed with reference to Figure 2A) for low-pass filtering (LPF) of the filtered input signal Si to generate an output signal So. The second filter stage 720 can be configured as a transimpedance amplifier (TIA) for converting the input current signal Si into an output voltage signal So. In other embodiments, multiple filter stages having current inputs and voltage outputs can be coupled together via resistors to convert a voltage output from one stage into a current for input to a subsequent stage.

[0053] The first filter stage 710 includes a shunt capacitor C0 coupled in parallel with the input signal current source Si (representing the source of the input signal Si) between node n1 and a voltage rail (e.g., ground); a first resonator including a first capacitor C1 coupled in series with a first gyrator L1 (providing inductive impedance) between node n1 and a voltage rail (e.g., ground); a second resonator including a second capacitor C2 coupled in series with a second gyrator L2 (providing inductive impedance) between node n1 and a voltage rail (e.g., ground); and a third resonator including a third capacitor C1 coupled in series with a third gyrator L3 (providing inductive impedance) between node n1 and a voltage rail (e.g., ground). The first filter stage 710 includes frequency responses with three notch filters specified by the capacitances and inductances of C1-L1, C2-L2, and C3-L3.

[0054] The second filter stage 720 includes an input resistor R1, a set of cascaded inverters 722-1 to 722-3 (e.g., three (3) in this example, but different numbers of cascaded inverters can be configured, as described above), a feedback capacitor C4, and a feedback resistor R2. The first resistor R1 is connected between the output (node ​​n1) of the first filter stage 710 and the input of the first cascaded inverter 722-1 in the set. The feedback capacitor C4 is connected between the output of the last cascaded inverter 722-3 in the set and the input of the first cascaded inverter 722-1. The feedback resistor R2 is connected between the output of the last cascaded inverter 722-3 and the output (node ​​n1) of the first filter stage 710.

[0055] The output of the final inverter 722-3 is configured to generate an output signal So based on the filter frequency response of the cascaded first filter stage 710 and second filter stage 720. The output signal So is a filtered version of the input signal Si. For fundamental frequency filtering or other applications, the filter frequency response of the second filter stage 720 can provide a low-pass filter that includes a zero (0) at the fundamental edge of the passband of the signal of interest, and a pole for providing a roll-off above the zero (0) frequency to reject unwanted signals. The resistance of resistors R1-R2 and the capacitance of capacitor C4 can be set to achieve the desired filter frequency response of the second filter stage 720.

[0056] As described above, the first filter stage 710 can be configured to provide frequency notches at frequencies where leakage from the jammer / blocker and transmitter (Tx) to receiver may occur. For example, such jammer / blocker and Tx leakage may be located in the roll-off portion of the filter frequency response of the second filter stage 720. If higher suppression of these jammer / blocker and Tx leakage is desired, the notches of the first filter stage 710 can be positioned at the frequencies of these jammer / blocker and Tx leakage or the desired frequencies. Therefore, the suppression of these jammer / blocker and Tx leakage will be the cumulative suppression provided by the roll-off of the frequency response of the second filter stage 720 and the corresponding notches of the frequency response of the first filter stage 710. It should be understood that although three notches are shown in Figure 7A (e.g., corresponding to the capacitors and inductors C1-L1, C2-L2, and C3-L3, respectively), more (e.g., four or more) or fewer (zero to two) notches can be implemented in the filter 700. In some embodiments, multiple notch filters connected in series in the signal path (e.g., as shown in Figure 7A) can be used to implement a stopband.

[0057] Figure 7B shows a schematic diagram of two gyrators 750 and 760 according to another aspect of the present disclosure, wherein each gyrator may replace any one of the inductors L1, L2 and L3 of the first filter stage 710.

[0058] The gyroscope 750 includes a set of cascaded inverters 752-1 to 752-3, a capacitor C5 connected between the output of the first cascaded inverter 752-1 and a voltage rail (e.g., ground), and a conductive feedback path 754 coupling the output of the last cascaded inverter 752-3 to the input of the first cascaded inverter 752-1. The gyroscope 750, used as an inductive element, can be configured in conjunction with series capacitors (e.g., C1, C2, or C3 of the first filter stage 710) to produce a higher Q value or a relatively narrow frequency notch, since capacitor C5 has essentially no resistive load.

[0059] The gyroscope 760 includes a set of cascaded inverters 762-1 to 762-3, a capacitor C5 coupled in series with a resistor R between the output of the first cascaded inverter 762-1 and a voltage rail (e.g., ground), and a conductive feedback path 764 coupling the output of the final cascaded inverter 762-3 to the input of the first cascaded inverter 762-1. The gyroscope 760, acting as an inductive element, can be configured in conjunction with series capacitors (e.g., C1, C2, or C3 of the first filter stage 710) to produce a lower Q value or a relatively wide frequency notch when the resistor R loads the capacitor C5. The frequency width of the notch can be controlled by the resistance of the resistor R.

[0060] In some embodiments, each of inverters 752 or 762 is identical to the others. In some embodiments, each of inverters 722 is identical to the others. In some embodiments, each of inverters 752 or 762 consists of transistors configured to resemble the transistors in each inverter 722. For example, each of inverters 752 or 762 may include a PMOS transistor coupled to an NMOS transistor, and each of inverters 722 may include a PMOS transistor coupled to an NMOS transistor; all PMOS transistors in inverters 752 or 762 and 722 may have the same size and the same layout, and all NMOS transistors in inverters 752 or 762 and 722 may have the same size and the same layout.

[0061] As can be seen in Figures 7A and 7B, the (fundamental frequency) filter described herein can be implemented using only an inverter, capacitors, and resistors. For example, such a filter can be implemented without operational amplifiers (and some of their components, such as current sources) and / or inductors.

[0062] Figure 8 shows a block diagram of an example receiver 800 according to another aspect of this disclosure. Receiver 800 may be an example of an application of one of the aforementioned filters discussed above. Receiver 800 includes a mixer 810, a baseband (BB) filter 820, an in-band blocker 830, a bypass switching device SW, an analog-to-digital converter (ADC) 840, and a digital filter 850.

[0063] Mixer 810 includes a first input configured to receive an RF signal and a second input configured to receive a local oscillator (LO) signal. Mixer 810 includes an output for providing a mixed signal. Baseband (BB) filter 820 is configured to substantially remove unwanted signals from the mixed signal generated by mixer 810, including high-frequency components, out-of-band jammers / blockers, transmission signal leakage, etc., and the baseband (BB) filter 820 may be configured as filter 700 or any other filter previously discussed. In some embodiments, receiver 800 includes a cellular receiver, and filter 820 is configured to remove unwanted signals to improve coexistence with WiFi systems or subsystems included in a device in which receiver 800 is implemented. As previously discussed, the bipolar frequency response of filter 820, including notches carefully positioned in frequency to coincide with out-of-band jammers / blockers and transmission signal leakage, can substantially remove unwanted signals from the mixed signal at the output of mixer 810.

[0064] In-band blocker 830 can perform additional filtering to reduce unwanted signals that may be located within the passband of the received signal of interest. In-band blocker 830 can be selectively bypassed by a bypass switch SW coupled in parallel with in-band blocker 830. ADC 840 converts the filtered signal at the output of fundamental frequency filter 820 (if bypass switch SW is closed) or the output of in-band blocker 830 (if bypass switch SW is open) into a digital signal based on the sampling rate fs. Since fundamental frequency filter 820 (e.g., configured as described above according to filter 700) can substantially reject unwanted signals outside the frequency band, the requirement for sampling rate fs can be relaxed, and good isolation can be maintained at that frequency (e.g., when filter 820 is configured as single-ended rather than pseudo-differential, as may be required in a configuration including operational amplifiers). Furthermore, this operation of the baseband filter 820 allows for a larger RX input signal in the presence of interference, for example, by reducing the need to attenuate such input signal due to consideration of interference and the dynamic range of the ADC 840. This may result in a better SNR when blocking and / or using adjacent channels. The digital filter 850 can further remove high-frequency noise and interference from the digital signal generated by the ADC 840 to generate the output baseband (BB) signal.

[0065] Figure 9 illustrates a schematic diagram of an example bias voltage generator 900 according to another aspect of this disclosure, configured to generate a supply voltage Vdd_inv for a group of cascaded inverters, as described above. An example inverter 910 is depicted receiving the supply voltage Vdd_inv from the bias voltage generator 900; this example inverter 910 can be an example of any inverter shown and / or described with respect to Figures 1A-7B. The bias voltage generator 900 is configured to generate the supply voltage Vdd_inv to compensate for resistance variations in one or more resistors present in the aforementioned filter. Specifically, the bias voltage generator 900 can change the supply voltage Vdd_inv to change the transconductance gain (gm) of the cascaded inverter inversely proportional to the resistance of the one or more resistors present in the filter. Therefore, the change in the transconductance gain (gm) of the cascaded inverter compensates for the resistance variations of the resistor(s)(s) in the aforementioned filter with process and / or temperature variations.

[0066] More specifically, the bias voltage generator 900 includes a p-channel metal-oxide-semiconductor field-effect transistor (PMOS FET) M1 and an n-channel metal-oxide-semiconductor field-effect transistor (NMOS FET) M3 connected in series between a bias voltage rail Vbias1 and a lower voltage rail (e.g., ground). The PMOS FET M1 and NMOS FET M3 include gates coupled together and are configured to receive a first component of a voltage, which may be a differential bandgap voltage kVbg as shown, where k is the Boltzmann constant. The PMOS FET M1 and NMOS FET M3 include drains coupled together.

[0067] Additionally, the bias voltage generator 900 includes a PMOS FET M2 connected in series with the NMOS FET M4 between the bias voltage rail Vbiasl and a lower voltage rail (e.g., ground). The PMOS FET M2 and NMOS FET M4 include gates coupled together and are configured to receive a second component of a voltage, which may be the differential bandgap voltage kVbg as shown. The PMOS FET M2 and NMOS FET M4 also include drains coupled together.

[0068] The bias voltage generator 900 includes an NMOS FET M5, which includes a drain and a gate configured to receive a bias current Ibias, which can be related to the bandgap voltage Vbg divided by the resistance (Vbg / R) of the resistor R associated with the aforementioned filter. The NMOS FET M5 is coupled between the source of the bias current Ibias and a lower voltage rail (e.g., ground).

[0069] Additionally, the bias voltage generator 900 includes PMOS FET M6, NMOS FET M7, and NMOS FET M8 connected in series between a first higher voltage rail Vdd1 and a lower voltage rail (e.g., ground). Furthermore, the bias voltage generator 900 includes PMOS FET M9, NMOS FET M10, and NMOS FET M11 connected in series between the first higher voltage rail Vdd1 and the lower voltage rail (e.g., ground). PMOS FETs M6 and M9 include gates coupled together and coupled to the drain of PMOS FET M6. NMOS FETs M7 and M10 include gates configured to receive a second bias voltage Vbias2. NMOS FETs M7 and M10 also include sources coupled to the drains of NMOS FETs M3 and M4, respectively. NMOS FETs M8 and M11 include gates coupled to the gate of NMOS FET M5.

[0070] Furthermore, the bias voltage generator 900 includes an NMOS FET M12 connected in series with an NMOS FET M13 between a second higher voltage rail Vdd2 and a lower voltage rail (e.g., ground). The first higher voltage rail Vdd1 may have a different supply voltage than the second higher voltage rail Vdd2. In some respects, Vdd1 may be higher than Vdd2. For example, Vdd1 may be approximately 1.2V, while Vdd2 may be approximately 0.8V. Additionally, the bias voltage generator 900 includes an NMOS FET M14 connected in series with an NMOS FET M15 between the second higher voltage rail Vdd2 and the lower voltage rail (e.g., ground). NMOS FETs M12 and M14 include gates coupled to the drain of a PMOS FET M9. NMOS FETs M13 and M15 include gates coupled to the gates of NMOS FETs M5, M8, and M11. The bias voltage Vbias1 associated with the Vbias1 voltage rail is generated at the source of NMOS FET M12, which is coupled to the sources of PMOS FETs M1 and M2.

[0071] The bias voltage generator 900 includes a first capacitor C1 connected between the drain of the PMOS FET M9 and a lower voltage rail (e.g., ground). Additionally, the bias voltage generator 900 includes a second capacitor C2 coupled between the source of the NMOS FET M14 and a lower voltage rail (e.g., ground). The supply voltage Vdd_inv is generated at the source of the NMOS FET M14 (i.e., across the second capacitor C2). When the control loop of the bias voltage generator 900 is stable, the bias voltage Vdd_inv, varying with process and / or temperature, inversely adjusts the transconductance gain (gm) of the inverter 910 in relation to the resistance of a resistor associated with the filter.

[0072] Figure 10 illustrates a schematic diagram of an example transmitter 1000 according to another aspect of this disclosure. Although the filters and / or rotators discussed herein have been described with reference to receiver applications, such as in the case of receiver 800, it should be understood that filters and / or rotators can also be used in transmitter applications. Transmitter 1000 is an example of a transmitter application employing filters as described herein.

[0073] More specifically, transmitter 1000 includes a digital carrier aggregator (CA) 1010 configured to generate a digital baseband transmission signal (BBTX) and a digital-to-analog converter (DAC) 1020 configured to convert the digital baseband transmission signal BBTX into an analog baseband transmission signal Si. However, it should be understood that in other configurations, the BBTX signal does not include the carrier aggregation signal, and the source of the BBTX signal may include other circuitry besides the digital CA 1010 (e.g., in the modem of a mobile device). Transmitter 1000 also includes a pair of cascaded filter stages 1030 and 1040 configured to filter the analog baseband transmission signal Si to remove signal mirroring, noise, and / or other unwanted signals to generate a filtered analog baseband transmission signal So. In transmitter applications, the filtered analog baseband transmission signal So can be directly up-converted to a radio frequency (RF) signal or up-converted to an intermediate frequency (IF) signal and then up-converted to an RF signal. Therefore, the output of filter stage 1040 can be coupled to a mixer (not shown), and filter stage 1040 is configured to provide the filtered analog baseband transmission signal So to the mixer. In other embodiments, filter stage 1040 is omitted, and filter stage 1030 is coupled to the mixer and configured to provide the filtered analog baseband signal to the mixer. In other embodiments, one or both of the first filter stage 1030 and the second filter stage 1040 can be replaced with different types of filters (e.g., as described above, which may include notch filters), and / or one or more additional filters can be coupled between the output of the second filter stage 1040 and the mixer.

[0074] The first-stage filter 1030 can be configured as a Rauch filter, such as the Rauch filter 200 previously described. The first-stage filter 1030 includes an input capacitor C1, an input resistor R1, a set of cascaded inverters 1032-1 to 1032-3, a feedback capacitor C2, and a feedback resistor R2. The input capacitor C1 is connected between the input (node) of the first filter stage 1030 (where signal Si is received) and a lower voltage rail (e.g., ground). The input resistor R1 is connected between the input (node) of the first filter stage 1030 and the input of the first cascaded inverter 1032-1. The feedback capacitor C2 is connected between the output of the last cascaded inverter 1032-3 and the input of the first cascaded inverter 1032-1. The feedback resistor R2 is connected between the output of the last cascaded inverter 1032-3 and the input (node) of the first filter stage 1030.

[0075] The second filter stage 1040 can also be configured as a Rauch filter, such as the Rauch filter 200 described previously. The second-stage filter 1040 includes a first input resistor R3, an input capacitor C3, a second input resistor R4, a set of cascaded inverters 1042-1 to 1042-3, a feedback capacitor C4, and a feedback resistor R5. The first input resistor R3 is coupled between the output of the first filter stage 1030 and node n1. The input capacitor C3 is connected between node n1 and a lower voltage rail (e.g., ground). The second input resistor R4 is connected between node n1 and the input of the first cascaded inverter 1042-1. The feedback capacitor C4 is connected between the output of the last cascaded inverter 1042-3 and the input of the first cascaded inverter 1042-1. The feedback resistor R5 is connected between the output of the last cascaded inverter 1042-3 and node n1. The output of the last cascaded inverter 1042-3 is configured to produce a filtered output signal S o.

[0076] Figure 11 shows a schematic diagram of another example transmitter 1100 according to another aspect of this disclosure. Transmitter 1100 is another example in which the filter described herein can be used to filter a signal generated by a digital-to-analog converter (DAC).

[0077] More specifically, transmitter 1100 includes a first-channel carrier component (CC) signal generator 1110-1, a first-channel DAC 1120-1, a first-channel baseband filter (BBF) 1130-1, and a first-channel mixer 1140-1. Transmitter 1100 may also include a second-channel carrier component (CC) signal generator 1110-2, a second-channel DAC 1120-2, a second-channel baseband filter (BBF) 1130-2, and an adder 1145. Additionally, transmitter 1100 may also include a third-channel carrier component (CC) signal generator 1110-3, a third-channel DAC 1120-3, a third-channel baseband filter (BBF) 1130-3, and a third-channel mixer 1140-3. Any of the baseband filters (BBFs) 1130-1, 1130-2, and 1130-3 can be configured as any filter comprising a set of cascaded inverters as described herein. In other embodiments, one or more BBF 1130s may be configured using operational amplifiers or otherwise without a set of cascaded inverters. Therefore, while transmitter 1100 may include the filters(s) described herein using a set of cascaded inverters, transmitter 1100 is not limited to such a configuration. In such other embodiments, BBF 1130 may use any other known configuration of a baseband filter.

[0078] Transmitter 1100 also includes a phase-locked loop (PLL) 1160 configured to generate a reference oscillator signal REF, and a frequency divider 1170 configured to generate local oscillator (LO) signals LO1 and LO2 based on the reference oscillator signal VREF (e.g., by dividing the frequency of the reference oscillator signal VREF). Frequency divider 1170 includes outputs coupled to the inputs of mixers 1140-1 and 1140-3 (where the LO1 and LO2 signals are generated). First mixer 1140-1 performs frequency conversion on the signal generated by BBF 1130-1 based on the LO1 signal. Second mixer 1140-3 performs frequency conversion on the signal generated by BBF 1130-3 based on the LO2 signal. The mixed signals from mixers 1140-1 and 1140-3 are applied to the input of adder 1145, and the signal from the output of BBF 1130-2 is also applied to another input of adder 1145. Adder 1145 adds the signals from mixers 1140-1 and 1140-3 and BBF 1130-2 to generate a carrier aggregation (CA) baseband signal. In some embodiments, the LO1 and LO2 signals have approximately equal frequencies of opposite polarities centered at zero. For example, LO1 and LO2 may have frequencies of several hundred (e.g., 300-500, or about 400) MHz. DAC 1120 may have an operating frequency greater than the frequencies of the LO1 and LO2 signals (e.g., greater than 500 MHz, such as about 600 MHz). BBF 1130 may have a bandwidth less than the frequencies of the LO1 and LO2 signals (e.g., less than 300 MHz, such as about 200 MHz).

[0079] Mixer 1150 includes a first input coupled to the output of adder 1145 (where the CA baseband signal is generated), and a second input for receiving the intermediate frequency (LO). Mixer 1150 mixes the CA baseband signal with the IF LO to generate an IF signal Sif. In some embodiments, the frequency of the IF LO signal is at least several orders of magnitude higher than the frequencies of the LO1 and LO2 signals. For example, the IF LO signal may have a frequency approximately 20 to 30 times that of the LO1 and LO2 signals. The IF signal Sif can then be filtered by, for example, any filter described herein or by another filter. The IF signal Sif can be further up-converted to generate an RF signal for transmission.

[0080] Figure 12 illustrates a flowchart of an example method 1200 for filtering an input signal according to another aspect of this disclosure. Method 1200 includes applying an input signal to the input of a first cascade inverter in a group of cascade inverters coupled to a group of one or more passive devices (block 1210); and outputting an output signal from the group of cascade inverters, the output signal being a filtered version of the input signal (block 1220).

[0081] Figure 13 shows a block diagram of an example pseudo-differential filter 1300 according to another aspect of this disclosure. The pseudo-differential filter 1300 includes a positive filter differential component 1310 and a negative filter differential component 1320. Each of the positive filter differential component 1310 and the negative filter differential component 1320 can be configured as any filter previously discussed, including a set of cascaded inverters, such as filters 200, 300, 400, and 700. Both the positive filter differential component 1310 and the negative filter differential component 1320 can be configured identically, wherein the resistors and capacitors constituting the positive filter differential component 1310 and the negative filter differential component 1320 have substantially the same resistor(s) and capacitor(s).

[0082] Input differential signals Si+ and Si- are applied to the inputs of the positive filter differential component 1310 and the negative filter differential component 1320, respectively. The positive filter differential component 1310 and the negative filter differential component 1320 are configured to filter the input differential signals Si+ and Si- to generate output differential signals So- and So+, respectively. The polarities between the input and output differential signals can be opposite, as most filters described herein employ negative feedback. However, positive feedback filters can have the same polarity, such as the Sallen-Key filter 400 discussed previously.

[0083] Figure 14 shows a block diagram of an example wireless communication device 1400 according to another aspect of this disclosure. Examples of the wireless communication device 1400 include cellular or mobile phones (e.g., smartphones), user terminals, personal computers, laptops, tablet devices, customer premises equipment (CPE), smartwatches and other personal wireless devices, wireless medical devices, vehicle (automotive) wireless devices, etc. The wireless communication device 1400 includes an integrated circuit (IC) 1410, which can be configured as a system-on-a-chip (SOC). The SOC 1410 may include a group of one or more digital signal processing cores 1420. The group of one or more digital signal processing cores 1420 can be configured to generate and / or process baseband (BB) signals, which can be received, for example, from a filter having a group of cascaded inverters as described herein, or can be provided to such a filter.

[0084] The wireless communication device 1400 also includes a transceiver 1450, which may include a filter and / or gyroscope 1460 having a set of cascaded inverters, as described herein. The filter and / or gyroscope 1460 may be used (in combination with other circuitry) to convert the BB signal received from the SOC 1410 into a radio frequency (RF) signal for application to the antenna 1470 for transmission to one or more remote devices. Alternatively, the filter and / or gyroscope 1460 may be used (in combination with other circuitry) to convert the RF signal received via the antenna 1470 into a BB signal for application to the SOC 1410 for further processing by the set of one or more digital signal processing cores 1420.

[0085] In some embodiments, the filter and / or gyrator 1460 may have a relatively wide bandwidth (e.g., several hundred MHz, such as 500-600 MHz or about 800 MHz or more), which may be advantageous when the transceiver 1450 operates using signals at millimeter-wave (mmW) frequencies. In some such embodiments, channels at mmW frequencies can have a wider bandwidth compared to channels established in older communication standards. These wide bandwidths can be achieved in low-noise, low-power, and / or high-linearity configurations.

[0086] As a more specific example of receiver application, wireless cellular networks such as Long Term Evolution (LTE) and New 5G include channel B25, which extends from 1930MHz to 1995MHz for downlink operation. Therefore, the baseband receive bandwidth is -32.5MHz to +32.5MHz. The associated transmission signal can extend from 1850MHz to 1915MHz. To prevent transmission signal leakage to the receiver baseband circuitry, the receiver baseband filter can be configured to have a stopband that begins at 47.5MHz below the low-voltage side of the passband of the B25 channel at the baseband. For example, a filter 700 including a second stage 720 in a Rauch configuration and a notch filter 700 generated by capacitor-inductor shunt resonances (C1-L1, C2-L2, and C3-L3) can be configured to provide the required frequency response to accommodate the passband and stopband of the B25 channel. For example, the filter can be configured to be zeroed to obtain a stopband greater than 20dB; thus making the filtered signal essentially the same level as the blocked signal in the frequency band.

[0087] The following provides an overview of aspects of this disclosure:

[0088] Aspect 1: An apparatus, filter, or first rotator, comprising: a first group of cascaded inverters; and a first group of one or more passive devices coupled to the first group of cascaded inverters.

[0089] Aspect 2: The apparatus according to aspect 1, wherein the first group of one or more passive devices of the filter is connected between the input of the first cascade inverter in the first group of cascade inverters and the output of the second cascade inverter in the first group of cascade inverters.

[0090] Aspect 3: The apparatus according to aspect 1 or 2, wherein the number of one or more cascaded inverters between the first cascaded inverter and the second cascaded inverter in the first group of cascaded inverters is odd.

[0091] Aspect 4: The apparatus according to any one of Aspects 1 to 3, wherein the first group of one or more passive devices includes a capacitor.

[0092] Aspect 5: The apparatus according to any one of Aspects 1 to 4, wherein the first group of one or more passive devices comprises: a first resistor connected between the input of the filter and the input of the first cascade inverter in the first group of cascade inverters; and a second resistor connected between the input of the filter and the output of the second cascade inverter in the first group of cascade inverters.

[0093] Aspect 6: The apparatus according to any one of Aspects 1 to 5, wherein the filter is configured to provide a filter frequency response of the Rauch filter.

[0094] Aspect 7: The apparatus according to Aspect 1, wherein the filter includes a first filter stage, the first filter stage including: a first group of cascaded inverters; and a first group of one or more passive devices coupled to the first group of cascaded inverters, wherein the first group of one or more passive devices includes: a first resistor connected between the input of the first filter stage and the input of the first cascaded inverter in the first group of cascaded inverters; and a second resistor, coupled in parallel with a first capacitor between the input of the first cascaded inverter in the first group of cascaded inverters and the output of the second cascaded inverter in the first group of cascaded inverters.

[0095] Aspect 8: The apparatus according to Aspect 7, wherein the filter further comprises a second filter stage, the second filter stage comprising: a second group of cascaded inverters; and a second group of one or more passive devices coupled to the second group of cascaded inverters, wherein the second group of one or more passive devices comprises: a third resistor connected between the output of the second cascaded inverter in the first group of cascaded inverters of the first filter stage and the input of the first cascaded inverter in the second group of cascaded inverters; and a second capacitor connected between the input of the first cascaded inverter in the second group of cascaded inverters and the output of the second cascaded inverter in the second group of cascaded inverters.

[0096] Aspect 9: The apparatus according to Aspect 7 or 8, wherein the filter further comprises a third filter stage, the third filter stage comprising: a third group of cascaded inverters; and a third group of one or more passive devices coupled to the third group of cascaded inverters, wherein the third group of one or more passive devices comprises: a fourth resistor connected between the output of the second cascaded inverter in the second group of cascaded inverters of the second filter stage and the input of the first cascaded inverter in the third group of cascaded inverters; and a fifth resistor connected between the input of the first cascaded inverter in the third group of cascaded inverters and the output of the second cascaded inverter in the third group of cascaded inverters.

[0097] Aspect 10: The apparatus according to aspect 9 further includes a sixth resistor connected between the input of the first cascaded inverter in the first group of cascaded inverters of the first filter stage and the output of the second cascaded inverter in the third group of cascaded inverters of the third filter stage.

[0098] Aspect 11: The apparatus according to aspect 9 or 10, wherein the first filter stage provides a bandpass filter (BPF) frequency response, and wherein the first filter stage, the second filter stage and the third filter stage together provide a low-pass filter (LPF) frequency response.

[0099] Aspect 12: The apparatus according to any one of Aspects 7 to 11, wherein the filter is configured to provide the filter frequency response of a Tow-Thomas dual second-order filter.

[0100] Aspect 13: The apparatus according to Aspect 1, wherein the first group of one or more passive devices of the filter comprises: a first resistor connected between the input of the filter and a first node; a second resistor connected between the first node and the input of a first cascade inverter in the first group of cascade inverters; a first capacitor connected between the first node and a voltage rail; a second capacitor connected between the first node and the output of a second cascade inverter in the first group of cascade inverters; and a third resistor and a fourth resistor connected in series between the output of the second cascade inverter in the first group of cascade inverters and the voltage rail, wherein a second node between the third resistor and the fourth resistor is coupled to the output of the first cascade inverter in the first group of cascade inverters.

[0101] Aspect 14: The apparatus according to any one of Aspects 1 to 13, wherein the number of cascaded inverters between the first cascaded inverter and the second cascaded inverter in the first group of cascaded inverters is zero (0) or an even number.

[0102] Aspect 15: The apparatus according to aspect 1, 13 or 14, wherein the filter is configured to provide the filter frequency response of a Sallen-Key filter.

[0103] Aspect 16: The apparatus according to Aspect 1, wherein the first group of one or more passive devices of the first rotator are connected between the output of the first cascade inverter in the first group of cascade inverters and the voltage rail, wherein the first rotator further includes an electrical conductor connected between the input of the first cascade inverter in the first group of cascade inverters and the output of the second cascade inverter in the first group of cascade inverters.

[0104] Aspect 17: The apparatus according to aspect 13 or 16, wherein the voltage rail includes grounding.

[0105] Aspect 18: The apparatus according to any one of aspects 1, 10, 11 or 17, wherein the first group of one or more passive devices includes a capacitor.

[0106] Aspect 19: The apparatus according to any one of Aspects 1 to 18, wherein the first group of one or more passive devices includes a capacitor connected in series with a resistor.

[0107] Aspect 20: The apparatus according to any one of Aspects 1 to 10, wherein the filter includes a first filter stage, the first filter stage including the first gyroscope, the first gyroscope being connected between the node and the voltage rail.

[0108] Aspect 21: The apparatus according to aspect 20, wherein the voltage rail includes grounding.

[0109] Aspect 22: The apparatus according to any one of Aspects 1 to 21, wherein the first rotator comprises: a first set of cascaded inverters, wherein the input of the first cascaded inverter in the first set of cascaded inverters serves as the node; a first electrical conductor connected between the input of the first cascaded inverter in the first set of cascaded inverters and the output of the second cascaded inverter in the first set of cascaded inverters; and a first set of one or more passive devices connected between the output of the first cascaded inverter in the first set of cascaded inverters and the voltage rail.

[0110] Aspect 23: The apparatus according to any one of Aspects 20 to 22, wherein the first filter stage further comprises a second gyroscope connected between the node and the voltage rail.

[0111] Aspect 24: The apparatus according to any one of Aspects 20 to 23, wherein the second rotator comprises: a second set of cascaded inverters, wherein the input of the first cascaded inverter in the second set of cascaded inverters serves as the node; a second electrical conductor connected between the input of the first cascaded inverter in the second set of cascaded inverters and the output of the second cascaded inverter in the second set of cascaded inverters; and a second set of one or more passive devices connected between the output of the first cascaded inverter in the second set of cascaded inverters and the voltage rail.

[0112] Aspect 25: The apparatus according to any one of Aspects 20 to 24, wherein the first filter stage further comprises a third rotator connected between the node and the voltage rail.

[0113] Aspect 26: The apparatus according to any one of Aspects 20 to 25, wherein the third rotator comprises: a third set of cascaded inverters, wherein the input of the first cascaded inverter in the third set of cascaded inverters serves as the node; a third electrical conductor connected between the input of the first cascaded inverter in the third set of cascaded inverters and the output of the second cascaded inverter in the third set of cascaded inverters; and a third set of one or more passive devices connected between the output of the first cascaded inverter in the third set of cascaded inverters and the voltage rail.

[0114] Aspect 27: The apparatus according to any one of Aspects 20 to 26, wherein the filter comprises a second filter stage, the second filter stage comprising: a first group of cascaded inverters; and a first group of one or more passive devices, wherein the first group of one or more passive devices comprises: a first resistor connected between the node and the input of the first cascaded inverter in the first group of cascaded inverters; a second resistor connected between the node and the output of the second cascaded inverter in the first group of cascaded inverters; and a capacitor connected between the input of the first cascaded inverter in the first group of cascaded inverters and the output of the second cascaded inverter in the first group of cascaded inverters.

[0115] Aspect 28: The apparatus according to any one of Aspects 1 to 27, wherein the first group of one or more passive devices includes a resistor, and the apparatus further includes a voltage generator configured to generate a power supply voltage for the first group of cascaded inverters, the power supply voltage being configured to change the transconductance gain of the first group of cascaded inverters inversely proportional to the resistance of the resistor in response to process and / or temperature variations associated with the filter or the first gyrator.

[0116] Aspect 29: The apparatus according to any one of Aspects 1 to 28, wherein the filter comprises a positive filter differential component and a negative filter differential component, wherein the positive filter differential component comprises: a first group of cascaded inverters; and a first group of one or more passive devices coupled to the first group of cascaded inverters; and wherein the negative filter differential component comprises: a second group of cascaded inverters; and a second group of one or more passive devices coupled to the second group of cascaded inverters.

[0117] Aspect 30: The apparatus according to any one of Aspects 1 to 29 further includes a mixer configured to mix a radio frequency (RF) signal with a local oscillator (LO) signal to generate a mixed signal, wherein the filter is configured to filter the mixed signal to generate an analog baseband signal; a bypassable in-band blocker configured to reduce unwanted signals located in the passband of a received signal of interest from the analog baseband signal; an analog-to-digital converter (ADC) configured to digitize the analog baseband signal or the analog signal generated by the in-band blocker; and a digital filter configured to filter the digital signal from the ADC to generate a baseband digital signal.

[0118] Aspect 31: The apparatus according to any one of Aspects 1 to 30, wherein the filter does not include an inductor or an operational amplifier.

[0119] Aspect 32: The apparatus according to any one of aspects 1 to 31, wherein the filter comprises an inverter, a capacitor, and a resistor.

[0120] Aspect 33: The apparatus according to any one of aspects 1 to 32, wherein the filter is configured to filter an analog fundamental frequency signal.

[0121] Aspect 34: The apparatus according to any one of Aspects 1 to 33, wherein the first cascade inverter and the second cascade inverter in the first group of cascade inverters are directly connected together, and no other element is connected between the first cascade inverter and the second cascade inverter or to a node between the first cascade inverter and the second cascade inverter.

[0122] Aspect 35: The apparatus according to any one of aspects 1 to 34, wherein the first group of one or more passive devices includes one or more reactances.

[0123] Aspect 36: A method comprising: applying an input signal to an input of a first cascade inverter in a group of cascade inverters coupled to a group of one or more passive devices; and receiving an output signal from the group of cascade inverters, the output signal being a filtered version of the input signal.

[0124] Aspect 37: A transceiver comprising: a filter including: a first group of cascaded inverters; and a first group of one or more passive devices coupled to the first group of cascaded inverters; and a mixer coupled to the filter.

[0125] Aspect 38: The transceiver according to aspect 37 further includes: a first signal generator configured to generate a first digital signal; and a first digital-to-analog converter (DAC) configured to generate a first analog signal based on the first digital signal, wherein the first filter is configured to filter the first analog signal to generate a first filtered analog signal, and wherein the first mixer is configured to mix the first filtered analog signal with a first local oscillator (LO) signal to generate a first transmission signal.

[0126] Aspect 39: The transceiver according to aspect 38 further includes: a second filter, comprising: a second set of cascaded inverters; and a second set of one or more passive devices coupled to the second set of cascaded inverters; and a second mixer coupled to the second filter; a second signal generator configured to generate a second digital signal; and a second digital-to-analog converter (DAC) configured to generate a second analog signal based on the second digital signal, wherein the second filter is configured to filter the second analog signal to generate a second filtered analog signal, and wherein the second mixer is configured to mix the second filtered analog signal with a second local oscillator (LO) signal to generate a second transmission signal.

[0127] Aspect 40: The transceiver according to any one of Aspects 37 to 39 further includes: a third filter comprising: a third group of cascaded inverters; and a third group of one or more passive devices coupled to the third group of cascaded inverters; a third signal generator configured to generate a third digital signal; a third digital-to-analog converter (DAC) configured to generate a third analog signal based on the third digital signal, wherein the third filter is configured to filter the third analog signal to generate a third transmission signal; and an adder for adding the first transmission signal, the second transmission signal, and the third transmission signal to generate a carrier aggregation transmission signal.

[0128] Aspect 41: The transceiver according to any one of Aspects 37 to 40 further includes a third mixer configured to mix the carrier aggregation transmission signal with a third local oscillator (LO) signal to generate an intermediate frequency (IF) or radio frequency (RF) transmission signal.

[0129] The foregoing description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

[0130] 100: Cascaded Inverter 110-1, 110-2, 110-N: Inverters 150: Operational amplifier 200: Filter 210-1, 210-2, 210-3: Cascaded Inverters 250: Filter 260: Operational Amplifier 300: Tow-Thomas dual second-order filter 310: First filter stage 320: Second filter stage 330: Third filter stage 312-1, 312-2, 312-3: First group of cascaded inverters 322-1, 322-2, 322-3: Second group of cascaded inverters 332-1, 332-2, 332-3: Third group of cascaded inverters 350: Tow-Thomas dual second-order filter 360: Cascaded Filter Stage 365: Operational Amplifier 370: Cascaded Filter Stage 375: Operational Amplifier 380: Cascaded Filter Stage 385: Operational Amplifier 400: Filter 410-1, 410-2, 410-3, 410-4: Cascaded Inverters 450: Filter 460: Operational Amplifier 500: Rotary 512-1, 512-2, 512-3: Cascaded Inverters 514: Conductive Feedback Path 550: Shunt inductor 600: Rotary 612-1, 612-2, 612-3: Cascaded Inverters 614: Conductive Feedback Path 650: Resistive Load Shunt Inductor 700: Filter 710: First filter stage 720: Second filter stage 722-1, 722-2, 722-3: Cascaded Inverters 750: Rotary Gear 752-1, 752-2, 752-3: Cascaded Inverters 754: Conductive Feedback Path 760: Rotary 762-1, 762-2, 762-3: Cascaded Inverters 764: Conductive Feedback Path 800: Receiver 810: Mixer 820: Filter 830: In-band blocker 840: Analog-to-Digital Converter (ADC) 850: Digital Filter 900: Bias Voltage Generator 910: Inverter 1000: Transmitter 1010: Digital Carrier Aggregator (CA) 1030: Filter stage 1032-1, 1032-2, 1032-3: Cascaded Inverters 1040: Filter stage 1042-1, 1042-2, 1042-3: Cascaded Inverters 1100: Transmitter 1110-1, 1110-2, 1110-3: Channel Carrier Component (CC) Signal Generator 1120-1, 1120-2, 1120-3: Channel DAC 1130-1, 1130-2, 1130-3: Channel Fundamental Frequency Filter (BBF) 1140-1, 1140-3: Channel mixers 1145: Adder 1150: Mixer 1160: Phase-Locked Loop (PLL) 1200: Method 1210, 1220: Steps 1300: Pseudo-differential filter 1310: Positive filter differential component 1320: Negative Filter Differential Component

Claims

1. A device for communication, comprising: A filter, configured to receive and filter an input signal to generate an output signal, includes a first filter stage and a second filter stage. The first filter stage includes: a first group of cascaded inverters; a first group of one or more passive devices coupled to the first group of cascaded inverters, wherein the first group of one or more passive devices is connected between the output of the first cascaded inverter in the first group of cascaded inverters and a voltage rail; and an electrical conductor extending in a feedback path from the input of the first cascaded inverter in the first group of cascaded inverters to the output of the second cascaded inverter in the first group of cascaded inverters, without any intermediate components. The second filter stage includes: a second group of one or more cascaded inverters; and a second group of one or more passive devices connected between the input of the first cascaded inverter in the second group of cascaded inverters and the output of the second cascaded inverter in the second group of cascaded inverters; and a signal generator located outside the filter, configured to generate the input signal and provide it to the filter, wherein the output of the first filter stage is coupled to the input of the second filter stage.

2. The apparatus according to claim 1, wherein the number of one or more cascaded inverters between the first cascaded inverter and the second cascaded inverter in the first group of cascaded inverters is odd.

3. The apparatus according to claim 1, wherein the first group of one or more passive devices includes a capacitor.

4. The apparatus according to claim 1, wherein the second group of one or more passive devices comprises: A first resistor is connected between the input of the second filter stage and the input of the first cascade inverter in the second set of cascaded inverters; And a second resistor, which is connected between the input of the second filter stage and the output of the second cascade inverter in the second set of cascade inverters.

5. The apparatus according to claim 1, wherein the second filter stage is configured to provide a Rauch filter.

6. The apparatus according to claim 1, wherein the voltage rail includes a ground.

7. The apparatus according to claim 1, wherein the first group of one or more passive devices includes a capacitor, or wherein the first group of one or more passive devices includes a capacitor connected in series with a resistor.

8. The apparatus according to claim 1, wherein the first filter stage does not include an inductor or an operational amplifier.

9. The apparatus according to claim 1, wherein the input signal includes an analog baseband signal.

10. The apparatus of claim 1, wherein the filter is configured to achieve at least 20 dB of suppression in the stopband.

11. The apparatus according to claim 1, wherein the second group of one or more passive devices comprises: A first resistor is connected between the input of the second filter stage and the input of the first cascade inverter in the second set of cascaded inverters; A second resistor is connected between the input of the second filter stage and the output of the second cascade inverter in the second set of cascade inverters; and a capacitor is connected between the input of the first cascade inverter in the second set of cascade inverters and the output of the second cascade inverter in the second set of cascade inverters.

12. A communication apparatus comprising a first filter stage, the first filter stage including a first gyrator connected between a node and a voltage rail, the first gyrator comprising: A first group of cascaded inverters; a first group of one or more passive devices coupled to the first group of cascaded inverters, wherein the first group of one or more passive devices is connected between the output of the first cascaded inverter in the first group of cascaded inverters and the voltage rail; and an electrical conductor extending in a feedback path from the input of the first cascaded inverter in the first group of cascaded inverters to the output of the second cascaded inverter in the first group of cascaded inverters, without any intermediate components, wherein the first filter stage further includes a second gyroscope connected between the node and the voltage rail.

13. The apparatus according to claim 12, wherein the voltage rail includes a ground.

14. The apparatus according to claim 12, wherein the second rotary comprises: The second set of cascaded inverters; The second electrical conductor is connected in the feedback path to the input of the first cascade inverter in the second set of cascade inverters and the output of the second cascade inverter in the second set of cascade inverters; And a second group of one or more passive devices, connected between the output of the first cascade inverter in the second group of cascade inverters and the voltage rail.

15. The apparatus of claim 14, wherein the first filter stage further comprises a third gyroscope connected between the node and the voltage rail.

16. The apparatus according to claim 15, wherein the third rotary comprises: The third group of cascaded inverters; A third electrical conductor is connected in the feedback path to the input of the first cascade inverter in the third set of cascade inverters and the output of the second cascade inverter in the third set of cascade inverters; And a third group of one or more passive devices, connected between the output of the first cascade inverter in the third group of cascade inverters and the voltage rail.

17. The apparatus of claim 15, wherein the first filter stage includes a capacitor coupled in series with the third gyroscope between the node and the voltage rail.

18. The apparatus according to claim 12 further includes a second filter stage, the second filter stage comprising: The second set of cascaded inverters; And a second group of one or more passive devices, wherein the second group of one or more passive devices includes: a first resistor connected between the node and the input of the first cascade inverter in the second group of cascade inverters; A second resistor is connected between the node and the output of the second cascade inverter in the second group of cascade inverters; and a capacitor is connected between the input of the first cascade inverter in the second group of cascade inverters and the output of the second cascade inverter in the second group of cascade inverters.

19. The apparatus of claim 12, wherein the first filter stage includes a capacitor coupled in series with the first gyrator between the node and the voltage rail.

20. The apparatus of claim 12, wherein the first filter stage includes a capacitor connected in series with the second gyrator between the node and the voltage rail.

21. The apparatus of claim 12, wherein the first group of one or more passive devices comprises a capacitor, or wherein the first group of one or more passive devices comprises a capacitor connected in series with a resistor.

22. The apparatus of claim 12, wherein the first filter stage does not include an inductor or an operational amplifier.

23. A communication apparatus comprising a first filter stage, the first filter stage including a first gyrator connected between a node and a voltage rail, the first gyrator comprising: A first group of cascaded inverters; a first group of one or more passive devices coupled to the first group of cascaded inverters, wherein the first group of one or more passive devices is connected between the output of the first cascaded inverter in the first group of cascaded inverters and the voltage rail; and an electrical conductor extending in a feedback path from the input of the first cascaded inverter in the first group of cascaded inverters to the output of the second cascaded inverter in the first group of cascaded inverters, without any intermediate components, wherein the first filter stage includes a capacitor, the capacitor being coupled in series with the first gyroscope between the node and the voltage rail.

24. The apparatus according to claim 23, wherein the voltage rail includes a ground.

25. The apparatus of claim 23, wherein the first group of one or more passive devices comprises a capacitor, or wherein the first group of one or more passive devices comprises a capacitor connected in series with a resistor.

26. The apparatus of claim 23, wherein the first filter stage does not include an inductor or an operational amplifier.

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