Memory system and operating method of memory system

Abstract

The embodiments of this disclosure relate to a memory system and a method of operating the memory system. According to the embodiments of this disclosure, the memory system can group multiple memory blocks included in each of a plurality of memory chips—each memory chip including multiple memory blocks—into one or more superblocks, calculate the number of superblocks in an erase state included in each memory chip, and move data stored in a first superblock to a second superblock, wherein the first superblock includes a first memory chip with the minimum number of superblocks in an erase state among the plurality of memory chips, and the second superblock includes a second memory chip with the maximum number of superblocks in an erase state among the plurality of memory chips.

Description

[Technical Field]

[0001] The various embodiments of the disclosed technology relate to a memory system and a method of operating the memory system. [Previous Technology]

[0002] Memory systems include data storage devices that store data based on requests from a host such as a computer, server, smartphone, tablet PC, or other electronic device. Examples of memory systems range from traditional disk-based hard disk drives (HDDs) to semiconductor-based data storage devices such as solid-state drives (SSDs), universal flash memory devices (UFS), or embedded MMC (eMMC) devices.

[0003] The memory system may further include a memory controller for controlling the memory device. The memory controller may receive commands from the host and may execute the commands on the memory device in the memory system or control read / write / erase operations on the memory device based on the received commands. The memory controller may be used to run firmware operations to perform logical operations for controlling these operations.

[0004] The memory system can perform a wear leveling operation to balance the wear and tear on the memory device in order to extend the life of the memory system. [Summary of the Invention]

[0005] Cross-reference to related applications: This patent application document claims priority and benefit to Korean Patent Application No. 10-2021-0131541, filed on October 5, 2021, which is incorporated herein by reference in its entirety.

[0006] The embodiments of the disclosed technology can provide a memory system and a method of operating the memory system, which can distribute data among memory chips included in a memory device and prevent data from being stored in a specific memory chip included in the memory device.

[0007] In one aspect, embodiments of the present disclosure may provide a memory system comprising: a memory device including a plurality of memory chips, each of the plurality of memory chips including a plurality of memory blocks for storing data, and different groups of memory blocks forming one or more superblocks; and a memory controller. The memory controller may count the number of superblocks in an erased state included in each memory chip to identify a first memory chip having a minimum number of superblocks in an erased state and a second memory chip having a maximum number of superblocks in an erased state, and move data stored in the first superblocks included in the first memory chip to the second superblocks included in the second memory chip.

[0008] In another aspect, embodiments of the present disclosure may provide a method of operating a memory system, the method comprising: counting the number of superblocks in an erased state included in each of a plurality of memory chips to identify a first memory chip having a minimum number of superblocks in an erased state and a second memory chip having a maximum number of superblocks in an erased state; and moving data stored in the first superblock included in the first memory chip to the second superblock included in the second memory chip.

[0009] According to embodiments of the present disclosure, the lifespan of a memory system can be extended by enabling data to be distributed and stored in a plurality of memory chips included in the memory device.

Implementation Method

[0011] Embodiments of the present disclosure are described in detail below with reference to drawings. Throughout the specification, references to “embodiment,” “another embodiment,” etc., are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. The term “embodiment” as used herein does not necessarily refer to all embodiments.

[0012] Embodiments of the disclosed technology are described in more detail below with reference to the drawings. We note that the disclosed technology may be implemented in different forms and variations and should not be construed as limited to the embodiments set forth herein. Throughout this disclosure, the same element symbols consistently refer to the same parts in the various drawings and embodiments of the disclosed technology.

[0013] The methods, processes, and / or operations described herein can be executed by code or instructions to be run by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those devices described herein or elements other than those described herein. Because the algorithms that form the basis of the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0014] When implemented at least in part in software, the controller, processor, device, module, unit, multiplexer, generator, logic circuit, interface, decoder, driver, generator and other signal generation and signal processing features may include, for example, memory or other storage devices for storing, for example, code or instructions to be executed by a computer, processor, microprocessor, controller or other signal processing device.

[0015] FIG1 is a schematic diagram illustrating the configuration of a memory system 100 based on an embodiment of the disclosed technology.

[0016] In some embodiments, the memory system 100 may include a memory device 110 configured to store data and a memory controller 120 configured to control the memory device 110.

[0017] The memory device 110 may include a plurality of memory blocks, each memory block including a plurality of memory cells for storing data. The memory device 110 may be configured to operate in response to control signals received from the memory controller 120. For example, the operation of the memory device 110 may include read operations, programming operations (also referred to as "write operations"), erase operations, etc.

[0018] The memory cells in the memory device 110 are used to store data and can be arranged in an array of memory cells. The array of memory cells can be divided into memory blocks composed of memory cells, and each block includes different pages of memory cells. In a typical implementation of a NAND flash memory device, the page of a memory cell is the smallest memory unit that can be programmed or written, and the data stored in the memory cell can be erased in blocks.

[0019] In some embodiments, the memory device 110 may be implemented as various types such as: Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Generation 4 Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin-Torque Random Access Memory (STT-RAM).

[0020] The memory device 110 can be implemented in a three-dimensional array structure. Some embodiments of the disclosed technology are applicable to any type of flash memory device having a charge storage layer. In one embodiment, the charge storage layer can be formed of a conductive material, and such a charge storage layer can be referred to as a floating gate. In another embodiment, the charge storage layer can be formed of an insulating material, and such a flash memory device can be referred to as charge-fetch flash memory (CTF).

[0021] The memory device 110 can be configured to receive commands and addresses from the memory controller 120 to access a region of the memory cell array selected using the address. That is, the memory device 110 can perform an operation corresponding to the received command on a memory region of the memory device, the memory region of the memory device having a physical address corresponding to the address received from the memory controller 120.

[0022] In some embodiments, the memory device 110 can perform programming operations, reading operations, erasing operations, etc. During a programming operation, the memory device 110 can write data to an area selected by an address. During a reading operation, the memory device 110 can read data from a memory area selected by an address. During an erasing operation, the memory device 110 can erase the data stored in the memory area selected by an address.

[0023] The memory controller 120 can control write (programming) operations, read operations, erase operations, and background operations performed on the memory device 110. Background operations may include, for example, operations implemented to optimize the overall performance of the memory device 110, such as garbage collection (GC) operations, wear leveling (WL) operations, and bad block management (BBM) operations.

[0024] The memory controller 120 can control the operation of the memory device 110 upon request from the host. Optionally, when the memory controller 120 performs these background operations of the memory device, the memory controller 120 can control the operation of the memory device 110 even without a request from the host.

[0025] The memory controller 120 and the host may be separate devices. In some embodiments, the memory controller 120 and the host may be integrated and implemented as a single device. In the following description, by way of example, the memory controller 120 and the host will be discussed as separate devices.

[0026] Referring to FIG1, the memory controller 120 may include a memory interface 122, a control circuit 123 and a host interface 121.

[0027] The host interface 121 can be configured to provide an interface for communicating with a host.

[0028] When a command is received from the host, the control circuit 123 can receive the command through the host interface 121 and can perform operations to process the received command.

[0029] The memory interface 122 can be directly or indirectly connected to the memory device 110 to provide an interface for communicating with the memory device 110. That is, the memory interface 122 can be configured to provide an interface to the memory device 110 and the memory controller 120, so that the memory controller 120 can perform memory operations on the memory device 110 based on control signals and instructions from the control circuit 123.

[0030] The control circuit 123 can be configured to control the operation of the memory device 110 through the memory controller 120. For example, the control circuit 123 may include a processor 124 and working memory 125. The control circuit 123 may further include an error detection / correction circuit (ECC circuit) 126, etc.

[0031] The processor 124 can control the overall operation of the memory controller 120. The processor 124 can perform logical operations. The processor 124 can communicate with the host through the host interface 121. The processor 124 can communicate with the memory device 110 through the memory interface 122.

[0032] The processor 124 can be used to perform operations associated with the flash translation layer (FTL) to efficiently manage memory operations on the memory system 100. The processor 124 can translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs) via the FTL. The FTL can receive LBAs and translate them into PBAs using a mapping table.

[0033] Based on the mapping unit, there are various address mapping methods that FTL can use. Typical address mapping methods can include page mapping method, block mapping method and hybrid mapping method.

[0034] The processor 124 can be configured to randomize data received from the host to write the randomized data into the memory cell array. For example, the processor 124 can randomize the data received from the host by using a randomization seed. The randomized data is provided to the memory device 110 and written into the memory cell array.

[0035] The processor 124 can be configured to derandomize data received from the memory device 110 during a read operation. For example, the processor 124 can derandomize data received from the memory device 110 by using a derandomization seed. The derandomized data can be output to the host.

[0036] The processor 124 can run firmware (FW) to control the operation of the memory controller 120. In other words, the processor 124 can control the overall operation of the memory controller 120, and in order to perform logical operations, it can run (drive) the firmware loaded into the working memory 125 during startup.

[0037] Firmware refers to a program or software stored on a specific non-volatile memory and running within the memory system 100.

[0038] In some embodiments, the firmware may include various functional layers. For example, the firmware may include at least one of a flash translation layer (FTL), a host interface layer (HIL), and a flash interface layer (FIL), wherein the flash translation layer (FTL) is configured to translate a logical address in a host request into a physical address of the memory device 110, the host interface layer (HIL) is configured to interpret commands issued by the host host to a data storage device such as the memory system 100 and is configured to pass the commands to the FTL, and the flash interface layer (FIL) is configured to pass commands issued by the FTL to the memory device 110.

[0039] For example, the firmware can be stored in memory device 110 and then loaded into working memory 125.

[0040] The working memory 125 may store firmware, program code, commands or data necessary to operate the memory controller 120. For example, the working memory 125 may include at least one of static RAM (SRAM), dynamic RAM (DRAM) and synchronous RAM (SDRAM) as volatile memory.

[0041] The error detection / correction circuit 126 can be configured to detect and correct one or more error bits in the data by using error detection and correction codes. In some embodiments, the data undergoing error detection and correction may include data stored in the working memory 125 and data retrieved from the memory device 110.

[0042] The error detection / correction circuit 126 can be implemented to decode data using error correction codes. The error detection / correction circuit 126 can be implemented using various decoding schemes. For example, a decoder that performs non-system code decoding or a decoder that performs system code decoding can be used.

[0043] In some embodiments, the error detection / correction circuit 126 may detect one or more error bits based on sectors. That is, each read data may include multiple sectors. In this patent application, a sector may refer to a data unit smaller than a flash memory read unit (e.g., a page). The sectors constituting each read data may be mapped based on addresses.

[0044] In some embodiments, the error detection / correction circuit 126 can calculate the bit error rate (BER) and determine, sector by sector, whether the number of erroneous bits in the data is within the error correction capability. For example, if the BER is higher than a reference value, the error detection / correction circuit 126 can determine that the erroneous bits in the corresponding sector are uncorrectable, and the corresponding sector is marked as "failed". If the BER is lower than or equal to the reference value, the error detection / correction circuit 126 can determine that the corresponding sector is correctable, or the corresponding sector can be marked as "passed".

[0045] The error detection / correction circuit 126 can sequentially perform error detection and correction operations on all read data. When a sector included in the read data is correctable, the error detection / correction circuit 126 can move to the next sector to check whether an error correction operation needs to be performed on the next sector. While performing error detection and correction operations on all read data in this manner, the error detection / correction circuit 126 can obtain information about which sector in the read data is considered uncorrectable. The error detection / correction circuit 126 can provide this information (e.g., the address of the uncorrectable bit) to the processor 124.

[0046] The memory system 100 may also include a bus 127 for providing a channel between the constituent elements 121, 122, 124, 125 and 126 of the memory controller 120. For example, the bus 127 may include a control bus for transmitting various types of control signals and commands, and a data bus for transmitting various types of data.

[0047] For example, FIG1 shows the aforementioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120. It should be noted that some of the elements shown in the figure may be omitted, or some of the aforementioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 may be integrated into a single element. Additionally, in some embodiments, one or more other constituent elements may be added to the aforementioned constituent elements of the memory controller 120.

[0048] FIG2 is a block diagram schematically showing a memory device 110 based on an embodiment of the disclosed technology.

[0049] In some embodiments, the memory device 110 based on the disclosed technology may include a memory cell array 210, an address decoder 220, a read / write circuit 230, control logic 240, and a voltage generation circuit 250.

[0050] The memory cell array 210 may include multiple memory blocks BLK1 to BLKz, where z is a natural number equal to or greater than 2.

[0051] In multiple memory blocks BLK1 to BLKz, multiple word lines WL and multiple bit lines BL can be set by row and column, and multiple memory cells MC can be arranged.

[0052] Multiple memory blocks BLK1 to BLKz can be connected to the address decoder 220 via multiple word lines WL. Multiple memory blocks BLK1 to BLKz can be connected to the read / write circuit 230 via multiple bit lines BL.

[0053] Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. For example, the plurality of memory cells are non-volatile memory cells. In some embodiments, these non-volatile memory cells may be arranged in a vertical channel structure.

[0054] The memory cell array 210 can be configured as a memory cell array with a two-dimensional structure. In some embodiments, the memory cell array 210 can be arranged in a three-dimensional structure.

[0055] Each of the plurality of memory cells included in the memory cell array 210 can store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 can be a single-level cell (SLC) configured to store one bit of data. As another example, each of the plurality of memory cells included in the memory cell array 210 can be a multi-level cell (MLC) configured to store two bits of data per memory cell. As another example, each of the plurality of memory cells included in the memory cell array 210 can be a three-level cell (TLC) configured to store three bits of data per memory cell. As another example, each of the plurality of memory cells included in the memory cell array 210 can be a four-level cell (QLC) configured to store four bits of data per memory cell. As yet another example, the memory cell array 210 can include a plurality of memory cells, each of which can be configured to store at least five bits of data per memory cell.

[0056] Referring to Figure 2, the address decoder 220, read / write circuit 230, control logic 240 and voltage generation circuit 250 can operate as peripheral circuits configured to drive the memory cell array 210.

[0057] The address decoder 220 can be connected to the memory cell array 210 through multiple character lines WL.

[0058] The address decoder 220 can be configured to operate in response to commands and control signals from the control logic 240.

[0059] The address decoder 220 can receive addresses through an input / output buffer within the memory device 110. The address decoder 220 can be configured to decode block addresses among the received addresses. The address decoder 220 can select at least one memory block based on the decoded block address.

[0060] The address decoder 220 can receive the read voltage Vread and the pass voltage Vpass from the voltage generation circuit 250.

[0061] During a read operation, the address decoder 220 may apply a read voltage Vread to the selected word line WL in the selected memory block and a pass voltage Vpass to the remaining unselected word lines WL.

[0062] During the programming verification operation, the address decoder 220 can apply the verification voltage generated by the voltage generation circuit 250 to the selected character line WL in the selected memory block, and can apply the pass voltage Vpass to the remaining unselected character lines WL.

[0063] Address decoder 220 can be configured to decode column addresses among received addresses. Address decoder 220 can transmit the decoded column addresses to read / write circuit 230.

[0064] The memory device 110 can perform read and program operations page by page. The address received when requesting a read or program operation may include at least one of a block address, a row address, and a column address.

[0065] The address decoder 220 can select a memory block and a word line based on the block address and the row address. The column address can be decoded by the address decoder 220 and provided to the read / write circuit 230.

[0066] The address decoder 220 may include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

[0067] The read / write circuit 230 may include multiple page buffers PB. The read / write circuit 230 may operate as a "read circuit" when the memory cell array 210 performs a read operation, and as a "write circuit" when the memory cell array 210 performs a write operation.

[0068] The above-described read / write circuit 230 is also referred to as a page buffer circuit including multiple page buffers PB, or a data register circuit. The read / write circuit 230 may include a data buffer involved in data processing functions, and in some embodiments, may further include a cache buffer for data caching.

[0069] Multiple page buffers PB can be connected to the memory cell array 210 via multiple bit lines BL. In order to detect or sense the threshold voltage Vth of the memory cell during read operations and program verification operations, the multiple page buffers PB can continuously supply sensing current to the bit lines BL connected to the memory cell to detect changes in current proportional to the amount of current that changes according to the programming state of the corresponding memory cell at the sensing node, and can store or latch the corresponding voltage as sensing data.

[0070] The read / write circuit 230 can operate in response to a page buffer control signal output from the control logic 240.

[0071] During a read operation, the read / write circuit 230 senses the voltage value of the memory cell and reads the voltage value as data. The read / write circuit 230 temporarily stores the retrieved data and outputs the data DATA to the input / output buffer of the memory device 110. In an embodiment, in addition to the page buffer PB or page register, the read / write circuit 230 may also include a column select circuit.

[0072] Control logic 240 can be connected to address decoder 220, read / write circuit 230 and voltage generation circuit 250. Control logic 240 can receive command CMD and control signal CTRL through the input / output buffer of memory device 110.

[0073] Control logic 240 can be configured to control the overall operation of memory device 110 in response to control signal CTRL. Control logic 240 can output control signals for adjusting the voltage levels of the sensing nodes of multiple page buffers PB to a pre-charge voltage level.

[0074] Control logic 240 can control read / write circuit 230 to perform read operations in memory cell array 210. Voltage generation circuit 250 can generate read voltage Vread and pass voltage Vpass used during read operations in response to voltage generation circuit control signals output from control logic 240.

[0075] The memory block BLK included in the memory device 110 may include multiple pages PG. In some embodiments, multiple memory cells arranged in columns form a memory cell string, while multiple memory cells arranged in rows form a memory block. Each of the multiple pages PG is coupled to a word line in the word line WL, and each of the memory cell string STR is coupled to a bit line in the bit line BL.

[0076] In the memory block BLK, multiple character lines WL and multiple bit lines BL can be arranged in rows and columns. For example, each character line in the multiple character lines WL can be arranged along the row direction, while each bit line in the multiple bit lines BL can be arranged along the column direction. As another example, each character line in the multiple character lines WL can be arranged along the column direction, while each bit line in the multiple bit lines BL can be arranged along the row direction.

[0077] In some embodiments, multiple word lines WL and multiple bit lines BL may intersect each other to address individual memory cells in an array of multiple memory cells MC. In some embodiments, each memory cell MC may include a transistor TR, which includes a layer of material capable of retaining charge.

[0078] For example, a transistor TR arranged in each memory cell MC may include a drain, a source, and a gate. The drain (or source) of the transistor TR may be connected directly or via another transistor TR to the corresponding bit line BL. The source (or drain) of the transistor TR may be connected directly or via another transistor TR to a source line (which may be ground). The gate of the transistor TR may include a floating gate (FG) surrounded by an insulator and a control gate (CG) to which a gate voltage is applied from the word line WL.

[0079] In each of the plurality of memory blocks BLK1 to BLKz, a first select line (also called a source select line or drain select line) may be additionally arranged outside the first outermost character line closer to the read / write circuit 230 among the two outermost character lines, and a second select line (also called a drain select line or source select line) may be additionally arranged outside the other second outermost character line.

[0080] In some embodiments, at least one additional dummy character line may be arranged between the first outermost character line and the first selection line. Additionally, at least one additional dummy character line may be arranged between the second outermost character line and the second selection line.

[0081] Read and program operations (write operations) of memory blocks can be performed page by page, and erase operations can be performed block by block.

[0082] FIG3 is a diagram showing the structure of the word line WL and bit line BL of the memory device 110 based on an embodiment of the disclosed technology.

[0083] Referring to FIG3, the memory device 110 has a core region where memory cells MC are arranged and an auxiliary region (the remaining region other than the core region) including circuitry for performing operations of the memory cell array 210.

[0084] In the kernel region, a certain number of memory units arranged in one direction can be called a “page” PG, while a certain number of memory units coupled in series can be called a “memory unit string” STR.

[0085] Character lines WL1 to WL9 can be connected to the row decoder 310. Bit lines BL can be connected to the column decoder 320. A data register 330 corresponding to the read / write circuit 230 of Figure 2 can exist between multiple bit lines BL and the column decoder 320.

[0086] Multiple character lines WL1 to WL9 can correspond to multiple pages PG.

[0087] For example, each of the multiple character lines WL1 to WL9 can correspond to a page PG as shown in Figure 3. When the size of each of the multiple character lines WL1 to WL9 is large, each of the multiple character lines WL1 to WL9 can correspond to at least two (e.g., two or four) page PGs. Each page PG is the smallest unit in programming and reading operations, and all memory units MC within the same page PG can perform synchronous operations during programming and reading operations.

[0088] Multiple bit lines BL can be connected to column decoder 320. In some implementations, multiple bit lines BL can be divided into odd bit lines BL and even bit lines BL, such that a pair of odd bit lines BL and even bit lines BL are coupled together to column decoder 320.

[0089] When accessing a memory cell MC, the row decoder 310 and the column decoder 320 are used to locate the desired memory cell based on the address.

[0090] In some embodiments, the data register 330 plays a crucial role because all data processing of the memory device 110, including programming and reading operations, occurs via the data register 330. If the data processing performed by the data register 330 is delayed, all other areas must wait until the data register 330 completes its data processing, which degrades the overall performance of the memory device 110.

[0091] Referring to the example shown in FIG3, in a memory cell string STR, multiple transistors TR1 to TR9 can be connected to multiple word lines WL1 to WL9 respectively. In some embodiments, the multiple transistors TR1 to TR9 correspond to memory cells MC. In this example, the multiple transistors TR1 to TR9 include a control gate CG and a floating gate FG.

[0092] The multiple character lines WL1 to WL9 include two outermost character lines WL1 and WL9. A first selection line DSL can be additionally arranged outside the first outermost character line WL1, which is closer to the data register 330 and has a shorter signal path compared to the other outermost character line WL9. A second selection line SSL can be additionally arranged outside the other second outermost character line WL9.

[0093] The first selection transistor D-TR, controlled by the first selection line DSL to be turned on / off, has a gate electrode connected to the first selection line DSL, but does not include a floating gate FG. The second selection transistor S-TR, controlled by the second selection line SSL to be turned on / off, has a gate electrode connected to the second selection line SSL, but does not include a floating gate FG.

[0094] The first selection transistor D-TR is used as a switch circuit to connect the corresponding memory cell string STR to the data register 330. The second selection transistor S-TR is used as a switch to connect the corresponding memory cell string STR to the source line SL. That is, the first selection transistor D-TR and the second selection transistor S-TR can be used to enable or disable the corresponding memory cell string STR.

[0095] In some embodiments, the memory system 100 applies a predetermined turn-on voltage Vcc to the gate electrode of the first select transistor D-TR to turn on the first select transistor D-TR, and applies a predetermined turn-off voltage (e.g., 0V) to the gate electrode of the second select transistor S-TR to turn off the second select transistor S-TR.

[0096] During a read or verification operation, the memory system 100 turns on both the first selection transistor D-TR and the second selection transistor S-TR. Therefore, during the read or verification operation, current can flow through the corresponding memory cell string STR and drain to the source line SL corresponding to ground, thereby allowing the voltage level of the bit line BL to be measured. However, during the read operation, there may be a time difference in the on / off timing between the first selection transistor D-TR and the second selection transistor S-TR.

[0097] During the erase operation, the memory system 100 may apply a predetermined voltage (e.g., +20V) to the substrate through the source line SL. During the erase operation, the memory system 100 applies a voltage to allow both the first select transistor D-TR and the second select transistor S-TR to float. Therefore, the applied erase voltage can remove charge from the floating gate FG of the selected memory cell.

[0098] Figure 4 shows a schematic structure of a memory system 100 according to an embodiment of the disclosed technology.

[0099] Referring to FIG4, the memory system 100 may include a memory device 110 and a memory controller 120.

[0100] The memory device 110 may include a plurality of memory chips (DIEs). Each of the plurality of memory chips (DIEs) may include a plurality of memory blocks (BLKs).

[0101] On the other hand, for example, each of the plurality of memory die DIEs may include a plurality of memory blocks BLK, such that each planar PLANE included in each of the plurality of memory die DIEs includes one or more memory blocks BLK.

[0102] The memory controller 120 of the memory system 100 can group multiple memory blocks BLK included in each memory die DIE into one or more super blocks SB.

[0103] The superblock SB is a unit that logically groups the multiple memory blocks BLK included in the memory device 110. The memory controller 120 can control the memory device 110 to perform erase operations in units of superblock SB.

[0104] In Figure 4, the superblock SB_1 includes two memory blocks BLK included in the memory die DIE_1. In this case, the two memory blocks BLK of the superblock SB_1 can be included in different planes of the memory die DIE_1. The superblock SB_1 can also include memory blocks included in the same plane of the memory die DIE_1.

[0105] Additionally, the superblock SB_2 may include the four memory blocks BLK included in the memory die DIE_2. In this case, the four memory blocks BLK of the superblock SB_2 may be included in two different planes in the memory die DIE_2. The two memory blocks BLK of the superblock SB_2 are included in the same plane of the memory die DIE_2.

[0106] Figure 5 illustrates a schematic operation of a memory system 100 according to an embodiment of the disclosed technology.

[0107] Referring to FIG5, the memory controller 120 of the memory system 100 can count the number of superblocks E_SB in the erasure state among the superblocks SB included in the plurality of memory dies DIE included in the memory device 110.

[0108] A superblock E_SB in an erased state refers to a superblock SB whose data has been erased. Therefore, a superblock E_SB in an erased state does not store any valid data.

[0109] The memory controller 120 of the memory system 100 can move the data stored in the first superblock 1st_SB to the second superblock 2nd_SB. The first superblock 1st_SB is included in the first memory die 1st_DIE of the multiple memory die DIEs, which has the minimum number of superblocks E_SB in the erasure state. The second superblock 2nd_SB is included in the second memory die 2nd_DIE of the multiple memory die DIEs, which has the maximum number of superblocks E_SB in the erasure state.

[0110] In Figure 5, the first memory die 1st_Die has the minimum number (i.e., 1) of superblocks E_SB in the erase state, and the second memory die 2nd_Die has the maximum number (i.e., 3) of superblocks E_SB in the erase state.

[0111] The memory controller 120 can identify one of the superblocks SB included in the first memory die 1st_Die as the first superblock 1st_SB. Moreover, the memory controller 120 can identify one of the superblocks SB included in the second memory die 2nd_Die as the second superblock 2nd_SB.

[0112] The memory controller 120 can move the data stored in the first superblock 1st_SB to the second superblock 2nd_SB. When the data stored in the first superblock 1st_SB is moved to the second superblock 2nd_SB, the first superblock 1st_SB can become a superblock E_SB in an erased state, and the second superblock 2nd_SB can become a superblock that has been written to and is in a write state.

[0113] The reason why the memory controller 120 performs the above operation is discussed below.

[0114] During the erase operation, the memory blocks included in the memory device 110 may deteriorate. Therefore, there is a limit to the number of times each of the multiple memory blocks BLK included in the memory device 110 can be erased.

[0115] In order to ensure the reliability of the data stored in the memory device 110 and extend the lifespan of the memory system 100, the memory controller 120 may perform certain operations to extend the lifespan of the memory device. For example, the memory controller 120 may perform a wear leveling operation to balance the wear levels of the memory blocks included in the memory device 110.

[0116] In the case where the memory device 110 includes a plurality of memory chips DIEs, in order to prevent the lifespan of a particular memory chip among the plurality of memory chips DIEs from being shortened, the memory controller 120 may allocate and store data among the plurality of memory chips.

[0117] If data is written to a specific memory die among multiple memory die DIEs and the superblock E_SB in the erased state included in the corresponding memory die is exhausted, the memory controller 120 may have difficulty allocating and storing data among the multiple memory die DIEs. As a result, the lifetime of the specific memory die is shortened, which leads to a shortened lifetime of the memory system 100.

[0118] Therefore, the memory controller 120 can move the data stored in the first superblock 1st_SB to the second superblock 2nd_SB, thereby increasing the number of superblocks E_SB in the erasure state included in the first memory die 1st_DIE, wherein the first superblock 1st_SB is included in the first memory die 1st_DIE with the minimum number of superblocks E_SB in the erasure state among the multiple memory dies DIE, and the second superblock 2nd_SB is included in the second memory die 2nd_DIE with the maximum number of superblocks E_SB in the erasure state among the multiple memory dies DIE.

[0119] Therefore, the memory controller 120 can prevent the allocation and storage of data among multiple memory dies from being limited due to the depletion of the superblock E_SB in the erase state in a particular memory die. Therefore, the memory controller 120 can extend the lifespan of the memory system 100.

[0120] Figure 6 shows an example of moving data in a memory system 100 according to an embodiment of the disclosed technology.

[0121] Referring to FIG6, the memory controller 120 of the memory system 100 can determine the first superblock 1st_SB as the superblock SB with the minimum erase count EC among the superblocks SB in the write state included in the first memory die 1st_DIE.

[0122] A superblock in write state refers to a superblock that stores valid data.

[0123] The memory controller 120 can count the erase count EC of each superblock SB, where the erase count EC is the number of erase operations that have occurred.

[0124] In FIG. 6, the memory controller 120 can determine the superblock SB with the smallest erase count EC among the superblocks SB in the write state included in the first memory die 1st_Die as the first superblock 1st_SB, and can move the data stored in the first superblock 1st_SB to the second superblock 2nd_SB included in the second memory die 2nd_Die. The method of selecting the second superblock among the memory blocks in the second memory die 2nd_Die will be explained with reference to FIG. 7.

[0125] Thereafter, the memory controller 120 can perform an erase operation on the first superblock 1st_SB. The memory controller 120 can then use the erased first superblock 1st_SB to write new data again.

[0126] For example, the erase counts EC of the superblock SB included in the first memory die 1st_Die of FIG6 are 6, 8, 3, 1, 2, 8, 3 and 7 respectively.

[0127] In this case, the memory controller 120 can identify the superblock with the smallest erase count EC, i.e. 1, among the superblocks SB in the write state included in the first memory die 1st_Die as the first superblock 1st_SB.

[0128] The memory controller 120 can move the data stored in the first superblock 1st_SB, where the erase count EC is 1, to the second superblock 2nd_SB of the second memory die 2nd_Die. Afterward, the memory controller 120 can erase the data stored in the first superblock 1st_SB, making the first superblock 1st_SB a superblock E_SB in an erased state, and then can increase the erase count EC of the first superblock 1st_SB from 1 to 2.

[0129] As described above, the memory controller 120 can change the superblock with the lowest erase count EC among the superblocks in the write state to the erase state to reuse the corresponding superblock. Therefore, the memory controller 120 can uniformly maintain the erase count EC of the superblocks SB included in the plurality of memory chips DIE of the memory device 110, thereby preventing a shortening of the lifespan of the memory system 100.

[0130] Figure 7 shows another example of moving data in memory system 100 according to an embodiment of the disclosed technology.

[0131] Referring to FIG7, the memory controller 120 of the memory system 100 can determine the second superblock 2nd_SB as the superblock with the maximum erase count EC among the superblocks E_SB in the erasure state included in the second memory die 2nd_Die.

[0132] In Figure 7, the memory controller 120 can identify the superblock with the maximum erase count EC among the superblocks E_SB in the erase state included in the second memory die 2nd_Die as the second superblock 2nd_SB, and can change the state of the second superblock 2nd_SB from the erase state to the write state by moving the data stored in the first superblock 1st_SB to the second superblock 2nd_SB.

[0133] As an example, in the second memory die 2nd_Die of Figure 7, the erase count EC of each superblock is 3, 7, 8, 2, 4, 5, 4, 9 respectively.

[0134] In this case, the memory controller 120 can confirm that the erase count EC of the superblock with the largest erase count EC in the superblock E_SB that is in the erase state is 9.

[0135] The memory controller 120 can identify the superblock SB with the maximum erase count EC (9) among the superblocks E_SB in the erase state included in the second memory die 2nd_Die as the second superblock 2nd_SB, and can move the data stored in the first superblock 1st_SB to the second superblock 2nd_SB. In this case, the memory controller 120 can change the state of the second superblock 2nd_SB from the erase state to the write state. The method of selecting the first superblock 1st_SB among the memory blocks in the first memory die 1st_Die has been described with reference to FIG6.

[0136] Compared to data that the host writes through a new request via a write command, data previously stored in the first superblock 1st_SB is more likely to be cold data with a relatively low access frequency.

[0137] Therefore, the memory controller 120 can write data previously stored in the first superblock 1st_SB to the second superblock 2nd_SB, which has a large erase count EC, to delay updating the erase count EC of the second superblock 2nd_SB. This is because the probability of data change (e.g., data corresponding to data newly requested by the host via a write command) when data is directly stored in the second superblock 2nd_SB and not in the first superblock 1st_SB is likely higher than the probability of data change when data was previously stored in the first superblock 1st_SB and moved to the second superblock 2nd_SB. By moving data previously stored in the first superblock 1st_SB to the second superblock 2nd_SB, the second superblock 2nd_SB, with its larger erase count EC, can store data with a relatively low probability of change. Therefore, it is possible to prevent data in the second superblock 2nd_SB from changing in a relatively short period of time and delay updating the erase count EC of the second superblock 2nd_SB.

[0138] Therefore, the memory controller 120 can prevent the lifespan of the memory system 100 from being shortened by uniformly maintaining the erase count of the superblock SB included in the memory die DIE.

[0139] FIG8 shows an example of a superblock SB included in a plurality of memory dies DIEs of a memory system 100 according to an embodiment of the present disclosure.

[0140] Referring to FIG8, the memory controller 120 of the memory system 100 can check the number of superblocks E_SB in an erased state included in each of the plurality of memory chips DIE included in the memory device 110.

[0141] In Figure 8, the number of superblocks E_SB in the erased state in each of the memory chips DIE included in the memory device 110 are 1, 2, 3, 2, 6, 2, 2 and 4, respectively.

[0142] The memory controller 120 can identify the memory die 1st_Die as the first memory die 1st_Die among the memory dies DIE included in the memory device 110, where the number of superblocks E_SB in the erasure state is the minimum value of 1.

[0143] The memory controller 120 can identify the memory die 2nd_Die as the second memory die among the memory dies DIE included in the memory device 110, where the number of superblocks E_SB in the erasure state is a maximum of 6.

[0144] In Figure 8, assume that the threshold THR is set to 5.

[0145] The memory controller 120 can check that the difference between the number of superblocks E_SB in the erasure state included in the first memory die 1st_Die and the number of superblocks E_SB in the erasure state included in the second memory die 2nd_Die is 5, which is equal to or greater than a set threshold THR.

[0146] Figure 9 illustrates an example of an operation in which a memory system 100 according to an embodiment of the present disclosure moves data stored in a first superblock 1st_SB to a second superblock 2nd_SB.

[0147] Referring to FIG9, when the difference between the number of superblocks E_SB in the erasure state included in the first memory die 1st_Die and the number of superblocks E_SB in the erasure state included in the second memory die 2nd_Die is equal to or greater than a set threshold THR, the memory controller 120 of the memory system 100 can move the data stored in the first superblock 1st_SB to the second superblock 2nd_SB.

[0148] For example, the memory controller 120 can determine the first superblock 1st_SB by considering the erase count EC of the superblock SB included in the first memory die 1st_Die, the state of the memory blocks included in the superblock SB in the first memory die 1st_Die, etc., so that the number of superblocks E_SB in the erasure state included in the multiple memory dies DIE becomes as uniform as possible.

[0149] Furthermore, the memory controller 120 can determine the second superblock 2nd_SB corresponding to the first superblock 1st_SB among the superblocks E_SB in the erased state in the second memory die 2nd_Die. In this case, the memory controller 120 can determine the second superblock 2nd_SB by considering the erase count EC of the superblocks SB included in the second memory die 2nd_Die, the state of the memory blocks included in the superblocks SB in the second memory die 2nd_Die, etc., so that the superblocks SB included in the second memory die 2nd_Die can be used as consistently or uniformly as possible.

[0150] In Figure 9, the memory controller 120 can move the data stored in the first superblock 1st_SB to the second superblock 2nd_SB.

[0151] Figure 10 shows an example of the state after the data stored in the first superblock 1st_SB is moved to the second superblock 2nd_SB according to an embodiment of the disclosed technology in the memory system 100.

[0152] Referring to Figure 10, after the memory controller 120 moves the data stored in the first superblock 1st_SB to the second superblock 2nd_SB, it can be determined that the first memory die 1st_Die includes two superblocks E_SB in an erase state, and the second memory die 2nd_Die includes five superblocks E_SB in an erase state. Compared with Figure 8, it can be seen that the difference between the number of superblocks E_SB in an erase state included in the first memory die 1st_Die and the number of superblocks E_SB in an erase state included in the second memory die 2nd_Die has decreased.

[0153] Figure 11 shows a plurality of partitions ZONE of a memory system 100 according to an embodiment of the disclosed technology.

[0154] Referring to FIG11, the memory controller 120 of the memory system 100 can allocate superblocks SB included in a plurality of memory chips DIEs included in the memory device 110 to a plurality of partition zones.

[0155] In embodiments of the disclosed technology, a zoned namespace may be applied to the memory system 100.

[0156] A partition namespace refers to dividing the memory device 110 into multiple partitions corresponding to areas indicated by logical addresses. When storing data in each of the multiple partitions, the memory controller 120 can store data while sequentially increasing logical addresses. Therefore, data with similar properties or characteristics can be stored in one partition.

[0157] The memory controller 120 can perform erase operations on a zone-by-zone basis. When using partition namespaces, the memory controller 120 may not perform a separate garbage collection operation. Garbage collection is performed by the memory controller 120 as a background operation, and additional resources are used to perform it. Therefore, garbage collection may cause delays in operations requested by the host, which can degrade the quality of service.

[0158] Since the memory system 100 that uses partitioned space does not perform garbage collection operations, the quality of service (QoS) degradation caused by garbage collection operations can be avoided or prevented.

[0159] A partition can have several states. For example, a partition can be empty, offline, fully loaded, or read-only. In this case, the corresponding partition ZONE can be considered a non-bootable partition.

[0160] A partition in an empty state does not store data, and the write pointer indicating the logical address of the data to be written points to the first logical address of the corresponding partition. In order to write data to the corresponding partition, it is necessary to change from an empty state to an open state.

[0161] A partition in a full state means that all data is stored in the corresponding partition. In this case, the write pointer indicates the last logical address of the corresponding partition. Data cannot be written to the corresponding partition unless the partition is reset and returns to an empty state.

[0162] A partition in read-only state can provide the host with the ability to use the partition namespace as read-only, even after part of the capacity has stopped working.

[0163] A partition in an offline state means that its lifecycle has ended and no further state transition will occur.

[0164] As another example, a partition ZONE can be in an open or closed state. In this case, the corresponding partition ZONE can be regarded as the boot partition.

[0165] Data can be written to a partition that is in an open state. In this case, the storage medium of memory device 110 can be mapped to the corresponding partition.

[0166] A partition in a closed state is started; however, data writing is temporarily restricted. For efficient operation of the memory system 100 using the partition namespace, the memory controller 120 can limit the number of partitions in an open state. In this case, a specific partition in an open state can be changed to a closed state.

[0167] Figure 12 illustrates an example of a memory system 100 according to an embodiment of the disclosed technology allocating a superblock to a specific partition.

[0168] Referring to FIG12, when the memory controller 120 of the memory system 100 starts a specific target partition ZONE_T among the above-mentioned multiple partitions ZONE, the memory controller 120 can allocate one or more of the superblocks SB included in the multiple memory chips DIE to the target partition ZONE_T.

[0169] As described above, the memory controller 120 can change the partition ZONE to an open state and start it to write data to the partition ZONE that is in an empty state.

[0170] In this case, the memory controller 120 can allocate one or more of the superblocks SB included in the multiple memory chips DIE according to the capacity of the corresponding partition.

[0171] In Figure 12, superblock SB_A and superblock SB_B are assigned to target partition ZONE_T.

[0172] When data is written to the target partition ZONE_T, the corresponding data can be written to superblock SB_A and superblock SB_B.

[0173] Figure 13 shows an example of memory system 100 selecting memory die DIE including a superblock to be allocated to target partition ZONE_T.

[0174] Referring to FIG13, when one or more of the superblocks SB included in the plurality of memory die DIEs are assigned to the target partition ZONE_T, the memory controller 120 of the memory system 100 can select memory dies from the plurality of memory die DIEs in a round-robin manner.

[0175] In Figure 13, assume there are multiple partitions ZONE_1, ZONE_2, ZONE_3, ZONE_4, ..., ZONE_N, and the first partition ZONE_1, the fourth partition ZONE_4, and the Nth partition ZONE_N are started. In addition, assume that the fourth partition ZONE_4 is the target partition ZONE_T.

[0176] When the memory controller 120 allocates a superblock to the target partition ZONE_T, the memory controller 120 may select a memory die DIE in a polling manner, and may allocate one or more of the superblocks SB included in the selected memory die to the target partition ZONE_T.

[0177] Therefore, when setting the target partition ZONE_T, the memory controller 120 can utilize the multiple memory chips DIEs included in the memory device 110 consistently or uniformly. Furthermore, the memory controller 120 can evenly distribute the memory chips DIEs including the superblock SB allocated to the target partition ZONE_T, and can concentrate the superblock SBs included in the target partition ZONE_T on specific memory chips. Therefore, the problem of superblock E_SB in the erased state among the superblock SBs included in the target partition ZONE_T being rapidly exhausted can be prevented.

[0178] Furthermore, when the target partition ZONE_T is set, the memory controller 120 can maximize the parallelism of the multiple memory chips (DIEs) included in the memory device 110. Therefore, the read and write speeds of the memory system 100 can be improved.

[0179] Figure 14 shows an example of a memory system 100 performing a reset operation of a target partition ZONE_T according to an embodiment of the disclosed technology.

[0180] In Figure 14, assume that the target partition ZONE_T is the fourth partition ZONE_4 among multiple partitions ZONE_1, ZONE_2, ZONE_3, ZONE_4, ..., ZONE_N.

[0181] Referring to FIG14, when the target partition ZONE_T is reset, the memory controller 120 of the memory system 100 can erase the data stored in the superblock SB allocated to the target partition ZONE_T.

[0182] The memory controller 120 can perform an erase operation on superblock SB_A and superblock SB_B allocated to the target partition ZONE_T to erase the data stored in superblock SB_A and superblock SB_B. In this case, superblock SB_A and superblock SB_B can be changed to an erased state.

[0183] In addition, the memory controller 120 can release superblock SB_A and superblock SB_B, which are superblocks allocated to the target partition ZONE_T.

[0184] The memory controller 120 can release the superblock SB_A and superblock SB_B allocated to the target partition ZONE_T, and thereafter, when a partition different from the target partition ZONE_T among multiple partitions ZONE_1, ZONE_2, ZONE_3, ZONE_4, ... ZONE_N is started, the controller can allocate the released superblock SB_A and superblock SB_B to another started partition.

[0185] Furthermore, the memory controller 120 can disable the target partition ZONE_T.

[0186] When resetting the target partition ZONE_T, the memory controller 120 can return the write pointer of the target partition ZONE_T to the starting point of the logical address of the target partition ZONE_T. In this case, the memory controller 120 can change the state of the target partition ZONE_T to an empty state, thereby deactivating it.

[0187] Figure 15 is a flowchart illustrating an example of an operation by which the memory system 100 moves data after resetting the target partition ZONE_T according to an embodiment of the disclosed technology.

[0188] Referring to FIG15, after resetting the target partition ZONE_T, the memory controller 120 can determine whether the number of superblocks SB in the erasure state among the plurality of memory chips DIEs included in the memory device 110 is unbalanced, and if necessary, can perform an operation to move data between the plurality of memory chips DIEs.

[0189] As described above, when the memory controller 120 resets the target partition ZONE_T, the superblock SB allocated to the target partition ZONE_T can be changed to an erased state. Therefore, for memory chips that include one or more superblock SBs changed to an erased state, the number of superblock SBs in the erased state included in the corresponding memory chip can be changed. Therefore, the number of superblock SBs in the erased state among the multiple memory chips DIE included in the memory device 110 may be unbalanced.

[0190] In Figure 15, the memory controller 120 can reset the target partition ZONE_T (S1510).

[0191] In addition, the memory controller 120 can determine whether the difference between the number of superblocks in the erasure state included in the first memory die 1st_Die and the number of superblocks in the erasure state included in the second memory die 2nd_Die is equal to or greater than a set threshold THR (S1520).

[0192] If the difference between the number of superblocks in the erasure state included in the first memory die 1st_Die and the number of superblocks in the erasure state included in the second memory die 2nd_Die is greater than or equal to the set threshold THR (S1520 - Yes), then the memory controller 120 can move the data stored in the first superblock 1st_SB to the second superblock 2nd_SB (S1530).

[0193] If the difference between the number of superblocks in the erasure state included in the first memory die 1st_Die and the number of superblocks in the erasure state included in the second memory die 2nd_Die is less than the threshold THR (S1520-No), the memory controller 120 can terminate the process without moving the data, since no data needs to be moved.

[0194] As described above, when the target domain ZONE_T is reset, the memory controller 120 can monitor the difference between the number of superblocks in the erasure state included in the first memory die 1st_Die and the number of superblocks in the erasure state included in the second memory die 2nd_Die, so that the memory controller 120 can effectively operate the memory system 100.

[0195] Figure 16 illustrates a method of operating a memory system 100 according to an embodiment of the disclosed technology.

[0196] Referring to FIG16, the operation method of memory system 100 may include: grouping multiple memory blocks BLK included in each of a plurality of memory dies DIEs—each memory die DIE includes multiple memory blocks BLKs—into one or more superblocks SB (S1610).

[0197] The operation method of the memory system 100 may include: counting the number of superblocks in the erasure state included in each memory die (S1620).

[0198] In addition, the operation method of the memory system 100 may include: moving the data stored in the first superblock 1st_SB to the second superblock 2nd_SB, wherein the first superblock 1st_SB is a first memory die 1st_DIE that has the minimum number of superblocks in the erasure state among a plurality of memory die DIEs, and the second superblock 2nd_SB is a second memory die 2nd_DIE that has the maximum number of superblocks in the erasure state among a plurality of memory die DIEs (S1630).

[0199] In S1630, the first superblock 1st_SB can be determined as the superblock with the smallest erase count among the superblocks in the write state included in the first memory die 1st_Die.

[0200] In S1630, the second superblock 2nd_SB can be determined as the superblock with the largest erase count among the superblocks in the erase state included in the second memory die 2nd_Die.

[0201] In addition, in S1630, when the difference between the number of superblocks in the erasure state included in the first memory die 1st_DIE and the number of superblocks in the erasure state included in the second memory die 2nd_DIE is greater than or equal to the set threshold THR, the data stored in the first superblock 1st_SB can be moved to the second superblock 2nd_SB.

[0202] The operation method of the memory system 100 may further include: allocating the superblock SB included in the multiple memory chips DIE to multiple partitions.

[0203] The operation method of the memory system 100 may further include: allocating one or more of the superblocks SB included in the multiple memory chips DIE to the target partition ZONE_T in the multiple partitions ZONE.

[0204] In this case, when the target partition ZONE_T is started, it is possible to assign one or more of the superblocks SB included in the multiple memory die DIEs to the target partition ZONE_T.

[0205] Assigning one or more of the superblocks SB included in a plurality of memory die DIEs to a target partition ZONE_T may include: selecting memory dies from a plurality of memory die DIEs in a round-robin manner, and assigning one or more of the superblocks SB included in the selected memory dies to the target partition ZONE_T.

[0206] The operation method of memory system 100 may further include: resetting the target partition ZONE_T.

[0207] In this case, resetting the target partition ZONE_T may include erasing the data stored in the superblock SB allocated to the target partition ZONE_T.

[0208] In addition, resetting the target partition ZONE_T may include: releasing the superblock SB allocated to the target partition ZONE_T.

[0209] Further, resetting the target partition ZONE_T may include: disabling the target partition ZONE_T.

[0210] The operation method of the memory system 100 may further include: when the difference between the number of superblocks in the erasure state included in the first memory die 1st_DIE and the number of superblocks in the erasure state included in the second memory die 2nd_DIE is greater than or equal to a set threshold THR, the data stored in the first superblock 1st_SB is moved to the second superblock 2nd_SB.

[0211] Figure 17 is a diagram showing the configuration of a computing system 1700 based on an embodiment of the disclosed technology.

[0212] Referring to FIG17, a computing system 1700 based on an embodiment of the disclosed technology may include: a memory system 100 electrically connected to a system bus 1760; a CPU 1710 configured to control the overall operation of the computing system 1700; a RAM 1720 configured to store data and information related to the operation of the computing system 1700; a user interface / user experience (UI / UX) module 1730 configured to provide a user environment to a user; a communication module 1740 configured to communicate with external devices in a wired and / or wireless manner; and a power management module 1750 configured to manage the power used by the computing system 1700.

[0213] The computing system 1700 may be a personal computer (PC) or may include a mobile terminal such as a smartphone, tablet computer or various electronic devices.

[0214] The computing system 1700 may further include a battery for providing operating voltage, and may further include an application chipset, a graphics-related module, a camera image processor, and DRAM. Other components will be apparent to those skilled in the art to which this invention pertains.

[0215] The memory system 100 may include not only devices such as hard disk drives (HDDs) configured to store data on a disk, but also devices such as solid-state drives (SSDs), general-purpose flash memory devices, or embedded MMC (eMMC) devices configured to store data in non-volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Furthermore, the memory system 100 may be implemented as various types of storage devices and installed inside various electronic devices.

[0216] Based on the embodiments of the disclosed technology described above, the operation latency of the memory system can be advantageously reduced or minimized. Furthermore, based on the embodiments of the disclosed technology, the overhead incurred during the invocation of specific functions can be advantageously reduced or minimized. Although various embodiments of the disclosed technology have been described in particular detail and with varying degrees of detail for illustrative purposes, it will be understood by those skilled in the art to which this invention pertains that various modifications, additions, and substitutions can be made based on the content disclosed or described in this patent application. [Simplified Explanation of the Diagram]

[0010] Figure 1 is a schematic diagram illustrating the configuration of a memory system based on an embodiment of the disclosed technology. Figure 2 is a block diagram schematically illustrating a memory device based on an embodiment of the disclosed technology. Figure 3 illustrates the structure of word lines and bit lines of a memory device based on an embodiment of the disclosed technology. Figure 4 illustrates an example of a schematic structure of a memory system according to an embodiment of the disclosed technology. Figure 5 illustrates an example of a schematic operation of a memory system according to an embodiment of the disclosed technology. Figure 6 illustrates an example of moving data in a memory system according to an embodiment of the disclosed technology. Figure 7 illustrates another example of moving data in a memory system according to an embodiment of the disclosed technology. Figure 8 illustrates an example of superblocks included in a plurality of memory dies in a memory system according to an embodiment of the disclosed technology. Figure 9 illustrates an example of the operation of moving data stored in a first superblock to a second superblock in a memory system according to an embodiment of the disclosed technology. Figure 10 illustrates an example of the state after moving data stored in a first superblock to a second superblock in a memory system according to an embodiment of the disclosed technology. Figure 11 illustrates a plurality of partitions in a memory system according to an embodiment of the disclosed technology. Figure 12 illustrates an example of allocating superblocks to specific partitions in a memory system according to an embodiment of the disclosed technology. Figure 13 illustrates an example of a memory system selecting a memory die according to an embodiment of the disclosed technology. Figure 14 illustrates an example of a memory system performing a target partition reset operation according to an embodiment of the disclosed technology. Figure 15 is a flowchart illustrating an example of an operation of moving data after the memory system resets the target partition according to an embodiment of the disclosed technology. Figure 16 illustrates an operation method of a memory system according to an embodiment of the disclosed technology. Figure 17 is a diagram illustrating the configuration of a computing system based on some embodiments of the disclosed technology.

Claims

1. A memory system, comprising: A memory device includes a plurality of memory chips, each of the plurality of memory chips including a plurality of memory blocks storing data, and different groups of memory blocks forming one or more superblocks; and a memory controller communicating with the memory device, wherein the memory controller: counts the number of superblocks in an erase state included in each memory chip to identify a first memory chip and a second memory chip, the first memory chip having a minimum number of superblocks in an erase state and the second memory chip having a maximum number of superblocks in an erase state, and moves data stored in the first superblocks included in the first memory chip to the second superblocks included in the second memory chip, wherein the memory controller moves data stored in the first superblock to the second superblock when the difference between the number of superblocks in the erase state included in the first memory chip and the number of superblocks in the erase state included in the second memory chip is greater than or equal to the set threshold. The memory controller further allocates the superblocks included in the plurality of memory dies to a plurality of partitions, the plurality of partitions being defined based on logical addresses corresponding to the plurality of partitions, and wherein garbage collection operations are not performed on the plurality of partitions.

2. The memory system as claimed in claim 1, wherein the memory controller further identifies the first superblock as the superblock with the minimum erase count among the superblocks in the write state included in the first memory die.

3. The memory system as claimed in claim 1, wherein the memory controller further identifies the second superblock as the superblock with the maximum erase count among the superblocks in the erase state included in the second memory die.

4. The memory system as claimed in claim 1, wherein the memory controller further activates a target partition of the plurality of partitions containing data to be written, and assigns one or more superblocks of the superblocks included in the plurality of memory dies to the target partition.

5. The memory system as claimed in claim 4, wherein the memory controller further selects memory chips among the plurality of memory chips in a polling manner, and assigns one or more superblocks included in the selected memory chips to the target partition.

6. The memory system as claimed in claim 4, wherein the memory controller further resets the target partition by erasing data stored in the superblock allocated to the target partition, releasing the superblock allocated to the target partition, and deactivating the target partition.

7. The memory system of claim 6, wherein the memory controller further moves data stored in the first superblock to the second superblock after resetting the target partition, wherein the data movement occurs when the difference between the number of superblocks in the erase state included in the first memory die and the number of superblocks in the erase state included in the second memory die is greater than or equal to a set threshold.

8. A method of operating a memory system, the method comprising: The number of superblocks in an erased state included in each of a plurality of memory chips is counted to identify a first memory chip and a second memory chip, the first memory chip having a minimum number of superblocks in an erased state and the second memory chip having a maximum number of superblocks in an erased state; and data stored in the first superblock included in the first memory chip is moved to the second superblock included in the second memory chip, and the superblocks included in the plurality of memory chips are allocated to a plurality of partitions, the plurality of partitions being defined based on logical addresses corresponding to the plurality of partitions, wherein when the difference between the number of superblocks in an erased state included in the first memory chip and the number of superblocks in an erased state included in the second memory chip is greater than or equal to a set threshold, the data stored in the first superblock is moved to the second superblock, and wherein garbage collection is not performed on the plurality of partitions.

9. The operating method as described in claim 8, further comprising: The first superblock is defined as the superblock with the smallest erase count among the superblocks in the write state included in the first memory die.

10. The operating method as described in claim 8, further comprising: The second superblock is defined as the superblock with the largest erase count among the superblocks in the erase state included in the second memory die.

11. The operating method as described in claim 8, further comprising: The target partition among the plurality of partitions is started; and one or more superblocks among the superblocks included in the plurality of memory dies are assigned to the target partition.

12. The method of operation as described in claim 11, wherein allocating one or more superblocks from the superblocks comprises: Memory chips are selected from the plurality of memory chips using a polling method; And assign one or more superblocks from the superblocks included in the selected memory die to the target partition.

13. The operation method as described in claim 11, further comprising resetting the target partition, wherein resetting the target partition includes: Erase the data stored in the superblock allocated to the target partition; Release the superblock allocated to the target partition; And disable the target partition.

14. The method of operation as described in claim 13, wherein after resetting the target partition, the data is moved from the first superblock to the second superblock, and the data movement occurs when the difference between the number of superblocks in the erase state included in the first memory die and the number of superblocks in the erase state included in the second memory die is greater than or equal to a set threshold.

Images