Ceramic electronic device and manufacturing method of the same

Abstract

This invention provides a ceramic electronic component capable of suppressing the peeling of external electrodes and a method for manufacturing the same. The ceramic electronic component is characterized by comprising: a multilayer wafer formed by alternately depositing a plurality of dielectric layers, with ceramic as the main component, and a plurality of internal electrode layers, wherein the deposited plurality of internal electrode layers are alternately exposed at a plurality of locations; and external electrodes disposed at each of the plurality of locations; wherein at least a portion of the external electrodes has a first metal layer disposed in contact with the multilayer wafer and a plating layer disposed on the first metal layer; the first metal layer comprises a first metal and a second metal having a Young's modulus lower than that of the first metal.

Description

[Technical Field]

[0001] This invention relates to a ceramic electronic component and its manufacturing method. [Previous Technology]

[0002] Ceramic electronic components such as multilayer ceramic capacitors have a structure in which a multilayer wafer and external electrodes are disposed. The multilayer wafer is formed by alternately depositing dielectric layers and internal electrode layers, with a plurality of internal electrode layers alternately exposed at a plurality of locations, and the external electrodes are disposed at these plurality of locations (see, for example, Patent Document 1). [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2015-65394 [Summary of the Invention]

[0004] [The problem the invention aims to solve]

[0005] However, external electrodes are sometimes peeled off from the stacked wafer.

[0006] This invention was made in view of the above-mentioned problems, and its object is to provide a ceramic electronic component capable of suppressing the peeling of external electrodes and a method for manufacturing the same. [Technical Means for Solving the Problem]

[0007] The ceramic electronic component of the present invention is characterized by comprising: a multilayer wafer, which is formed by alternately depositing a plurality of dielectric layers of ceramic as the main component and a plurality of internal electrode layers, wherein the plurality of internal electrode layers are alternately exposed at a plurality of locations; and an external electrode disposed at each of the plurality of locations; wherein the external electrode has at least a portion having a first metal layer disposed in contact with the multilayer wafer and a plating layer disposed on the first metal layer, wherein the first metal layer comprises a first metal and a second metal having a Young's modulus lower than that of the first metal.

[0008] In the above-mentioned ceramic electronic component, the external electrode has a structure in which the plating layer is provided on a bottom layer that is in contact with the plurality of locations, and the first metal layer is in contact with the laminated wafer at the interruption location of the bottom layer.

[0009] In the above-mentioned ceramic electronic components, the Young's modulus of the second metal may be less than 2 / 3 of the Young's modulus of the first metal.

[0010] In the first metal layer of the ceramic electronic component, when the first metal is set to 100 at%, the amount of the second metal may be 1 at% or less.

[0011] In the above-mentioned ceramic electronic components, the first metal may be Ti or Cr.

[0012] In the above-mentioned ceramic electronic components, the second metal may be Sn or In.

[0013] In the above-mentioned ceramic electronic components, the thickness of the first metal layer may be 5 nm or more and 100 nm or less.

[0014] The above-mentioned ceramic electronic component may further include a second metal layer disposed between the first metal layer and the plating layer.

[0015] In the above-mentioned ceramic electronic components, the dielectric layer may use barium titanate as the main component.

[0016] The method for manufacturing ceramic electronic components of the present invention is characterized by comprising the following steps: preparing a multilayer wafer, wherein the multilayer wafer is formed by alternately depositing a plurality of dielectric layers of ceramic as the main component and a plurality of internal electrode layers, wherein the plurality of internal electrode layers are alternately exposed at a plurality of locations; forming a metal layer in contact with the multilayer wafer and electrically connected to the internal electrode layers exposed at the plurality of locations by sputtering or vapor deposition; and forming a plating layer on the metal layer; wherein the metal layer comprises a first metal and a second metal having a Young's modulus lower than that of the first metal. [Effects of the Invention]

[0017] According to the present invention, a ceramic electronic component capable of suppressing the peeling of external electrodes and a method thereof can be provided.

Implementation Method

[0019] Hereinafter, the embodiments will be described with reference to the drawings on one side and the embodiments on the other.

[0020] (Embodiment) FIG1 is a partial cross-sectional perspective view of the multilayer ceramic capacitor 100 according to the embodiment. FIG2 is a cross-sectional view along line AA of FIG1. ​​FIG3 is a cross-sectional view along line BB of FIG1. ​​As illustrated in FIG1 to 3, the multilayer ceramic capacitor 100 includes a multilayer wafer 10 having a generally rectangular parallelepiped shape and external electrodes 20a and 20b disposed on any two end faces of the multilayer wafer 10 located on opposite sides. Furthermore, the two surfaces of the multilayer wafer 10 other than the two end faces, excluding the upper and lower surfaces in the stacking direction, are referred to as side surfaces. The external electrodes 20a and 20b extend on the upper surface, lower surface, and two side surfaces in the stacking direction of the multilayer wafer 10. However, the external electrodes 20a and 20b are separated from each other.

[0021] Furthermore, in Figures 1 to 3, the X-axis direction is the direction in which the two end faces of the stacked wafer 10 face each other, and it is also the direction in which the external electrodes 20a and 20b face each other. The Y-axis direction is the direction in which the two side faces of the stacked wafer 10 face each other. The Z-axis direction is the stacking direction, and it is also the direction in which the upper and lower surfaces of the stacked wafer 10 face each other. The X-axis, Y-axis, and Z-axis directions are orthogonal to each other.

[0022] The multilayer wafer 10 has a configuration in which dielectric layers 11 comprising ceramic material functioning as dielectric and internal electrode layers 12 comprising base metal material are alternately deposited. The ends of each internal electrode layer 12 are alternately exposed at multiple locations on the multilayer wafer 10. For example, the ends of each internal electrode layer 12 are alternately exposed on the end face of the multilayer wafer 10 where external electrodes 20a and external electrodes 20b are disposed. In this way, each internal electrode layer 12 is alternately electrically connected to the external electrodes 20a and 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which multiple dielectric layers 11 are deposited with internal electrode layers 12 in between. Furthermore, in the multilayer body of dielectric layers 11 and internal electrode layers 12, the internal electrode layer 12 is disposed on the outermost layer in the stacking direction, and the upper and lower surfaces of the multilayer body are covered by a capping layer 13. The capping layer 13 uses ceramic material as the main component. For example, regarding the material of the capping layer 13, the main component of the ceramic material can be the same as that of the dielectric layer 11.

[0023] The dimensions of the multilayer ceramic capacitor 100 are, for example, a length of 1.0 ± 0.05 mm in the X-axis direction, a width of 0.5 ± 0.05 mm in the Y-axis direction, and a height of 0.0975 ± 0.0125 mm in the Z-axis direction, or a length of 0.6 mm, a width of 0.3 mm, and a height of 0.110 mm, or a length of 1.0 mm, a width of 0.5 mm, and a height of 0.1 mm, but are not limited to these dimensions.

[0024] The internal electrode layer 12 uses base metals such as Ni (nickel), Cu (copper), and Sn (tin) as its main components. Noble metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or alloys containing these metals, may also be used as the internal electrode layer 12. The thickness of the internal electrode layer 12 is, for example, 0.1 μm to 3 μm, 0.1 μm to 1 μm, or 0.1 μm to 0.5 μm.

[0025] The dielectric layer 11 is, for example, a ceramic material having a perovskite structure represented by the general formula ABO3 as the main phase. Furthermore, this perovskite structure includes ABO3-α in addition to its stoichiometric composition. For example, as this ceramic material, at least one selected from BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), MgTiO3 (magnesium titanate), and Ba1-x-yCaxSryTi1-zZrzO3 (0≦x≦1, 0≦y≦1, 0≦z≦1) forming the perovskite structure can be used. Ba1-x-yCaxSryTi1-zZrzO3 is derived from barium strontium titanate, barium calcium titanate, barium zirconate, barium zirconate titanate, calcium zirconate titanate, and barium calcium zirconate titanate. The thickness of each dielectric layer 11 is, for example, 0.05 μm to 5 μm, or 0.1 μm to 3 μm, or 0.2 μm to 1 μm.

[0026] As illustrated in Figure 2, the regions of the inner electrode layer 12 connected to the external electrode 20a and the inner electrode layer 12 connected to the external electrode 20b, facing each other, are regions in the multilayer ceramic capacitor 100 that generate capacitance. Therefore, the region that generates this capacitance is called the capacitance region 14. That is, the capacitance region 14 is the region of adjacent inner electrode layers 12 connected to different external electrodes that face each other.

[0027] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without being separated from the internal electrode layers 12 connected to the external electrode 20b is called the end margin 15. Similarly, the region where the internal electrode layers 12 connected to the external electrode 20b face each other without being separated from the internal electrode layers 12 connected to the external electrode 20a is also called the end margin 15. In other words, the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without being separated from the internal electrode layers 12 connected to different external electrodes. The end margin 15 is a region that does not generate capacitance.

[0028] As illustrated in Figure 3, the region extending from two sides of the stacked wafer 10 to the internal electrode layer 12 is referred to as the side margin 16. That is, the side margin 16 is a region formed by the plurality of internal electrode layers 12 stacked in the above-described stacked structure, covering the ends extending towards the two sides. The side margin 16 is also a region that does not generate capacitance.

[0029] Figure 4 is a cross-sectional view of the external electrode 20b, and a partial cross-sectional view along line AA in Figure 1. Furthermore, the shading lines representing the cross-section are omitted in Figure 4. As illustrated in Figure 4, the external electrode 20b has a structure in which a plating layer is formed on the substrate 24. The plating layer, for example, includes, from the substrate 24 side, a first plating layer 21 such as Cu, a second plating layer 22 such as Ni, and a third plating layer 23 such as Sn in sequence.

[0030] The bottom layer 24 is disposed in such a way that it contacts and covers the end face of the stacked wafer 10. The bottom layer 24 may extend from the end face toward the opposite end face on two side surfaces, the upper surface, and the lower surface of the stacked wafer 10. The bottom layer 24 may use metals such as Cu, Ni, Al (aluminum), and Zn (zinc) as the main component, and may contain glass components for densifying the bottom layer 24 or the same material for controlling the sinterability of the bottom layer 24. The bottom layer 24 containing a large amount of such ceramic components has good adhesion to the dielectric layer 11 and the capping layer 13, which are mainly composed of ceramic materials. The external electrode 20a also has the same stacked structure as the external electrode 20b.

[0031] A first metal layer 25 is disposed between the bottom layer 24 and the plating layer. The first metal layer 25 covers the plating layer side surface of the bottom layer 24. The first metal layer 25 extends toward the opposite end face on two side surfaces, the upper surface, and the lower surface of the laminated wafer 10. The first metal layer 25 extends beyond the bottom layer 24 to the opposite end face side. In the region where the first metal layer 25 extends beyond the bottom layer 24 to the opposite end face side, the first metal layer 25 is disposed in contact with the surface of the laminated wafer 10, and a plating layer is disposed in contact with the first metal layer 25. For example, in the region where the bottom layer 24 is not disposed, the first metal layer 25 is disposed in contact with the surface of the cover layer 13 and the side distance 16. Furthermore, since the first metal layer 25 is in contact with the bottom layer 24, it is also electrically connected to the internal electrode layer. The external electrode 20a also has the same laminated structure as the external electrode 20b.

[0032] In the areas where the base layer 24 is not provided, the first metal layer 25 functions as a seed layer in the plating step. Therefore, by providing the first metal layer 25 in the areas where the base layer 24 is not provided, the peeling of the plating layer can be suppressed.

[0033] In areas where the underlayer 24 is provided, there may be interruptions (holes, etc.) where the underlayer 24 is not formed. For example, when the underlayer 24 is formed by calcining metal paste, sometimes the metal paste may not adhere to a portion of the surface of the laminated wafer 10 due to non-adhesion. In this case, as illustrated in FIG5, there is a risk that the underlayer 24 will not be formed on the areas where the metal paste is not adhered. There is a risk that the plating layer will peel off from the laminated wafer 10 on the areas where the underlayer 24 is not formed. However, in this embodiment, since the first metal layer 25 is provided on the areas where the underlayer 24 is not formed, the peeling of the plating layer can be suppressed.

[0034] The first metal layer 25 uses, for example, titanium (Ti) as the main component. However, Ti has a relatively large Young's modulus of about 106 GPa. Therefore, during the plating step or subsequent processing steps, it is not flexible enough to withstand the impact generated by the collision between the multilayer ceramic capacitors, and there is a risk of peeling off the external electrodes 20a and 20b. Therefore, in this embodiment, the first metal layer 25 has a second metal with a Young's modulus smaller than that of the first metal. This reduces the Young's modulus of the first metal layer 25 as a whole, making the first metal layer 25 more flexible. Therefore, peeling off the external electrodes 20a and 20b can be suppressed. The Young's modulus of each metal is illustrated in Table 1. [Table 1] Ti Sn Al Au Ag Pb Bi Zn In Ni Cu Young's Modulus (Gpa) 115.7 49.9 70.3 78.0 82.7 16.1 3.19 108.4 11.0 219.2 129.8

[0035] From the viewpoint of improving the flexibility of the first metal layer 25, the smaller the Young's modulus of the second metal, the better. For example, the Young's modulus of the second metal is preferably less than 2 / 3 of the Young's modulus of the first metal, more preferably less than 1 / 2, and even more preferably less than 1 / 3.

[0036] If the amount of the second metal in the first metal layer 25 is excessive, there is a risk of melting. Therefore, it is preferable to set an upper limit on the amount of the second metal in the first metal layer 25. For example, when (first metal + second metal) is set to 100 at%, the amount of the second metal is preferably 20 at% or less, more preferably 5 at% or less, and even more preferably 1 at% or less.

[0037] For example, since the resistivity of Ti is about 20 to 30 times that of Cu, if the first metal layer 25 is formed too thick, there is a risk of poor connection. Therefore, it is preferable to set an upper limit on the thickness of the first metal layer 25. For example, the thickness of the first metal layer 25 is preferably 100 nm or less, more preferably 75 nm or less, and even more preferably 50 nm or less.

[0038] On the other hand, if the first metal layer 25 is formed too thin, there is a risk of peeling. Therefore, it is preferable to set a lower limit for the thickness of the first metal layer 25. For example, the thickness of the first metal layer 25 is preferably 5 nm or more, more preferably 10 nm or more, and even more preferably 20 nm or more.

[0039] For example, Ti is preferably used as the first metal. This is because Ti forms a Ti-O bond with the barium titanate substrate, and a Ti-Cu bond is formed when the first coating layer 21 is Cu, thus improving adhesion. Alternatively, Cr or the like is preferably used as the first metal. This is because it forms Cr-O and Cr-Cu bonds.

[0040] For example, tin (Sn) is preferably used as the second metal. This is because peeling is suppressed by using a material with a smaller Young's modulus. Alternatively, In is preferably used as the second metal. This is because its atomic number is close to that of Sn, and its mechanical and electrical properties are similar to those of Sn.

[0041] Furthermore, as illustrated in FIG5, a second metal layer 26 may also be provided between the first metal layer 25 and the plating layer. For example, the second metal layer 26 may be provided in a manner that covers the first metal layer 25. The second metal layer 26 is provided from the viewpoint of the adhesion of the plating layer. For example, it is preferable to use the same metal as the first plating layer 21 as the second metal layer 26. Furthermore, since Cu has the function of preventing hydrogen intrusion, it is preferable that both the first plating layer 21 and the second metal layer 26 are Cu.

[0042] Furthermore, when the bottom layer 24 is made thinner from the viewpoint of suppressing the thickness of the external electrodes 20a and 20b, the bottom layer 24 is prone to interruption, and the effect of providing the first metal layer 25 is significant. For example, when the thickness of the bottom layer 24 is 0.1 μm to 10 μm, 0.2 μm to 5 μm, or 0.5 μm to 3 μm, the effect of providing the first metal layer 25 is significant.

[0043] In each of the external electrodes 20a and 20b, the length of the region on the upper surface, lower surface and two side surfaces of the multilayer wafer 10 where the bottom layer 24 is not provided and the first metal layer 25 contacts the multilayer wafer 10 is, for example, more than 1 / 10 and less than 4 / 10 of the length of the multilayer ceramic capacitor 100.

[0044] Next, the manufacturing method of the multilayer ceramic capacitor 100 will be described. Figure 6 is a flowchart illustrating the manufacturing method of the multilayer ceramic capacitor 100.

[0045] (Raw Material Powder Preparation Steps) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site and B-site elements contained in the dielectric layer 11 are typically contained in the dielectric layer 11 in the form of a sintered body of ABO3 particles. For example, BaTiO3 is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can usually be obtained by reacting titanium raw materials such as titanium dioxide with barium raw materials such as barium carbonate to synthesize barium titanate. Various methods are known for synthesizing the ceramic as the main component of the dielectric layer 11, such as the solid-state method, sol-gel method, and hydrothermal method. In this embodiment, any one of these methods can be used.

[0046] To the obtained ceramic powder, a specific additive compound may be added as desired. Examples of additive compounds include: oxides of tin (Sn), magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), thorium (Gd), tbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thionium (Tm) and ytterbium (Yb)), or oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K) or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium or silicon.

[0047] For example, a compound containing the additive compound is wet-mixed into ceramic raw material powder, dried, and pulverized to prepare a ceramic material. For example, the particle size of the ceramic material obtained as described above can also be adjusted by pulverization as needed, or by combining it with a classification process. Based on the above steps, a dielectric material is obtained.

[0048] (Lamination Step) Next, binders such as polyvinyl butyral (PVB) resin, organic solvents such as ethanol and toluene, and plasticizers are added to the obtained dielectric material, and wet mixing is performed. Using the obtained slurry, for example by die coating or blade coating, a dielectric preform 52 is coated onto the substrate 51 and dried. The substrate 51 is, for example, a PET (polyethylene glycol terephthalate) film.

[0049] Next, as illustrated in FIG7(a), an internal electrode pattern 53 is formed on the dielectric preform 52. In FIG7(a), as an example, a four-layer internal electrode pattern 53 is formed by leaving specific intervals on the dielectric preform 52. The film formation method is not particularly limited, for example, an electrode paste containing the main component metal of the internal electrode layer 12 can be used. Alternatively, vacuum film formation such as sputtering using a target of the main component metal of the internal electrode layer 12 can also be used. The dielectric preform 52 with the internal electrode pattern 53 is used as a stacking unit.

[0050] Next, while peeling the dielectric preform 52 from the substrate 51, as illustrated in FIG7(b), stacking units are stacked. Then, a specific number (e.g., 2 to 10 layers) of cover sheets 55 are stacked on top and below the stacked body obtained by stacking the stacking units, and thermo-pressed together to form a specific wafer size (e.g., 1.0 mm × 0.5 mm). In the example of FIG7(b), the cut is made along the dotted line. The cover sheet 55 may have the same composition as the dielectric preform 52, but the added compounds may differ.

[0051] (Calcination Step) After the ceramic multilayer obtained in this way is treated with a debinding agent under a N2 atmosphere, as shown in Figure 8(a), a metal paste 54 is applied to both ends of the ceramic multilayer to form the bottom layer 24 of the external electrodes 20a and 20b by an impregnation method. The multilayer is then calcined at 1100 to 1300°C for 10 minutes to 2 hours in a reducing gas atmosphere with an oxygen partial pressure of 10⁻⁵ to 10⁻⁸ atm.

[0052] (Re-oxidation treatment step) Afterwards, re-oxidation treatment can also be carried out in an N2 gas atmosphere at 600℃~1000℃.

[0053] (Metal Layer Formation Step) Next, the area where the external electrodes 20a and 20b are disposed is covered with a metal mask, as illustrated in FIG8(b), to form a first metal layer 25. Sputtering or vapor deposition can be used as the film formation method. Vapor deposition can be chemical vapor deposition or physical vapor deposition. For example, an alloy of the first metal and the second metal contained in the first metal layer 25 can be used as a target to form the first metal layer 25. Furthermore, as illustrated in FIG8(b), a second metal layer 26 can also be formed by covering the first metal layer 25. The second metal layer 26 can also be formed by sputtering or vapor deposition.

[0054] (Platinum plating process) Subsequently, through plating, the first metal layer 25 is used as a seed layer to form the first plating layer 21, the second plating layer 22, and the third plating layer 23. When the second metal layer 26 is provided, the second metal layer 26 is used as a seed layer.

[0055] According to the manufacturing method of this embodiment, since the first metal layer 25 is formed by sputtering or vapor deposition, a denser film with higher purity can be formed compared to the case of coating Ni paste by dipping or other methods. This results in good conductivity of the first metal layer 25 and faster deposition of the plating layer. Furthermore, since the first metal layer 25 is formed by sputtering or vapor deposition, it can also be formed on interrupted areas where the metal paste 54 is not adhered due to non-adhesion or other reasons. Therefore, peeling of the plating layer can be suppressed at the interrupted areas of the metal paste 54. Moreover, since the first metal layer 25 includes a second metal having a Young's modulus smaller than that of the first metal, the Young's modulus of the first metal layer 25 as a whole can be reduced, making the first metal layer 25 more flexible. Therefore, peeling of the external electrodes 20a and 20b can be suppressed.

[0056] Furthermore, after obtaining the stacked wafer 10 by calcination, the underlayer 24 can also be formed. For example, a metal paste 54 for forming the underlayer, containing metal powder, glass frit, binder, and solvent, can be applied to both ends of the stacked wafer 10, dried, and then the metal paste for forming the underlayer can be sintered. In this way, the underlayer 24 can be formed.

[0057] Furthermore, in the above embodiments, a multilayer ceramic capacitor was described as an example of a ceramic electronic component, but it is not a limitation. For example, other electronic components such as rheostats or thermistors can also be used. [Example]

[0058] Hereinafter, a multilayer ceramic capacitor will be manufactured according to the embodiment.

[0059] Additives are added to barium titanate powder, and the dielectric material is obtained by wet mixing and pulverizing using a ball mill. Butyraldehyde is added to the dielectric material as an organic binder, and toluene and ethanol are added as solvents. A dielectric preform is coated onto a PET substrate using a doctor blade method. Next, an internal electrode pattern is formed on the dielectric preform using a slurry containing Ni powder.

[0060] Next, while peeling the dielectric preform from the substrate, the stacking units are stacked. Next, a specific number of cover sheets are stacked on top and bottom of the stacked body obtained by stacking the stacking units, and then thermo-pressed together. After that, it is cut into a specific wafer size.

[0061] The ceramic multilayer obtained in this way is treated with a debinding agent under a N2 gas atmosphere, and then coated with a metal paste to form the bottom layer of the external electrode by an impregnation method, and calcined under a reducing gas atmosphere.

[0062] After calcination, the area where the external electrode is located is left, covered with a metal shield, and a Ti metal layer is formed by sputtering. An alloy of Ti and Sn is used as the target. In this alloy, Ti is set to 100 at%, and Sn is set to 20 at%. The thickness of the Ti metal layer is 0.05 μm. Then, a Cu layer is formed on the Ti metal layer by sputtering. The thickness of the Cu layer is 0.4 μm. Then, a Cu layer with a thickness of 5 μm, a Ni layer with a thickness of 3 μm, and a Sn layer with a thickness of 2 μm are sequentially deposited.

[0063] Figure 9(a) is a SEM image depicting a cross-section. Figure 9(b) is an enlarged view of part A in Figure 9(a). Figure 9(c) is an enlarged view of part B in Figure 9(a). As shown in Figure 9(b), a first metal layer 25 of Ti and a second metal layer 26 of Cu are formed on the bottom layer 24. On the second metal layer 26, a first plating layer 21 of Cu, a second plating layer 22 of Ni, and a third plating layer 23 of Sn are formed sequentially. Furthermore, as shown in Figure 9(c), in the areas where the bottom layer 24 should have been formed but was not, the first metal layer 25 of Ti is formed by contact with the surface of the laminated wafer. Thus, it can be seen that in the areas where the bottom layer 24 is not formed, the first metal layer 25 can be formed by sputtering.

[0064] The embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific embodiments. Various changes and modifications can be made within the scope of the spirit of the present invention as described in the claims. [Simplified Explanation of the Diagram]

[0018] Figure 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. Figure 2 is a cross-sectional view along line AA in Figure 1. Figure 3 is a cross-sectional view along line BB in Figure 1. Figure 4 is a cross-sectional view of the external electrode, and also a partial cross-sectional view along line AA in Figure 1. Figure 5 is a partial enlarged view of Figure 4. Figure 6 is a flowchart illustrating the manufacturing method of the multilayer ceramic capacitor. Figures 7(a) and (b) are diagrams illustrating the multilayering steps. Figure 8(a) is a diagram illustrating the application of metal paste, and Figure 8(b) is a diagram illustrating the metal layer formation steps. Figure 9(a) is a SEM photograph depicting a cross-section, Figure 9(b) is an enlarged view of part A, and Figure 9(c) is an enlarged view of part B.

Claims

1. A ceramic electronic component, characterized by comprising: a multilayer wafer formed by alternately depositing a plurality of dielectric layers of ceramic as the main component and a plurality of internal electrode layers, wherein the plurality of internal electrode layers are alternately exposed at a plurality of locations; and an external electrode disposed at each of the plurality of locations; wherein the external electrode has at least a portion having a first metal layer disposed in contact with the multilayer wafer and a plating layer disposed on the first metal layer, the first metal layer comprising a first metal and a second metal having a Young's modulus lower than that of the first metal, the external electrode having a structure in which the plating layer is disposed on a bottom layer disposed in contact with the plurality of locations, wherein the first metal layer is disposed in contact with the multilayer wafer at an interruption of the bottom layer.

2. The ceramic electronic component as claimed in claim 1, wherein the Young's modulus of the second metal is less than 2 / 3 of the Young's modulus of the first metal.

3. In the ceramic electronic component of claim 1 or 2, where the first metal in the first metal layer is set to 100 at%, the amount of the second metal is 1 at% or less.

4. Ceramic electronic components as claimed in item 1 or 2, wherein the first metal is Ti or Cr.

5. Ceramic electronic components as claimed in item 1 or 2, wherein the second metal is Sn or In.

6. For ceramic electronic components as claimed in claim 1 or 2, wherein the thickness of the first metal layer is 5 nm or more and 100 nm or less.

7. The ceramic electronic component of claim 1 or 2 further comprises a second metal layer disposed between the first metal layer and the plating layer.

8. The ceramic electronic component as claimed in claim 1 or 2, wherein the dielectric layer uses barium titanate as the main component.

9. A ceramic electronic component, characterized by comprising: a laminated wafer formed by alternately depositing a plurality of dielectric layers of ceramic as the main component and a plurality of internal electrode layers, wherein the plurality of internal electrode layers are alternately exposed at a plurality of locations; and an external electrode disposed at each of the plurality of locations; wherein the external electrode has at least a portion having a first metal layer disposed in contact with the laminated wafer and a plating layer disposed on the first metal layer, wherein the first metal layer comprises a first metal and a second metal having a Young's modulus lower than that of the first metal, and wherein, in the first metal layer, when the first metal is 100 at%, the amount of the second metal is 1 at% or less.

10. A method for manufacturing a ceramic electronic component, comprising the following steps: A multilayer wafer is prepared by alternately depositing a plurality of dielectric layers with ceramic as the main component and a plurality of internal electrode layers, wherein the plurality of internal electrode layers are alternately exposed at a plurality of locations; a metal layer is formed by sputtering or vapor deposition that is in contact with the multilayer wafer and electrically connected to the internal electrode layers exposed at the plurality of locations; and a plating layer is formed on the metal layer; wherein the metal layer comprises a first metal and a second metal having a Young's modulus lower than that of the first metal, and the metal layer has a structure in which the plating layer is disposed on a bottom layer disposed in contact with the plurality of locations, and the metal layer is disposed in contact with the multilayer wafer at the interruption locations of the bottom layer.

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