Apparatus, method and non-transitory computer-readable medium for meshlet shading atlas

Abstract

The various forms presented herein relate to methods and devices for graphics processing, including devices such as GPUs. The device can divide at least one scene into a plurality of small meshes, each of which comprises a plurality of primitives, and each of which comprises a plurality of vertices. The device can also compute texture coordinate pairs for each of the plurality of vertices. Furthermore, the device can select the size of each of the plurality of small meshes in the at least one scene based on the texture coordinate pairs and based on the perspective projection of each of the plurality of small meshes. The device can also compute layout information for each of the at least one small mesh in the small mesh atlas. Furthermore, the device can color each of the plurality of primitives in the small mesh atlas based on the computed layout information.

Description

Technical Field

[0001] This patent application claims the benefit and priority of U.S. Provisional Application No. 63 / 261,909 entitled "MESHLET SHADING ATLAS", filed on September 30, 2021, and U.S. Patent Application No. 17 / 934,159 entitled "MESHLET SHADING ATLAS", filed on September 21, 2022, the entire contents of which are expressly incorporated herein by reference.

[0002] This invention relates generally to a processing system, and more specifically to one or more graphics processing techniques. Prior Technology

[0003] Computing devices typically perform graphics and / or display processing (e.g., using a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices can include, for example, computer workstations, mobile phones (such as smartphones), embedded systems, personal computers, tablets, and video game consoles. A GPU is configured to execute a graphics processing pipeline comprising one or more processing stages that operate together to execute graphics processing commands and output frames. A CPU can control the operation of a GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of executing multiple applications simultaneously, each of which may require the use of the GPU during execution. A display processor is configured to convert digital information received from the CPU into analog values ​​and can issue commands to a display panel for displaying visual content. Devices that provide content for visual representation on a display can utilize a GPU and / or a display processor.

[0004] The device's GPU can be configured to execute programs in the graphics processing pipeline. Additionally, a display processor or display processing unit (DPU) can be configured to execute programs for display processing. However, with the advent of wireless communication and smaller handheld devices, the demand for improved graphics or display processing is increasing. Summary of the Invention

[0005] The following is a simplified overview of one or more states to provide a basic understanding of them. This overview is not a comprehensive overview of all conceived states, and is not intended to identify key or important elements of all states, nor to outline the scope of any or all states. Its sole purpose is to present some concepts of one or more states in a simplified form as an introduction to the more detailed descriptions that follow.

[0006] In one embodiment of this invention, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a graphics processing unit (GPU) or any apparatus capable of performing graphics processing. The apparatus may divide at least one scene into a plurality of small meshes, each of the plurality of small meshes comprising a plurality of primitives, and each of the plurality of primitives comprising a plurality of vertices. The apparatus may also identify the visibility of each of the plurality of small meshes in at least one scene, wherein each of the plurality of small meshes is identified as visible or invisible. Additionally, the apparatus may discard each of the plurality of small meshes identified as invisible. The apparatus may also calculate texture coordinate pairs for each of the plurality of vertices of each of the plurality of primitives in each of the plurality of small meshes. The device can also select the size of each of a plurality of small meshes in at least one scene based on texture coordinate pairs of each of a plurality of vertices of each of a plurality of primitives in each of a plurality of small meshes and based on the perspective projection of each of the plurality of small meshes. Furthermore, the device can calculate layout information for each of the plurality of small meshes in at least one scene in a small mesh atlas, the layout information for each small mesh in the small mesh atlas being based on the selected size of the small mesh. The device can also color each of the plurality of primitives in the small mesh atlas based on the layout information calculated in the small mesh atlas. The device can also render each of the plurality of small meshes identified as visible, wherein the small mesh atlas is sampled to determine the color of each of the plurality of primitives in the output image. Furthermore, the device can send an output image to a display or panel, the output image including the rendered plurality of small meshes identified as visible.

[0007] Details of one or more embodiments of this application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of this application will be apparent from the description and drawings, as well as from the claims. Simple Explanation of the Diagram

[0008] Figure 1 is a block diagram illustrating the generation system based on one or more technologies in this case.

[0009] Figure 2 illustrates an example GPU based on one or more technologies in this case.

[0010] Figure 3 is a diagram of the coloring spectrum of the example illustration.

[0011] Figure 4A is a diagram of the illustrated example three-dimensional (3D) model.

[0012] Figure 4B is a diagram of the illustrated example visualization model.

[0013] Figure 4C is a diagram of the small grid in the illustration example.

[0014] Figure 5A is a diagram of the screen space bounding box of the illustrated example.

[0015] Figure 5B is a diagram of the spatial block of the illustrated example.

[0016] Figure 6 is a diagram of the small grid in the illustration example.

[0017] Figure 7 is a communication flowchart illustrating the instance communication between the GPU component and the display / panel.

[0018] Figure 8 is a flowchart of the example graphics processing method.

[0019] Figure 9 is a flowchart of the example graphics processing method. Implementation

[0020] Some forms of graphics processing can utilize different types of shading procedures, such as object-space shading or texel shading. Object-space shading stores the shading results in object space, rather than in the final image space as in other types of shading. Object space can be the texture space of the model, as in texel shading. In a shading graph stream, object space is a graph that shades model patches within blocks (e.g., rectangular blocks). In some forms of graphics processing, different object-space shading methods can encapsulate the shading workload differently (e.g., in different types of shading units). This can improve shading efficiency and enable data streaming and / or reuse of shading information. Some forms of texel shading can use primitive tiles (e.g., 8×8 primitive tiles) in the original texture space of each texture. Furthermore, shading graph streams can use patches mapped to rectangular blocks (e.g., up to 3 primitives / triangles). In contrast, screen-space methods can operate at the per-primal level (or within screen-space tiles), which may require recalculation approximately per frame. Therefore, screen-space methods may be difficult to use and / or stream data with sufficient temporal coherence. Object-space shading methods may also result in a mismatch between the object-space sampling style and the target screen-space sampling style. This mismatch can lead to oversampling, which wastes GPU performance (e.g., up to 400% of processed primitives). Furthermore, a mismatch can lead to undersampling, which degrades image quality. In some cases, due to rectangle mapping to blocks, distorted primitives / triangles in the shading map may suffer undersampling on one axis and oversampling on another. The morphisms of this invention can provide shading methods, such as object-space shading methods, that include sampling styles that match the target screen-space sampling style. For example, the morphisms of this invention can include, for example, large shading units in texture space whose mapping is primarily view-independent and distortion-free for all possible views. The morphisms of this invention can also provide shading units that are sufficiently large and approximately aligned with their screen-space size. By doing so, the effects of oversampling and undersampling can be minimized in the anisotropic samples of this case.

[0021] The various forms of systems, apparatuses, computer program products, and methods are described more fully below with reference to the accompanying drawings. However, this invention can be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout this invention. Rather, these forms are provided to make the invention thorough and complete, and to fully convey the scope of this invention to those skilled in the art to which it pertains. Based on the teachings herein, those skilled in the art to which this invention pertains should understand that the scope of this invention is intended to cover any form of the systems, apparatuses, computer program products, and methods disclosed herein, whether implemented independently of or in combination with other forms of this invention. For example, any number of forms set forth herein can be used to implement an apparatus or practice a method. Furthermore, the scope of this invention is intended to cover such apparatuses or methods practiced using structures, functions, or structures and functions other than those set forth herein. Any form disclosed herein may be embodied by one or more elements of a claim.

[0022] Although various forms are described herein, many variations and arrangements of these forms fall within the scope of this application. While some potential benefits and advantages of the various forms of this application are mentioned, the scope of this application is not intended to be limited to any particular benefit, use, or objective. Rather, the various forms of this application are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transport protocols, some of which are illustrated by way of example in the accompanying drawings and the following description. The detailed description and drawings are illustrative only and not limiting, and the scope of this application is defined by the appended claims and their equivalents.

[0023] Various devices and methods are presented to illustrate several aspects. These devices and methods will be described in detail below and illustrated in the accompanying drawings using various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system.

[0024] For example, an element, any part of an element, or any combination of elements can be implemented as a "processing system" comprising one or more processors (also referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, system-on-a-chip (SoCs), baseband processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, individual hardware circuitry, and other suitable hardware configured to perform the various functions described herein. One or more processors in a processing system can execute software. Software can be broadly interpreted as instructions, instruction sets, code, code fragments, code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, executable threads, programs, functions, etc., regardless of whether they are called software, firmware, middleware, microcode, hardware description languages, or others. The term "application" can refer to software. As described herein, one or more technologies can refer to an application, i.e., software, configured to perform one or more functions. In such instances, the application can be stored in memory, such as on-chip memory of a processor, system memory, or any other memory. The hardware described herein (such as a processor) can be configured to execute the application. For example, an application can be described as including code that, when executed by the hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware can access code from memory and execute the code accessed from memory to perform one or more technologies described herein. In some instances, components are identified in the content of this document. In such instances, a component can be hardware, software, or a combination thereof. A component can be a single component or a sub-component of a single component.

[0025] Therefore, in one or more of the examples described herein, the described functions can be implemented in hardware, software, or any combination thereof. If implemented in software, the functions can be stored on a computer-readable medium or encoded as one or more instructions or codes on a computer-readable medium. Computer-readable media includes computer storage media. Storage media can be any available media accessible by a computer. For example, but not limited to, such computer-readable media can include random access memory (RAM), read-only memory (ROM), electronically erasable programmable ROM (EEPROM), optical disc storage devices, magnetic storage devices, other magnetic storage devices, combinations of computer-readable media of the above types, or any other media that can be used to store computer-executable code in the form of computer-accessible instructions or data structures.

[0026] Generally, this document describes techniques for having a graphics processing pipeline in a single device or multiple devices, improving the rendering of graphics content, and / or reducing the load on processing units (i.e., any processing unit, such as a GPU, configured to perform one or more of the techniques described herein). For example, this document describes techniques for graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this document.

[0027] As used herein, instances of the term "content" can refer to "graphic content," "imagery," or vice versa. This applies regardless of whether these terms are used as adjectives, nouns, or other parts of speech. In some instances, as used herein, the term "graphic content" can refer to content produced by one or more programs in the graphics processing pipeline. In some instances, as used herein, the term "graphic content" can refer to content produced by a processing unit configured to perform graphics processing. In some instances, as used herein, the term "graphic content" can refer to content produced by a graphics processing unit.

[0028] In some instances, as used herein, the term "display content" can refer to content generated by a processing unit configured to perform display processing. Graphical content can be processed into display content. For example, a graphics processing unit can output graphical content (such as frames) to a buffer (which may be referred to as a frame buffer). A display processing unit can read graphical content (such as one or more frames) from the buffer and perform one or more display processing techniques thereon to produce display content. For example, a display processing unit can be configured to perform compositing on one or more rendered layers to produce frames. As another example, a display processing unit can be configured to composite, blend, or otherwise combine two or more layers together into a single frame. A display processing unit can be configured to perform scaling (e.g., zooming in or zooming out) on the frame. In some instances, a frame can represent a layer. In other instances, a frame can refer to two or more layers that have been blended together to form a frame; that is, the frame includes two or more layers, and frames including two or more layers can then be blended.

[0029] Figure 1 is a block diagram illustrating an example content generation system 100 configured to implement one or more technologies of this invention. The content generation system 100 includes a device 104. Device 104 may include one or more components or circuits for performing the various functions described herein. In some instances, one or more components of device 104 may be components of a System-on-a-Chip (SOC). Device 104 may include one or more components configured to perform one or more technologies of this invention. In the illustrated example, device 104 may include a processing unit 120, a content encoder / decoder 122, and system memory 124. In some cases, device 104 may include multiple components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. Reference to display 131 may refer to one or more displays 131. For example, display 131 may include a single display or multiple displays. Display 131 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some instances, the first and second displays may receive different frames for rendering on them. In other instances, the first and second displays may receive the same frames for rendering on them. In still other instances, the results of graphics processing may not be displayed on the device; for example, the first and second displays may not receive any frames for rendering on them. Instead, the frames or graphics processing results may be transferred to another device. In some cases, this can be called split rendering.

[0030] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing, such as in graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some instances, device 104 may include a display processor, such as display processor 127, to perform one or more display processing techniques on one or more frames generated by processing unit 120 before they are presented by one or more displays 131. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise present frames processed by display processor 127. In some instances, one or more displays 131 may include one or more of the following: liquid crystal display (LCD), plasma display, organic light-emitting diode (OLED) display, projection display device, augmented reality display device, virtual reality display device, head-mounted display, or any other type of display device.

[0031] External memory (such as system memory 124) of the processing unit 120 and content encoder / decoder 122 can be accessed by the processing unit 120 and content encoder / decoder 122. For example, the processing unit 120 and content encoder / decoder 122 can be configured to read from and / or write to external memory (such as system memory 124). The processing unit 120 and content encoder / decoder 122 can be communicatively coupled to system memory 124 via a bus. In some instances, the processing unit 120 and content encoder / decoder 122 can be communicatively coupled to each other via a bus or different connections.

[0032] Content encoder / decoder 122 can be configured to receive graphical content from any source, such as system memory 124 and / or communication interface 126. System memory 124 can be configured to store received encoded or decoded graphical content. Content encoder / decoder 122 can be configured to receive, for example, encoded or decoded graphical content in the form of encoded primitive data from system memory 124 and / or communication interface 126. Content encoder / decoder 122 can be configured to encode or decode any graphical content.

[0033] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memory or storage devices. In some instances, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), flash memory, magnetic data media or optical storage media, or any other type of memory.

[0034] According to some examples, internal memory 121 or system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagating signal. However, the term "non-transitory" should not be construed as meaning that internal memory 121 or system memory 124 is immovable or that its contents are static. As one example, system memory 124 may be removed from device 104 and moved to another device. As another example, system memory 124 may not be removable from device 104.

[0035] Processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit capable of being configured to perform graphics processing. In some instances, processing unit 120 may be integrated into the motherboard of device 104. In some instances, processing unit 120 may reside on a graphics card mounted in a port on the motherboard of device 104, or may otherwise be incorporated into a peripheral device configured to interact with device 104. Processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the processing unit 120 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and one or more processors may be used to execute the instructions in hardware to perform the technology of this invention. Any of the foregoing (including hardware, software, combinations of hardware and software, etc.) may be considered as one or more processors.

[0036] The content encoder / decoder 122 can be any processing unit configured to perform content decoding. In some instances, the content encoder / decoder 122 can be integrated into the motherboard of device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is implemented in part in software, the content encoder / decoder 122 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and one or more processors may be used to execute the instructions in hardware to perform the technology of this invention. Any of the foregoing (including hardware, software, combinations of hardware and software, etc.) can be considered as one or more processors.

[0037] In some embodiments, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any of the receiving functions described herein with respect to device 104. Additionally, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, or location information. The transmitter 130 may be configured to perform any of the sending functions described herein with respect to device 104. For example, the transmitter 130 may be configured to send information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined to form a transceiver 132. In such instances, the transceiver 132 may be configured to perform any of the receiving and / or sending functions described herein with respect to device 104.

[0038] Referring again to Figure 1, in some configurations, processing unit 120 may include a small mesh component 198 configured to divide at least one scene into a plurality of small meshes, each of which comprises a plurality of primitives, and each of which comprises a plurality of vertices. The small mesh component 198 may also be configured to identify the visibility of each of the plurality of small meshes in at least one scene, wherein each of the plurality of small meshes is identified as visible or invisible. The small mesh component 198 may also be configured to discard each of the plurality of small meshes identified as invisible. The small mesh component 198 may also be configured to compute texture coordinate pairs for each of the plurality of vertices of each of the plurality of primitives in each of the plurality of small meshes. The small mesh component 198 can also be configured to select the size of each of the plurality of small meshes in at least one scene based on texture coordinate pairs of each vertex of each of the plurality of primitives in each of the plurality of small meshes and based on the perspective projection of each of the plurality of small meshes. The small mesh component 198 can also be configured to calculate layout information for each of the plurality of small meshes in at least one scene in a small mesh atlas, the layout information for each small mesh in the small mesh atlas being based on the selected size of the small mesh. The small mesh component 198 can also be configured to shade each of the plurality of primitives in the small mesh atlas based on the layout information calculated in the small mesh atlas. The small mesh component 198 can also be configured to render each of the plurality of small meshes identified as visible, wherein the small mesh atlas is sampled to determine the color of each of the plurality of primitives in the output image. The small grid component 198 can also be configured to send an output image to a display or panel, the output image comprising a plurality of rendered small grids that are identified as visible. Although the following description may focus on graphics processing, the concepts described herein can be applied to other similar processing techniques.

[0039] As described herein, a device (such as device 104) can refer to any device, apparatus, or system configured to perform one or more of the technologies described herein. For example, a device can be a server, base station, user equipment, client equipment, station, access point, computer (e.g., personal computer, desktop computer, laptop computer, tablet computer, computer workstation, or mainframe computer), terminal product, apparatus, telephone, smartphone, server, video game platform or console, handheld device (e.g., portable video game device or personal digital assistant (PDA)), wearable computing device (e.g., smartwatch), augmented reality device or virtual reality device, non-wearable device, display or display device, television set, set-top box, intermediate network device, digital media player, video streaming device, content streaming device, in-vehicle computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more of the technologies described herein. The processing described herein can be described as being performed by a specific component (e.g., GPU); however, in further embodiments, it may be performed using other components (e.g., CPU) consistent with the disclosed embodiments.

[0040] A GPU can process various types of data or data packets within the GPU pipeline. For example, in some cases, a GPU can process two types of data or data packets, such as context register packets and draw call data. A context register packet can be a set of global state information, such as information about global registers, shaders, or constant data, which can regulate how the graphics context will be handled. For example, a context register packet may include information about color formats. In some cases of context register packets, there may be bits indicating which workload belongs to the context register. Furthermore, multiple functions or programs may execute simultaneously and / or in parallel. For example, a function or program may describe an operation, such as a color mode or color format. Therefore, context registers can define multiple states of the GPU.

[0041] Context states can be used to determine how individual processing units (e.g., vertex extractors (VFDs), vertex shaders (VSs), shader processors, or geometry processors) operate and / or in what modes they operate. To do this, the GPU can use context registers and programming data. In some cases, the GPU can generate workloads in the pipeline based on context register definitions for modes or states, such as vertex or primitive workloads. Some processing units (e.g., VFDs) can use these states to determine certain functions, such as how vertices are assembled. Because these modes or states can change, the GPU may need to modify the corresponding context. Additionally, workloads corresponding to a particular mode or state can follow the changed mode or state.

[0042] Figure 2 illustrates an example GPU 200 according to one or more technologies of this invention. As shown in Figure 2, GPU 200 includes a command processor (CP) 210, a draw call packet 212, a VFD 220, a VS 222, a vertex cache memory (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z-processing engine (ZPE) 230, a primitive interpolator (PI) 232, a fragment shader (FS) 234, a rendering backend (RB) 236, a level 2 (L2) cache memory (UCHE) 238, and system memory 240. Although Figure 2 shows GPU 200 including processing units 220-238, GPU 200 may include multiple additional processing units. Furthermore, processing units 220-238 are merely examples, and any combination or order of processing units may be used by the GPU according to this invention. GPU 200 also includes command buffer 250, context register packet 260, and context state 261.

[0043] As shown in Figure 2, the GPU can utilize a CP (e.g., CP 210) or a hardware accelerator to resolve the command buffer into a context register packet (e.g., context register packet 260) and / or a draw call data packet (e.g., draw call packet 212). The CP 210 can then send the context register packet 260 or the draw call packet 212 to a processing unit or block in the GPU via a separate path. Furthermore, the command buffer 250 can alternate between different states of the context register and the draw call. For example, the command buffer can be constructed as follows: a context register for context N, a draw call for context N, a context register for context N+1, and a draw call for context N+1.

[0044] GPUs can render images in various ways. In some cases, GPUs can use both rendering and / or tile rendering to render images. In a tile-rendering GPU, an image can be divided or segmented into different parts or tiles. After the image is divided, each segment or tile can be rendered separately. A tile-rendering GPU can divide a computer graphics image into a grid format, so that each part of the grid (i.e., a tile) is rendered individually. In some cases, during binning passes, the image can be divided into different bins or tiles. In some cases, during binning passes, a visibility stream can be built, where visible primitives or draw calls can be identified. In contrast to tile rendering, direct rendering does not divide the frame into smaller bins or tiles. Instead, in direct rendering, the entire frame is rendered at once. Additionally, some types of GPUs allow both tile rendering and direct rendering.

[0045] In some cases, the GPU can apply drawing or rendering procedures to different bins or tiles. For example, the GPU can render to a bin and perform all drawing of the primitives or primitives within that bin. During the bin-to-bin procedure, the render target may reside in GMEM. In some cases, after rendering to a bin, the contents of the render target can be moved to system memory, and GMEM is released to render the next bin. Alternatively, the GPU can render to another bin and perform drawing of the primitives or primitives within that bin. Thus, in some cases, there may be a small number of bins (e.g., four bins) that cover all drawing on a surface. Furthermore, the GPU can loop through all drawing in a bin but only perform drawing for visible drawing calls (i.e., drawing calls that include visible geometry). In some cases, a visibility stream can be generated, for example, during binning to determine the visibility information of each primitive in the image or scene. For example, the visibility stream can identify whether a primitive is visible. In some cases, this information can be used, for example, to remove invisible primitives in a render pass. In addition, at least some primitives identified as visible can be rendered in the rendering pass.

[0046] In some states of tile rendering, multiple processing stages or passes can exist. For example, rendering can be performed in two passes: a visibility or box visibility pass and a rendering or box rendering pass. During the visibility pass, the GPU can input the rendering workload, record the position of primitives or triangles, and then determine which primitives or triangles fall into which box or region. In some states of the visibility pass, the GPU can also identify or mark the visibility of each primitive or triangle in the visibility stream. During the rendering pass, the GPU can input the visibility stream and process one box or region at a time. In some states, the visibility stream can be analyzed to determine which primitives or primitive vertices are visible or invisible. Thus, visible primitives or primitive vertices can be processed. By doing so, the GPU can reduce the unnecessary workload of processing or rendering invisible primitives or triangles.

[0047] In some cases, certain types of primitive geometry (e.g., positional geometry only) can be processed during the visibility pass. Additionally, primitives can be categorized into different bins or regions depending on their position or location. In some cases, primitives or triangles can be categorized into different bins by determining their visibility information. For example, the GPU can determine or write the visibility information for each primitive to each bin or region, such as system memory. This visibility information can be used to determine or generate a visibility stream. In the rendering pass, primitives in each bin can be rendered individually. In these cases, the visibility stream can be obtained from memory used to discard primitives that are not visible to that bin.

[0048] Some GPU or GPU architectures offer several different rendering options, such as software rendering and hardware rendering. In software rendering, the driver or CPU can copy the entire frame geometry by processing each view once. Additionally, different states can be changed depending on the view. Thus, in software rendering, the software can copy the entire workload by changing some states available for rendering each viewpoint of the image. In some cases, this can increase the management burden because the GPU can submit the same workload multiple times for each viewpoint of the image. In hardware rendering, the hardware or GPU can be responsible for copying or processing the geometry of each viewpoint of the image. Therefore, the hardware can manage the copying or processing of primitives or triangles for each viewpoint in the image.

[0049] In some cases, rendering can be performed in multiple locations and / or on multiple devices, for example, to divide the rendering workload among different devices. For instance, rendering can be split between server and client devices, which can be called "split rendering". In some cases, split rendering can be a method for bringing content to a user device or head-mounted display (HMD), where a portion of the graphics processing can be performed outside of that device or HMD, such as on a server.

[0050] Split rendering can be performed for several different types of applications (e.g., Virtual Reality (VR) applications, Augmented Reality (AR) applications, and / or Extended Reality (XR) applications). In VR applications, the content displayed on the user's device can correspond to artificial or animated content. In AR or XR content, a portion of the content displayed on the user's device can correspond to real-world content (e.g., real-world objects), and a portion of that content can be artificial or animated content. Moreover, the artificial or animated content and the real-world content can be displayed in an optical or visual perspective device, allowing the user to view real-world objects and artificial or animated content simultaneously. In some cases, the artificial or animated content can be referred to as augmented content, or vice versa.

[0051] Figure 3 illustrates an example of a shading map 300 used in graphics processing. As shown in Figure 3, some forms of graphics processing can utilize shading map data streams, such as via shading map 300. A shading map stream is an object space rendering framework suitable for streaming virtual reality (VR) content. In some cases, a shading map stream may also be referred to as a vector stream. A shading map stream can dynamically render patches of primitives into a texture map. A shading map stream can also patch multiple primitives or triangles (e.g., one (1) to three (3) primitives or triangles) assigned to a rectangle in the map.

[0052] Some aspects of graphics processing can also determine the visibility of patches of two or three adjacent primitives / triangles. Graph memory management can be directly derived from the potential visible set (PVS) of the current and predicted viewpoints (i.e., using the extended field of view (FOV)). This graph memory management procedure can be executed dynamically on the graphics processing unit (GPU). Newly visible patches can be allocated to the graph, while patches that have become invisible can be removed from the graph. Furthermore, the patch size can be determined based on the projected area of ​​the patch on the screen. During the shading stage, visible patches can be shaded into the graph using standard geometry channels.

[0053] In split-rendering applications (e.g., applications involving server and client devices), the server can compute coloring information in a colorimetric map (e.g., colorimetric map 300). The colorimetric map can be encoded (e.g., MPEG encoding) and streamed to the client device (e.g., a standalone head-mounted display (HMD)). The colorimetric map can be temporally coherent, facilitating efficient MPEG compression and data streaming. The client device can render the final view at a higher frame rate. Additionally, coloring can be sampled from the colorimetric map. As the user moves their head, new views can be rendered. These new views can utilize the latest colorimetric frames available at the client device.

[0054] Some aspects of graphics processing can utilize different types of shading procedures (e.g., object-space shading or texel shading). Object-space shading stores the shading results in object space, rather than in the final image space as is common in other types of shading. Object space can be the texture space of the model, as in texel shading. In a shading atlas stream, object space is an atlas that shades model patches within blocks (e.g., rectangular blocks). For example, shading atlas 300 in Figure 3 can be an object space where model patches are shaded within blocks.

[0055] In some forms of graphics processing, different object-space shading methods can encapsulate shading workloads differently. This can improve shading efficiency and enable data streaming and / or reuse of shading information. Some forms of texel shading can group shading workloads by using primitive tiles (e.g., 8×8 primitive tiles) in the original texture space of each texture. Furthermore, shading map streaming can group shading workloads by using patches mapped to rectangular blocks (e.g., groups of up to 3 primitives / triangles). In contrast, screen-space methods can operate at the per-primal level (or within screen-space tiles), which may require recalculation approximately per frame. Therefore, screen-space methods may struggle to reuse and / or stream data with sufficient temporal coherence.

[0056] Object-space shading methods can also lead to a mismatch between the object-space sampling style and the target screen-space sampling style. This mismatch can result in oversampling, wasting GPU performance. Furthermore, it can lead to undersampling, causing image quality degradation. In some cases, due to rectangle-to-block mapping, distorted primitives / triangles in the shading map may suffer undersampling on one axis and oversampling on another. Based on these considerations, it may be beneficial to provide a shading method that includes a sampling style that matches the target screen-space sampling style. It may also be beneficial to identify large areas that can be continuously shading (e.g., in texture space), whose mapping is primarily view-independent and distortion-free for all possible views. Additionally, it may be beneficial to include shading units that are sufficiently large and roughly aligned with their screen-space size.

[0057] The morphic samples of this invention can provide a shading method (e.g., an object-space shading method) that includes a sampling style that matches the sampling style of the target screen space. For example, the morphic samples of this invention can include (e.g., in texture space) large shading units whose mapping is primarily view-independent and distortion-free for all possible views. The morphic samples of this invention can also provide shading units that are sufficiently large and approximately aligned with their screen space size. By doing so, the morphic samples of this invention can minimize the effects of oversampling and undersampling.

[0058] In some morphologies, the shading atlas flow can rely on object-space shading and can use patches (e.g., up to three primitives or triangles) mapped into rectangular blocks as unit building blocks. Object-space shading methods can suffer from the fact that their sampling style does not match the target screen space sampling style, which can lead to oversampling and undersampling. The morphologies presented in this paper propose object-space shading methods to address this problem, including sampling styles that match the target screen space sampling style. For example, the morphologies presented in this paper can utilize shading units whose mapping is view-independent and distortion-free for multiple views (e.g., all possible views). The morphologies presented in this paper can also utilize shading units that are large enough and roughly aligned with their screen space size to minimize the effects of oversampling and undersampling.

[0059] In some cases, the isomorphisms of this invention can define the set of primitives used for shading by dividing the scene into small meshes and precompiling multiple view-independent graphs. For example, the isomorphisms of this invention can precompile a two-dimensional (2D) graph (i.e., a UV graph) including a first axis (U) and a second axis (V). A small mesh is a set of geometric primitives that may or may not be connected. Small meshes can be generated to be relatively flat so that self-occlusion does not occur within the small mesh to avoid artifacts. As described herein, each small mesh may include one or more primitives or triangles. Furthermore, small meshes can be a convenient representation for modern rendering engines. For example, mesh shaders can significantly increase the performance of modern rendering pipelines.

[0060] The various states in this case can utilize or target small meshes with the largest primitive / triangle count. Furthermore, the various states in this case can use existing shading map memory management to render small meshes into the map. In some states, a fixed UV chart for each small mesh can be streamed once during initialization, and this UV chart can update the offset in the map. Additionally, larger small meshes may result in fewer instances requiring processing and data streaming.

[0061] Furthermore, the various samples in this invention can utilize a rendering process comprising multiple different stages. For example, the various samples in this invention can be rendered using a preprocessing stage, a visibility stage, a memory management stage, a shading stage, and / or a display stage. During the preprocessing stage, the various samples in this invention can generate small meshes and a UV map by applying a least-squares conformal mapping method. During the visibility stage, the various samples in this invention can determine which small meshes are visible and which are invisible. During the memory management stage, the various samples in this invention can allocate space for each visible small mesh in the atlas. During the shading stage, the various samples in this invention can shade each small mesh of the allocated atlas block. Finally, during the display stage, the various samples in this invention can render the final view / image using the visible small meshes with offsets in the atlas and / or the pre-computed UV map. To display the final view / image, the view / image can be transmitted to a monitor or display panel.

[0062] Figures 4A, 4B, and 4C illustrate Figures 400, 420, and 440 of the example shaded 3D model 402, the example small mesh visualization model 422, and the example small mesh 442, respectively. More specifically, Figures 400, 420, and 440 in Figures 4A, 4B, and 4C illustrate different stages of the transformation process. As illustrated in Figures 4A, 4B, and 4C, the transformation process includes the shaded 3D model 402, the small mesh visualization model 422, and the small mesh 442 in the color atlas. As shown in Figure 4A, Figure 400 includes the shaded 3D model 402, which includes a distinguishing region (i.e., a white border). This distinguishing region corresponds to an area in the color atlas that includes at least one small mesh (e.g., small mesh 442). As shown in Figure 4B, Figure 420 includes the small mesh visualization model 422, which includes the distinguishing region (i.e., a white border). Similar to Figure 4A, the identification region corresponds to an area in the color map that includes at least one small grid (e.g., small grid 442). As illustrated in Figure 4C, Figure 440 includes small grid 442 in the color map, which corresponds to the identification region in Figures 4A and 4B.

[0063] The various forms in this case can also utilize temporal coherence methods. For example, since the UV chart is pre-computed, changes in the projection size of the small grid may lead to a scaling adjustment of the mapping from the small grid to the atlas. This scaling procedure can be similar to that in standard coloring atlases. Moreover, this procedure can be combined with temporal reuse and cache memory to produce higher efficiency (this can be similar to temporally self-adjusting coloring). Furthermore, streaming transcoders can utilize temporal coherence similar to that of standard coloring atlases.

[0064] As mentioned earlier, the various morphologies in this case can utilize a memory management phase during the rendering process. In the memory management phase, the size of the small mesh can be determined in a manner similar to the original shading map. For example, the size of the small mesh can be determined based on the maximum angle between the small mesh center, the camera, and the vertices in the small mesh. This mesh size determination can be performed to avoid perspective projection problems. In some morphologies, the individual sides of the bounding box (e.g., the screen space bounding box) can be enlarged to a power of a certain power (e.g., the next power of two). Furthermore, blocks of corresponding sizes (e.g., map space blocks) can be allocated in the shading map. Additionally, an offset (i.e., an offset similar to that in the original shading map) can be applied to the bounding box size. This procedure can be used to limit the amount of shading workload.

[0065] Figures 5A and 5B illustrate Figures 500 and 520, respectively, of an instance screen space bounding box and an instance atlas space block. As shown in Figure 5A, Figure 500 includes a screen space bounding box 502. As mentioned herein, the screen space bounding box 502 can be used during the memory management phase of the rendering process. More specifically, during the memory management phase, a bias can be applied to the size of the bounding box. Furthermore, the individual sides of the screen space bounding box 502 can be enlarged to a power of a certain power (e.g., a power of 2). As shown in Figure 5B, Figure 520 includes an atlas space block 522. As mentioned above, the atlas space block 522 can be allocated in the shading atlas. For example, the atlas space block 522 can correspond to the size of the screen space bounding box 502 and be allocated in the shading atlas. Furthermore, the length of the atlas space block 522 can correspond to a certain amount (e.g., 2^m), and the width of the atlas space block 522 can correspond to another amount (e.g., 2^n), where m and n are integers.

[0066] Figure 6 illustrates a sample mesh 600 used during the shading phase. As shown in Figure 6, Figure 600 includes a mesh 610 and shading primitives 620. As mentioned above, the various embodiments of this invention can utilize the shading phase during the rendering process. During the shading phase, a mesh shader can be used to shade certain meshes (e.g., visible meshes) in a shading atlas (or mesh atlas). As illustrated in Figure 6, a border of shading primitives (e.g., shading primitives 620) can be added around each shading mesh (e.g., mesh 610). By adding a border of shading primitives 620 around mesh 610, texture filtering can be allowed when sampling from the atlas. The shading atlas can contain shading information corresponding to the visible surfaces of the rendered scene. The mesh atlas can contain mesh information corresponding to the visible surfaces of the rendered scene. Furthermore, layout information can be information about the arrangement of elements within the rendered scene.

[0067] The various states in this case can also utilize the display phase during the rendering process. In some cases, this display phase can be the direct rendering pass. For example, texture coordinates can be calculated in the vertex shader using a pre-computed UV map (i.e., stored per vertex) and offsets in the atlas. Texture coordinates are coordinates in texture space. Texture coordinates can be relative to a position in texture space (e.g., (0,0)). Furthermore, when a texture is applied to a primitive, its texel addresses can be mapped to object coordinates. Object coordinates can then be converted to screen coordinates or primitive positions. Additionally, the fragment shader can utilize texture coordinates from the vertex shader to perform texture inspection of the shading atlas.

[0068] The morphisms presented in this paper can include many different benefits or advantages. As mentioned above, the morphisms can provide a robust texture space shading approach that utilizes certain shading methods, such as small meshes and mesh shaders. The texture space shading solution according to this paper can be largely independent of the texture resolution of the original model. Furthermore, the texture space shading solution can reduce sampling artifacts by employing a view-independent pre-computed UV graph. For example, the view-independent pre-computed UV graph can combine primitives / triangles, such as as many primitives / triangles as possible. The texture space shading solution can also maintain efficient memory management, temporal coherence, potential data streaming capabilities, and / or compactness of the shading map. Therefore, the morphisms presented herein can provide a practical approach for utilizing texture space cache memory and / or rendering engines. For example, the morphisms presented herein can be used with many procedures, such as global illumination, temporal accumulation / cache memory / anti-aliasing, and baking.

[0069] Figure 7 is a communication flowchart 700 of graphics processing according to one or more technologies of this invention. As shown in Figure 7, Figure 700 includes an example of communication between GPU component 702 (e.g., a component in the GPU pipeline), display or panel 704 and GPU component 706 (e.g., a component in the GPU pipeline) according to one or more technologies of this invention.

[0070] At 710, GPU component 702 can divide at least one scene into a plurality of small meshes, each of which comprises a plurality of primitives, and each of which comprises a plurality of vertices. In some states, GPU component 702 can receive an indication of at least one scene (e.g., GPU component 702 can receive an indication of at least one scene 712 from GPU component 706). In some states, each of the plurality of primitives in each of the plurality of small meshes can be adjacent to at least one other primitive among the plurality of primitives, within a threshold distance of the at least one other primitive, or spatially coherent with the at least one other primitive.

[0071] At 720, GPU component 702 can identify the visibility of each of a plurality of small meshes in at least one scene, wherein each of the plurality of small meshes is identified as visible or invisible. In some cases, each of the plurality of small meshes identified as visible may correspond to at least one primitive among a plurality of colored primitives in a small mesh atlas.

[0072] At 730, GPU component 702 can discard each of the plurality of small grids that are identified as invisible.

[0073] At 740, GPU component 702 can compute texture coordinate pairs for each vertex of each primitive within each of a plurality of sub-mesh units. These texture coordinate pairs for each vertex of each of the plurality of sub-mesh units can be pre-computed based on a minimum distortion arrangement of the sub-mesh units. Furthermore, these texture coordinate pairs for each vertex of each of the plurality of sub-mesh units can be dynamically computed based on the perspective projection of the sub-mesh units. Additionally, these texture coordinate pairs for each vertex of each of the plurality of sub-mesh units can be computed in a mesh shader, vertex shader, or compute shader.

[0074] At 750, GPU component 702 can select the size of each of the plurality of small meshes in at least one scene based on texture coordinate pairs of each of the plurality of vertices of each of the plurality of primitives in each of the plurality of small meshes and based on the perspective projection of each of the plurality of small meshes. The perspective projection of each of the plurality of small meshes can be a projection of each small mesh onto an image plane corresponding to the current viewpoint of at least one scene. Furthermore, the size of each of the plurality of small meshes can be based on the maximum value of the angle between the center of each of the plurality of small meshes and each of the plurality of vertices of the small mesh, where the angle corresponds to the current viewpoint of at least one scene.

[0075] At 760, GPU component 702 can calculate layout information for each of a plurality of small meshes in at least one scene in a small mesh atlas, the layout information for each small mesh in the small mesh atlas being based on a selected size of the small mesh. In some cases, calculating the layout information in the small mesh atlas may include allocating space for each of a plurality of small meshes in at least one scene in the small mesh atlas, wherein the space allocated for each of the plurality of small meshes in the shading atlas is based on a selected size of the small mesh. The small mesh atlas may correspond to an object space shading representation. Furthermore, the small mesh atlas may be associated with a graphics application, including at least one of the following: a data streaming application, a global illumination application, a temporal accumulation application, a cache memory application, or an anti-aliasing application.

[0076] At 770, GPU component 702 can color each of a plurality of primitives in a minimesh map based on layout information calculated in the minimesh map. In some cases, coloring each of a plurality of primitives in a minimesh map may include calculating the surface color of each of the plurality of primitives in the minimesh map. For example, GPU component can calculate the surface color of each of the plurality of primitives in the minimesh map. In addition, coloring each of a plurality of primitives in a minimesh map may include calculating at least one of the following: transparency information of each of the plurality of primitives in the minimesh map, object identification code of each of the plurality of primitives in the minimesh map, one or more surface normals of each of the plurality of primitives in the minimesh map, or world space position of each of the plurality of primitives in the minimesh map. For example, a GPU component can compute at least one of the following: transparency information of each of a plurality of primitives in a small mesh map, object identification code of each of a plurality of primitives in a small mesh map, one or more surface normals of each of a plurality of primitives in a small mesh map, or world space position of each of a plurality of primitives in a small mesh map.

[0077] At 780, GPU component 702 can render each of a plurality of small grids that are identified as visible, wherein the small grid map is sampled to determine the color of each of a plurality of primitives in the output image.

[0078] At 790, GPU component 702 may send an output image to a display or panel (e.g., display / panel 704), the output image comprising a plurality of rendered small grids that are identified as visible (e.g., GPU component 702 may transmit image 792 to display / panel 704).

[0079] Figure 8 is a flowchart 800 of an example graphics processing method according to one or more technologies of this invention. The method can be executed by a GPU, such as a graphics processing device, another graphics processor, a GPU pipeline, a wireless communication device, and / or any device capable of performing graphics processing as described in the examples of Figures 1 through 7.

[0080] At 802, the GPU can divide at least one scene into a plurality of small meshes, each of which comprises a plurality of primitives, and each of which comprises a plurality of vertices, as described in conjunction with the examples in Figures 1 through 7. For example, as described at 710 in Figure 7, GPU component 702 can divide at least one scene into a plurality of small meshes, each of which comprises a plurality of primitives, and each of which comprises a plurality of vertices. Furthermore, step 802 can be performed by processing unit 120 in Figure 1. In some states, each of the plurality of primitives in each of the plurality of small meshes can be adjacent to at least one other primitive among the plurality of primitives, within a threshold distance of the at least one other primitive, or spatially coherent with the at least one other primitive. In some states, the GPU can receive an indication of at least one scene (e.g., the GPU can receive an indication of at least one scene from another GPU component).

[0081] At 808, the GPU can compute texture coordinate pairs for each vertex of each primitive in each of a plurality of small meshes, as described in conjunction with the examples in Figures 1 to 7. For example, as shown at 740 in Figure 7, GPU component 702 can compute texture coordinate pairs for each vertex of each primitive in each of a plurality of small meshes. Furthermore, step 808 can be performed by processing unit 120 in Figure 1. The texture coordinate pairs for each vertex of each of a plurality of small meshes can be pre-computed based on a minimum distortion arrangement of the small meshes. Furthermore, the texture coordinate pairs for each vertex of each of a plurality of small meshes can be dynamically computed based on the perspective projection of the small meshes. Furthermore, the pair of texture coordinates for each vertex of each of the plurality of vertices in each of the plurality of subgrids can be computed in the mesh shader, vertex shader, or compute shader.

[0082] At 810, the GPU can select the size of each of the plurality of small meshes in at least one scene based on texture coordinate pairs of each of the plurality of vertices of each of the plurality of primitives in each of the plurality of small meshes and based on the perspective projection of each of the plurality of small meshes, as described in conjunction with the examples in Figures 1 to 7. For example, as described at 750 in Figure 7, GPU component 702 can select the size of each of the plurality of small meshes in at least one scene based on texture coordinate pairs of each of the plurality of vertices of each of the plurality of primitives in each of the plurality of small meshes and based on the perspective projection of each of the plurality of small meshes. Furthermore, step 810 can be performed by processing unit 120 in Figure 1. The perspective projection of each of the plurality of small meshes can be a projection of each small mesh onto an image plane corresponding to the current viewpoint of at least one scene. Furthermore, the size of each of the plurality of small grids can be based on the maximum value of the angle between the center of each of the plurality of small grids and each of the plurality of vertices of the small grid, where the angle corresponds to the current viewpoint of at least one scene.

[0083] At 812, the GPU can compute layout information for each of a plurality of small meshes in at least one scene within a small mesh atlas, the layout information for each small mesh in the small mesh atlas being based on a selected size of the small mesh, as described in conjunction with the examples in Figures 1 through 7. For example, as described at 760 in Figure 7, GPU component 702 can compute layout information for each of a plurality of small meshes in at least one scene within a small mesh atlas, the layout information for each small mesh in the small mesh atlas being based on a selected size of the small mesh. Furthermore, step 812 can be performed by processing unit 120 in Figure 1. In some cases, computing the layout information in the small mesh atlas may include allocating space in the small mesh atlas for each of a plurality of small meshes in at least one scene, wherein the space allocated for each of the plurality of small meshes in the shading atlas is based on a selected size of the small mesh. The small mesh atlas may correspond to an object space shading representation. In addition, small grid maps can be associated with graphics applications, including at least one of the following: data streaming applications, global illumination applications, time accumulation applications, cache memory applications, or anti-aliasing applications.

[0084] At step 814, the GPU can color each of the plurality of primitives in the small mesh map based on layout information calculated in the small mesh map, as described in conjunction with the examples in Figures 1 to 7. For example, as shown at 770 in Figure 7, GPU component 702 can color each of the plurality of primitives in the small mesh map based on layout information calculated in the small mesh map. Furthermore, step 814 can be performed by processing unit 120 in Figure 1. In some cases, coloring each of the plurality of primitives in the small mesh map may include calculating the surface color of each of the plurality of primitives in the small mesh map. For example, the GPU can calculate the surface color of each of the plurality of primitives in the small mesh map. Additionally, shading each of a plurality of primitives in a small mesh map may include calculating at least one of the following: transparency information of each of the plurality of primitives in the small mesh map, object identification code of each of the plurality of primitives in the small mesh map, one or more surface normals of each of the plurality of primitives in the small mesh map, or world space position of each of the plurality of primitives in the small mesh map. For example, a GPU component may calculate at least one of the following: transparency information of each of the plurality of primitives in the small mesh map, object identification code of each of the plurality of primitives in the small mesh map, one or more surface normals of each of the plurality of primitives in the small mesh map, or world space position of each of the plurality of primitives in the small mesh map.

[0085] Figure 9 is a flowchart 900 of an example graphics processing method according to one or more technologies of this invention. The method can be executed by a GPU, such as a graphics processing device, another graphics processor, a GPU pipeline, a wireless communication device, and / or any device capable of performing graphics processing as described in the examples of Figures 1 through 7.

[0086] At 902, the GPU can divide at least one scene into a plurality of small meshes, each of which comprises a plurality of primitives, and each of which comprises a plurality of vertices, as described in conjunction with the examples in Figures 1 through 7. For example, as described at 710 in Figure 7, GPU component 702 can divide at least one scene into a plurality of small meshes, each of which comprises a plurality of primitives, and each of which comprises a plurality of vertices. Furthermore, step 902 can be performed by processing unit 120 in Figure 1. In some states, each of the plurality of primitives in each of the plurality of small meshes can be adjacent to at least one other primitive among the plurality of primitives, within a threshold distance of the at least one other primitive, or spatially coherent with the at least one other primitive. In some states, the GPU can receive an indication of at least one scene (e.g., the GPU can receive an indication of at least one scene from another GPU component).

[0087] At 904, the GPU can identify the visibility of each of a plurality of small meshes in at least one scene, wherein each of the plurality of small meshes is identified as visible or invisible, as described in conjunction with the examples in Figures 1 through 7. For example, as described at 720 in Figure 7, GPU component 702 can identify the visibility of each of a plurality of small meshes in at least one scene, wherein each of the plurality of small meshes is identified as visible or invisible. Furthermore, step 904 can be performed by processing unit 120 in Figure 1. In some cases, each of the plurality of small meshes identified as visible may correspond to at least one primitive among a plurality of colored primitives in a small mesh atlas.

[0088] At 906, the GPU can discard each of the plurality of small meshes identified as invisible, as described in conjunction with the examples in Figures 1 through 7. For example, as described at 730 in Figure 7, GPU component 702 can discard each of the plurality of small meshes identified as invisible. Furthermore, step 906 can be performed by processing unit 120 in Figure 1.

[0089] At 908, the GPU can compute texture coordinate pairs for each vertex of each primitive in each of a plurality of small meshes, as described in conjunction with the examples in Figures 1 to 7. For example, as described at 740 in Figure 7, GPU component 702 can compute texture coordinate pairs for each vertex of each primitive in each of a plurality of small meshes. Furthermore, step 908 can be performed by processing unit 120 in Figure 1. The texture coordinate pairs for each vertex of each of a plurality of small meshes can be pre-computed based on a minimum distortion arrangement of the small meshes. Furthermore, the texture coordinate pairs for each vertex of each of a plurality of small meshes can be dynamically computed based on the perspective projection of the small meshes. Furthermore, the pair of texture coordinates for each vertex of each of the plurality of vertices in each of the plurality of subgrids can be computed in the mesh shader, vertex shader, or compute shader.

[0090] At 910, the GPU can select the size of each of the plurality of small meshes in at least one scene based on texture coordinate pairs of each of the plurality of vertices of each of the plurality of primitives in each of the plurality of small meshes and based on the perspective projection of each of the plurality of small meshes, as described in conjunction with the examples in Figures 1 to 7. For example, as described at 750 in Figure 7, GPU component 702 can select the size of each of the plurality of small meshes in at least one scene based on texture coordinate pairs of each of the plurality of vertices of each of the plurality of primitives in each of the plurality of small meshes and based on the perspective projection of each of the plurality of small meshes. Furthermore, step 910 can be performed by processing unit 120 in Figure 1. The perspective projection of each of the plurality of small meshes can be a projection of each small mesh onto an image plane corresponding to the current viewpoint of at least one scene. Furthermore, the size of each of the plurality of small grids can be based on the maximum value of the angle between the center of each of the plurality of small grids and each of the plurality of vertices of the small grid, where the angle corresponds to the current viewpoint of at least one scene.

[0091] At 912, the GPU can compute layout information for each of a plurality of small meshes in at least one scene within a small mesh atlas, the layout information for each small mesh in the small mesh atlas being based on a selected size of the small mesh, as described in conjunction with the examples in Figures 1 through 7. For example, as described at 760 in Figure 7, GPU component 702 can compute layout information for each of a plurality of small meshes in at least one scene within a small mesh atlas, the layout information for each small mesh in the small mesh atlas being based on a selected size of the small mesh. Furthermore, step 912 can be performed by processing unit 120 in Figure 1. In some cases, computing the layout information in the small mesh atlas may include allocating space in the small mesh atlas for each of a plurality of small meshes in at least one scene, wherein the space allocated for each of the plurality of small meshes in the shading atlas is based on a selected size of the small mesh. The small mesh atlas may correspond to an object space shading representation. In addition, small grid maps can be associated with graphics applications, including at least one of the following: data streaming applications, global illumination applications, time accumulation applications, cache memory applications, or anti-aliasing applications.

[0092] At step 914, the GPU can color each of the plurality of primitives in the small mesh map based on layout information calculated in the small mesh map, as described in conjunction with the examples in Figures 1 to 7. For example, as shown at 770 in Figure 7, GPU component 702 can color each of the plurality of primitives in the small mesh map based on layout information calculated in the small mesh map. Furthermore, step 914 can be performed by processing unit 120 in Figure 1. In some cases, coloring each of the plurality of primitives in the small mesh map may include calculating the surface color of each of the plurality of primitives in the small mesh map. For example, the GPU can calculate the surface color of each of the plurality of primitives in the small mesh map. Additionally, shading each of a plurality of primitives in a small mesh map may include calculating at least one of the following: transparency information of each of the plurality of primitives in the small mesh map, object identification code of each of the plurality of primitives in the small mesh map, one or more surface normals of each of the plurality of primitives in the small mesh map, or world space position of each of the plurality of primitives in the small mesh map. For example, a GPU may calculate at least one of the following: transparency information of each of the plurality of primitives in the small mesh map, object identification code of each of the plurality of primitives in the small mesh map, one or more surface normals of each of the plurality of primitives in the small mesh map, or world space position of each of the plurality of primitives in the small mesh map.

[0093] At 916, the GPU can render each of the plurality of small grids identified as visible, wherein the small grid map is sampled to determine the color of each of the plurality of primitives in the output image, as described in conjunction with the examples in Figures 1 through 7. For example, as described at 780 in Figure 7, GPU component 702 can render each of the plurality of small grids identified as visible, wherein the small grid map is sampled to determine the color of each of the plurality of primitives in the output image. Furthermore, step 916 can be performed by processing unit 120 in Figure 1.

[0094] At 918, the GPU can send an output image to a display or panel, the output image comprising a plurality of rendered small grids identified as visible, as described in conjunction with the examples in Figures 1 through 7. For example, as described at 790 in Figure 7, GPU component 702 can send an output image to a display or panel, the output image comprising a plurality of rendered small grids identified as visible. Furthermore, step 918 can be performed by processing unit 120 in Figure 1.

[0095] In this configuration, a method or apparatus for graphics processing is provided. The apparatus may be a GPU, a graphics processing unit, or some other processor capable of performing graphics processing. In various embodiments, the apparatus may be a processing unit 120 within device 104, or may be some other hardware within device 104 or another device. The apparatus (e.g., processing unit 120) may include components for dividing at least one scene into a plurality of small meshes, each of the plurality of small meshes comprising a plurality of primitives, and each of the plurality of primitives comprising a plurality of vertices. The apparatus (e.g., processing unit 120) may also include components for calculating texture coordinate pairs for each vertex of each of the plurality of vertices of each of the plurality of primitives in each of the plurality of small meshes. The apparatus (e.g., processing unit 120) may also include components for selecting the size of each of a plurality of small meshes in at least one scene based on texture coordinate pairs of each of a plurality of vertices of each of a plurality of primitives in each of a plurality of small meshes and based on the perspective projection of each of the plurality of small meshes. The apparatus (e.g., processing unit 120) may also include components for calculating layout information for each of a plurality of small meshes in at least one scene in a small mesh atlas, the layout information for each small mesh in the small mesh atlas being based on a selected size of the small mesh. The apparatus (e.g., processing unit 120) may also include components for coloring each of a plurality of primitives in a small mesh atlas based on the layout information calculated in the small mesh atlas. The apparatus (e.g., processing unit 120) may also include components for identifying the visibility of each of a plurality of small meshes in at least one scene, wherein each of the plurality of small meshes is identified as visible or invisible. The apparatus (e.g., processing unit 120) may also include components for discarding each of a plurality of small grids identified as invisible. The apparatus (e.g., processing unit 120) may also include components for rendering each of a plurality of small grids identified as visible, wherein the small grid map is sampled to determine the color of each of a plurality of primitives in the output image. The apparatus (e.g., processing unit 120) may also include components for sending an output image to a display or panel, the output image including the rendered plurality of small grids identified as visible.

[0096] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the described graphics processing techniques can be used by a GPU, a graphics processing unit, or some other processor capable of performing graphics processing to implement the small-grid colorimetric technique described herein. This can also be achieved at a lower cost compared to other graphics processing techniques. Furthermore, the graphics processing techniques of this invention can improve or accelerate data processing or execution. In addition, the graphics processing techniques of this invention can improve resource or data utilization and / or resource efficiency. Furthermore, various embodiments of this invention can utilize small-grid colorimetric techniques to improve memory bandwidth efficiency and / or increase processing speed at the GPU.

[0097] It should be understood that the specific order or hierarchy of blocks in the disclosed program / flowchart is an example of the method. Based on design preferences, it should be understood that the specific order or hierarchy of blocks in the program / flowchart can be rearranged. Furthermore, some blocks can be combined or omitted. The attached method request presents the elements of each block in a sample order and is not intended to limit us to the specific order or hierarchy presented.

[0098] The foregoing description is provided to enable those skilled in the art to practice the various embodiments described herein. Those skilled in the art will readily understand various modifications to these embodiments, and the general principles defined herein can be applied to other embodiments. Therefore, the claims are not intended to be limited to the embodiments shown herein, but rather to conform to the full scope consistent with the language of the claims, wherein, unless expressly stated otherwise, reference to an element in the singular does not mean "one and only one," but rather "one or more." The word "exemplary" is used herein to mean "serving as an example, illustration, or description." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0099] Unless otherwise expressly stated, the term "some" means one or more, and the term "or" can be interpreted as "and / or," where the context does not specify otherwise. Combinations such as "at least one of A, B, or C," "one or more of A, B, or C," "at least one of A, B, and C," "one or more of A, B, and C," and "A, B, C, or any combination thereof" include any combination of A, B, and / or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as "at least one of A, B, or C," "one or more of A, B, or C," "at least one of A, B, and C," "one or more of A, B, and C," and "A, B, C, or any combination thereof" can be only A, only B, only C, A and B, A and C, B and C, or A and B and C, where any such combination may contain one or more members of A, B, or C. All structural and functional equivalents of the elements described herein, which are known or will be known in the art to which this invention pertains and are applicable throughout the various forms described herein, are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended for public use, whether or not it is expressly described in the claims. Terms such as “module,” “mechanism,” “element,” and “device” may not be substitutes for the term “component.” Therefore, unless the element is explicitly described using the phrase “component for…,” no element in the claims should be construed as a component plus a function.

[0100] In one or more instances, the functionality described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used herein, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any functionality, processing unit, technology, or other module described herein is implemented in software, then the functionality, processing unit, technology, or other module described herein may be stored on or transmitted via a computer-readable medium as one or more instructions or codes.

[0101] According to this case, the term "or" can be interpreted as "and / or" unless otherwise specified in the context. Furthermore, although phrases such as "one or more" or "at least one" may be used for some features disclosed herein but not for others, features not using such language may be interpreted as having this implied meaning unless otherwise specified in the context.

[0102] In one or more instances, the functionality described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used herein, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any functionality, processing unit, technology, or other module described herein is implemented in software, then the functionality, processing unit, technology, or other module described herein may be stored on or transmitted via a computer-readable medium as one or more instructions or codes. A computer-readable medium may include computer data storage media or communication media, including any medium that facilitates the transfer of computer programs from one place to another. Thus, a computer-readable medium may generally correspond to (1) a tangible computer-readable storage medium that is non-transitory, or (2) a communication medium, such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementing the technology described herein. For example, but not limited to, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, magnetic storage devices or other magnetic storage devices. As used herein, magnetic disks and optical discs include compact magnetic disks (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, wherein magnetic disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media. Computer program products may include computer-readable media.

[0103] The code can be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field-programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, as used herein, the term "processor" can refer to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. Furthermore, these techniques can be implemented entirely within one or more circuit or logic elements.

[0104] The technology described herein can be implemented in various devices or apparatuses, including wireless mobile phones, integrated circuits (ICs), or a set of ICs (e.g., chipsets). Various components, modules, or units are described herein to emphasize the functional characteristics of devices configured to perform the disclosed technology, but they do not necessarily need to be implemented by different hardware units. Rather, as mentioned above, various units can be combined in any hardware unit, or provided by a collection of interactively operating hardware units, including one or more processors as described above, along with suitable software and / or firmware. Therefore, as used herein, the term "processor" can represent any of the foregoing structures or any other structure suitable for implementing the technology described herein. Furthermore, such technologies can be implemented entirely within one or more circuit or logic elements.

[0105] The following examples are illustrative only and may be combined with, but not limited to, other examples or teachings described herein.

[0106] State Sample 1 is an apparatus for graphics processing, the apparatus including at least one processor coupled to memory and based at least in part on first information stored in the memory, the at least one processor being configured to: divide at least one scene into a plurality of small meshes, each of the plurality of small meshes comprising a plurality of primitives, and each of the plurality of primitives comprising a plurality of vertices; calculate texture coordinate pairs for each of the plurality of vertices of each of the plurality of primitives in each of the plurality of small meshes; and based on first information stored in the memory, the at least one processor is configured to: divide at least one scene into a plurality of small meshes, each of the plurality of small meshes comprising a plurality of primitives, and each of the plurality of primitives comprising a plurality of vertices; calculate texture coordinate pairs for each of the plurality of vertices of each of the plurality of small meshes; and based on first information stored in the memory, the processor is configured to: divide at least one scene into a plurality of small meshes, each of the plurality of small meshes comprising a plurality of primitives, and each of the plurality of primitives comprising a plurality of vertices; and divide at least one scene into a plurality of small meshes, each of the plurality of small meshes comprising a plurality of primitives, and ... The texture coordinates of each vertex of each of the plurality of primitives in the small mesh are determined, and the size of each of the plurality of small meshes in the at least one scene is selected based on the perspective projection of each of the plurality of small meshes; layout information for each of the plurality of small meshes in the at least one scene is calculated in the small mesh atlas, the layout information for each small mesh in the small mesh atlas being based on the selected size of the small mesh; and each of the plurality of primitives in the small mesh atlas is colored based on the layout information calculated in the small mesh atlas.

[0107] State 2 is a device of State 1, wherein the at least one processor is also configured to: identify the visibility of each of the plurality of small grids in the at least one scene, wherein each of the plurality of small grids is identified as visible or invisible.

[0108] State 3 is a device of State 2, wherein the at least one processor is also configured to discard each of the plurality of small grids that are identified as invisible.

[0109] State 4 is a device of state 2, wherein each of the plurality of small grids identified as visible corresponds to at least one of the plurality of colored primitives in the small grid map.

[0110] State 5 is the device of any one of states 1 to 4, wherein the perspective projection of each of the plurality of small grids is the projection of each small grid onto an image plane corresponding to the current viewpoint of the at least one scene.

[0111] State 6 is the device of any one of states 1 to 5, wherein the size of each of the plurality of small grids is based on the maximum value of the angle between the center of each of the plurality of small grids and each of the plurality of vertices of the small grid, wherein the angle corresponds to the current viewpoint of the at least one scene.

[0112] State 7 is the apparatus of any one of states 1 to 6, wherein, in order to calculate the layout information in the small mesh atlas, the at least one processor is configured to: allocate space for each of the plurality of small meshes in the at least one scene in the small mesh atlas, wherein the space allocated for each of the plurality of small meshes in the shading atlas is based on the selected size of the small mesh.

[0113] State 8 is the apparatus of any one of states 1 to 7, wherein, in order to color each of the plurality of elements in the small grid pattern, the at least one processor is configured to: calculate the surface color of each of the plurality of elements in the small grid pattern.

[0114] State 9 is the apparatus of any one of states 1 to 8, wherein, in order to color each of the plurality of primitives in the small mesh map, the at least one processor is configured to: calculate at least one of the following: transparency information of each of the plurality of primitives in the small mesh map, object identification code of each of the plurality of primitives in the small mesh map, one or more surface normals of each of the plurality of primitives in the small mesh map, or world space position of each of the plurality of primitives in the small mesh map.

[0115] State 10 is an apparatus according to any one of states 1 to 9, wherein the at least one processor is also configured to: render each of the plurality of small grids identified as visible, wherein the small grid map is sampled to determine the color of each of the plurality of primitives in the output image.

[0116] State 11 is a device of State 10, wherein the at least one processor is also configured to send the output image to a display or panel, the output image comprising a plurality of rendered small grids that are identified as visible.

[0117] State 12 is the device of any one of states 1 to 11, wherein each of the plurality of elements in each of the plurality of small grids is adjacent to at least one other element among the plurality of elements, within a threshold distance of the at least one other element, or spatially coherent with the at least one other element.

[0118] State 13 is the apparatus of any one of states 1 to 12, wherein the texture coordinate pair for each vertex of each of the plurality of small grids is pre-calculated based on the least-distortion arrangement of the small grid.

[0119] State 14 is the apparatus of any one of states 1 to 13, wherein the texture coordinate pair for each vertex of the plurality of vertices in each of the plurality of small grids is dynamically calculated based on the perspective projection of the small grid.

[0120] State 15 is the apparatus of any one of states 1 to 14, wherein the texture coordinate pair for each of the plurality of vertices in each of the plurality of small meshes is computed in a mesh shader, a vertex shader or a compute shader.

[0121] State 16 is the device of any one of states 1 to 15, wherein the small grid pattern corresponds to the object space coloring representation.

[0122] State 17 is the device of any one of states 1 to 16, wherein the small grid pattern is associated with a graphics application, which includes at least one of the following: a data streaming application, a global illumination application, a time accumulation application, a cache memory application, or an anti-aliasing application.

[0123] State 18 is the device of any one of states 1 to 17, wherein the device is a wireless communication device and also includes at least one of an antenna or a transceiver coupled to the at least one processor, wherein the at least one processor is configured to receive an indication of the scene via the antenna or the at least one of the transceivers.

[0124] State 19 is a graphic processing method for implementing any one of states 1 to 17.

[0125] State 20 is a device for graphics processing, which includes components for implementing any one of states 1 to 18.

[0126] State 21 is a computer-readable medium (e.g., a non-transitory computer-readable medium) that stores computer-executable code, which, when executed by a processor, causes the at least one processor to implement any one of states 1 to 17.

[0127] 100: Content Generation System 104: Equipment 107: Graphics Processing Pipeline 120: Processing Unit 121: Internal Memory 122: Content Encoder / Decoder 123: Internal Memory 124: System Memory 126: Communication Interface 127: Display Processor 128: Receiver 130: Transmitter 131: Monitor 132: Transceiver 198: Small mesh component 200: GPU 210: Command Processor (CP) 212: Drawing the call packet 220:VFD 222:VS 224: Vertex Cache (VPC) 226: Triangle Setting Engine (TSE) 228: Rasterization Program (RAS) 230: Z Processing Engine (ZPE) 232: Primitive Interpolator (PI) 234: Fragment Shader (FS) 236: Render Backend (RB) 238: Level 2 (L2) Cache (UCHE) 240: System Memory 250: Command Buffer 260: Context register packet 261: Context State 400: Figure 402: Shaded 3D Model 420: Picture 422: Small Mesh Visualization Model 440: Figure 442: Small grid 500: Image 502: Screen Space Bounding Box 520: Picture 522: Graph Space Block 600: Figure 610: Small grid 620: Shaded Primitives 700: Figure 702: GPU Component 704: Monitor or panel 706: GPU Components 710: Square 712: Square 720: Square 730: Square 740: Square 750: Square 760: Square 770: Square 780: Square 790: Square 792: Square 800: Flowchart 802: Square 808: Square 810: Square 812: Square 814: Square 900: Flowchart 902: Square 904: Square 906: Square 908: Square 910: Square 912: Square 914: Square 916: Square 918: Square

[0128] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An apparatus for graphics processing, comprising: One memory; and at least one processor coupled to the memory, and based at least in part on first information stored in the memory, the at least one processor is configured to: divide at least one scene into a plurality of small meshes, each of the plurality of small meshes comprising a plurality of primitives, and each of the plurality of primitives comprising a plurality of vertices; identify a visibility of each of the plurality of small meshes in the at least one scene, wherein each of the plurality of small meshes is identified as visible or invisible, wherein each of the plurality of small meshes identified as visible corresponds to at least one pixel among a plurality of pixels in a small mesh atlas; calculate a texture coordinate pair for each of the plurality of vertices of each of the plurality of primitives in each of the plurality of small meshes; Based on the texture coordinate pairs of the vertices of the plurality of primitives in each of the plurality of small meshes and based on a perspective projection of the plurality of small meshes, a size of each of the plurality of small meshes in the at least one scene is selected; layout information of the plurality of small meshes in the small mesh atlas for each of the plurality of small meshes in the at least one scene is calculated, the layout information of the small mesh atlas for each small mesh is based on the selected size of the small mesh; and each of the plurality of pixels in the small mesh atlas is colored based on the layout information calculated in the small mesh atlas.

2. The apparatus according to claim 1, wherein the at least one processor is also configured to: discard each of the plurality of small grids that are identified as invisible.

3. The apparatus according to claim 1, wherein the perspective projection of each of the plurality of small grids is a projection of each small grid onto an image plane corresponding to a current viewpoint of the at least one scene.

4. The apparatus according to claim 1, wherein the size of each of the plurality of small grids is based on a maximum value of an angle between a center of each of the plurality of small grids and a vertex of each of the plurality of vertices of the small grid, wherein the angle corresponds to a current viewpoint of the at least one scene.

5. The apparatus according to claim 1, wherein, in order to calculate the layout information in the small mesh atlas, the at least one processor is configured to: allocate space for each of the plurality of small meshes in the at least one scene in the small mesh atlas, wherein the space allocated for each of the plurality of small meshes in a shading atlas is based on the selected size of the small mesh.

6. The apparatus according to claim 1, wherein, in order to color each of the plurality of pixels in the small mesh pattern, the at least one processor is configured to: calculate a surface color of each of the plurality of pixels in the small mesh pattern.

7. The apparatus according to claim 1, wherein, in order to color each of the plurality of pixels in the small mesh map, the at least one processor is configured to: calculate at least one of the following: transparency information of each of the plurality of pixels in the small mesh map, an object identifier of each of the plurality of pixels in the small mesh map, one or more surface normals of each of the plurality of pixels in the small mesh map, or a world space position of each of the plurality of pixels in the small mesh map.

8. The apparatus according to claim 1, wherein the at least one processor is also configured to: render each of the plurality of small grids identified as visible, wherein the small grid map is sampled to determine a color of each of the plurality of pixels in an output image.

9. The apparatus according to claim 8, wherein the at least one processor is also configured to: send the output image to a display or a panel, the output image comprising a plurality of rendered small grids that are identified as visible.

10. The apparatus according to claim 1, wherein each of the plurality of elements in each of the plurality of small grids is adjacent to at least one other element among the plurality of elements, within a threshold distance of the at least one other element, or spatially coherent with the at least one other element.

11. The apparatus according to claim 1, wherein the texture coordinate pair for each vertex of each of the plurality of vertices in each of the plurality of small meshes is pre-calculated based on a minimum distortion arrangement of the small meshes.

12. The apparatus according to claim 1, wherein the texture coordinate pair for each vertex of each of the plurality of vertices in each of the plurality of small meshes is dynamically calculated based on the perspective projection of the small mesh.

13. The apparatus of claim 1, wherein, in order to compute the texture coordinate pair for each of the plurality of vertices in each of the plurality of small meshes, the at least one processor is configured to compute the texture coordinate pair for each of the plurality of vertices in each of the plurality of small meshes in a mesh shader, a vertex shader or a compute shader.

14. The apparatus according to claim 1, wherein the small grid map corresponds to an object space coloring representation.

15. The apparatus according to claim 1 also includes at least one of an antenna or a transceiver coupled to the at least one processor, wherein the at least one processor is configured to receive an indication of the scene via the at least one of the antenna or the transceiver, and wherein the small grid pattern is associated with a graphics application, the graphics application including at least one of: a data streaming application, a global illumination application, a time accumulation application, a cache application, or an anti-aliasing application.

16. A graphics processing method comprising the steps of: dividing at least one scene into a plurality of small meshes, each of the plurality of small meshes comprising a plurality of primitives, and each of the plurality of primitives comprising a plurality of vertices; identifying a visibility of each of the plurality of small meshes in the at least one scene, wherein each of the plurality of small meshes is identified as visible or invisible, wherein each of the plurality of small meshes identified as visible corresponds to at least one pixel among a plurality of pixels in a small mesh atlas; and calculating a texture coordinate pair for each of the plurality of vertices of each of the plurality of primitives in each of the plurality of small meshes. Based on the texture coordinate pairs of the vertices of the plurality of primitives in each of the plurality of small meshes and based on a perspective projection of the plurality of small meshes, a size of each of the plurality of small meshes in the at least one scene is selected; layout information of the plurality of small meshes in the small mesh atlas for each of the plurality of small meshes in the at least one scene is calculated, the layout information of the small mesh atlas for each small mesh is based on the selected size of the small mesh; and each of the plurality of pixels in the small mesh atlas is colored based on the layout information calculated in the small mesh atlas.

17. The method according to claim 16 also includes the following steps: discarding each of the plurality of small grids that are identified as invisible.

18. The method of claim 16, wherein the perspective projection of each of the plurality of small grids is a projection of each small grid onto an image plane corresponding to a current viewpoint of the at least one scene.

19. The method of claim 16, wherein the size of each of the plurality of small grids is based on a maximum value of an angle between a center of each of the plurality of small grids and a vertex of each of the plurality of vertices of the small grid, wherein the angle corresponds to a current viewpoint of the at least one scene.

20. The method of claim 16, wherein calculating the layout information in the small mesh atlas includes the steps of: allocating space for each of the plurality of small meshes in the at least one scene in the small mesh atlas, wherein the space allocated for each of the plurality of small meshes in a shading atlas is based on the selected size of the small mesh.

21. The method according to claim 16, wherein coloring each of the plurality of pixels in the small mesh atlas includes: Calculating a surface color for each of the plurality of pixels in the small mesh map, or coloring each of the plurality of pixels in the small mesh map, includes the following steps: Calculate at least one of the following: transparency information of each of the plurality of pixels in the small mesh map, an object identifier of each of the plurality of pixels in the small mesh map, one or more surface normals of each of the plurality of pixels in the small mesh map, or a world space position of each of the plurality of pixels in the small mesh map.

22. The method according to claim 16 also includes the following steps: rendering each of the plurality of small grids identified as visible, wherein the small grid map is sampled to determine a color of each of the plurality of pixels in an output image; and sending the output image to a display or a panel, the output image including the plurality of rendered small grids identified as visible.

23. The method of claim 16, wherein each of the plurality of primitives in each of the plurality of small grids is adjacent to at least one other primitive among the plurality of primitives, within a threshold distance of the at least one other primitive, or spatially coherent with the at least one other primitive, and wherein the texture coordinate pair for each of the plurality of vertices in each of the plurality of small grids is pre-computed based on a minimum distortion arrangement of the small grid.

24. The method of claim 16, wherein the texture coordinate pair for each vertex of each of the plurality of vertices in each of the plurality of small meshes is dynamically calculated based on the perspective projection of the small mesh, wherein the texture coordinate pair for each vertex of each of the plurality of vertices in each of the plurality of small meshes is calculated in a mesh shader, a vertex shader or a compute shader, wherein the small mesh map corresponds to an object space shading representation, and wherein the small mesh map is associated with a graphics application, the graphics application including at least one of: a data streaming application, a global illumination application, a time accumulation application, a cache memory application or an anti-aliasing application.

25. An apparatus for graphics processing, comprising: Means for dividing at least one scene into a plurality of small meshes, each of the plurality of small meshes comprising a plurality of primitives, and each of the plurality of primitives comprising a plurality of vertices; means for identifying the visibility of each of the plurality of small meshes in the at least one scene, wherein each of the plurality of small meshes is identified as visible or invisible, wherein each of the plurality of small meshes identified as visible corresponds to at least one pixel among a plurality of pixels in a small mesh atlas; means for calculating a texture coordinate pair for each of the plurality of vertices of each of the plurality of primitives in each of the plurality of small meshes; Means for selecting a size of each of the plurality of small meshes in the at least one scene based on the texture coordinate pairs of the vertices of the plurality of primitives in each of the plurality of small meshes and based on a perspective projection of each of the plurality of small meshes; means for calculating layout information of each of the plurality of small meshes in the at least one scene in the small mesh atlas, the layout information of each small mesh in the small mesh atlas being based on the selected size of the small mesh; and means for coloring each of the plurality of pixels in the small mesh atlas based on the layout information calculated in the small mesh atlas.

26. A non-transitory computer-readable medium storing computer-executable code for graphics processing, the code, when executed by a processor, causing the processor to: divide at least one scene into a plurality of small meshes, each of the plurality of small meshes comprising a plurality of primitives, and each of the plurality of primitives comprising a plurality of vertices; identify a visibility of each of the plurality of small meshes in the at least one scene, wherein each of the plurality of small meshes is identified as visible or invisible, wherein each of the plurality of small meshes identified as visible corresponds to at least one pixel among a plurality of pixels in a small mesh atlas; and compute a texture coordinate pair for each of the plurality of vertices of each of the plurality of primitives in each of the plurality of small meshes. Based on the texture coordinate pairs of the vertices of the plurality of primitives in each of the plurality of small meshes and based on a perspective projection of the plurality of small meshes, a size of each of the plurality of small meshes in the at least one scene is selected; layout information of the plurality of small meshes in the small mesh atlas for each of the plurality of small meshes in the at least one scene is calculated, the layout information of the small mesh atlas for each small mesh is based on the selected size of the small mesh; and each of the plurality of pixels in the small mesh atlas is colored based on the layout information calculated in the small mesh atlas.

Images