Solid-state camera element

Abstract

This invention improves image quality in solid-state imaging elements where all pixels are exposed simultaneously. A solid-state imaging device includes a front-end circuit, a plurality of capacitors, a selection circuit, and a back-end circuit. In this solid-state imaging device, the front-end circuit converts charge into voltage using a plurality of capacitors with varying conversion efficiencies and outputs it to a front-end node. One end of each of the plurality of capacitors is connected to the front-end node. The selection circuit connects the other end of any one of the plurality of capacitors to the back-end node. The back-end circuit reads the voltage from the back-end node.

Description

[Technical Field]

[0001] This technology relates to a solid-state imaging element. More specifically, it relates to a voltage-domain solid-state imaging element. [Previous Technology]

[0002] In recent years, global shutter CMOS (Complementary Metal-Oxide-Semiconductor) image sensors that convert signal charge into voltage and hold it in the voltage domain have attracted much attention. Hereinafter, this type of sensor will be referred to as "VD.GS". Since VD.GS is susceptible to kTC noise degradation, a configuration is proposed that includes a sample-and-hold circuit with a pair of capacitor elements for each pixel (for example, see Non-Patent Document 1). [Prior Art Documents] [Non-Patent Documents]

[0003] Non-patent literature 1: Geunsook Park, et al., A 2.2 μm stacked back side illuminated voltage domain global shutter CMOS image sensor, IEDM 2019. [Summary of the Invention]

[0004] [The problem the invention aims to solve]

[0005] In the aforementioned prior art, kTC noise is reduced in the VD.GS by maintaining the voltage in the sample-and-hold circuit. However, in the aforementioned solid-state imaging element, it is impossible to switch the conversion efficiency when converting charge to voltage. Therefore, there is a risk of insufficient saturation charge in high-light conditions and insufficient sensitivity in low-light conditions. Due to these insufficient saturation charge or sensitivity, the image quality of the captured image data in the aforementioned VD.GS may be reduced.

[0006] This technology was developed in view of this situation, and its purpose is to improve image quality in solid-state imaging devices where all pixels are exposed simultaneously. [Technical means to solve the problem]

[0007] This technology was developed to solve the aforementioned problems. Its first state is a solid-state imaging element, comprising: a front-end circuit that converts charge into voltage using a plurality of conversion efficiencies and outputs it to a front-end node; a plurality of capacitors, one end of which is commonly connected to the front-end node; a selection circuit that connects the other end of any one of the plurality of capacitors to a back-end node; and a back-end circuit that reads the voltage through the back-end node. This reduces kTC noise.

[0008] Furthermore, in the first state, the plurality of capacitor elements may include high-capacitance elements with capacitance values ​​higher than a specific value and low-capacitance elements with capacitance values ​​lower than the specific value. The high-capacitance elements maintain the voltage generated by the highest high conversion efficiency among the plurality of conversion efficiencies, and the low-capacitance elements maintain the voltage generated by a conversion efficiency lower than the high conversion efficiency among the plurality of conversion efficiencies. This achieves the effect of reducing kTC noise.

[0009] Furthermore, in the first state, the area of ​​the high-capacitance element can be larger than that of the low-capacitance element. This allows the high-capacitance element to achieve a larger capacitance value.

[0010] Furthermore, in the first state, the capacitance density of the high-capacitance element can be higher than that of the low-capacitance element. This achieves the effect of making the area of ​​each capacitance element equal.

[0011] Furthermore, as in the first state, the aforementioned high-capacitance element may comprise a plurality of unit capacitor elements connected in parallel. This achieves the effect of ensuring uniform capacitance density and area among the capacitor elements.

[0012] Furthermore, in the first state, the aforementioned front-end circuit, selection circuit, and back-end circuit may also be configured on the first chip, and the aforementioned plurality of capacitor elements may be configured on the second chip. This facilitates pixel miniaturization.

[0013] Furthermore, in the first state, the distance from the output terminal of the aforementioned front-end circuit to the aforementioned high-capacitance element can be longer than the distance from the aforementioned output terminal to the aforementioned low-capacitance element. This allows for an increase in the wiring capacitance of the wiring to the high-capacitance element.

[0014] Furthermore, in the first state, the first chip may comprise a plurality of stacked substrates. This allows for an increase in the area of ​​the photoelectric conversion element or transistor.

[0015] Furthermore, in the first state, the aforementioned front-end circuit may include: a photoelectric conversion element; a front-end transmission transistor that transmits the charge from the photoelectric conversion element to the floating diffusion layer; a first reset transistor that initializes the floating diffusion layer; a front-end amplification transistor that amplifies the voltage and outputs it to the front-end node; and a specific number of conversion efficiency control transistors that control the conversion efficiency. This allows the conversion efficiency to be switched by turning the conversion efficiency control transistors on and off.

[0016] Furthermore, in the first state, the aforementioned front-end circuit may also include an additional capacitor, the aforementioned conversion efficiency control transistor is inserted between the aforementioned floating diffusion layer and the aforementioned additional capacitor, and the aforementioned additional capacitor is disposed on the aforementioned second wafer. This allows for the expansion of the area of ​​the additional capacitor.

[0017] Furthermore, in the first state, the aforementioned front-end circuit may also include an additional capacitor and a discharge transistor for discharging the charge from the aforementioned photoelectric conversion element. The specific number of conversion efficiency control transistors includes a first and a second conversion efficiency control transistor connected in series between the floating diffusion layer and the additional capacitor. The additional capacitor is disposed on either the first or the second wafer. This achieves the function of suppressing potential fluctuations in the floating diffusion layer.

[0018] Furthermore, as in the first state, it may also include: a switching unit that adjusts the source voltage supplied to the source of the aforementioned front-end amplifying transistor; the aforementioned front-end circuit further includes a current source transistor that supplies current to the drain of the aforementioned front-end amplifying transistor, the aforementioned current source transistor moving from an on state to an off state after the exposure period ends. This enables the front-end source follower to function as an off state during readout.

[0019] Furthermore, in the first state, the switching unit can supply a specific power supply voltage as the source voltage during the exposure period, and supply a generation voltage different from the power supply voltage as the source voltage after the exposure period ends. This allows for the adjustment of the source voltage of the front-end source follower.

[0020] Furthermore, in the first state, it may also include: a control circuit that controls the reset power supply voltage of the aforementioned front-end circuit; the aforementioned first reset transistor initializes the voltage of the floating diffusion layer to the aforementioned reset power supply voltage; and the aforementioned control circuit, during the readout period of reading the aforementioned voltage, sets the aforementioned reset power supply voltage to a voltage different from that during the exposure period. This improves sensitivity uniformity.

[0021] Furthermore, in the first state, it may also include: a digital signal processing unit that adds a pair of consecutive frames; the plurality of capacitor elements including a first and a second capacitor element; the voltage including a reset level and a signal level; the front-end circuit maintaining the reset level at one of the first and second capacitor elements during the exposure period of one of the pair of frames, and subsequently maintaining the signal level at the other of the first and second capacitor elements; and maintaining the reset level at the other of the first and second capacitor elements during the exposure period of the other pair of frames, and subsequently maintaining the signal level at one of the first and second capacitor elements. This improves sensitivity uniformity.

[0022] Furthermore, as in the first state, it may also include: an analog-to-digital converter that converts the aforementioned output voltage into a digital signal. This enables the generation of digital image data.

[0023] Furthermore, in the first state, the analog-to-digital converter may include: a comparator that compares the level of the vertical signal line transmitting the voltage with a specific ramp signal and outputs the comparison result; and a counter that counts the count value during the traversal until the comparison result reverses, and outputs the digital signal representing the count value. In this way, analog-to-digital conversion is achieved with a simple configuration.

[0024] Furthermore, in the first state, the comparator may include: a comparator that compares the levels of each of a pair of input terminals and outputs a comparison result; and an input-side selector that selects either the node of the vertical signal line and a specific reference voltage to be connected to one of the pair of input terminals; and inputs the ramp signal to one of the pair of input terminals. This suppresses the black spot phenomenon.

[0025] Furthermore, the first state may also include: a control unit that determines whether the illuminance is higher than a specific value based on the comparison result and outputs the determination result; a CDS (Correlated Double Sampling) processing unit that performs correlated double sampling processing on the digital signal; and an output selector that outputs either the digital signal after performing the correlated double sampling processing or the digital signal of the specific value, based on the determination result. This achieves the effect of suppressing black spot phenomena.

[0026] Furthermore, in the first state, it may also include: a vertical scanning circuit that controls the conversion efficiency of the aforementioned front-end circuit; the same capacitance value for each of the aforementioned plurality of capacitor elements; and the voltage including a reset level and a signal level corresponding to the exposure amount. This achieves the function of maintaining the level at the plurality of capacitor elements.

[0027] Furthermore, in the first state, the vertical scanning circuit can set any of the plurality of conversion efficiencies, such that the reset level is maintained at half of the plurality of capacitor elements, and the signal level is maintained at the remaining half of the plurality of capacitor elements. This reduces noise when the conversion efficiency is fixed.

[0028] Furthermore, in the first state, the plurality of capacitor elements may also include a plurality of first capacitor elements, a plurality of second capacitor elements, and a plurality of third capacitor elements. The vertical scanning circuit sets any of the plurality of conversion efficiencies, so that the reset level is maintained at half of the plurality of first capacitor elements, and the signal level is maintained at the plurality of second capacitor elements. This reduces noise when the conversion efficiency is fixed.

[0029] Furthermore, in the first state, the plurality of capacitor elements may also include a plurality of first capacitor elements, a plurality of second capacitor elements, a plurality of third capacitor elements, and a plurality of fourth capacitor elements. The vertical scanning circuit sequentially sets two of the plurality of conversion efficiencies, such that the reset level generated by the higher of the two conversion efficiencies is maintained on the plurality of first capacitor elements, the signal level generated by the higher of the two conversion efficiencies is maintained on the plurality of second capacitor elements, the reset level generated by the lower of the two conversion efficiencies is maintained on the plurality of third capacitor elements, and the signal level generated by the lower of the two conversion efficiencies is maintained on the plurality of fourth capacitor elements. This reduces noise when switching conversion efficiencies.

[0030] Furthermore, in the first state, the plurality of capacitor elements may also include a plurality of first capacitor elements, a plurality of second capacitor elements, a specific number of third capacitor elements less than the first capacitor elements, and a specific number of fourth capacitor elements. The vertical scanning circuit sequentially sets two of the plurality of conversion efficiencies, such that the reset level generated by the higher of the two conversion efficiencies is maintained on the plurality of first capacitor elements, the signal level generated by the higher of the two conversion efficiencies is maintained on the plurality of second capacitor elements, the reset level generated by the lower of the two conversion efficiencies is maintained on the specific number of third capacitor elements, and the signal level generated by the lower of the two conversion efficiencies is maintained on the specific number of fourth capacitor elements. This reduces noise when switching conversion efficiencies.

[0031] Furthermore, in the first state, the voltage may also include: a first reset level generated moment before the end of the first exposure period, a first signal level generated at the end of the first exposure period, a second reset level generated moment before the end of the second exposure period, and a second signal level generated at the end of the second exposure period; the plurality of capacitor elements includes a first capacitor element holding the first reset level, a second capacitor element holding the first signal level, a third capacitor element holding the second reset level, and a fourth capacitor element holding the second signal level; the second exposure period begins immediately after the end of the first exposure period, and the downstream circuit reads out the voltage while avoiding the sampling and holding period of the voltage. This improves the continuous shooting function.

[0032] Furthermore, as in the first state, the voltage may also include a third reset level generated just before the end of the third exposure period and a third signal level generated at the end of the third exposure period; the plurality of capacitor elements further includes a fifth capacitor element holding the third reset level and a sixth capacitor element holding the third signal level; the third exposure period begins immediately after the end of the second exposure period. This achieves the function of capturing three frames.

[0033] Furthermore, in the first state, the voltage may also include: a first reset level generated moment before the end of the first exposure period, a first signal level generated at the end of the first exposure period, and a second signal level generated at the end of the second exposure period; the plurality of capacitor elements includes a first capacitor element holding the first reset level, a second capacitor element holding the first signal level, and a third capacitor element holding the second signal level; the second exposure period begins immediately after the end of the first exposure period, and the downstream circuit reads out the voltage while avoiding the sampling and holding period of the voltage. This allows for an increase in the number of continuous shots.

[0034] Furthermore, the second state of this technology is a solid-state imaging element, comprising: a photoelectric conversion element; a first additional capacitor; a second additional capacitor, the capacitance of which is different from that of the first additional capacitor; a transmission transistor that transmits charge from the photoelectric conversion element to the floating diffusion layer; a first conversion efficiency control transistor that opens and closes the path between the floating diffusion layer and the first additional capacitor; and a second conversion efficiency control transistor that opens and closes the path between the connection node of the first conversion efficiency control transistor and the first additional capacitor and the second additional capacitor. This achieves the effect of increasing the difference in the combined capacitance before and after switching the conversion efficiency.

Implementation Method

[0036] Hereinafter, the form in which this technology is implemented (hereinafter referred to as the embodiment) will be described. The description will proceed in the following order. 1. First embodiment (example of maintaining pixel signals by the first and second capacitor elements) 2. Second embodiment (example of maintaining pixel signals by adding an additional discharge transistor) 3. Third embodiment (example of maintaining pixel signals by the first and second capacitor elements and controlling the reset power supply voltage) 4. Fourth embodiment (example of maintaining pixel signals by the first and second capacitor elements and changing the level maintained for each frame) 5. Fifth embodiment (example of maintaining pixel signals by the first and second capacitor elements and suppressing black spot phenomenon) 6. Sixth embodiment (example of maintaining pixel signals by the first and second capacitor elements and performing rolling shutter action) 7. Seventh embodiment (example of maintaining pixel signals by the first and second capacitor elements and setting the front-end source slave to the off state during readout) 8. Eighth embodiment (example of maintaining voltage by multiple capacitor elements with different capacitance values) 9. Ninth Embodiment (Example of maintaining voltage for a plurality of capacitor elements with different capacitance densities) 10. Tenth Embodiment (Example of optimizing the layout of a plurality of capacitor elements with different capacitance values) 11. Eleventh Embodiment (Example of maintaining voltage for a plurality of capacitor elements with different capacitance values ​​by setting the pixel chip in a multilayer structure) 12. Twelfth Embodiment (Example of providing a plurality of additional capacitors with different capacitance values) 13. Thirteenth Embodiment (Example of maintaining voltage for a plurality of capacitor elements with different capacitance values ​​by providing additional capacitors) 14. Fourteenth Embodiment (Example of maintaining voltage for a plurality of capacitor elements with different capacitance values ​​by providing additional capacitors and discharging transistors) 15. Application Example to a Moving Body

[0037] <1. First Embodiment> [Structure Example of Camera Device] FIG1 is a block diagram showing a configuration example of a camera device 100 according to the first embodiment of the present technology. The camera device 100 is a device for capturing image data and includes a camera lens 110, a solid-state imaging element 200, a recording unit 120, and a camera control unit 130. As the camera device 100, a digital camera or an electronic device with camera function (such as a smartphone or personal computer) is envisioned.

[0038] The solid-state imaging element 200 is used to capture image data under the control of the imaging control unit 130. The solid-state imaging element 200 supplies image data to the recording unit 120 via the signal line 209.

[0039] The camera lens 110 focuses and guides light to the solid-state imaging element 200. The camera control unit 130 controls the solid-state imaging element 200 to capture image data. For example, the camera control unit 130 supplies a camera control signal including the vertical synchronization signal VSYNC to the solid-state imaging element 200 via the signal line 139. The recording unit 120 records image data.

[0040] Here, the vertical synchronization signal VSYNC is a signal that displays the camera timing. A periodic signal of a specific frequency (60 Hz, etc.) can be used as the vertical synchronization signal VSYNC.

[0041] Alternatively, the camera device 100 records image data, but it can also transmit the image data to an external location. In this case, an external interface for transmitting the image data is provided. Alternatively, the camera device 100 can also display the image data. In this case, a display unit is provided.

[0042] [Solid-State Imaging Element Configuration Example] FIG2 is a block diagram showing a configuration example of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a vertical scanning circuit 211, a pixel array section 220, a timing control circuit 212, a DAC (Digital to Analog Converter) 213, a load MOS (Metal-Oxide-Semiconductor) circuit block 250, and a horizontal signal processing circuit 260. In the pixel array section 220, a plurality of pixels 300 are arranged in a two-dimensional grid pattern. Furthermore, each circuit within the solid-state imaging element 200 is, for example, disposed on a single semiconductor wafer.

[0043] Hereinafter, the set of pixels 300 arranged in the horizontal direction will be called a "column", and the set of pixels 300 arranged in the direction perpendicular to the column will be called a "row".

[0044] The timing control circuit 212 synchronizes with the vertical synchronization signal VSYNC from the camera control unit 130 to control the operation timing of the vertical scanning circuit 211, DAC 213, and horizontal signal processing circuit 260.

[0045] The DAC213 generates a sawtooth-shaped ramp signal through DA (Digital to Analog) conversion. The DAC213 supplies the generated ramp signal to the horizontal signal processing circuit 260.

[0046] The vertical scanning circuit 211 sequentially selects and drives columns to output analog pixel signals. The pixel 300 generates analog pixel signals by photoelectric conversion of incident light. The pixel 300 supplies pixel signals to the row signal processing circuit 260 via the load MOS circuit block 250.

[0047] In the load MOS circuit block 250, a MOS transistor supplying a constant current is provided for each row.

[0048] The line signal processing circuit 260 performs signal processing such as AD conversion or CDS (Correlated Double Sampling) processing on the pixel signal for each line. The line signal processing circuit 260 supplies image data containing the processed signal to the recording unit 120.

[0049] [Pixel Configuration Example] FIG3 is a circuit diagram showing a configuration example of a pixel 300 according to a first embodiment of the present technology. The pixel 300 includes a front-end circuit 310, capacitor elements 321 and 322, a selection circuit 330, a rear-end reset transistor 341, and a rear-end circuit 350.

[0050] The front-end circuit 310 includes a photoelectric conversion element 311, a transmission transistor 312, an FD (Floating Diffusion) reset transistor 313, an FD 314, a front-end amplification transistor 315, and a current source transistor 316.

[0051] The photoelectric conversion element 311 generates charge through photoelectric conversion. The transmitting transistor 312 transmits charge from the photoelectric conversion element 311 to the FD314 based on the transmission signal trg from the vertical scanning circuit 211.

[0052] The FD reset transistor 313 initializes the FD 314 by extracting charge from it based on the FD reset signal rst from the vertical scanning circuit 211. The FD 314 accumulates charge and generates a voltage corresponding to the amount of charge. The front-end amplification transistor 315 amplifies the voltage level of the FD 314 and outputs it to the front-end node 320. Furthermore, the FD reset transistor 313 is an example of the first reset transistor described in the claims.

[0053] Furthermore, the sources of the FD reset transistor 313 and the preamplifier transistor 315 are connected to the power supply voltage VDD. The current source transistor 316 is connected to the drain of the preamplifier transistor 315. The current source transistor 316 supplies current id1 according to the control of the vertical scanning circuit 211.

[0054] One end of each of capacitor elements 321 and 322 is connected to the front node 320, and the other end of each is connected to the selection circuit 330.

[0055] The selection circuit 330 includes a selection transistor 331 and a selection transistor 332. The selection transistor 331 opens or closes the path between the capacitor element 321 and the downstream node 340 based on the selection signal Φr from the vertical scanning circuit 211. The selection transistor 332 opens or closes the path between the capacitor element 322 and the downstream node 340 based on the selection signal Φs from the vertical scanning circuit 211.

[0056] The downstream reset transistor 341 initializes the level of the downstream node 340 to a specific potential Vreg based on the downstream reset signal rstb from the vertical scan circuit 211. For the potential Vreg, a potential different from the power supply potential VDD is set (e.g., a potential lower than VDD).

[0057] The back-end circuit 350 includes a back-end amplifying transistor 351 and a back-end selection transistor 352. The back-end amplifying transistor 351 amplifies the level of the back-end node 340. The back-end selection transistor 352 outputs the level signal amplified by the back-end amplifying transistor 351 as a pixel signal to the vertical signal line 309 based on the back-end selection signal selb from the vertical scanning circuit 211.

[0058] Additionally, as for various transistors (transmission transistor 312, etc.) within the pixel 300, for example, an nMOS (n-channel metal oxide semiconductor) transistor is used.

[0059] At the start of exposure, the vertical scanning circuit 211 supplies a high-level FD reset signal rst and a transmission signal trg to all pixels. This initializes the photoelectric conversion element 311. Hereinafter, this control will be referred to as "PD reset".

[0060] Furthermore, just before the end of exposure, the vertical scanning circuit 211 sets the post-reset signal rstb and the selection signal Φr to a high level for all pixels, and supplies the high-level FD reset signal rst during the traversal pulse. This initializes FD314, and holds the level corresponding to the current level of FD314 in capacitor element 321. Hereinafter, this control will be referred to as "FD reset".

[0061] Hereinafter, the level of FD314 during FD reset and the level corresponding to that level (the holding level of capacitor element 321 or the level of vertical signal line 309) are collectively referred to as "P phase" or "reset level".

[0062] At the end of exposure, the vertical scanning circuit 211 sets the post-reset signal rstb and the selection signal Φs to a high level for all pixels, and supplies a high-level transmission signal trg during the traversal pulse. This transmits the signal charge corresponding to the exposure amount to FD314, and holds the level corresponding to the current level of FD314 in capacitor element 322.

[0063] Hereinafter, the level of FD314 during signal charge transmission and the level corresponding to that level (the holding level of capacitor element 322 or the level of vertical signal line 309) are collectively referred to as "D phase" or "signal level".

[0064] This type of exposure control, in which all pixels start and end exposure simultaneously, is called global shutter mode. Through this exposure control, the front-end circuits 310 of all pixels sequentially generate reset level and signal level. The reset level is held in capacitor element 321, and the signal level is held in capacitor element 322.

[0065] After exposure, the vertical scanning circuit 211 sequentially selects columns and sequentially outputs the reset level and signal level of that column. When outputting the reset level, the vertical scanning circuit 211 sets the FD reset signal rst and the subsequent selection signal selb of the selected column to a high level, and supplies the high level selection signal Φr during a specific period. Herein, the capacitor element 321 is connected to the subsequent node 340 to read the reset level.

[0066] After reading the reset level, the vertical scan circuit 211 maintains the FD reset signal rst and the subsequent selection signal selb of the selected column at the high level, and supplies the subsequent reset signal rstb of the high level during the traversal pulse. This initializes the level of the subsequent node 340. At this time, both selection transistors 331 and 332 are in the on state, and capacitors 321 and 322 are disconnected from the subsequent node 340.

[0067] After initialization at the downstream node 340, the vertical scanning circuit 211 maintains the FD reset signal rst and the downstream selection signal selb of the selected column at a high level, and supplies the high-level selection signal Φs during a specific period. Herein, the capacitor element 322 is connected to the downstream node 340 to read the signal level.

[0068] Through the above-described readout control, the selection circuit 330 of the selected column sequentially performs control to connect capacitor element 321 to the downstream node 340, control to disconnect capacitor elements 321 and 322 from the downstream node 340, and control to connect capacitor element 322 to the downstream node 340. Furthermore, when disconnecting capacitor elements 321 and 322 from the downstream node 340, the downstream reset transistor 341 of the selected column initializes the level of the downstream node 340. Furthermore, the downstream circuit 350 of the selected column reads the reset level and signal level sequentially from capacitor elements 321 and 322 via the downstream node 340 and outputs them to the vertical signal line 309.

[0069] [Example of the configuration of the horizontal signal processing circuit] Figure 4 is a block diagram showing an example of the configuration of the load MOS circuit block 250 and the horizontal signal processing circuit 260 in the first embodiment of the present technology.

[0070] In the load MOS circuit block 250, vertical signal lines 309 are wired in each row. If the number of rows is set to I (I is an integer), then there are I vertical signal lines 309. Furthermore, each vertical signal line 309 is connected to a load MOS transistor 251 that supplies a specific current id2.

[0071] In the line signal processing circuit 260, a plurality of ADCs 261 and a digital signal processing unit 262 are configured. ADCs 261 are configured for each line. If the number of lines is set to I, then I ADCs 261 are configured.

[0072] ADC261 is a device that uses the ramp signal Rmp from DAC213 to convert the analog pixel signal from the corresponding row into a digital signal. ADC261 supplies the digital signal to digital signal processing unit 262. For example, ADC261 may be a single-ramp type ADC equipped with a comparator and a counter.

[0073] The digital signal processing unit 262 is a specific signal processor that performs CDS processing and other operations on each digital signal in each row. The digital signal processing unit 262 supplies image data containing the processed digital signals to the recording unit 120.

[0074] [Example of Solid State Imaging Element Operation] Figure 5 is a timing diagram showing an example of global shutter operation in the first embodiment of this technology. Starting from timing T0 one moment before exposure begins, the vertical scanning circuit 211 traverses through the pulse period and then to timing T1, supplying a high-level FD reset signal rst and a transmission signal trg to all columns (in other words, all pixels). This performs PD reset on all pixels, and all columns begin exposure simultaneously.

[0075] Here, rst_[n] and trg_[n] in the figure represent the signal for the nth pixel in the N columns. N is an integer representing the number of all columns, and n is an integer from 1 to N.

[0076] Furthermore, at timing T2, just before the end of the exposure period, the vertical scan circuit 211 sets the rear reset signal rstb and the selection signal Φr to a high level for all pixels, and supplies the high-level FD reset signal rst during the traversal pulse. In this way, FD reset is performed on all pixels, and the reset level is sampled and maintained. Here, rstb_[n] and Φr_[n] in this figure show the signal for the nth column pixel.

[0077] At timing T3 after timing T2, the vertical scanning circuit 211 restores the selection signal Φr to a low level.

[0078] At the end of exposure, time T4, the vertical scan circuit 211 sets the rear reset signal rstb and selection signal Φs to a high level in all pixels, and supplies a high-level transmission signal trg during the traversal pulse. This maintains the sampled signal level. Furthermore, the level of the front node 320 is reduced from the self-reset level (VDD-Vsig) to the signal level (VDD-Vgs-Vsig). Here, VDD is the power supply voltage, and Vsig is the actual signal level obtained through CDS processing. Vgs is the gate-source voltage of the front amplification transistor 315. Also, Φs_[n] in this diagram represents the signal for the nth column pixel.

[0079] At timing T5 after timing T4, the vertical scanning circuit 211 restores the selection signal Φs to the low level.

[0080] Furthermore, the vertical scanning circuit 211 controls the current source transistors 316 of all columns (all pixels) to supply current id1. Here, id1_[n] in this diagram represents the current of the nth column pixel. Since the IR bit drop increases when the current id is a large current, the current id1 needs to be set to the level of several nanoamps (nA) to tens of nanoamps (nA). On the other hand, the load MOS transistors 251 of all rows are in the off state, and no current id2 is supplied to the vertical signal line 309.

[0081] Figure 6 is a timing diagram showing an example of the readout operation of the first embodiment of the present technology. During the readout of the nth column from timing T10 to timing T17, the vertical scan circuit 211 sets the FD reset signal rst and the subsequent segment selection signal selb of the nth column to a high level. Furthermore, during the readout period, the subsequent segment reset signals rstb of all columns are controlled to a low level. Here, selb_[n] in this figure represents the signal for the nth column pixel.

[0082] During the period from timing T11 to timing T13 immediately following timing T10, the vertical scanning circuit 211 supplies a high-level selection signal Φr to the nth column. The potential of the subsequent node 340 is the reset level Vrst.

[0083] During the period from timing T12 to timing T13 after traversing timing T11, DAC213 gradually increases the ramp signal Rmp. ADC261 compares the ramp signal Rmp with the level Vrst' of the vertical signal line 309, counting the value until the comparison result is reversed. In this way, the P phase level (reset level) is read out.

[0084] During the traversal pulse of timing T14 immediately following timing T13, the vertical scanning circuit 211 supplies a high-level post-stage reset signal rstb to the nth column. This allows the deletion of the signal process held above the parasitic capacitance when a parasitic capacitance exists in the post-stage node 340.

[0085] During the period from timing T15 to timing T17 immediately following the initialization of the subsequent node 340, the vertical scan circuit 211 supplies a high-level selection signal Φs to the nth column. The potential of the subsequent node 340 is the signal level Vsig. During exposure, the signal level is lower than the reset level, but during readout, since the subsequent node 340 is used as the reference, the signal level is higher than the reset level. The difference between the reset level Vrst and the signal level Vsig is equivalent to the actual signal level after removing the reset noise or offset noise of the FD.

[0086] During the period from timing T16 to timing T17 after traversing timing T15, DAC213 gradually increases the ramp signal Rmp. ADC261 compares the ramp signal Rmp with the level Vrst' of the vertical signal line 309, counting the value until the comparison result is reversed. This allows the D phase level (signal level) to be read.

[0087] Furthermore, during the period when the vertical scanning circuit 211 traverses the timing sequence T10 to T17, it controls the current source transistor 316 of the nth column of the readout object to supply current id1. Furthermore, during the readout period of all columns, the timing control circuit 212 controls the load MOS transistors 251 of all rows to supply current id2.

[0088] Alternatively, the solid-state imaging element 200 reads out the signal level after resetting the level, but this order is not limited. As illustrated in FIG7, the solid-state imaging element 200 may also read out the reset level after the signal level. In this case, as illustrated in the figure, the vertical scanning circuit 211 supplies the high-level selection signal Φr after the high-level selection signal Φs. Furthermore, in this case, the slope of the ramp signal needs to be reversed.

[0089] Figure 8 is a circuit diagram showing one of the pixel configuration examples of the comparative example. In this comparative example, the selection circuit 330 is not provided, and a transmission transistor is inserted between the front-end node 320 and the front-end circuit. Furthermore, capacitors C1 and C2 are inserted instead of capacitor elements 321 and 322. Capacitor C1 is inserted between the front-end node 320 and the ground terminal, and capacitor C2 is inserted between the front-end node 320 and the rear-end node 340.

[0090] The pixel exposure control and readout control of this comparative example are described, for example, in Figure 5.5.2 of Non-Patent Document 1. In this comparative example, if the capacitance values ​​of capacitors C1 and C2 are assumed to be C, the level Vn of the kTC noise during exposure and readout is expressed by the following formula. In the above formula, k is the Boltzmann constant, and the unit is, for example, joules per Kelvin (J / K). T is the absolute temperature, and the unit is, for example, Kelvin (K). Also, the unit of Vn is, for example, volts (V), and the unit of C is, for example, farads (F).

[0091] Figure 9 is a diagram showing an example of the state of each pixel during readout reset timing and initialization of the downstream node in the first embodiment of the present technology. Figure a shows the state of pixel 300 during readout reset timing, and Figure b shows the state of pixel 300 during initialization of the downstream node 340. Furthermore, in this figure, for ease of explanation, switch symbols are used to represent select transistor 331, select transistor 332, and downstream reset transistor 341.

[0092] As illustrated in Figure a, the vertical scanning circuit 211 sets the selection transistor 331 to the off state and sets the selection transistor 332 and the downstream reset transistor 341 to the on state. In this way, the reset level is read out via the downstream circuit 350.

[0093] After reading the reset level, as illustrated in Figure b, the vertical scanning circuit 211 sets the select transistors 331 and 332 to the on state and the downstream reset transistor 341 to the off state. This disconnects capacitors 321 and 322 from the downstream node 340 and initializes the level of the downstream node 340.

[0094] Thus, the parasitic capacitance Cp of the segment node 340 after being disconnected from capacitor elements 321 and 322 is very small compared to capacitor elements 321 and 322. For example, if the parasitic capacitance Cp is set to a few nanofarads (fF), then capacitor elements 321 and 322 are in the tens of nanofarads range.

[0095] Figure 10 is a diagram showing an example of the state of the pixel 300 with the readout signal bit in the first embodiment of the present technology.

[0096] After initialization of the downstream node 340, the vertical scanning circuit 211 sets the selection transistor 332 to the off state and sets the selection transistor 331 and the downstream reset transistor 341 to the on state. In this way, the signal level is read out via the downstream circuit 350.

[0097] Here, consider the kTC noise during the exposure of pixel 300. During exposure, the sampling of the reset level and the sampling of the signal level at the moment before the end of the exposure generate kTC noise. If the capacitance values ​​of capacitors 321 and 322 are assumed to be C, the level Vn of the kTC noise during exposure is expressed by the following formula.

[0098] Furthermore, as illustrated in Figures 9 and 10, kTC noise is generated during readout because the downstream reset transistor 341 is driven. However, when the downstream reset transistor 341 is driven, capacitor elements 321 and 322 are disconnected, resulting in a smaller parasitic capacitance Cp. Therefore, the kTC noise during readout is negligible compared to the kTC noise during exposure. Thus, the kTC noise during exposure and readout is represented by Equation 2.

[0099] As can be seen from Equations 1 and 2, among the 300 pixels whose capacitors are disconnected during readout, the kTC noise is smaller than that of pixels whose capacitors cannot be disconnected during readout. This improves the image quality of the image data.

[0100] Figure 11 is a flowchart showing an example of the operation of the solid-state imaging element 200 of the first embodiment of the present technology. This operation begins, for example, when a specific application for capturing image data is executed.

[0101] The vertical scanning circuit 211 exposes all pixels (step S901). The vertical scanning circuit 211 then selects the column to be read (step S902). The row signal processing circuit 260 reads the reset level of that column (step S903), and then reads the signal level (step S904).

[0102] The solid-state imaging element 200 determines whether the reading of all columns has been completed (step S905). If the reading of all columns has not been completed (step S905; No), the solid-state imaging element 200 repeats the steps after step S902. On the other hand, if the reading of all columns has been completed (step S905; Yes), the solid-state imaging element 200 performs CDS processing, etc., and ends the operation for shooting. When continuously shooting multiple image data, steps S901 to S905 are repeated in sync with the vertical sync signal.

[0103] Thus, in the first embodiment of this technology, when the selection circuit 330 disconnects the capacitor elements 321 and 322 from the downstream node 340, the downstream reset transistor 341 initializes the downstream node 340. Since the capacitor elements 321 and 322 are disconnected, the level of the reset noise caused by this drive becomes a level corresponding to the parasitic capacitance, which is smaller than those capacitors. By reducing this noise, the image quality of the image data can be improved.

[0104] [First Variation] In the first embodiment described above, the signal is read out while the front-end circuit 310 is connected to the front-end node 320. However, in this configuration, it is not possible to cut off the noise from the front-end node 320 during readout. The difference between the pixel 300 in this first variation of the first embodiment and the first embodiment is that a transistor is inserted between the front-end circuit 310 and the front-end node 320.

[0105] Figure 12 is a circuit diagram showing an example of the configuration of pixel 300 in a first variation of the first embodiment of the present technology. The difference between pixel 300 in the first variation of the first embodiment and that in the first embodiment is that it further includes a front-end reset transistor 323 and a front-end selection transistor 324. Furthermore, the power supply voltage of the front-end circuit 310 and the back-end circuit 350 in the first variation of the first embodiment is set to VDD1.

[0106] The front-end reset transistor 323 initializes the level of the front-end node 320 using the power supply voltage VDD2. It is desired that the power supply voltage VDD2 be set to a value that satisfies the following formula. In the above formula, Vgs is the gate-source voltage of the front-end amplification transistor 315.

[0107] By setting the value to satisfy Equation 3, the potential variation between the front node 320 and the rear node 340 can be reduced when it is darker. This can improve the sensitivity non-uniformity (PRNU: Photo Response Non-Uniformity).

[0108] The front-end selection transistor 324 opens or closes the path between the front-end circuit 310 and the front-end node 320 based on the front-end selection signal sel from the vertical scanning circuit 211.

[0109] Figure 13 is a timing diagram showing an example of a global shutter operation in a first variation of the first embodiment of the present technology. The difference between the timing diagram of the first variation of the first embodiment and that of the first embodiment is that the vertical scanning circuit 211 further supplies a front-end reset signal rsta and a front-end selection signal sel. In this figure, rsta_[n] and sel_[n] represent the signals for the nth column pixel.

[0110] The vertical scanning circuit 211 traverses timings T2 to T5 one moment before the end of exposure, supplying the high-level front-end selection signal sel to all pixels. The front-end reset signal rsta is controlled to the low level.

[0111] Figure 14 is a timing diagram showing an example of the readout operation of a first variation of the first embodiment of the present technology. When reading each column, the front-end select signal sel is controlled to a low level. By this control, the front-end select transistor 324 is switched on, disconnecting the front-end node 320 from the front-end circuit 310. This cuts off noise from the front-end node 320 during readout.

[0112] Also, during the readout period of the nth column from timing T10 to timing T17, the vertical scanning circuit 211 supplies the high-level pre-stage reset signal rsta to the nth column.

[0113] Furthermore, during readout, the vertical scanning circuit 211 controls the current source transistors 316 of all pixels to stop the supply of current id1. Current id2 is supplied in the same manner as in the first embodiment. Thus, compared with the first embodiment, the control of current id1 is simpler.

[0114] Thus, according to the first variation of the first embodiment of the present technology, since the front-end select transistor 324 is switched to the on state during readout, the front-end circuit 310 is disconnected from the front-end node 320, and thus the noise from the front-end circuit 310 can be cut off.

[0115] [Second Variation] In the first embodiment described above, the circuitry within the solid-state imaging element 200 is housed on a single semiconductor wafer. However, in this configuration, there is a risk that the elements cannot be housed within the semiconductor wafer when miniaturizing the pixels 300. The difference between the solid-state imaging element 200 in the second variation of the first embodiment and the first embodiment is that the circuitry within the solid-state imaging element 200 is distributed across two semiconductor wafers.

[0116] Figure 15 is a diagram showing an example of the multilayer structure of a solid-state imaging element 200 according to a second variation of the first embodiment of the present technology. The solid-state imaging element 200 of the second variation of the first embodiment includes a lower pixel chip 202 and an upper pixel chip 201 stacked on the lower pixel chip 202. These chips are electrically connected, for example, by Cu-Cu bonding. Alternatively, in addition to Cu-Cu bonding, they can also be connected by vias or bumps.

[0117] An upper pixel array 221 is disposed on the upper pixel chip 201. A lower pixel array 222 and a line signal processing circuit 260 are disposed on the lower pixel chip 202. For each pixel in the pixel array 220, a portion is disposed on the upper pixel array 221 and the remaining portion is disposed on the lower pixel array 222.

[0118] Furthermore, a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250 are also configured on the lower pixel chip 202. These circuits are omitted in this figure.

[0119] Furthermore, the upper pixel chip 201 is manufactured, for example, by a pixel-specific process, and the lower pixel chip 202 is manufactured, for example, by a CMOS (Complementary MOS) process. Additionally, the upper pixel chip 201 is an example of the first chip described in the claims, and the lower pixel chip 202 is an example of the second chip described in the claims.

[0120] Figure 16 is a circuit diagram showing an example of the configuration of a pixel 300 in a second variation of the first embodiment of the present technology. In the pixel 300, the front-end circuitry 310 is disposed on the upper pixel chip 201, while other circuits or components (such as capacitors 321 and 322) are disposed on the lower pixel chip 202. Furthermore, the current source transistor 316 can also be disposed on the lower pixel chip 202. As illustrated in the figure, by distributing the components within the pixel 300 across the upper pixel chip 201 and the lower pixel chip 202 of the stack, the pixel area can be reduced, making pixel miniaturization easier.

[0121] Thus, according to the second variation of the first embodiment of the present technology, since the circuits or components within the pixel 300 are distributed on two semiconductor wafers, pixel miniaturization becomes easy.

[0122] [Third Variation] In the second variation of the first embodiment described above, a portion of the pixel 300 and peripheral circuitry (such as the line signal processing circuit 260) are disposed on the lower pixel chip 202. However, in this configuration, the area of ​​the circuitry or components on the lower pixel chip 202 side is larger than that of the peripheral circuitry on the upper pixel chip 201, which may result in unused space without circuitry or components on the upper pixel chip 201. The difference between the solid-state imaging element 200 of the third variation of the first embodiment and the second variation of the first embodiment is that the circuitry within the solid-state imaging element 200 is distributed across three semiconductor chips.

[0123] Figure 17 is a diagram showing an example of the multilayer structure of a solid-state imaging element 200 according to a third variation of the first embodiment of the present technology. The solid-state imaging element 200 of the third variation of the first embodiment includes an upper pixel chip 201, a lower pixel chip 202, and a circuit chip 203. These chips are multilayered and electrically connected, for example, by Cu-Cu bonding. Alternatively, in addition to Cu-Cu bonding, they can also be connected by vias or bumps.

[0124] An upper pixel array 221 is disposed on the upper pixel chip 201. A lower pixel array 222 is disposed on the lower pixel chip 202. For each pixel in the pixel array 220, a portion is disposed on the upper pixel array 221 and the remaining portion is disposed on the lower pixel array 222.

[0125] Furthermore, on the circuit chip 203, a horizontal signal processing circuit 260, a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250 are configured. Circuits other than the horizontal signal processing circuit 260 are omitted in this figure.

[0126] By configuring it as a 3-layer structure as illustrated in the figure, compared with a 2-layer structure, useless space can be reduced, and the pixels can be further miniaturized. In addition, it can also be used to manufacture the pixel chip 202 under the second layer using a dedicated process for capacitors or switches.

[0127] Thus, in the third variation of the first embodiment of the present technology, since the circuitry within the solid-state imaging element 200 is distributed across three semiconductor wafers, the pixels can be further miniaturized compared to the case where the circuitry is distributed across two semiconductor wafers.

[0128] <2. Second Embodiment> In the first embodiment described above, the sampling and holding reset level is maintained during the exposure period. However, in this configuration, it is not possible to set the exposure period to be shorter than the sampling and holding period of the reset level. The difference between the solid-state imaging element 200 of the second embodiment and the first embodiment is that the exposure period is further shortened by adding a transistor that discharges charge from the photoelectric conversion element.

[0129] FIG18 is a circuit diagram showing an example of the configuration of a pixel 300 according to a second embodiment of the present technology. The difference between the pixel 300 of the second embodiment and the first embodiment is that a discharge transistor 317 is further provided in the front-end circuit 310.

[0130] The discharge transistor 317 functions as an overflow absorber for the discharge of charge from the photoelectric conversion element 311 based on the discharge signal ofg from the vertical scanning circuit 211. An nMOS transistor is used as the discharge transistor 317, for example.

[0131] In a configuration where the discharge transistor 317 is not provided, as in the first embodiment, when charge is transferred from the photoelectric conversion element 311 to the FD 314 for all pixels, scintillation may sometimes occur. Furthermore, during FD reset, the potential of FD 314 and the preceding node 320 decreases. Following this potential decrease, charging and discharging currents are continuously generated in the capacitor elements 321 and 322, and the IR potential of the power supply or ground changes from a stable state without scintillation.

[0132] On the other hand, when sampling and holding the signal level of all pixels, since the charge in the photoelectric conversion element 311 becomes empty after the signal charge is transmitted, no halos are generated, and the IR drop of the power supply or ground becomes a stable state without halos. Due to the difference in IR drop when sampling and holding these reset levels and signal levels, bar-shaped noise will be generated.

[0133] In this respect, in the second embodiment where the discharge transistor 317 is provided, the charge of the photoelectric conversion element 311 is discharged to the overflow draw-in side. Therefore, the IR level is reduced to the same level when the sampling hold reset level and the signal level are both reduced, and stripe noise can be suppressed.

[0134] Figure 19 is a timing diagram showing an example of the global shutter operation in the second embodiment of the present technology. At timing T0 before the start of exposure, the vertical scanning circuit 211 sets the discharge signal ofg of all pixels to a high level, and during the traversal pulse, supplies a high-level FD reset signal rst to all pixels. This performs PD reset and FD reset on all pixels. Furthermore, the reset level is sampled and held. Here, ofg_[n] in this figure represents the signal for the nth pixel in the N columns.

[0135] Furthermore, at the start of exposure time T1, the vertical scanning circuit 211 restores the discharge signal ofg of all pixels to a low level. And, during the period from the moment before the end of exposure T2 to the end of exposure T3, the vertical scanning circuit 211 supplies a high-level transmission signal trg to all pixels. This maintains the sample-and-hold signal level.

[0136] In the configuration without the discharge transistor 317 as in the first embodiment, both the transmission transistor 312 and the FD reset transistor 313 must be turned on at the start of exposure (i.e., during PD reset). In this control, FD 314 must also be reset simultaneously during PD reset. Therefore, FD reset must be performed again during the exposure period, and the reset level must be sampled and held, making it impossible to set the exposure period shorter than the sample holding period of the reset level. When sampling and holding the reset level of all pixels, a certain waiting time is required until the voltage or current settles, for example, a sample holding period of several microseconds (μs) to tens of microseconds (μs) is required.

[0137] In this regard, in the second embodiment of the discharge transistor 317, PD reset and FD reset can be performed individually. Therefore, as illustrated in the figure, FD reset can be performed before PD reset is released (exposure begins), and the reset level can be sampled and held. In this way, the exposure period can be set to a shorter sampling and holding period than the reset level.

[0138] Alternatively, the first to third variations of the first embodiment may also be applied in the second embodiment.

[0139] Thus, according to the second embodiment of this technology, since a discharge transistor 317 for discharging charge from the photoelectric conversion element 311 is provided, FD reset and sampling to maintain the reset level can be performed before the start of exposure. In this way, the sampling and holding period of the exposure period can be set to be shorter than that of the reset level.

[0140] <3. Third Embodiment> In the first embodiment described above, the FD314 has been initialized by the power supply voltage VDD. However, in this configuration, there is a risk of deterioration in sensitivity non-uniformity (PRNU) due to the deviation of capacitor elements 321 and 322 or parasitic capacitance. The difference between the solid-state imaging element 200 in the third embodiment and the first embodiment is that the PRNU is improved by reducing the power supply of the FD reset transistor 313 during readout.

[0141] FIG20 is a circuit diagram showing an example of the configuration of a pixel 300 according to a third embodiment of the present technology. The difference between the pixel 300 of the third embodiment and the first embodiment is that the power supply of the FD reset transistor 313 is separated from the power supply voltage VDD of the pixel 300.

[0142] In the third embodiment, the drain of the FD reset transistor 313 is connected to the reset power supply voltage VRST. This reset power supply voltage VRST is controlled, for example, by a timing control circuit 212. Furthermore, the timing control circuit 212 is an example of the control circuit described in the claims.

[0143] Here, referring to Figures 21 and 22, the degradation of the PRNU of pixel 300 in the first embodiment is considered. In the first embodiment, as illustrated in Figure 21, at the timing T0 just before the start of exposure, the potential of FD 314 decreases due to the reset feedthrough of FD reset transistor 313. This change is set as Vft.

[0144] In the first embodiment, since the power supply voltage of the FD reset transistor 313 is VDD, the potential of FD314 changes from VDD to VDD-Vft at timing T0. Also, the potential of the front node 320 during exposure is VDD-Vft-Vsig.

[0145] Furthermore, in the first embodiment, as illustrated in FIG22, during readout, the FD reset transistor 313 is switched to the ON state, and the FD 314 is fixed to the power supply voltage VDD. By means of the variation Vft of the FD 314, the potentials of the front node 320 and the rear node 340 during readout are shifted by about Vft. However, due to the deviation of the capacitance values ​​of capacitor elements 321 and 322 or parasitic capacitance, the amount of voltage shift will vary in each pixel, becoming a cause of PRNU degradation.

[0146] When the front node 320 changes Vft, the change in the subsequent node 340 is represented by the following formula. In the above formula, Cs is the capacitance value of the capacitor element 322 on the signal level side, δCs is the deviation of Cs. Cp is the capacitance value of the parasitic capacitance of the subsequent node 340.

[0147] Equation 4 can be approximated by the following equation.

[0148] As can be seen from Equation 5, the deviation of the later node 340 can be expressed by the following formula.

[0149] If (δCs / Cs) is set to 10-2, (Cp / Cs) is set to 10-1, and Vft is set to 400 millivolts (mV), then according to Equation 6, PRNU is 400 μVrms, which is a relatively large value.

[0150] In particular, when reducing the kTC noise during the sampling and holding of the input conversion capacitor, it is necessary to increase the charge-to-voltage conversion efficiency of the FD314. To increase the charge-to-voltage conversion efficiency, the capacitance of the FD314 must be reduced, but the smaller the capacitance of the FD314, the larger the variation Vft, which may become hundreds of millivolts (mV). In this case, as can be seen from Equation 6, the effect of PRNU may become non-negligible.

[0151] Figure 23 is a timing diagram showing an example of voltage control in a third embodiment of the present technology.

[0152] During the readout period of the unit after timing T9, the timing control circuit 212 will reset the power supply voltage VRST to a value different from that during the exposure period.

[0153] For example, during exposure, the timing control circuit 212 sets the reset power supply voltage VRST to the same value as the power supply voltage VDD. On the other hand, during readout, the timing control circuit 212 reduces the reset power supply voltage VRST to VDD-Vft. That is, during readout, the timing control circuit 212 reduces the reset power supply voltage VRST by an amount approximately the same as the variation Vft caused by the reset feedthrough. By means of this control, the reset level of FD314 can be made consistent during exposure and readout.

[0154] By controlling the reset power supply voltage VRST, as illustrated in the figure, the voltage fluctuation between FD314 and the front-end node 320 can be reduced. This can suppress the deterioration of PRNU caused by the deviation of capacitor elements 321 and 322 or by parasitic capacitance.

[0155] Alternatively, the first to third variations of the first embodiment or the second embodiment may be applied to the third embodiment.

[0156] Thus, according to the third embodiment of this technology, since the timing control circuit 212 reduces the change in reset power supply voltage VRST caused by reset feedthrough Vft during readout, the reset level can be made consistent with that during exposure and readout. This suppresses the deterioration of sensitivity non-uniformity (PRNU).

[0157] <4. Fourth Embodiment> In the first embodiment described above, the signal level is read out after resetting the level for each frame. However, in this configuration, there is a risk of deterioration in sensitivity non-uniformity (PRNU) due to the deviation of capacitor elements 321 and 322 or parasitic capacitance. The difference between the solid-state imaging element 200 in the fourth embodiment and the first embodiment is that PRNU is improved by changing the level held at capacitor element 321 and the level held at capacitor element 322 for each frame.

[0158] The solid-state imaging element 200 of the fourth embodiment continuously captures a plurality of frames in sync with a vertical synchronization signal. Odd-numbered frames are referred to as "odd-numbered frames," and even-numbered frames are referred to as "even-numbered frames." Furthermore, odd-numbered frames and even-numbered frames are examples of a pair of frames described in the claims.

[0159] Figure 24 is a timing diagram showing an example of the global shutter operation of the odd-numbered frames in the fourth embodiment. During the exposure period of the odd-numbered frames, the front-end circuit 310 in the solid-state imaging element 200 sets the selection signal Φs to a high level after the selection signal Φr, thereby keeping the capacitor element 321 at the reset level, and then keeping the capacitor element 322 at the signal level.

[0160] Figure 25 is a timing diagram showing an example of the readout operation of an odd-numbered frame in the fourth embodiment of the present technology. During the readout of the odd-numbered frame, the downstream circuit 350 in the solid-state imaging element 200 sets the selection signal Φs to a high level after the selection signal Φr, and reads out the signal level after resetting the level.

[0161] Figure 26 is a timing diagram showing an example of the global shutter operation of an even-numbered frame in the fourth embodiment. During the exposure period of the even-numbered frame, the front-end circuit 310 in the solid-state imaging element 200 sets the selection signal Φr to a high level after the selection signal Φs, thereby keeping the capacitor element 322 at the reset level, and then keeping the capacitor element 321 at the signal level.

[0162] Figure 27 is a timing diagram showing an example of the readout operation of an even-numbered frame in the fourth embodiment of the present technology. During the readout period of the even-numbered frame, the downstream circuit 350 in the solid-state imaging element 200 sets the selection signal Φr to a high level after the selection signal Φs, and reads out the signal level after resetting the level.

[0163] As illustrated in Figures 24 and 26, the levels of capacitors 321 and 322 are kept opposite in even-numbered frames and odd-numbered frames. Therefore, the polarity of the PRNU is also opposite in even-numbered frames and odd-numbered frames. The subsequent horizontal signal processing circuit 260 calculates the average value of the odd-numbered frames and even-numbered frames. This allows the PRNUs with opposite polarities to cancel each other out.

[0164] This control is effective when shooting animation or adding frames together. Furthermore, it can be achieved simply by changing the driving method, without needing to add components to pixel 300.

[0165] Alternatively, the first to third variations of the first embodiment, or the second and third embodiments, may be applied to the fourth embodiment.

[0166] Thus, in the fourth embodiment of this technology, since the level held in capacitor element 321 is opposite to the level held in capacitor element 322 in odd-numbered frames and even-numbered frames, the polarity of the PRNU can be set to opposite in odd-numbered frames and even-numbered frames. By adding these odd-numbered frames and even-numbered frames together by the line signal processing circuit 260, PRNU degradation can be suppressed.

[0167] <5. Fifth Embodiment> In the first embodiment described above, the line signal processing circuit 260 calculates the difference between the reset level and the signal level for each line. However, in this configuration, when very high-intensity light is incident on a pixel, there is a risk of brightness reduction due to charge overflow from the photoelectric conversion element 311, resulting in black spots. The difference between the solid-state imaging element 200 in this fifth embodiment and the first embodiment is that it determines whether a black spot phenomenon occurs for each pixel.

[0168] Figure 28 is a circuit diagram showing an example configuration of a line signal processing circuit 260 according to a fifth embodiment of the present invention. In this fifth embodiment of the line signal processing circuit 260, a plurality of ADCs 270 and a digital signal processing unit 290 are configured. Furthermore, in the digital signal processing unit 290, a plurality of CDS processing units 291 and a plurality of selectors 292 are configured. The ADCs 270, CDS processing units 291, and selectors 292 are configured for each line.

[0169] Furthermore, the ADC270 includes a comparator 280 and a counter 271. The comparator 280 compares the level of the vertical signal line 309 with the ramp signal Rmp from the DAC213 and outputs the comparison result VCO. The comparison result VCO is supplied to the counter 271 and the timing control circuit 212. The comparator 280 includes a selector 281, capacitors 282 and 283, automatic zeroing switches 284 and 286, and a comparator 285.

[0170] Selector 281 connects either the vertical signal line 309 of the corresponding row or the node of the specific reference voltage VREF to the non-inverting input terminal (+) of comparator 285 via capacitor element 282, based on the input-side selection signal selin. The input-side selection signal selin is supplied from timing control circuit 212. Furthermore, selector 281 is an example of the input-side selector described in the claims.

[0171] Comparator 285 compares the levels of the non-inverting input terminal (+) and the inverting input terminal (-), and outputs the comparison result VCO to counter 271. For the inverting input terminal (-), a ramp signal Rmp is input via capacitor element 283.

[0172] Automatic zeroing switch 284 short-circuits the non-inverting input terminal (+) and output terminal of the comparison result VCO based on the automatic zeroing signal Az from the timing control circuit 212. Automatic zeroing switch 286 short-circuits the inverting input terminal (-) and output terminal of the comparison result VCO based on the automatic zeroing signal Az.

[0173] The counter 271 counts the count value until the comparison result VCO reverses, and outputs the digital signal CNT_out representing the count value to the CDS processing unit 291.

[0174] The CDS processing unit 291 performs CDS processing on the digital signal CNT_out. The CDS processing unit 291 calculates the difference between the digital signal CNT_out corresponding to the reset level and the digital signal CNT_out corresponding to the signal level, and outputs it as CDS_out to the selector 292.

[0175] Selector 292 outputs either the CDS-processed digital signal CDS_out or the full-code digital signal FULL as the pixel data for the corresponding row, based on the output-side selection signal selout from the timing control circuit 212. Furthermore, selector 292 is one example of the output-side selector described in the claims.

[0176] Figure 29 is a timing diagram showing an example of global shutter operation in the fifth embodiment of the present technology. The control method of the transistor during global shutter in the fifth embodiment is the same as that in the first embodiment.

[0177] Here, very high illuminance light is incident on pixel 300. In this case, the charge of photoelectric conversion element 311 is fully charged, and the charge overflows from photoelectric conversion element 311 to FD314. After FD reset, the potential of FD314 decreases. The dotted chain line in the figure represents the potential change of FD314 when weaker sunlight is incident, with a relatively smaller amount of overflowed charge. The dashed line in the figure represents the potential change of FD314 when stronger sunlight is incident, with a relatively larger amount of overflowed charge.

[0178] When weaker sunlight is incident, at time T3 when the FD reset is completed, the reset level decreases, but the level does not completely decrease at that time.

[0179] On the other hand, when strong sunlight is incident, the reset level drops completely at time T3. In this case, since the signal level and the reset level are the same, their potential difference is "0", so the digital signal after CDS processing turns black, just like in the dark state. Thus, the phenomenon that the pixel turns black even when very high-intensity light such as sunlight is incident is called black spot phenomenon or halo.

[0180] Furthermore, if the level of FD314 of the pixel causing the black spot phenomenon drops excessively, the operating point of the front-end circuit 310 cannot be guaranteed, and the current id1 of the current source transistor 316 changes. Since the current source transistors 316 of each pixel are connected to a common power supply or ground, when the current in a certain pixel changes, the change in the IR level of that pixel will affect the sampling level of other pixels. The pixel causing the black spot phenomenon is the source of interference, and the pixels whose sampling level changes due to that pixel are the affected by the interference. As a result, bar-shaped noise is generated.

[0181] Furthermore, when an ejector transistor 317 is provided as in the second embodiment, the overflowing charge in pixels with black spots (halos) is discarded to the ejector transistor 317 side, thus reducing the likelihood of black spot phenomena. However, even with the ejector transistor 317, some charge may still flow to the FD314, potentially making it impossible to completely eliminate the black spot phenomenon. Moreover, there is a disadvantage that the ratio of effective area to charge amount per pixel decreases due to the addition of the ejector transistor 317. Therefore, it is desirable to suppress the black spot phenomenon without using the ejector transistor 317.

[0182] Two methods are considered as ways to suppress the black spot phenomenon without using the discharge transistor 317. The first method is to adjust the limiting level of FD314. The second method is to determine whether a black spot phenomenon occurs during reading, and if a black spot phenomenon occurs, replace the output with the full code.

[0183] Regarding the first method, the high level of the FD reset signal rst (in other words, the gate of the FD reset transistor 313) in this figure is the power supply voltage VDD, and the low level corresponds to the limiting level of FD314. In the first embodiment, the difference between these high and low levels (i.e., amplitude) is set to a value corresponding to the dynamic range. In the fifth embodiment, this value is adjusted by adding a tolerance value. Here, the value corresponding to the dynamic range is the difference between the power supply voltage VDD and the potential of FD314 when the digital signal becomes full code.

[0184] By reducing the gate voltage (low level of FD reset signal rst) when the FD reset transistor 313 is turned off, it is possible to prevent the FD314 from being excessively reduced due to corona, which would damage the operating point of the front-end amplification transistor 315.

[0185] Furthermore, the dynamic range varies depending on the analog gain of the ADC. A larger dynamic range is required when the analog gain is low, and conversely, a smaller dynamic range is required when the analog gain is high. Therefore, the gate voltage when the FD reset transistor 313 is turned off can also be changed according to the analog gain.

[0186] Figure 30 is a timing diagram showing an example of the readout operation in the fifth embodiment of this technology. Immediately following the readout start timing T10, timing T11, when the selection signal Φr becomes high-order, the potential change of the vertical signal line 309 in the pixel with sunlight incidence. The dotted chain line in this figure represents the potential change of the vertical signal line 309 when weaker sunlight incidence occurs. The dashed line in this figure represents the potential change of the vertical signal line 309 when stronger sunlight incidence occurs.

[0187] During the automatic zeroing period from timing T10 to timing T12, the timing control circuit 212 provides, for example, an input-side selection signal selin of "0", so that the comparator 285 is connected to the vertical signal line 309. During this automatic zeroing period, the timing control circuit 212 performs automatic zeroing by means of the automatic zeroing signal Az.

[0188] Regarding the second method, during the decision period from timing T12 to timing T13, the timing control circuit 212, for example, supplies an input-side selection signal selin for "1". Using this input-side selection signal selin, the comparator 285 is disconnected from the vertical signal line 309 and connected to the node of the reference voltage VREF. The reference voltage VREF is set to the expected value of the level of the vertical signal line 309 when no halos is generated. For example, when the gate-source voltage of the downstream amplification transistor 351 is set to Vgs2, Vrst is equivalent to Vreg-Vgs2. Furthermore, during the decision period, the DAC 213 lowers the level of the ramp signal Rmp from Vrmp_az to Vrmp_sun.

[0189] Furthermore, when no scintillation occurs during the determination period, the reset level Vrst of the vertical signal line 309 is approximately the same as the reference voltage VREF, and the potential of the inverting input terminal (+) of the comparator 285 is almost identical to that during automatic zeroing. On the other hand, since the non-inverting input terminal (-) has decreased from Vrmp_az to Vrmp_sun, the comparison result VCO becomes a high level.

[0190] Conversely, in the event of a halo effect, the reset level Vrst is sufficiently higher than the reference voltage VREF. When the following equation holds, the comparison result VCO becomes the low level.

[0191] That is, the timing control circuit 212 can determine whether scintillation occurs by determining whether the comparison result VCO becomes a low level during the determination period.

[0192] In addition, in order to avoid misjudgment caused by deviation of the threshold voltage of the amplified transistor 351 in the later stage or the IR drop difference of Vreg in the plane, it is necessary to ensure that the tolerance for solar determination (the right side of Equation 7) is large enough to a certain extent.

[0193] After timing T13 following the determination period, timing control circuit 212 connects comparator 285 to vertical signal line 309. Furthermore, after the P-phase settling period from timing T13 to T14, the P-phase is read out during the period from timing T14 to T15. After the D-phase settling period from timing T15 to T19, the D-phase is read out during the period from timing T19 to T20.

[0194] When it is determined that no suffocation occurred during the determination period, the timing control circuit 212 controls the selector 292 by the output side selection signal selout to directly output the digital signal CDS_out after CDS processing.

[0195] On the other hand, when it is determined that smudges occur during the determination period, the timing control circuit 212 controls the selector 292 by using the output-side selection signal selout to replace the digital signal CDS_out processed by CDS and output the full code FULL. In this way, the black spot phenomenon can be suppressed.

[0196] Alternatively, the first to third variations of the first embodiment, or the second to fourth embodiments, can also be applied to the fifth embodiment.

[0197] Thus, according to the fifth embodiment of the present technology, since the timing control circuit 212 determines whether a black spot phenomenon is generated based on the comparison result VCO, and outputs the full code when a black spot phenomenon is generated, the black spot phenomenon can be suppressed.

[0198] <6. Sixth Embodiment> In the first embodiment described above, the vertical scanning circuit 211 controls the simultaneous exposure of all columns (all pixels) (i.e., global shutter operation). However, in situations where simultaneous exposure is not required and low noise is needed, such as during testing or resolution, a rolling shutter operation is desirable. The difference between the solid-state imaging element 200 of this sixth embodiment and the first embodiment is that a rolling shutter operation is performed during testing, etc.

[0199] Figure 31 is a timing diagram showing an example of the rolling shutter action in the sixth embodiment of the present technology. The vertical scanning circuit 211 sequentially selects multiple columns to control the start of exposure. This figure shows the exposure control of the nth column.

[0200] During the time intervals T0 to T2, the vertical scanning circuit 211 supplies the high-level post-stage selection signal selb, selection signal Φr, and selection signal Φs to the nth column. Also, at the start of exposure time T0, during the traversal pulse period, the vertical scanning circuit 211 supplies the high-level FD reset signal rst and the post-stage reset signal rstb to the nth column. At the end of exposure time T1, the vertical scanning circuit 211 supplies the transmission signal trg to the nth column. Through this rolling shutter action, the solid-state imaging element 200 can generate low-noise image data.

[0201] In addition, during normal video recording, the solid-state imaging element 200 of the sixth embodiment performs global shutter operation in the same way as the first embodiment.

[0202] Alternatively, the first to third variations of the first embodiment, or the second to fifth embodiments, can be applied to the sixth embodiment.

[0203] Thus, according to the sixth embodiment of this technology, since the vertical scanning circuit 211 sequentially selects a plurality of columns to control the start of exposure (i.e., rolling shutter action), low-noise image data can be generated.

[0204] <7. Seventh Embodiment> In the first embodiment described above, the source of the front-end source follower (front-end amplifying transistor 315 and current source transistor 316) is connected to the power supply voltage VDD, and readout is performed in column units when the source follower is turned on. However, in this driving method, there is a risk that circuit noise from the front-end source follower will be transmitted to the later stage during column unit readout, increasing random noise. The difference between the solid-state imaging element 200 in the seventh embodiment and the first embodiment is that noise is reduced by setting the front-end source follower to the off state during readout.

[0205] FIG32 is a block diagram showing a configuration example of a solid-state imaging element 200 according to a seventh embodiment of the present technology. The difference between this seventh embodiment and the first embodiment is that it further includes an adjuster 420 and a switching unit 440. Furthermore, in the pixel array unit 220 of the seventh embodiment, a plurality of effective pixels 301 and a specific number of dummy pixels 430 are arranged. The dummy pixels 430 are arranged around the area where the effective pixels 301 are arranged.

[0206] Furthermore, a power supply voltage VDD is supplied to each of the dummy pixels 430, and a power supply voltage VDD and a source voltage Vs are supplied to each of the effective pixels 301. The signal line supplying the power supply voltage VDD to the effective pixels 301 is omitted in this figure. Furthermore, the power supply voltage VDD is supplied from the solder pads 410 on the outside of the solid-state imaging element 200.

[0207] The regulator 420 generates a constant generation voltage Vgen based on the input potential Vi from the dummy pixel 430 and supplies it to the switching unit 440. The switching unit 440 selects either the power supply voltage VDD from the pad 410 or the generation voltage Vgen from the regulator 420 and supplies it as the source voltage Vs to each row of the effective pixel 301.

[0208] Figure 33 is a circuit diagram showing an example of the configuration of one of the dummy pixel 430, the regulator 420, and the switching unit 440 in the seventh embodiment of the present technology. Figure a is a circuit diagram of the dummy pixel 430 and the regulator 420, and Figure b is a circuit diagram of the switching unit 440.

[0209] As illustrated in Figure a, the dummy pixel 430 includes a reset transistor 431, an FD 432, an amplifying transistor 433, and a current source transistor 434. The reset transistor 431 initializes the FD 432 according to the reset signal RST from the vertical scanning circuit 211. The FD 432 accumulates charge and generates a voltage corresponding to the amount of charge. The amplifying transistor 433 amplifies the voltage level of the FD 432 and supplies it as the input voltage Vi to the regulator 420.

[0210] Furthermore, the sources of the reset transistor 431 and the amplifying transistor 433 are connected to the power supply voltage VDD. The current source transistor 434 is connected to the drain of the amplifying transistor 433. The current source transistor 434 supplies current id1 according to the control of the vertical scanning circuit 211.

[0211] The regulator 420 includes a low-pass filter 421, a buffer amplifier 422, and a capacitor element 423. The low-pass filter 421 allows the low-frequency components of the input voltage Vi signal that do not reach a specific frequency to pass through as the output voltage Vj.

[0212] The non-inverting input terminal (+) of the buffer amplifier 422 receives the output voltage Vj. The inverting input terminal (-) of the buffer amplifier 422 is connected to its output terminal. The capacitor element 423 holds the voltage at the output terminal of the buffer amplifier 422 as Vgen. This Vgen is supplied to the switching unit 440.

[0213] As illustrated in Figure b, the switching unit 440 includes an inverter 441 and a plurality of switching circuits 442. The switching circuits 442 are configured for each row of effective pixels 301.

[0214] Inverter 441 is used to invert the switching signal SW from timing control circuit 212. Inverter 441 supplies the inverted signal to each of switching circuits 442.

[0215] The switching circuit 442 selects either the power supply voltage VDD or the generated voltage Vgen as the source voltage Vs to supply to the corresponding row within the pixel array section 220. The switching circuit 442 includes switches 443 and 444. Switch 443 opens or closes the path between the node of the power supply voltage VDD and the corresponding row according to the switching signal SW. Switch 444 opens or closes the path between the node of the generated voltage Vgen and the corresponding row according to the inversion signal of the switching signal SW.

[0216] Figure 34 is a timing diagram showing an example of the operation of the dummy pixel 430 and the regulator 420 in the seventh embodiment of the present technology. At timing T10, just before reading out a certain column, the vertical scanning circuit 211 supplies a high-level (here, power supply voltage VDD) reset signal RST to each of the dummy pixels 430. The potential Vfd of FD432 in the dummy pixel 430 is initialized to the power supply voltage VDD. Furthermore, when the reset signal RST becomes low-level, it changes to VDD-Vft through the reset feedthrough.

[0217] Furthermore, the input voltage Vi decreases to VDD-Vgs-Vsig after the reset. By passing through the low-pass filter 421, Vj and Vgen become approximately constant voltages.

[0218] After timing T20, one moment before the next column is read, the same control is performed on each column to supply a constant generation voltage Vgen.

[0219] FIG35 is a circuit diagram showing an example of the configuration of an effective pixel 301 in the seventh embodiment of the present technology. The circuit configuration of the effective pixel 301 is the same as that of the pixel 300 in the first embodiment, except that the source voltage Vs from the switching unit 440 is supplied to the source of the front-end amplifying transistor 315.

[0220] Figure 36 is a timing diagram showing an example of the global shutter operation in the seventh embodiment of the present technology. In the seventh embodiment, when all pixels are exposed simultaneously, the switching unit 440 selects the power supply voltage VDD and supplies it as the source voltage Vs. Furthermore, the voltage of the front-end node decreases from VDD-Vgs-Vth to VDD-Vgs-Vsig at timing T4. Here, Vth is the threshold voltage of the transistor 312.

[0221] Figure 37 is a timing diagram showing an example of the readout operation of the seventh embodiment of the present technology. In this seventh embodiment, during readout, the switching unit 440 selects the generation voltage Vgen and supplies it as the source voltage Vs. The generation voltage Vgen is adjusted to VDD-Vgs-Vft. Furthermore, in the seventh embodiment, the vertical scan circuit 211 controls the current source transistors 316 of all columns (all pixels) to stop supplying current id1.

[0222] Figure 38 is a diagram illustrating the effect of the seventh embodiment of the present technology. In the first embodiment, when reading out each column, the source follower (front-end amplification transistor 315 and current source transistor 316) of the pixel 300 to be read out is turned on. However, in this driving method, circuit noise from the front-end source follower is transmitted to the back end (capacitor element, back-end source follower or ADC), which may increase the readout noise.

[0223] For example, in the first embodiment, as illustrated in the figure, the kTC noise generated in the pixel during global shutter operation is 450 (μVrms). Furthermore, during readout of each column, the noise generated in the front-end source follower (front-end amplifying transistor 315 and current source transistor 316) is 380 (μVrms). The noise generated after the rear-end source follower is 160 (μVrms). Therefore, the total noise is 610 (μVrms). Thus, in the first embodiment, the contribution of the noise from the front-end source follower is relatively large in the total noise value.

[0224] To reduce noise from the front-end source follower, in the seventh embodiment, an adjustable voltage (Vs) is supplied to the source of the front-end source follower as described above. During the full-range shutter (exposure) operation, the switching unit 440 selects the power supply voltage VDD as the source voltage Vs for supply. After the exposure is completed, the switching unit 440 switches the source voltage Vs to VDD-Vgs-Vft. Furthermore, the timing control circuit 212 turns on the front-end current source transistor 316 during the full-range shutter (exposure) operation and turns it off after the exposure is completed.

[0225] Through the above control, as illustrated in Figures 36 and 37, the potential of the front-end nodes is consistent during global shutter operation and during readout of each column, which improves PRNU. Furthermore, since the front-end source follower is in the off state during readout of each column, as illustrated in Figure 38, no source follower circuit noise is generated, resulting in 0 (μVrms). Additionally, the front-end amplifying transistor 315 in the front-end source follower is in the on state.

[0226] Thus, according to the seventh embodiment of this technology, since the source follower is set to the off state during readout, the noise generated in the source follower can be reduced.

[0227] <8. Eighth Embodiment> In the first embodiment described above, the conversion efficiency of converting charge into voltage has been kept constant, but in this configuration, it is difficult to further improve the image quality. The difference between the solid-state imaging element 200 in the eighth embodiment and the first embodiment is that the conversion efficiency is switched in two stages.

[0228] Figure 39 is a circuit diagram showing an example of the configuration of a pixel 300 in the eighth embodiment of the present technology. The difference between the pixel 300 in the eighth embodiment and the first embodiment is that a conversion efficiency control transistor 361 is further configured in the front-end circuit 310, and the number of capacitor elements and selection transistors is increased.

[0229] In detail, a conversion efficiency control transistor 361, a switching transistor 363, and a pre-charge transistor 364 are further configured within the front-end circuit 310. For example, nMOS transistors are used as the conversion efficiency control transistor 361, the switching transistor 363, and the pre-charge transistor 364. Furthermore, capacitor elements 321-1, 322-1, 321-2, and 322-2 are configured instead of capacitor elements 321 and 322. For example, MIM (Metal Insulator Metal) structure elements are used as these capacitor elements. Moreover, selection transistors 331-1, 332-1, 331-2, and 332-2 are configured instead of selection transistors 331 and 332.

[0230] The connection configuration of the photoelectric conversion element 311, the transmission transistor 312, the FD reset transistor 313, FD 314, the preamplifier transistor 315, and the current source transistor 316 is the same as in the first embodiment. However, in the eighth embodiment, a conversion efficiency control transistor 361 is inserted between the FD reset transistor 313 and FD 314. Furthermore, a switching transistor 363 and a precharge transistor 364 are inserted between the preamplifier transistor 315 and the current source transistor 316.

[0231] The conversion efficiency control transistor 361 is switched on and off by a control signal fdg from the vertical scanning circuit 211. The switching transistor 363 switches the path between the front-end amplification transistor 315 and the front-end node 320 according to the control signal sw from the vertical scanning circuit 211. The pre-charge transistor 364 switches the path between the front-end node 320 and the current source transistor 316 according to the control signal PC from the vertical scanning circuit 211.

[0232] One end of capacitor elements 321-1, 322-1, 321-2 and 322-2 is commonly connected to the front node 320. The selection circuit 330 connects the other end of any of these capacitor elements to the rear node 340.

[0233] Selector transistor 331-1 opens or closes the path between capacitor element 321-1 and subsequent node 340 based on the selection signal ΦRH from vertical scanning circuit 211. Selector transistor 332-1 opens or closes the path between capacitor element 321-1 and subsequent node 340 based on the selection signal ΦSH from vertical scanning circuit 211. Selector transistor 331-2 opens or closes the path between capacitor element 321-2 and subsequent node 340 based on the selection signal ΦRL from vertical scanning circuit 211. Selector transistor 332-2 opens or closes the path between capacitor element 322-2 and subsequent node 340 based on the selection signal ΦSL from vertical scanning circuit 211.

[0234] Furthermore, a portion of the components within pixel 300 are disposed on the upper pixel chip 201, and the remaining portion is disposed on the lower pixel chip 202. For example, photoelectric conversion element 311, transmission transistor 312, FD reset transistor 313, conversion efficiency control transistor 361, FD 314, front-end amplification transistor 315, and switching transistor 363 are disposed on the upper pixel chip 201. The circuitry after the pre-charge transistor 364 is disposed on the lower pixel chip 202. Alternatively, the solid-state imaging element 200 may not be configured as a multilayer structure, and each component may be disposed on a single semiconductor chip.

[0235] With the circuit configuration described above, the conversion efficiency when the conversion efficiency control transistor 361 is in the off state is higher than when the conversion efficiency control transistor 361 is in the on state. Hereinafter, the higher conversion efficiency will be referred to as "HCG (High Conversion Gain)" and the lower conversion efficiency will be referred to as "LCG (Low Conversion Gain)". At the end of the exposure in global shutter mode, the front-end circuit 310 converts charge into voltage using HCG and LCG respectively and outputs it to the front-end node 320 in sequence. Since the voltage of the reset level or signal level is generated, the four reset levels and signal levels generated by HCG and LCG are output in sequence.

[0236] When outputting a reset level corresponding to HCG, the selection circuit 330 selects only transistor 331-1 to be switched on, and maintains the reset level at capacitor element 321-1. When outputting a signal level corresponding to HCG, the selection circuit 330 selects only transistor 332-1 to be switched on, and maintains the signal level at capacitor element 322-1. Thus, the voltage corresponding to HCG is maintained at capacitor elements 321-1 and 322-1.

[0237] Furthermore, when outputting a reset level corresponding to the LCG, the selection circuit 330 selects only transistor 331-2 to be switched on, and maintains the reset level at capacitor element 321-2. When outputting a signal level corresponding to the LCG, the selection circuit 330 selects only transistor 332-2 to be switched on, and maintains the signal level at capacitor element 322-2. Thus, the voltage corresponding to the LCG is maintained at capacitor elements 321-2 and 322-2.

[0238] Here, the capacitance values ​​of capacitor elements 321-1 and 322-1 corresponding to HCG are the same. Also, the capacitance values ​​of capacitor elements 321-2 and 322-2 corresponding to LCG are also the same. Furthermore, the combined capacitance value of capacitor elements 321-1 and 322-1 corresponding to HCG is greater than the combined capacitance value of capacitor elements 321-2 and 322-2 corresponding to LCG. When LCG is set, compared to when HCG is set, optical shot noise becomes dominant, and the kTC noise generated during sample-and-hold has little contribution to image quality. On the other hand, when HCG is set, the adverse effects caused by kTC noise are relatively greater. Also, generally, when sampling signals from capacitor elements, increasing their capacitance value can reduce kTC noise during sampling. Therefore, by setting the capacitance value of the capacitor element corresponding to HCG, which has a greater impact on kTC noise, relatively large, kTC noise can be suppressed and image quality improved.

[0239] After exposure, the back-end circuit 350 reads out the voltage (reset level and signal level) corresponding to HCG and the voltage corresponding to LCG sequentially through the back-end node 340.

[0240] The subsequent horizontal signal processing circuit 260 performs CDS processing to calculate the reset level corresponding to HCG and the difference between the signal level corresponding to HCG, generating a digital signal corresponding to HCG. Furthermore, the horizontal signal processing circuit 260 performs CDS processing to calculate the reset level corresponding to LCG and the difference between the signal level corresponding to LCG, generating a digital signal corresponding to LCG.

[0241] Furthermore, the horizontal signal processing circuit 260 determines whether the illuminance is higher than a specific value in frame units or pixel units. Moreover, when the illuminance is high, the horizontal signal processing circuit 260 outputs the digital signal corresponding to LCG as the pixel signal of that pixel, and when the illuminance is low, it outputs the digital signal corresponding to HCG as the pixel signal.

[0242] When switching conversion efficiency based on illumination at the frame level, insufficient saturation charge or sensitivity can be suppressed. This improves image quality. Furthermore, when switching conversion efficiency based on illumination at the pixel level, the dynamic range can be expanded. Also, since it is not necessary to capture two frames with conversion efficiencies varying depending on the frame, frame rate reduction can be suppressed. Therefore, when switching conversion efficiency at the pixel level, frame rate reduction can be suppressed, and image quality is improved.

[0243] Furthermore, during the exposure period, the vertical scanning circuit 211, via control signals sw and PC, only turns on the switching transistor 363 among the switching transistor 363 and the pre-charge transistor 364. Then, during the exposure period, the vertical scanning circuit 211, via control signals sw and PC, only turns on the pre-charge transistor 364. During readout, both the switching transistor 363 and the pre-charge transistor 364 are controlled to be off. This control suppresses the influence of noise generated in the current source transistor 316.

[0244] Alternatively, although a switching transistor 363 and a pre-charge transistor 364 are provided, the configuration may also be configured not to include them.

[0245] FIG40 is a top view showing an example of the component layout of the eighth embodiment of the present technology. As described above, for each pixel, a portion of the components within the pixel is disposed on the upper pixel chip 201, and the remaining portion is disposed on the lower pixel chip 202. For each pixel, the area where the upper components are disposed is designated as the upper pixel area 223, and the area where the lower components are disposed is designated as the lower pixel area 224.

[0246] Various transistors, such as photoelectric conversion element 311 and transmission transistor 312, are disposed in the upper pixel area 223. Furthermore, the switching transistor 363 is connected to the lower pixel area 224 via the output terminal 225.

[0247] Capacitor elements 321-1 and 322-1 corresponding to HCG and capacitor elements 321-2 and 322-2 corresponding to LCG are disposed in the lower pixel area 224. These capacitor elements have the same capacitance density, and the area of ​​capacitor elements 321-1 and 322-1 corresponding to HCG is larger than that of capacitor elements 321-2 and 322-2 corresponding to LCG. This increases the capacitance value of capacitor elements 321-1 and 322-1 corresponding to HCG.

[0248] Furthermore, hereafter, a specific axis parallel to the chip plane of the upper pixel chip 201 or the lower pixel chip 202 is designated as the "X-axis", and an axis perpendicular to the chip plane is designated as the "Z-axis". An axis perpendicular to both the X-axis and the Z-axis is designated as the "Y-axis".

[0249] As shown in Figures 39 and 40, the conversion efficiency is achieved by switching between two stages, but it can also be achieved by switching between three stages.

[0250] Figure 41 is a circuit diagram showing an example of a pixel configuration when switching conversion efficiency in three stages according to the eighth embodiment of the present technology. In this case, a conversion efficiency control transistor 362, capacitor elements 321-3 and 322-3, and selection transistors 331-3 and 332-3 are added. For example, an nMOS transistor is used as the conversion efficiency control transistor 362.

[0251] The conversion efficiency control transistor 362 is inserted between the FD reset transistor 313 and the conversion efficiency control transistor 361, and is switched on and off by the control signal fcg from the vertical scanning circuit 211.

[0252] One end of capacitor elements 321-3 and 322-3 is commonly connected to the front node 320. Selector transistor 331-3 opens and closes the path between capacitor element 321-3 and the rear node 340 based on the select signal ΦRL from the vertical scanning circuit 211. Selector transistor 332-3 opens and closes the path between capacitor element 322-3 and the rear node 340 based on the select signal ΦSL from the vertical scanning circuit 211. Furthermore, selector transistors 331-2 and 332-2 are opened and closed based on select signals ΦRM and ΦSM.

[0253] When only conversion efficiency control transistor 361 is in the ON state among conversion efficiency control transistors 361 and 362, the conversion efficiency is lower than when both conversion efficiency control transistors 361 and 362 are in the OFF state. Furthermore, when both conversion efficiency control transistors 361 and 362 are in the ON state, the conversion efficiency is lower than when only conversion efficiency control transistor 361 is in the ON state. Thus, conversion efficiency is controlled in three stages. The highest conversion efficiency among the three stages is defined as HCG, and the lowest conversion efficiency is defined as LCG. The conversion efficiency between HCG and LCG is called "MCG (Middle Conversion Gain)". By switching conversion efficiency in three stages, a more appropriate conversion efficiency can be achieved compared to switching in two stages.

[0254] The capacitance values ​​of capacitor elements 321-1 and 322-1 corresponding to HCG are greater than those of capacitor elements corresponding to MCG and LCG. Furthermore, the capacitance values ​​of capacitor elements 321-2 and 322-2 corresponding to MCG are the same as those of capacitor elements 321-3 and 322-3 corresponding to LCG. Additionally, capacitor elements 321-1 and 322-1 are examples of high-capacitance elements described in the claims. Capacitor elements 321-2, 322-2, 321-3, and 322-3 are examples of low-capacitance elements described in the claims.

[0255] Furthermore, although the conversion efficiency is set to 3 stages, it can also be set to 4 stages or more. When it is set to 4 stages or more, simply add conversion efficiency control transistors, capacitors, and select transistors according to the number of stages.

[0256] Figure 42 is a top view showing an example of the component layout when switching conversion efficiency in three stages in the eighth embodiment of the present technology. A conversion efficiency control transistor 362 is further arranged in the upper pixel area 223, and capacitor elements 321-3 and 322-3 are further arranged in the lower pixel area 224.

[0257] Furthermore, the area of ​​capacitor elements 321-1 and 322-1 corresponding to HCG is larger than that of capacitor elements corresponding to MCG and LCG.

[0258] Alternatively, each of the second to seventh embodiments can be applied to the eighth embodiment.

[0259] Thus, according to the eighth embodiment of this technology, since the conversion efficiency is switched in two stages, the image quality can be improved by switching the conversion efficiency according to the illuminance. Furthermore, since the capacitance values ​​of the capacitor elements 321-1 and 322-1 corresponding to HCG are made greater than those of the capacitor elements corresponding to MCG or LCG, kTC noise can be reduced, thereby further improving the image quality.

[0260] <9. Ninth Embodiment> In the above-described eighth embodiment, the areas of the capacitor elements 321-1 and 322-1 corresponding to the HCG are set to be relatively large, but it is preferable that the areas of each capacitor element are the same. The difference between the solid-state imaging element 200 of the ninth embodiment and the eighth embodiment is that the capacitance density of the capacitor elements 321-1 and 322-1 corresponding to the HCG is set to be relatively large.

[0261] Figure 43 is a top view showing an example of the component layout of the ninth embodiment of the present invention. In the ninth embodiment, the capacitance density of capacitor elements 321-1 and 322-1 corresponding to HCG is higher than the capacitance density of capacitor elements 321-2 and 322-2 corresponding to LCG. Furthermore, the areas of capacitor elements 321-1, 322-1, 321-2, and 322-2 are approximately the same.

[0262] By setting the capacitance density of the capacitor elements 321-1 and 322-1 corresponding to HCG to a relatively high level, the capacitance value of the capacitor elements 321-1 and 322-1 can be set to a relatively high level, and the area of ​​each capacitor element can be made consistent.

[0263] Alternatively, in the 9th embodiment, the conversion efficiency is set to 2 stages, but it can also be set to 3 stages or more.

[0264] Thus, according to the ninth embodiment of the present technology, by increasing the capacitance density of the capacitor elements 321-1 and 322-1 corresponding to HCG, the area of ​​each capacitor element can be made equal.

[0265] [Variation Example] In the 9th embodiment described above, the area of ​​the capacitor elements is made consistent by increasing the capacitance density of the capacitor elements 321-1 and 322-1 corresponding to the HCG. However, in this configuration, two types of elements with different capacitance densities need to be provided. The difference between the solid-state imaging element 200 in this variation of the 9th embodiment and the 9th embodiment is that an element in which a plurality of capacitor elements are connected in parallel is used as the capacitor element corresponding to the HCG.

[0266] Figure 44 is a circuit diagram showing a configuration example of one of the pixels 300 in a variation of the ninth embodiment of the present technology. In this variation of the ninth embodiment, capacitor elements 321-1a, 321-1b, 322-1a, and 322-1b are configured as capacitor elements corresponding to HCG. The capacitance values ​​of these capacitor elements are substantially the same as those of the capacitor elements corresponding to LCG.

[0267] Capacitor elements 321-1a and 321-1b are connected in parallel between the front node 320 and the select transistor 331-1. These capacitor elements can be treated as equivalent elements to capacitor element 321-1 in FIG. 39. Capacitor elements 322-1a and 322-1b are connected in parallel between the front node 320 and the select transistor 332-1. These capacitor elements can be treated as equivalent elements to capacitor element 322-1 in FIG. 39. Furthermore, although two capacitor elements are connected in parallel, three or more capacitor elements can also be connected in parallel.

[0268] Figure 45 is a top view showing an example of the component layout of a variation of the ninth embodiment of the present technology. As illustrated in the figure, capacitor elements 321-1a, 321-1b, 322-1a, and 322-1b are arranged as capacitor elements corresponding to HCG. The area and capacitance density of these capacitor elements are substantially the same as those of the capacitor elements corresponding to LCG.

[0269] Capacitor elements 321-1a and 321-1b are connected in parallel and are circuitally equivalent to capacitor element 321-1. Capacitor elements 322-1a and 322-1b are connected in parallel and are circuitally equivalent to capacitor element 322-1. Furthermore, capacitor elements 321-1a, 321-1b, 322-1a, and 322-1b are examples of the unit capacitor elements described in the claims.

[0270] By using capacitor elements 321-1a and 321-1b connected in parallel as capacitor element 321-1 corresponding to HCG, the area and capacitance density of each capacitor element can be made equal. Since this configuration can be designed with only a single MIM capacitor, it is also effective in promoting and reducing development costs.

[0271] In addition, in the variation of the 9th embodiment, the conversion efficiency is set to 2 stages, but it can also be set to 3 stages or more.

[0272] Thus, according to a variation of the ninth embodiment of the present technology, since a plurality of capacitor elements connected in parallel are used as capacitor elements 321-1 or 322-1 corresponding to HCG, the capacitance density and area of ​​each capacitor element can be made equal.

[0273] <10. Tenth Embodiment> In the eighth embodiment described above, in the multilayer structure, capacitor elements 321-1 and 322-1 corresponding to HCG and capacitor elements 321-2 and 322-2 corresponding to LCG are arranged on the lower wafer. In this configuration, it is preferable to arrange the elements in a manner that allows for a relatively long wiring distance between the capacitor elements corresponding to HCG. The difference between the solid-state imaging element 200 of the tenth embodiment and the eighth embodiment is that the layout of the capacitor elements is optimized.

[0274] Figure 46 is a top view showing an example of the component layout of the tenth embodiment of the present technology. Capacitor element 321-1 corresponding to HCG and capacitor element 321-2 corresponding to LCG are arranged in the X-axis direction. In this arrangement direction (i.e., the X-axis direction), the position of the output terminal 225 of the upper pixel area 223 is set to X2. The distance from the position X2 of the output terminal 225 on the X-axis to the connection terminal (not shown) of capacitor element 321-1 is longer than the distance to the connection terminal (not shown) of capacitor element 321-2. Also, the distance from position X2 to the connection terminal (not shown) of capacitor element 322-1 is longer than the distance to the connection terminal (not shown) of capacitor element 322-2.

[0275] Figure 47 is an example of a cross-sectional view of a solid-state imaging element 200 according to a tenth embodiment of the present technology. The figure shows a cross-sectional view viewed from the Y-axis direction. The upper pixel chip 201 includes a substrate 501. On the substrate 501, elements (not shown) from the photoelectric conversion element 311 in the front-end circuit 310 to the switching transistor 363 are formed. The output terminal 225 of the front-end circuit 310 is connected to the connection terminals 226 and 227 via wiring 510.

[0276] Furthermore, the lower pixel chip 202 includes a substrate 502 and a plurality of capacitor elements such as capacitor elements 321-1 and 321-2. One end of capacitor element 321-1 is connected to connection terminal 226, and one end of capacitor element 321-2 is connected to connection terminal 227. The distance on the X-axis from position X2 of output terminal 225 to position X1 of connection terminal 226 of capacitor element 321-1 corresponding to HCG is longer than the distance to position X2 of connection terminal 227 of capacitor element 321-2 corresponding to LCG.

[0277] By setting the distance to the capacitor element 321-1 corresponding to HCG to be relatively long, the wiring distance to the capacitor element 321-1 can be set to be relatively long. The longer the wiring distance, the larger the parasitic capacitance between the wirings. For example, a parasitic capacitance, represented by a dashed line, is generated between wiring 510 and the nearby wiring 511. This parasitic capacitance can increase the capacitance value on the HCG side, further suppressing kTC noise.

[0278] Furthermore, in the tenth embodiment, the conversion efficiency is set to two stages, but it may also be set to three or more stages. Also, the ninth embodiment or its variations may be applied to the tenth embodiment.

[0279] Thus, according to the 10th embodiment of this technology, since the distance from the output terminal 225 to the capacitor element 321-1 corresponding to HCG is set to be relatively long, the capacitance value on the HCG side can be increased to increase the amount of parasitic capacitance in the wiring.

[0280] <11. Eleventh Embodiment> In the tenth embodiment described above, the elements are disposed on a single substrate 501 in the upper pixel chip 201. However, in this configuration, it is difficult to increase the area of ​​the photoelectric conversion element 311 or the transistor. The difference between the solid-state imaging element 200 of the eleventh embodiment and the tenth embodiment is that the upper pixel chip 201 has a multilayer structure.

[0281] Figure 48 is a top view showing an example of the component layout of the 11th embodiment of the present technology. The difference between the solid-state imaging element 200 of the 11th embodiment and the 10th embodiment is that the upper pixel chip 201 includes stacked substrates 501-1 and 501-2. For each pixel, the components within the pixel are distributed on the uppermost substrate 501-1, the middle substrate 501-2, and the lower pixel chip 202. For each pixel, the area where the uppermost component is disposed is designated as the upper pixel area 223-1, and the area where the middle component is disposed is designated as the middle pixel area 223-2.

[0282] In the upper pixel area 223-1, a photoelectric conversion element 311, a transmission transistor 312, and an FD 314 are configured. In the middle pixel area 223-2, an FD reset transistor 313, a conversion efficiency control transistor 361, a front-end amplification transistor 315, and a switching transistor 363 are configured.

[0283] Figure 49 is an example of a cross-sectional view of a solid-state imaging element 200 according to a tenth embodiment of the present technology. As illustrated in the figure, substrates 501-1 and 501-2 are laminated in the upper pixel chip 201. Photoelectric conversion elements 311 (not shown) or transistors are dispersed on these substrates. In this way, compared with the case where the upper pixel chip 201 is not laminated, the area of ​​the photoelectric conversion elements 311 or transistors can be increased.

[0284] In addition, in the 11th embodiment, the conversion efficiency is set to two stages, but it may also be set to three or more stages. Furthermore, the 9th embodiment or its variations may also be applied to the 11th embodiment.

[0285] Thus, according to the 11th embodiment of the present technology, since the upper pixel chip 201 is configured as a multilayer structure, the area of ​​the photoelectric conversion element 311 or transistor can be increased.

[0286] <12. Twelfth Embodiment> In the eighth embodiment described above, the capacitance value of the sampling signal capacitor element in VD.GS is set to a different value on the HCG side and the LCG side. However, multiple additional capacitors with different capacitance values ​​can also be provided in the configuration other than VD.GS. The difference between the solid-state imaging element 200 of the 12th embodiment and the 8th embodiment is that multiple additional capacitors with different capacitance values ​​are provided.

[0287] Figure 50 is a circuit diagram showing an example of the configuration of a pixel 300 according to a 12th embodiment of the present technology. The pixel 300 of this 12th embodiment includes a photoelectric conversion element 311, a transmission transistor 312, an FD reset transistor 313, conversion efficiency control transistors 361 and 362, an FD 314, and an amplification transistor 367. Furthermore, the pixel 300 includes additional capacitors 365 and 366.

[0288] The connection configuration of the photoelectric conversion element 311, transmission transistor 312, FD reset transistor 313, conversion efficiency control transistor 361 and 362, and FD 314 in the 12th embodiment is the same as that in the 8th embodiment.

[0289] An additional capacitor 365 is inserted between the connection node of the conversion efficiency control transistors 361 and 362 and the power supply voltage VDD. An additional capacitor 366 is inserted between the connection node of the FD reset transistor 313 and the conversion efficiency control transistor 362 and the power supply voltage VDD. Furthermore, the amplifying transistor 367 outputs the amplified voltage to the vertical signal line 309.

[0290] With the circuit configuration described above, the conversion efficiency control transistor 361 opens and closes the path between FD314 and the additional capacitor 365. The conversion efficiency control transistor 362 opens and closes the path between the conversion efficiency control transistor 361 and the additional capacitor 366. When both conversion efficiency control transistors 361 and 362 are in the off state, the conversion efficiency is HCG; when only conversion efficiency control transistor 361 is in the on state, the conversion efficiency is MCG; when both conversion efficiency control transistors 361 and 362 are in the on state, the conversion efficiency is LCG.

[0291] Furthermore, the capacitance values ​​of the additional capacitors 365 and 366 are different. For example, in the case of LCG, the capacitance value of the additional capacitor 366 is greater than that of the additional capacitor 365. In addition, the additional capacitors 365 and 366 are examples of the first and second additional capacitors described in the claims.

[0292] Additionally, capacitors 365 and 366 are disposed on the lower pixel chip 202, and photoelectric conversion element 311 or transistor is disposed on the upper pixel chip 201. Alternatively, the solid-state imaging element 200 may not be configured as a multilayer structure, but each element may be disposed on a single semiconductor chip.

[0293] While a larger added capacitor can increase the saturation charge, random noise will also increase. Therefore, when the illuminance is lower than a specific threshold Th1, only the HCG of FD314 is set. Furthermore, when the illuminance is above the threshold Th1 but below the specific threshold Th2, the MCG of FD314 and the added capacitor 365 is set. Furthermore, when the illuminance is above the threshold Th2, the LCG of FD314, the added capacitor 365, and the added capacitor 366 is set. By setting a relatively large added capacitor value for the LCG, both the increase in saturation charge and the reduction in noise can be achieved simultaneously.

[0294] Figure 51 is a top view showing an example of the component layout of the 12th embodiment of the present technology. A photoelectric conversion element 311 and a transistor are disposed in the upper pixel region 223, and additional capacitors 365 and 366 are disposed in the lower pixel region 224. Furthermore, the additional capacitors 365 and 366 have the same capacitance density, but the area of ​​the additional capacitor 366 is larger than that of the additional capacitor 365.

[0295] Furthermore, although the conversion efficiency is set to three stages, it can also be set to four or more stages. When it is set to four or more stages, it is only necessary to add conversion efficiency control transistors and capacitors according to the number of stages. Also, the ninth embodiment with different capacitance density values ​​or variations thereof can be applied to the 12th embodiment.

[0296] Figure 52 is an example of a pixel potential diagram of the 12th embodiment of this technology. When the transmission transistor 312 is switched on, charge is transferred from the photoelectric conversion element 311 to the FD 314. The gray area in this figure represents the accumulated charge. When the conversion efficiency control transistor 361 is switched on, an additional capacitor 365 is connected. Furthermore, when the conversion efficiency control transistor 362 is switched on, an additional capacitor 366 is connected.

[0297] Thus, according to the 12th embodiment of the present technology, since the conversion efficiency control transistors 361 and 362 are connected to at least one of the additional capacitors 365 and 366 with different capacitance values, the saturation charge can be increased and the noise can be reduced simultaneously.

[0298] <13. Thirteenth Embodiment> In the above-described 12th embodiment, an additional capacitor is provided in a configuration other than VD.GS, but the additional capacitor may also be provided in VD.GS. The difference between the solid-state imaging element 200 of the 13th embodiment and the 12th embodiment is that an additional capacitor is provided in VD.GS.

[0299] FIG53 is a circuit diagram showing an example of the configuration of a pixel 300 in the 13th embodiment of the present technology. The pixel 300 in the 13th embodiment further includes an additional capacitor 365 in the circuit illustrated in FIG39.

[0300] An additional capacitor 365 is disposed on the lower pixel chip 202 and inserted between the connection node of the FD reset transistor 313 and the conversion efficiency control transistor 361 and the power supply voltage VDD. Alternatively, the solid-state imaging element 200 may not be configured as a multilayer structure, but each element may be disposed on a single semiconductor chip.

[0301] Figure 54 is a top view showing an example of the layout of the elements in the 13th embodiment of the present technology. As illustrated in the figure, an additional capacitor 365 is further configured in the lower pixel area 224.

[0302] Figure 55 is an example of a pixel potential diagram according to the 13th embodiment of this technology. When the transmission transistor 312 is switched on, charge is transferred from the photoelectric conversion element 311 to the FD 314. When the conversion efficiency control transistor 361 is switched on, an additional capacitor 365 is connected. By connecting the additional capacitor 365, the capacitance value when switching to LCG can be increased compared to the case where the additional capacitor 365 is not connected.

[0303] Furthermore, although the conversion efficiency is set to two stages, it can also be set to three or more stages. When it is set to three or more stages, it is only necessary to add conversion efficiency control transistors and capacitors according to the number of stages. Also, the 9th embodiment or its variations can be applied to the 13th embodiment. The 10th and 11th embodiments can also be applied to the 13th embodiment.

[0304] Thus, according to the 13th embodiment of this technology, since the conversion efficiency control transistor 361 is connected to an additional capacitor 365 when switching to LCG, the capacitance value when switching to LCG can be increased.

[0305] <14. 14th Embodiment> In the 13th embodiment described above, the photoelectric conversion element 311 is only connected to the transmission transistor 312. However, in this configuration, there is a risk that charge may overflow from the photoelectric conversion element 311 to the FD314 during sampling of the photoelectric conversion element 311 at the reset level corresponding to HCG. If the potential of the FD314 continues to change due to this overflow, the current that charges the corresponding capacitor element will flow, resulting in an IR drop of VDD or Vreg, which may sometimes cause changes in the pixel signal. The difference between the solid-state imaging element 200 of the 14th embodiment and the 13th embodiment is that it further includes a discharge transistor 317.

[0306] Figure 56 is a circuit diagram showing an example of the configuration of a pixel 300 according to a 14th embodiment of the present technology. The pixel 300 of this 14th embodiment differs from that of the 13th embodiment in that it further includes an exhaust transistor 317, a conversion efficiency control transistor 362, and a front-end reset transistor 323. These exhaust transistors 317, conversion efficiency control transistors 362, and front-end reset transistors 323 are disposed on the upper pixel chip 201. Alternatively, the solid-state imaging element 200 may not be configured as a multilayer structure, but rather each element may be disposed on a single semiconductor chip.

[0307] The conversion efficiency control transistor 362 is inserted between the additional capacitor 365 and the connection node between the FD reset transistor 313 and the conversion efficiency control transistor 361. The discharge transistor 317 is inserted between the additional capacitor 365 and the photoelectric conversion element 311. The front-end reset transistor 323 is inserted between the connection node between the front-end reset transistor 315 and the switching transistor 363 and the power supply voltage VDD.

[0308] Immediately following the sample hold for resetting the level, the vertical scanning circuit 211 controls the discharge transistor 317 to be in the ON state during the traversal pulse. This allows the charge overflowing from the photoelectric conversion element 311 after initialization to be discharged through the discharge transistor 317 to the path leading to the additional capacitor 365, thus suppressing potential fluctuations in FD314 caused by the overflowing charge.

[0309] The front-end reset transistor 323 is based on the front-end reset signal rsta, and during readout, it fixes the level of the front-end node 320 to the power supply voltage VDD.

[0310] Figure 57 is a top view showing an example of the layout of the elements in the 14th embodiment of the present technology. As illustrated in the figure, an exhaust transistor 317, a conversion efficiency control transistor 362, and a front-end reset transistor 323 are arranged in the upper pixel area 223.

[0311] Alternatively, as illustrated in Figures 58 and 59, an additional capacitor 365 may also be configured on the lower pixel chip 202.

[0312] Furthermore, although the conversion efficiency is set to 3 stages, it can also be set to 2 stages or more than 4 stages. Also, the 9th embodiment or its variations can be applied to the 14th embodiment. The 10th and 11th embodiments can also be applied to the 14th embodiment.

[0313] Thus, according to the 14th embodiment of the present technology, since the discharge transistor 317 discharges the charge overflowing from the photoelectric conversion element 311 to the path leading to the additional capacitor 365, the potential change of FD314 caused by the overflowing charge can be suppressed.

[0314] <15. 15th Embodiment> In the 14th embodiment described above, the capacitance value of the capacitor element corresponding to the HCG is set to be relatively large, and the vertical scanning circuit 211 maintains the voltage (reset level or signal level) on one capacitor element. However, in this configuration, the capacitance value of the capacitor element corresponding to the LCG becomes relatively small, which may not be sufficient to reduce noise. The difference between the solid-state imaging element 200 in the 15th embodiment and the 14th embodiment is that the capacitance value of each capacitor element is set to be the same, and the vertical scanning circuit 211 maintains the voltage on a plurality of capacitor elements.

[0315] FIG60 is a circuit diagram showing an example of the configuration of a pixel 300 according to a 15th embodiment of the present technology. The pixel 300 of the 15th embodiment includes a front-end circuit 310, a plurality of capacitor elements, a plurality of selection transistors, a rear-end reset transistor 341, and a rear-end circuit 350.

[0316] The circuit configuration of the front circuit 310 and the rear circuit 350 in the 15th embodiment is the same as that in the 14th embodiment.

[0317] Furthermore, the number of capacitor elements is four or more, for example, six capacitor elements 321-1 to 321-6 are configured. Also, the capacitance value of each capacitor element is the same. The number of selectable transistors is the same as the number of capacitor elements, for example, selectable transistors 331-1 to 331-6 are configured.

[0318] One end of each of the capacitor elements 321-1 to 321-6 is connected to the front node 320. The selection transistors 331-1 to 331-6 open or close the path between the other end of the capacitor elements 321-1 to 321-6 and the rear node 340 according to the selection signals Φ1 to Φ6 from the vertical scanning circuit 211.

[0319] Figure 61 is a diagram illustrating the driving method of pixel 300 in the 15th embodiment of the present technology. The solid-state imaging element 200 can use any of the driving methods in driving examples 1 to 4.

[0320] In driving examples 1 and 2, the vertical scanning circuit 211 controls the front-end circuit 310 to set any one of the multiple conversion efficiencies such as HCG, MCG, and LCG. Furthermore, in driving examples 1 and 2, the vertical scanning circuit 211 uses selection signals Φ1 to Φ6 to maintain the P phase level (reset level) on multiple capacitor elements and maintain the D phase level (signal level) on another multiple capacitor elements.

[0321] In driving example 1, the vertical scan circuit 211 maintains the reset level on 3 out of the 6 capacitor elements and maintains the signal level on the remaining 3. In driving example 2, the vertical scan circuit 211 maintains the reset level on 2 out of the 6 capacitor elements and maintains the signal level on the other 2. The voltage can be maintained on all capacitor elements as in driving example 1, or on a subset of capacitor elements as in driving example 2. In driving example 1, 4 or more capacitor elements are provided for each pixel; in driving example 2, 6 or more capacitor elements are provided.

[0322] In driving examples 3 and 4, the vertical scanning circuit 211 controls the front-end circuit 310 to sequentially set two of a plurality of conversion efficiencies such as HCG, MCG, and LCG. For example, HCG and LCG are set sequentially.

[0323] Furthermore, in driving example 3, the vertical scanning circuit 211 maintains the reset level and signal level generated by the higher conversion efficiency in a plurality of capacitor elements. Also, the vertical scanning circuit 211 maintains the reset level and signal level generated by the lower conversion efficiency in another plurality of capacitor elements. For example, capacitor elements 321-7 and 321-8 are added. Furthermore, the vertical scanning circuit 211 maintains the reset level corresponding to HCG in capacitor elements 321-1 and 321-2, and maintains the signal level corresponding to HCG in capacitor elements 321-3 and 321-4. Moreover, the vertical scanning circuit 211 maintains the reset level corresponding to LCG in capacitor elements 321-5 and 321-6, and maintains the signal level corresponding to LCG in capacitor elements 321-7 and 321-8.

[0324] Furthermore, in driving example 4, the vertical scanning circuit 211 maintains the reset level and signal level generated by higher conversion efficiency in a plurality of capacitor elements. Also, the vertical scanning circuit 211 maintains the reset level and signal level generated by lower conversion efficiency in a smaller number of capacitor elements. For example, the vertical scanning circuit 211 maintains the reset level corresponding to HCG in capacitor elements 321-1 and 321-2, and the signal level corresponding to HCG in capacitor elements 321-3 and 321-4. Furthermore, the vertical scanning circuit 211 maintains the reset level corresponding to LCG in capacitor element 321-5, and the signal level corresponding to LCG in capacitor element 321-6.

[0325] Furthermore, in driving example 3, eight or more capacitor elements are provided for each pixel, and in driving example 4, six or more capacitor elements are provided. Also, in driving examples 3 and 4, capacitor elements may be added further, and three or more conversion efficiencies may be set sequentially.

[0326] As illustrated in the figure, when using one or two of the three conversion efficiencies, the vertical scanning circuit 211 maintains the voltage across a plurality of capacitor elements, thereby suppressing noise compared to the case where it is maintained across one.

[0327] Figure 62 is a diagram showing an example of the pixel state during sampling and holding in the driving example 1 of the 15th embodiment of the present technology. HCG, MCG and LCG are set. As illustrated in Figure a, the vertical scanning circuit 211 only turns on the selection transistors 331-1 to 331-3, and keeps the reset level P_HCG corresponding to HCG at the capacitor elements 321-1 to 321-3. Also, as illustrated in Figure b, the vertical scanning circuit 211 only turns on the selection transistors 331-4 to 331-6, and keeps the signal level D_HCG corresponding to HCG at the capacitor elements 321-4 to 321-6.

[0328] Figure 63 is a diagram showing an example of the state of a pixel during sampling and holding in the driving example 2 of the 15th embodiment of the present technology. HCG, MCG, and LCG are set. As illustrated in Figure a, the vertical scanning circuit 211 only turns on the selection transistors 331-1 and 331-2, and holds the reset level P_HCG corresponding to HCG at capacitor elements 321-1 and 321-2. Also, as illustrated in Figure b, the vertical scanning circuit 211 only turns on the selection transistors 331-3 and 331-4, and holds the signal level D_HCG corresponding to HCG at capacitor elements 321-3 and 321-4.

[0329] Figure 64 is a diagram showing an example of the state of a pixel when sampling and holding a level corresponding to a higher conversion efficiency in the driving example 3 of the 15th embodiment of the present technology. HCG and LCG are set sequentially among HCG, MCG and LCG. As illustrated in Figure a, the vertical scanning circuit 211 only turns on the selection transistors 331-1 and 331-2, and keeps the reset level P_HCG corresponding to HCG at the capacitor elements 321-1 and 321-2. Also, as illustrated in Figure b, the vertical scanning circuit 211 only turns on the selection transistors 331-3 and 331-4, and keeps the signal level D_HCG corresponding to HCG at the capacitor elements 321-3 and 321-4.

[0330] Figure 65 is a diagram showing an example of the state of a pixel when sampling and holding a level corresponding to a lower conversion efficiency in the driving example 3 of the 15th embodiment of the present technology. As illustrated in Figure a, the vertical scanning circuit 211 only turns on the selection transistors 331-5 and 331-6, and holds the reset level P_HCG corresponding to LCG at the capacitor elements 321-5 and 321-6. Also, as illustrated in Figure b, the vertical scanning circuit 211 only turns on the selection transistors 331-7 and 331-8, and holds the signal level D_LCG corresponding to LCG at the capacitor elements 321-7 and 321-8.

[0331] Figure 66 is a diagram showing an example of the state of a pixel when sampling and holding a level corresponding to a higher conversion efficiency in the driving example 4 of the 15th embodiment of the present technology. HCG and LCG are set sequentially among HCG, MCG and LCG. As illustrated in Figure a, the vertical scanning circuit 211 only turns on the selection transistors 331-1 and 331-2, and keeps the reset level P_HCG corresponding to HCG at the capacitor elements 321-1 and 321-2. Also, as illustrated in Figure b, the vertical scanning circuit 211 only turns on the selection transistors 331-3 and 331-4, and keeps the signal level D_HCG corresponding to HCG at the capacitor elements 321-3 and 321-4.

[0332] Figure 67 is a diagram showing an example of the state of a pixel when sampling and holding a level corresponding to a lower conversion efficiency in the driving example 4 of the 15th embodiment of the present technology. As illustrated in Figure a, the vertical scanning circuit 211 only sets the selection transistor 331-5 to the on state, and keeps the reset level P_LCG corresponding to LCG at the capacitor element 321-5. Also, as illustrated in Figure b, the vertical scanning circuit 211 only sets the selection transistor 331-6 to the on state, and keeps the signal level D_LCG corresponding to LCG at the capacitor element 321-6.

[0333] Alternatively, the 15th embodiment can also be applied to each of the 8th to 13th embodiments.

[0334] Thus, according to the 15th embodiment of the present technology, the vertical scanning circuit 211 maintains the voltage across a plurality of capacitor elements, thereby suppressing noise compared to the case where it is maintained across only one.

[0335] [Variation Example] In the 15th embodiment described above, one end of the capacitor element 321-1, etc., is connected to the front node 320, and a selector transistor 331-1, etc., is inserted between the other end of the capacitor element 321-1 and the rear node 340. However, this circuit configuration is not limited as long as VD.GS can be implemented. The difference between the solid-state imaging element 200 in this variation of the 15th embodiment and the 15th embodiment is that the connection between the capacitor element 321-1, etc., and the selector transistor 331-1, etc., is different.

[0336] Figure 68 is a circuit diagram showing a configuration example of pixel 300 in a variation of the 15th embodiment of the present technology. In the pixel 300 of this variation of the 15th embodiment, the front node 320 of the front circuit 310 is connected to the rear node 340.

[0337] Furthermore, a selector transistor 331-1 is inserted between one end of capacitor element 321-1 and the front node 320, and a selector transistor 331-2 is inserted between one end of capacitor element 321-2 and the front node 320. A selector transistor 331-3 is inserted between one end of capacitor element 321-3 and the front node 320, and a selector transistor 331-4 is inserted between one end of capacitor element 321-4 and the front node 320. A selector transistor 331-5 is inserted between one end of capacitor element 321-5 and the front node 320, and a selector transistor 331-6 is inserted between one end of capacitor element 321-6 and the front node 320. The other end of each of capacitor elements 321-1 to 321-6 is connected to a ground terminal.

[0338] VD.GS can also be implemented using the circuit illustrated in the figure. Furthermore, the driving examples 1 to 4 illustrated in Figure 61 can be applied.

[0339] Thus, according to a variation of the 15th embodiment of this technology, since a selector transistor 331-1 is inserted between the front node 320 and one end of the capacitor element 321-1, and the other end of the capacitor element is grounded, VD.GS can be realized. Furthermore, driving examples 1 to 4 can be applied to this circuit.

[0340] <16. Sixteenth Embodiment> In the above-described 14th embodiment, the solid-state imaging element 200 expands the dynamic range by switching the conversion efficiency according to illumination in pixel units or frame units. However, the dynamic range can also be expanded by fixing the conversion efficiency and taking multiple frames during different exposure periods, and then combining them. In this case, it is preferable to improve the continuous shooting function. The difference between the solid-state imaging element 200 in the 16th embodiment and the 14th embodiment is that the continuous shooting function is improved by starting the exposure of the next frame immediately after the exposure of a certain frame ends, and performing readout during the exposure period.

[0341] Figure 69 is a timing diagram showing an example of the operation of the solid-state imaging element 200 according to the 16th embodiment of the present technology. In this 16th embodiment, the vertical scanning circuit 211 controls the front-end circuit 310 to fix the conversion efficiency to any one of HCG, MCG, and LCG, and performs multiple frame captures. With m set as an integer, the vertical scanning circuit 211 maintains the reset level and signal level of the 3mth frame at capacitor elements 321-1 and 321-2. Furthermore, the vertical scanning circuit 211 maintains the reset level and signal level of the (3m+1)th frame at capacitor elements 321-3 and 321-4. The vertical scanning circuit 211 maintains the reset level and signal level of the (3m+2)th frame at capacitor elements 321-5 and 32-6.

[0342] Furthermore, at least two of the frames in the 3m, (3m+1), and (3m+2) frames have different exposure periods. The subsequent circuitry (such as the line signal processing circuit 260) can combine these three frames to generate a composite frame that expands the dynamic range.

[0343] The vertical scanning circuit 211 drives all pixels and begins exposure of frame F0 at timing T0, and ends exposure of frame F0 at timing T1. A moment before timing T1, the vertical scanning circuit 211 generates a reset level and holds it at capacitor element 321-1. Furthermore, the vertical scanning circuit 211 generates a signal level at timing T1 and holds it at capacitor element 321-2. The sampling and holding period of this signal level ends at timing T2.

[0344] Furthermore, immediately after timing T2, the vertical scanning circuit 211 drives all pixels and begins the exposure of the next frame F1, and ends the exposure of frame F1 at timing T3. A moment before timing T3, the vertical scanning circuit 211 generates a reset level, holding it at capacitor element 321-3. Also, at timing T3, the vertical scanning circuit 211 generates a signal level, holding it at capacitor element 321-4. The sampling and holding period of this signal level ends at timing T4.

[0345] Next, immediately after timing T4, the vertical scanning circuit 211 drives all pixels and begins exposure of frame F2, and ends exposure of frame F2 at timing T6. A moment before timing T6, the vertical scanning circuit 211 generates a reset level and holds it at capacitor element 321-5. Also, at timing T6, the vertical scanning circuit 211 generates a signal level and holds it at capacitor element 321-6. The sampling and holding period for these reset and signal levels is included in the period from timing T5 to T7.

[0346] Furthermore, the downstream circuit 350 or the row signal processing circuit 260 may perform reset level or signal level readouts during the sample-and-hold period. For example, during the period from the end of the sample-and-hold period, timing T4, to the beginning of the next sample-and-hold period, timing T5, frame F0 is read out. If not all columns of frame F0 are read out during this period, the remaining columns of frame F0 are read out during the period from the end of the sample-and-hold period, timings T7 to T8.

[0347] Immediately after the readout of frame F0 is completed at timing T8, the vertical scan circuit 211 drives all pixels and begins the exposure of frame F3, ending the exposure of frame F3 at timing T10. A moment before timing T10, the vertical scan circuit 211 generates a reset level, holding it at capacitor element 321-1. Also, at timing T10, the vertical scan circuit 211 generates a signal level, holding it at capacitor element 321-2. The sampling and holding period for these reset and signal levels is included within the period from timing T9 to T11. Frame F1 is read out during the period from timing T8 to the start of the sampling and holding period at timing T9. If the readout of all columns of frame F1 is not completed during this period, the remaining columns of frame F1 are read out during the period from timing T11 to T12 at the end of the sampling and holding period. Frames F2 and F3 are also read out outside the sampling and holding period. The same control is performed after the next frame following frame F3.

[0348] As illustrated in the figure, the vertical scanning circuit 211 has a fixed conversion efficiency and maintains a different frame level for each capacitor pair (321-1 and 321-2, etc.). In this way, the exposure of the next frame can begin immediately after the exposure of a certain frame ends. This enables high-speed continuous shooting with almost no gap between frames.

[0349] Furthermore, by linearly performing readout during the exposure period while avoiding the sample-and-hold period, the time from the end of high-speed continuous shooting from frame F0 to F2 until the start of the exposure of the next frame F3 can be shortened. In this figure, the readout of frame F0 is performed during the exposure period of frame F2, thereby shortening the time until the start of the exposure of frame F3 compared to the case where the readout begins after the exposure of frame F2 ends. Also, in this figure, since the exposure period of frame F1 is relatively short, the line signal processing circuit 260 does not perform readout during this exposure period, but if the exposure period of frame F1 is sufficiently long, readout can also be performed during this exposure period.

[0350] Figure 70 is a timing diagram showing an example of the first and second exposure control of the 16th embodiment of the present technology. At timing T0, the vertical scanning circuit 211 sets the discharge signal ofg of all pixels to a low level and begins the exposure of frame F0. Furthermore, during the traversal pulse period from timing T1, the vertical scanning circuit 211 supplies a high-level transmission signal trg to all pixels, ending the exposure of frame F0.

[0351] Furthermore, during the sampling and holding period from timing T21 to T22, which precedes timing T1, the vertical scanning circuit 211 supplies a high-level selection signal Φ1 to all pixels to maintain the reset level. Also, during the sampling and holding period from timing T23 to T2, which immediately follows timing T1, the vertical scanning circuit 211 supplies a high-level selection signal Φ2 to all pixels to maintain the signal level.

[0352] Furthermore, at timing T2, the vertical scanning circuit 211 restores the exit signal ofg of all pixels to a high level, and immediately thereafter at timing T24 sets the exit signal ofg of all pixels to a low level to begin exposure of frame F1. Also, during the traversal pulse period from timing T3, the vertical scanning circuit 211 supplies a high-level transmission signal trg to all pixels, ending the exposure of frame F1.

[0353] Furthermore, during the sampling and holding period from timing T25 to T26, immediately before timing T3, the vertical scanning circuit 211 supplies a high-level selection signal Φ3 to all pixels to maintain the reset level. Immediately following timing T3, during the sampling and holding period from timing T27 to T4, the vertical scanning circuit 211 supplies a high-level selection signal Φ4 to all pixels to maintain the signal level. Readout is performed outside these sampling and holding periods. The period from timing T26 to T27 is not a sampling and holding period, but because this period is very short, readout is not performed; instead, readout is performed after timing T4. Furthermore, at timing T4, the vertical scanning circuit 211 restores the output signal ofg of all pixels to a high level.

[0354] Additionally, the solid-state imaging element can capture 3 frames in a burst, but it can also capture 4 or more frames in a burst. Each time the number of frames in a burst is increased by 1, 2 capacitor elements are added within the pixel.

[0355] Figure 71 is a timing diagram showing an example of the third exposure control in the 16th embodiment of the present technology. Immediately after the end of the sample-and-hold period, the vertical scan circuit 211 sets the discharge signal ofg of all pixels to a low level at timing T41, thus starting the exposure of frame F2. Furthermore, during the traversal pulse period from timing T6, the vertical scan circuit 211 supplies a high-level transmission signal trg to all pixels, ending the exposure of frame F2.

[0356] Furthermore, during the sampling and holding period from timing T5 to T42, immediately preceding timing T6, the vertical scanning circuit 211 supplies a high-level selection signal Φ5 to all pixels to maintain the reset level. Also, immediately following timing T6, during the sampling and holding period from timing T43 to T7, the vertical scanning circuit 211 supplies a high-level selection signal Φ6 to all pixels to maintain the signal level. Readout is performed during the period from timing T5 to T7, which includes these sampling and holding periods.

[0357] Figure 72 is a timing diagram showing an example of the readout operation of the first frame in the 16th embodiment of the present technology. During the exposure period of frame F2, frame F0 is read out by traversing the period from the end of the sample-and-hold period timing T4 to the start of the next sample-and-hold period timing T5. During this readout period, the vertical scan circuit 211 drives the columns sequentially. Rn in this figure represents the readout period of the nth column.

[0358] During the readout period of the nth column during traversal timings T51 to T56, the vertical scan circuit 211 supplies a high-level post-stage selection signal selb to the nth column. Furthermore, during the traversal pulse period from timing T52, the vertical scan circuit 211 supplies a high-level post-stage reset signal rstb to the nth column, and during a specific traversal period from timing T53, supplies a high-level selection signal Φ1 to the nth column. In this way, the reset level of the nth column is read out.

[0359] Furthermore, during the pulse traversal period from timing T54, the vertical scanning circuit 211 supplies a high-level reset signal rstb to the nth column, and during the specific period traversed from timing T55, supplies a high-level selection signal Φ2 to the nth column. In this way, the signal level of the nth column is read out.

[0360] Figure 73 is a timing diagram showing an example of the readout operation in the second frame of the 16th embodiment of this technology. During the period from timing T8 to timing T9, which marks the beginning of the sampling and holding period, the readout frame F1 is generated.

[0361] During the readout period of the nth column traversing timings T61 to T66, the vertical scan circuit 211 supplies a high-level post-stage selection signal selb to the nth column. Furthermore, during the traversal pulse period from timing T62, the vertical scan circuit 211 supplies a high-level post-stage reset signal rstb to the nth column, and during a specific traversal period from timing T63, supplies a high-level selection signal Φ3 to the nth column. In this way, the reset level of the nth column is read out.

[0362] Furthermore, during the pulse traversal period from timing T64, the vertical scanning circuit 211 supplies a high-level reset signal rstb to the nth column, and during a specific period traversed from timing T65, supplies a high-level selection signal Φ4 to the nth column. In this way, the signal level of the nth column is read out.

[0363] Alternatively, the 16th embodiment can be applied to each of the 8th to 13th embodiments. Also, variations of the 15th embodiment can be applied to the 16th embodiment.

[0364] Thus, according to the 16th embodiment of this technology, the exposure of the next frame begins immediately after the exposure of a certain frame ends, and readout is performed during the exposure period while avoiding the sample hold period, thereby improving the continuous shooting function.

[0365] [First Variation] In the above-described 16th embodiment, six capacitive elements are used to continuously capture three frames, but the number of consecutive shots is not limited to three. The difference between the solid-state imaging element 200 in the first variation of the 16th embodiment and the first embodiment is that the number of consecutive shots is two.

[0366] Figure 74 is a timing diagram showing an example of the operation of the solid-state imaging element 200 in the first variation of the 16th embodiment of the present technology. The control up to the end of the sampling and holding period of the signal frame F1 in the first variation of the 16th embodiment is the same as that in the 16th embodiment.

[0367] Furthermore, in the first variation of the 16th embodiment, the vertical scanning circuit 211 drives all pixels to begin exposure of frame F2 at timing T5 after timing T4, and ends exposure of frame F2 at timing T8. Immediately after timing T8, the vertical scanning circuit 211 drives all pixels to begin exposure of frame F3, and ends exposure of frame F3 at timing T11.

[0368] Furthermore, during the period from the end of the sampling hold period (time T4) to the beginning of the next sampling hold period (time T7), frame F0 is read out. During the period from the end of the sampling hold period (time T9) to the beginning of the next sampling hold period (time T10), frame F1 is read out. If the reading of all columns of frame F1 is not completed during this period, then during the period from the end of the sampling hold period (time T12) to time T13, the remaining columns of frame F1 are read out.

[0369] When there are 6 capacitor elements, as in the 16th embodiment, a 3-shot burst can be performed, but it can also be set to a 2-shot burst as illustrated in the first variation of the 16th embodiment. In this way, since the readout of frame F0 is not interrupted, the time until the exposure of frame F3 begins can be further shortened. Furthermore, in this figure, frame F2 is shot after the 2-shot burst, but it can also be configured so that the shooting of this frame is not performed. When frame F2 is not shot, the number of capacitor elements can remain unchanged at 6, or it can be reduced by 2.

[0370] Thus, according to the first variation of the 16th embodiment of this technology, since the number of shots is set to 2, the time from the end of the exposure of frame F2 to the start of the exposure of frame F3 can be further shortened.

[0371] [Second Variation] In the 16th embodiment described above, the reset level and signal level are maintained at the capacitor element for each frame. However, in this configuration, two capacitor elements are required within a pixel for each frame, and the number of consecutive shots is limited to half the number of capacitor elements. For example, when there are six capacitor elements within a pixel, the number of consecutive shots is limited to three. The difference between the solid-state imaging element 200 in this second variation of the 16th embodiment and the 16th embodiment is that the number of consecutive shots is increased by maintaining only the signal level after the second frame.

[0372] Figure 75 is a timing diagram showing an example of the operation of the solid-state imaging element 200 in the second variation of the 16th embodiment of the present technology. The vertical scanning circuit 211 drives all pixels at timing T0 to begin exposure of frame F0, and ends exposure of frame F0 at timing T1. The vertical scanning circuit 211 generates a reset level one moment before timing T1, maintaining it at capacitor element 321-1. Furthermore, the vertical scanning circuit 211 generates a signal level at timing T1, maintaining it at capacitor element 321-2.

[0373] Furthermore, the vertical scanning circuit 211 drives all pixels immediately after timing T1 to begin exposure of frame F1, and ends exposure of frame F1 at timing T2. The vertical scanning circuit 211 generates a signal level at timing T2 and maintains it at capacitor elements 321-3. On the other hand, it does not maintain the reset level of frame F1.

[0374] Immediately following timing T2, the vertical scanning circuit 211 drives all pixels to begin exposure of frame F2, and ends exposure of frame F2 at timing T3. At timing T3, the vertical scanning circuit 211 generates a signal level and holds it at capacitor element 321-4. Also, immediately following timing T3, the vertical scanning circuit 211 drives all pixels to begin exposure of frame F3, and ends exposure of frame F3 at timing T4. At timing T4, the vertical scanning circuit 211 generates a signal level and holds it at capacitor element 321-5. Furthermore, immediately following timing T4, the vertical scanning circuit 211 drives all pixels to begin exposure of frame F4, and ends exposure of frame F4 at timing T5. At timing T5, the vertical scanning circuit 211 generates a signal level and holds it at capacitor element 321-6. On the other hand, the reset level for frames F2 to F4 is not maintained.

[0375] Furthermore, after timing T6 at the end of the sampling hold period, the reset level and signal level of frame F0, and the signal levels of frames F2 to F4 are read out sequentially. In addition, the exposure periods of at least two of the five frames are different.

[0376] As illustrated in the figure, by maintaining only the signal level after frame F1, the number of shots in a burst can be increased to 5. The number of shots in a burst is not limited to 5; it can also be set to 2 to 4. In this case, as in the first variation of embodiment 16, shots can be taken after the 3rd shot, or no shots can be taken. Furthermore, when the number of shots in a burst is set to 2 to 4, the number of capacitors can remain unchanged at 6, or the required number of shots in a burst can be reduced. Also, shots of 6 or more can be taken in a burst; in this case, one capacitor is added each time the number of shots in a burst is increased by 1.

[0377] Figure 76 is a timing diagram showing an example of exposure control in the second variation of the 16th embodiment of the present technology. In the second variation of the 16th embodiment, at the moment before the end of exposure of frame F1 at timing T2, no high-level selection signal is supplied, and the reset level is not maintained. Furthermore, during the sampling and holding period from timing T27 to T3 immediately following timing T2, the vertical scanning circuit 211 supplies a high-level selection signal Φ3 to all pixels to maintain the signal level. Similarly, only the signal level is maintained after frame F2.

[0378] Figure 77 is a timing diagram showing an example of the readout operation of the second variation of the 16th embodiment of the present technology. During the period from timing T6 to timing T7 after the end of the sampling and holding period, the reset level and signal level of the readout frame F0 are read out. During the readout period of the nth column in timings T71 to T72, the vertical scan circuit 211 supplies a high-level selection signal Φ1 to the nth column, followed by a high-level selection signal Φ2. This reads out the reset level and signal level of the nth column.

[0379] During the traversal of timings T7 to T8, the signal level of frame F1 is read out. During the readout period of the nth column in timings T73 to T74, the vertical scan circuit 211 traverses a specific period to supply a high-level selection signal Φ3 to the nth column. This allows the signal level of the nth column to be read out. Then, using the same control, the signal levels of frames F2 to F4 are read out sequentially via selection signals Φ4, Φ5, and Φ6.

[0380] The line signal processing circuit 260 holds the reset level of frame F0 in advance, performs CDS processing to calculate the difference between the signal level and the reset level of each frame from F0 to F4, and generates 5 frames.

[0381] Thus, according to the second variation of the 16th embodiment of this technology, since the vertical scanning circuit 211 only maintains the signal level after the second frame, the number of consecutive shots can be increased.

[0382] <17. Application Examples to Mobile Bodies> The technology disclosed herein (the technology) can be applied to various products. For example, the technology disclosed herein can be implemented as a device mounted on any type of mobile body such as automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobility vehicles, airplanes, drones, ships, and robots.

[0383] Figure 78 is a block diagram showing a schematic configuration example of a mobile body control system to which the technology disclosed herein can be applied, namely a vehicle control system.

[0384] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG78, the vehicle control system 12000 includes a drive system control unit 12010, a vehicle body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, the integrated control unit 12050 is shown to have the following functional components: a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0385] The drive system control unit 12010 controls the operation of devices associated with the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a drive force generating device such as an internal combustion engine or drive motor for generating drive force for the vehicle, a drive force transmission mechanism for transmitting drive force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, and a braking device for generating braking force for the vehicle.

[0386] The vehicle system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs. For example, the vehicle system control unit 12020 functions as a control device for keyless start systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, or fog lights. In this case, radio waves or various switch signals emitted by a portable device that replaces the key can be input to the vehicle system control unit 12020. The vehicle system control unit 12020 accepts such radio wave or signal inputs and controls the vehicle's door lock devices, power window devices, lights, etc.

[0387] The exterior information detection unit 12030 detects information about the exterior of the vehicle equipped with the vehicle control system 12000. For example, a camera unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform object detection processing or distance detection processing, such as detection of people, vehicles, obstacles, signs, or text on the road surface.

[0388] The camera unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output the electrical signal as an image or as distance measurement information. Furthermore, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0389] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver status detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, and can also determine whether the driver is dozing off.

[0390] The microcomputer 12051 can calculate the control target values ​​of the drive force generating device, steering mechanism, or braking device based on the information obtained from the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control for the purpose of realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on inter-vehicle distance, vehicle speed maintenance, vehicle collision warning, or vehicle lane departure warning.

[0391] Furthermore, the microcomputer 12051 can control the drive force generating device, steering mechanism or braking device, etc., based on the information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040. In this way, coordinated control can be performed for the purpose of autonomous driving, which is not based on the driver's operation.

[0392] Furthermore, the microcomputer 12051 can output control commands to the vehicle system control unit 12020 based on the external information obtained by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of the vehicle in front or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control such as switching the high beam to the low beam to achieve the purpose of anti-glare.

[0393] The audio-visual output unit 12052 transmits an output signal of at least one of sound and image to an output device that can provide visual or auditory notification information to the occupants of the vehicle or to the outside of the vehicle. In the example of FIG78, an amplifier 12061, a display unit 12062, and an instrument panel 12063 are shown as output devices. The display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0394] Figure 79 is an example of the installation position of the camera unit 12031.

[0395] As shown in Figure 79, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104, and 12105.

[0396] Cameras 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front bumper, side mirrors, rear bumper, tailgate, and above the windshield inside the vehicle 12100. The camera 12101 mounted on the front bumper and the camera 12105 mounted above the windshield inside the vehicle primarily acquire images of the area in front of the vehicle 12100. The cameras 12102 and 12103 mounted on the side mirrors primarily acquire images of the side of the vehicle 12100. The camera 12104 mounted on the rear bumper or tailgate primarily acquires images of the area behind the vehicle 12100. The camera 12105 mounted above the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lane markings ahead.

[0397] Additionally, Figure 79 shows an example of the imaging range of camera units 12101 to 12104. Camera range 12111 shows the imaging range of camera unit 12101 installed on the front bumper; camera ranges 12112 and 12113 show the imaging ranges of camera units 12102 and 12103 installed on the side mirrors, respectively; and camera range 12114 shows the imaging range of camera unit 12104 installed on the rear bumper or tailgate. For example, by overlaying the image data captured by camera units 12101 to 12104, a top-down image of the vehicle 12100 can be obtained.

[0398] At least one of the camera units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera containing a plurality of camera elements, or a camera element having pixels for phase difference detection.

[0399] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12051 calculates the distances between itself and various three-dimensional objects within the camera range 12111 to 12114, and the temporal changes in those distances (relative speed to vehicle 12100). This allows it to identify, in particular, the nearest three-dimensional object on the path of vehicle 12100, and the three-dimensional object traveling in approximately the same direction as vehicle 12100 at a specific speed (e.g., 0 km / h or higher), as the vehicle ahead. Furthermore, microcomputer 12051 can set a pre-defined distance to ensure proximity to the vehicle ahead, and perform automatic braking control (including follow-stop control) or automatic acceleration control (including follow-start control), etc. Thus, coordinated control can be performed for purposes such as autonomous driving without driver input.

[0400] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12051 can classify three-dimensional object data related to three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and capture them for automatic obstacle avoidance. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles visible to the driver of vehicle 12100 and obstacles that are difficult to see. Furthermore, microcomputer 12051 determines the collision risk of colliding with each obstacle. When the collision risk is above a set value and there is a possibility of collision, it outputs an alarm to the driver via loudspeaker 12061 or display unit 12062, or performs forced deceleration or evasive steering via drive system control unit 12010, thereby providing driving support for collision avoidance.

[0401] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 may identify a pedestrian by determining whether a pedestrian exists in the image captured by the camera units 12101 to 12104. The pedestrian identification is performed, for example, by the following sequence: capturing feature points of the image captured by the camera units 12101 to 12104, which are infrared cameras; performing pattern matching processing on a series of feature points of the outline of the displayed object and determining whether it is a pedestrian. If the microcomputer 12051 determines that a pedestrian exists in the image captured by the camera units 12101 to 12104 and identifies the pedestrian, the audio-visual output unit 12052 controls the display unit 12062 to overlay a square outline for emphasis on the identified pedestrian. Furthermore, the audio-visual output unit 12052 can also control the display unit 12062 to display pedestrian icons or the like at desired locations.

[0402] The above has described an example of a vehicle control system to which the technology disclosed herein can be applied. The technology disclosed herein can be applied to the camera unit 12031 in the configuration described above. Specifically, for example, the camera device 100 of FIG1 can be applied to the camera unit 12031. By applying the technology disclosed herein to the camera unit 12301, kTC noise can be reduced, and a more easily observable photographic image can be obtained, thereby reducing driver fatigue.

[0403] Furthermore, the above-described embodiments are examples used to embody the present technology, and the matters in the embodiments correspond to the specific matters of the invention within the scope of the patent application. Similarly, the specific matters of the invention within the scope of the patent application correspond to the matters in the embodiments of the present technology bearing the same name. However, the present technology is not limited to the embodiments, and can be embodied by implementing various changes to the embodiments without departing from its main purpose.

[0404] In addition, the effects described in this instruction manual are for illustrative purposes only and are not limited thereto; other effects may also be described.

[0405] Alternatively, this technology can also be configured as follows. (1) A solid-state imaging element comprising: a front-end circuit that converts charge into voltage and outputs it to a front-end node by means of a plurality of conversion efficiencies; a plurality of capacitor elements, one end of which is commonly connected to the front-end node; a selection circuit that connects the other end of any of the plurality of capacitor elements to a back-end node; and a back-end circuit that reads the voltage through the back-end node. (2) The solid-state imaging element as described in (1) above, wherein the plurality of capacitor elements comprises: a high-capacitance element having a capacitance value higher than a specific value; and a low-capacitance element having a capacitance value lower than the specific value; and the high-capacitance element maintaining the voltage generated by means of the highest high conversion efficiency among the plurality of conversion efficiencies; and the low-capacitance element maintaining the voltage generated by means of a conversion efficiency lower than the high conversion efficiency among the plurality of conversion efficiencies. (3) The solid-state imaging element as described in (2) above, wherein the area of ​​the high-capacitance element is larger than that of the low-capacitance element. (4) The solid-state imaging element as described in (2) above, wherein the capacitance density of the high-capacitance element is higher than that of the low-capacitance element. (5) The solid-state imaging element as described in (2) above, wherein the high-capacitance element comprises a plurality of unit capacitor elements connected in parallel. (6) The solid-state imaging element as described in any one of (2) to (5) above, wherein the front-end circuit, the selection circuit, and the back-end circuit are disposed on a first wafer; and the plurality of capacitor elements are disposed on a second wafer. (7) The solid-state imaging element as described in (6) above, wherein the distance from the output terminal of the front-end circuit to the high-capacitance element is longer than the distance from the output terminal to the low-capacitance element. (8) The solid-state imaging element as described in technical solution 6, wherein the first wafer comprises a plurality of stacked substrates. (9) A solid-state imaging element as described in any one of (6) to (8) above, wherein the front-end circuit comprises: a photoelectric conversion element; a front-end transmission transistor that transmits the charge from the photoelectric conversion element to the floating diffusion layer; a first reset transistor that initializes the floating diffusion layer; a front-end amplification transistor that amplifies the voltage and outputs it to the front-end node; and a specific number of conversion efficiency control transistors that control the conversion efficiency. (10) A solid-state imaging element as described in (9) above, wherein the front-end circuit further comprises an additional capacitor; the conversion efficiency control transistor is inserted between the floating diffusion layer and the additional capacitor; the additional capacitor is disposed on the second chip.(11) The solid-state imaging element as described in (9) above, wherein the front-end circuit further comprises: an additional capacitor; and a discharge transistor that discharges the charge from the photoelectric conversion element; and the specific number of conversion efficiency control transistors includes a first and a second conversion efficiency control transistor connected in series between the floating diffusion layer and the additional capacitor; the additional capacitor is disposed on either the first or the second wafer. (12) The solid-state imaging element as described in any one of (9) to (11) above, further comprises: a switching unit that adjusts the source voltage supplied to the source of the front-end amplification transistor; and the front-end circuit further comprises a current source transistor that supplies current to the drain of the front-end amplification transistor; the current source transistor moves from an on state to an off state after the exposure period ends. (13) In the solid-state imaging element described in (12) above, the switching unit supplies a specific power supply voltage as the source voltage during the exposure period, and supplies a generation voltage different from the power supply voltage as the source voltage after the exposure period ends. (14) In the solid-state imaging element described in (9) above, it further includes: a control circuit that controls the reset power supply voltage of the front-end circuit; and the first reset transistor initializes the voltage of the floating diffusion layer to the reset power supply voltage; and the control circuit sets the reset power supply voltage to a voltage different from the exposure period during the readout period of the voltage. (15) The solid-state imaging element as described in (1) above further comprises: a digital signal processing unit that adds a pair of consecutive frames; and the plurality of capacitor elements includes a first capacitor element and a second capacitor element; the voltage includes a reset level and a signal level; the front-end circuit maintains the reset level at one of the first and second capacitor elements during the exposure period of one of the pair of frames, and then maintains the signal level at the other of the first and second capacitor elements, and maintains the reset level at the other of the first and second capacitor elements during the exposure period of the other pair of frames, and then maintains the signal level at one of the first and second capacitor elements. (16) The solid-state imaging element as described in any one of (1) to (15) above further comprises: an analog-to-digital converter that converts the output voltage into a digital signal. (17) The solid-state imaging element as described in (16) above, wherein the analog-to-digital converter comprises: a comparator that compares the level of the vertical signal line transmitting the voltage with a specific ramp signal and outputs a comparison result; and a counter that counts a count value during the period of traversal until the comparison result is reversed and outputs the digital signal representing the count value.(18) The solid-state imaging element described in (17) above, wherein the comparator comprises: a comparator that compares the levels of each of a pair of input terminals and outputs a comparison result; and an input-side selector that selects either the node of the vertical signal line and the node of the specific reference voltage and connects it to one of the pair of input terminals; and inputs the ramp signal to one of the pair of input terminals. (19) The solid-state imaging element described in (18) above further comprises: a control unit that determines whether the illuminance is higher than a specific value based on the comparison result and outputs a determination result; a CDS (Correlated Double Sampling) processing unit that performs correlated double sampling processing on the digital signal; and an output-side selector that outputs either the digital signal after performing the correlated double sampling processing or the digital signal of the specific value based on the determination result. (20) The solid-state imaging element described in (1) above further comprises: a vertical scanning circuit that controls the front-end circuit to set the conversion efficiency; and the capacitance values ​​of each of the plurality of capacitor elements are the same; the voltage includes a reset level and a signal level corresponding to the exposure. (21) The solid-state imaging element described in (20) above, wherein the vertical scanning circuit sets any one of the plurality of conversion efficiencies, holds the reset level at half of the plurality of capacitor elements, and holds the signal level at the remaining half of the plurality of capacitor elements. (22) The solid-state imaging element described in (20) above, wherein the plurality of capacitor elements includes a plurality of first capacitor elements, a plurality of second capacitor elements, and a plurality of third capacitor elements; the vertical scanning circuit sets any one of the plurality of conversion efficiencies, holds the reset level at half of the plurality of first capacitor elements, and holds the signal level at the plurality of second capacitor elements. (23) The solid-state imaging element as described in (20) above, wherein the plurality of capacitor elements includes a plurality of first capacitor elements, a plurality of second capacitor elements, a plurality of third capacitor elements and a plurality of fourth capacitor elements; the vertical scanning circuit sequentially sets two of the plurality of conversion efficiencies, such that the reset level generated by the higher of the two conversion efficiencies is maintained at the plurality of first capacitor elements, the signal level generated by the higher of the two conversion efficiencies is maintained at the plurality of second capacitor elements, the reset level generated by the lower of the two conversion efficiencies is maintained at the plurality of third capacitor elements, and the signal level generated by the lower of the two conversion efficiencies is maintained at the plurality of fourth capacitor elements.(24) The solid-state imaging element as described in (20) above, wherein the plurality of capacitor elements includes a plurality of first capacitor elements, a plurality of second capacitor elements, a specific number of third capacitor elements less than the first capacitor elements, and the specific number of fourth capacitor elements; The vertical scanning circuit sequentially sets two of the plurality of conversion efficiencies, such that the reset level generated by the higher of the two conversion efficiencies is maintained at the plurality of first capacitor elements, the signal level generated by the higher of the two conversion efficiencies is maintained at the plurality of second capacitor elements, the reset level generated by the lower of the two conversion efficiencies is maintained at the specific number of third capacitor elements, and the signal level generated by the lower of the two conversion efficiencies is maintained at the specific number of fourth capacitor elements. (25) The solid-state imaging element as described in (1) above, wherein the voltage comprises: a first reset level generated at the moment before the end of the first exposure period, a first signal level generated at the end of the first exposure period, a second reset level generated at the moment before the end of the second exposure period, and a second signal level generated at the end of the second exposure period; the plurality of capacitor elements comprises a first capacitor element holding the first reset level, a second capacitor element holding the first signal level, a third capacitor element holding the second reset level, and a fourth capacitor element holding the second signal level; the second exposure period begins immediately after the end of the first exposure period; the downstream circuitry reads out the voltage while avoiding the sampling and holding period of the voltage. (26) The solid-state imaging element as described in (25) above, wherein the voltage further includes a third reset level generated just before the end of the third exposure period and a third signal level generated at the end of the third exposure period; the plurality of capacitor elements further includes a fifth capacitor element holding the third reset level and a sixth capacitor element holding the third signal level; the third exposure period begins immediately after the end of the second exposure period. (27) The solid-state imaging element as described in (1) above, wherein the voltage includes: a first reset level generated moment before the end of the first exposure period, a first signal level generated at the end of the first exposure period, and a second signal level generated at the end of the second exposure period; the plurality of capacitor elements includes a first capacitor element holding the first reset level, a second capacitor element holding the first signal level, and a third capacitor element holding the second signal level; the second exposure period begins immediately after the end of the first exposure period; the downstream circuitry reads out the voltage while avoiding the sampling and holding period of the voltage.(28) A solid-state imaging element comprising: a photoelectric conversion element; a first additional capacitor; a second additional capacitor having a capacitance value different from that of the first additional capacitor; a transmission transistor that transmits charge from the photoelectric conversion element to a floating diffusion layer; a first conversion efficiency control transistor that opens and closes the path between the floating diffusion layer and the first additional capacitor; and a second conversion efficiency control transistor that opens and closes the path between the connection node of the first conversion efficiency control transistor and the first additional capacitor and the second additional capacitor. [Simplified Explanation of the Diagram]

[0035] Figure 1 is a block diagram showing an example of the configuration of an imaging device according to the first embodiment of the present technology. Figure 2 is a block diagram showing an example of the configuration of a solid-state imaging element according to the first embodiment of the present technology. Figure 3 is a circuit diagram showing an example of the configuration of a pixel according to the first embodiment of the present technology. Figure 4 is a block diagram showing an example of the configuration of a horizontal signal processing circuit and a load MOS circuit block according to the first embodiment of the present technology. Figure 5 is a timing diagram showing an example of a global shutter operation according to the first embodiment of the present technology. Figure 6 is a timing diagram showing an example of a readout operation according to the first embodiment of the present technology. Figure 7 is a timing diagram showing another example of a readout operation according to the first embodiment of the present technology. Figure 8 is a circuit diagram showing an example of the configuration of a pixel according to a comparative example. Figures 9a and 9b are diagrams showing an example of the state of each pixel during reset level readout and during initialization of the subsequent node according to the first embodiment of the present technology. Figure 10 is a diagram showing an example of the state of a pixel during signal level readout in the first embodiment of the present invention. Figure 11 is a flowchart showing an example of the operation of the solid-state imaging element in the first embodiment of the present invention. Figure 12 is a circuit diagram showing an example of the pixel configuration in the first variation of the first embodiment of the present invention. Figure 13 is a timing diagram showing an example of the global shutter operation in the first variation of the first embodiment of the present invention. Figure 14 is a timing diagram showing an example of the readout operation in the first variation of the first embodiment of the present invention. Figure 15 is a diagram showing an example of the multilayer structure of the solid-state imaging element in the second variation of the first embodiment of the present invention. Figure 16 is a circuit diagram showing an example of the pixel configuration in the second variation of the first embodiment of the present invention. Figure 17 is a diagram showing an example of the multilayer structure of the solid-state imaging element in the third variation of the first embodiment of the present invention. Figure 18 is a circuit diagram showing an example of the pixel configuration in the second embodiment of the present invention. Figure 19 is a timing diagram showing an example of global shutter operation in the second embodiment of the present technology. Figure 20 is a circuit diagram showing an example of pixel configuration in the third embodiment of the present technology. Figure 21 is a diagram illustrating the reset feedthrough in the third embodiment of the present technology. Figure 22 is a diagram illustrating the level deviation caused by the reset feedthrough in the third embodiment of the present technology. Figure 23 is a timing diagram showing an example of voltage control in the third embodiment of the present technology. Figure 24 is a timing diagram showing an example of global shutter operation in odd-numbered frames in the fourth embodiment of the present technology. Figure 25 is a timing diagram showing an example of readout operation in odd-numbered frames in the fourth embodiment of the present technology. Figure 26 is a timing diagram showing an example of global shutter operation in even-numbered frames in the fourth embodiment of the present technology. Figure 27 is a timing diagram showing an example of readout operation in even-numbered frames in the fourth embodiment of the present technology. Figure 28 is a circuit diagram showing an example of the configuration of a line signal processing circuit according to the fifth embodiment of the present technology.Figure 29 is a timing diagram showing an example of the global shutter action of the fifth embodiment of the present technology. Figure 30 is a timing diagram showing an example of the readout action of the fifth embodiment of the present technology. Figure 31 is a timing diagram showing an example of the rolling shutter action of the sixth embodiment of the present technology. Figure 32 is a block diagram showing an example of the configuration of a solid-state imaging element of the seventh embodiment of the present technology. Figures 33a and 33b are circuit diagrams showing an example of the configuration of a dummy pixel, regulator, and switching unit of the seventh embodiment of the present technology. Figure 34 is a timing diagram showing an example of the operation of the dummy pixel and regulator of the seventh embodiment of the present technology. Figure 35 is a circuit diagram showing an example of the configuration of an effective pixel of the seventh embodiment of the present technology. Figure 36 is a timing diagram showing an example of the global shutter action of the seventh embodiment of the present technology. Figure 37 is a timing diagram showing an example of the readout action of the seventh embodiment of the present technology. Figure 38 is a diagram used to illustrate the effect of the seventh embodiment of the present technology. Figure 39 is a circuit diagram showing an example of pixel configuration in the eighth embodiment of the present technology. Figure 40 is a top view showing an example of component layout in the eighth embodiment of the present technology. Figure 41 is a circuit diagram showing an example of pixel configuration in the eighth embodiment of the present technology when switching conversion efficiency in three stages. Figure 42 is a top view showing an example of component layout in the eighth embodiment of the present technology when switching conversion efficiency in three stages. Figure 43 is a top view showing an example of component layout in the ninth embodiment of the present technology. Figure 44 is a circuit diagram showing an example of pixel configuration in a variation of the ninth embodiment of the present technology. Figure 45 is a top view showing an example of component layout in a variation of the ninth embodiment of the present technology. Figure 46 is a top view showing an example of component layout in the tenth embodiment of the present technology. Figure 47 is an example of a cross-sectional view of a solid-state imaging element in the tenth embodiment of the present technology. Figures 48a-d are top views showing an example of component layout in the eleventh embodiment of the present technology. Figure 49 is an example of a cross-sectional view of a solid-state imaging element according to the 11th embodiment of the present technology. Figure 50 is a circuit diagram showing an example of a pixel configuration according to the 12th embodiment of the present technology. Figure 51 is a top view showing an example of a component layout according to the 12th embodiment of the present technology. Figure 52 is an example of a potential diagram of a pixel according to the 12th embodiment of the present technology. Figure 53 is a circuit diagram showing an example of a pixel configuration according to the 13th embodiment of the present technology. Figure 54 is a top view showing an example of a component layout according to the 13th embodiment of the present technology. Figure 55 is an example of a potential diagram of a pixel according to the 13th embodiment of the present technology. Figure 56 is a circuit diagram showing an example of a pixel configuration according to the 14th embodiment of the present technology. Figure 57 is a top view showing an example of a component layout according to the 14th embodiment of the present technology. Figure 58 is a circuit diagram showing another example of a pixel according to the 14th embodiment of the present technology.Figure 59 is a top view showing another example of the component layout of the 14th embodiment of the present invention. Figure 60 is a circuit diagram showing an example of the pixel configuration of the 15th embodiment of the present invention. Figure 61 is a diagram illustrating the pixel driving method of the 15th embodiment of the present invention. Figures 62a and 62b are diagrams showing an example of the pixel state during sampling and holding in driving example 1 of the 15th embodiment of the present invention. Figures 63a and 63b are diagrams showing an example of the pixel state during sampling and holding in driving example 2 of the 15th embodiment of the present invention. Figures 64a and 64b are diagrams showing an example of the pixel state during sampling and holding at a level corresponding to high conversion efficiency in driving example 3 of the 15th embodiment of the present invention. Figures 65a and 65b are diagrams showing an example of the pixel state during sampling and holding at a level corresponding to low conversion efficiency in driving example 3 of the 15th embodiment of the present invention. Figures 66a and 66b show an example of the state of a pixel when sampling and holding at a level corresponding to high conversion efficiency in driving example 4 of the 15th embodiment of the present technology. Figures 67a and 67b show an example of the state of a pixel when sampling and holding at a level corresponding to low conversion efficiency in driving example 4 of the 15th embodiment of the present technology. Figure 68 is a circuit diagram showing an example of the pixel configuration in a variation example of the 15th embodiment of the present technology. Figure 69 is a timing diagram showing an example of the operation of a solid-state imaging element in the 16th embodiment of the present technology. Figure 70 is a timing diagram showing an example of the first and second exposure control in the 16th embodiment of the present technology. Figure 71 is a timing diagram showing an example of the third exposure control in the 16th embodiment of the present technology. Figure 72 is a timing diagram showing an example of the readout operation of the first image in the 16th embodiment of the present technology. Figure 73 is a timing diagram showing an example of the readout operation of the second image in the 16th embodiment of the present technology. Figure 74 is a timing diagram showing an example of the operation of a solid-state imaging element in the first variation of the 16th embodiment of the present technology. Figure 75 is a timing diagram showing an example of the operation of a solid-state imaging element in the second variation of the 16th embodiment of the present technology. Figure 76 is a timing diagram showing an example of exposure control in the second variation of the 16th embodiment of the present technology. Figure 77 is a timing diagram showing an example of readout operation in the second variation of the 16th embodiment of the present technology. Figure 78 is a block diagram showing a schematic configuration example of a vehicle control system. Figure 79 is an explanatory diagram showing an example of the installation position of the camera unit.

Claims

1. A solid-state imaging element comprising: a front-end circuit that converts charge into voltage and outputs it to a front-end node by means of a plurality of conversion efficiencies; a plurality of capacitor elements, one end of which is commonly connected to the front-end node; a selection circuit that connects the other end of any one of the plurality of capacitor elements to a rear-end node; and a rear-end circuit that reads the voltage through the rear-end node.

2. The solid-state imaging element of claim 1, wherein the plurality of capacitive elements comprises: a high-capacitance element having a capacitance value higher than a specific value; and a low-capacitance element having a capacitance value lower than the specific value; wherein the high-capacitance element maintains the voltage generated by the highest high conversion efficiency among the plurality of conversion efficiencies; and the low-capacitance element maintains the voltage generated by a conversion efficiency lower than the high conversion efficiency among the plurality of conversion efficiencies.

3. The solid-state imaging element of claim 2, wherein the area of ​​the high-capacitance element is larger than that of the low-capacitance element.

4. The solid-state imaging element of claim 2, wherein the capacitance density of the high-capacitance element is higher than that of the low-capacitance element.

5. The solid-state imaging element of claim 2, wherein the high-capacitance element comprises a plurality of unit capacitor elements connected in parallel.

6. The solid-state imaging element of claim 2, wherein the aforementioned front-end circuit, the aforementioned selection circuit and the aforementioned back-end circuit are disposed on a first chip; and the aforementioned plurality of capacitor elements are disposed on a second chip.

7. The solid-state imaging element of claim 6, wherein the distance from the output terminal of the aforementioned front-end circuit to the aforementioned high-capacitance element is longer than the distance from the aforementioned output terminal to the aforementioned low-capacitance element.

8. The solid-state imaging element of claim 6, wherein the first chip comprises a plurality of stacked substrates.

9. The solid-state imaging element of claim 6, wherein the front-end circuit comprises: a photoelectric conversion element; a front-end transmission transistor that transmits the charge from the photoelectric conversion element to the floating diffusion layer; a first reset transistor that initializes the floating diffusion layer; a front-end amplification transistor that amplifies the voltage and outputs it to the front-end node; and a specific number of conversion efficiency control transistors that control the conversion efficiency.

10. The solid-state imaging element of claim 9, wherein the front-end circuit further includes an additional capacitor; the conversion efficiency control transistor is inserted between the floating diffusion layer and the additional capacitor; the additional capacitor is disposed on the second wafer.

11. The solid-state imaging element of claim 9, wherein the aforementioned front-end circuit further comprises: an additional capacitor; and a discharge transistor that discharges the charge from the aforementioned photoelectric conversion element; and the aforementioned specific number of conversion efficiency control transistors includes a first and a second conversion efficiency control transistor inserted in series between the aforementioned floating diffusion layer and the aforementioned additional capacitor; the aforementioned additional capacitor is disposed on either of the aforementioned first and second wafers.

12. The solid-state imaging element of claim 9 further comprises: a switching unit that adjusts the source voltage supplied to the source of the aforementioned front-end amplifying transistor; and the aforementioned front-end circuit further comprises a current source transistor that supplies current to the drain of the aforementioned front-end amplifying transistor; the aforementioned current source transistor moves from an on state to an off state after the exposure period ends.

13. The solid-state imaging element of claim 12, wherein the switching unit supplies a specific power supply voltage as the source voltage during the exposure period, and supplies a generation voltage different from the power supply voltage as the source voltage after the exposure period ends.

14. The solid-state imaging element of claim 9 further comprises: a control circuit that controls the reset power supply voltage of the aforementioned front-end circuit; and the aforementioned first reset transistor initializes the voltage of the floating diffusion layer to the aforementioned reset power supply voltage; and the aforementioned control circuit sets the aforementioned reset power supply voltage to a voltage different from that during the exposure period when reading out the aforementioned voltage.

15. The solid-state imaging element of claim 1, further comprising: a digital signal processing unit that adds a pair of consecutive frames; and the plurality of capacitor elements including a first and a second capacitor element; the voltage including a reset level and a signal level; wherein the front-end circuit, during the exposure period of one of the pairs of frames, holds the reset level at one of the first and second capacitor elements, and holds the signal level at the other of the first and second capacitor elements; and during the exposure period of the other pair of frames, holds the reset level at the other of the first and second capacitor elements, and holds the signal level at one of the first and second capacitor elements.

16. The solid-state imaging element of claim 1 further comprises: an analog-to-digital converter that converts the output voltage into a digital signal.

17. The solid-state imaging element of claim 16, wherein the analog-to-digital converter comprises: a comparator that compares the level of a vertical signal line transmitting the voltage with a specific ramp signal and outputs a comparison result; and a counter that counts a count value during traversal until the comparison result is reversed and outputs the digital signal representing the count value.

18. The solid-state imaging element of claim 17, wherein the comparator comprises: a comparator that compares the levels of each of a pair of input terminals and outputs a comparison result; and an input-side selector that selects either the node of the vertical signal line and the node of the specific reference voltage and is connected to one of the pair of input terminals; and inputs the ramp signal to one of the pair of input terminals.

19. The solid-state imaging element of claim 18 further comprises: a control unit that determines whether the illuminance is higher than a specific value based on the comparison result and outputs the determination result; a CDS (Correlated Double Sampling) processing unit that performs correlated double sampling processing on the digital signal; and an output-side selector that outputs either the digital signal after performing the correlated double sampling processing or the digital signal of the specific value based on the determination result.

20. The solid-state imaging element of claim 1 further comprises: a vertical scanning circuit that controls the aforementioned front-end circuit to set the conversion efficiency; and the capacitance values ​​of each of the aforementioned plurality of capacitor elements are the same; the aforementioned voltage includes a reset level and a signal level corresponding to the exposure amount.

21. The solid-state imaging element of claim 20, wherein the vertical scanning circuit sets any one of the plurality of conversion efficiencies, holds the reset level at half of the plurality of capacitor elements, and holds the signal level at the other half of the plurality of capacitor elements.

22. The solid-state imaging element of claim 20, wherein the plurality of capacitor elements comprises a plurality of first capacitor elements, a plurality of second capacitor elements, and a plurality of third capacitor elements; the vertical scanning circuit sets any of the plurality of conversion efficiencies such that the reset level is maintained at half of the plurality of first capacitor elements, and the signal level is maintained at the plurality of second capacitor elements.

23. The solid-state imaging element of claim 20, wherein the plurality of capacitor elements comprises a plurality of first capacitor elements, a plurality of second capacitor elements, a plurality of third capacitor elements, and a plurality of fourth capacitor elements; the vertical scanning circuit sequentially sets two of the plurality of conversion efficiencies such that the reset level generated by the higher of the two conversion efficiencies is maintained at the plurality of first capacitor elements, the signal level generated by the higher of the two conversion efficiencies is maintained at the plurality of second capacitor elements, the reset level generated by the lower of the two conversion efficiencies is maintained at the plurality of third capacitor elements, and the signal level generated by the lower of the two conversion efficiencies is maintained at the plurality of fourth capacitor elements.

24. The solid-state imaging element of claim 20, wherein the plurality of capacitor elements comprises a plurality of first capacitor elements, a plurality of second capacitor elements, a specific number of third capacitor elements less than the first capacitor elements, and the specific number of fourth capacitor elements; the vertical scanning circuit sequentially sets two of the plurality of conversion efficiencies such that the reset level generated by the higher of the two conversion efficiencies is maintained on the plurality of first capacitor elements, the signal level generated by the higher of the two conversion efficiencies is maintained on the plurality of second capacitor elements, the reset level generated by the lower of the two conversion efficiencies is maintained on the specific number of third capacitor elements, and the signal level generated by the lower of the two conversion efficiencies is maintained on the specific number of fourth capacitor elements.

25. The solid-state imaging element of claim 1, wherein the voltage comprises: a first reset level generated moment before the end of the first exposure period, a first signal level generated at the end of the first exposure period, a second reset level generated moment before the end of the second exposure period, and a second signal level generated at the end of the second exposure period; the plurality of capacitor elements comprises a first capacitor element holding the first reset level, a second capacitor element holding the first signal level, a third capacitor element holding the second reset level, and a fourth capacitor element holding the second signal level; the second exposure period begins immediately after the end of the first exposure period; and the downstream circuitry reads out the voltage while avoiding the sampling and holding period of the voltage.

26. The solid-state imaging element of claim 25, wherein the voltage further includes a third reset level generated moment before the end of the third exposure period and a third signal level generated at the end of the third exposure period; the plurality of capacitor elements further includes a fifth capacitor element holding the third reset level and a sixth capacitor element holding the third signal level; the third exposure period begins immediately after the end of the second exposure period.

27. The solid-state imaging element of claim 1, wherein the voltage comprises: a first reset level generated moment before the end of the first exposure period, a first signal level generated at the end of the first exposure period, and a second signal level generated at the end of the second exposure period; the plurality of capacitor elements comprises a first capacitor element holding the first reset level, a second capacitor element holding the first signal level, and a third capacitor element holding the second signal level; the second exposure period begins immediately after the end of the first exposure period; and the downstream circuitry reads out the voltage while avoiding the sampling and holding period of the voltage.

Images