Network switch and circuit board

Abstract

A network switch may include a high-precision time protocol module and a circuit board. The high-precision time protocol module provides a first clock signal and includes a predetermined interface. The circuit board may include a slot, an oscillator, and a selection unit. The slot can be inserted into the predetermined interface to receive the first clock signal. The oscillator provides a second clock signal. The selection unit may include a first terminal, a second terminal, an output terminal, and a selection terminal. When the predetermined interface is inserted into the slot, the first terminal can receive the first clock signal. The second terminal can receive the second clock signal. The output terminal can output one of the first clock signal and the second clock signal. The selection terminal can receive a selection signal to control the output terminal to output either the first clock signal or the second clock signal.

Description

Technical Field

[0001] This disclosure relates to a network switch and circuit board, and more particularly to a network switch and circuit board using a pluggable high-precision time protocol module. Prior Technology

[0002] In traditional Ethernet architectures, asynchronous signals can be used for control, and according to Ethernet protocols, this can be achieved through retry mechanisms. However, for high-speed applications, such as 5G and 6G communications, these traditional asynchronous mechanisms are no longer suitable. High-speed applications require precise synchronous control solutions to meet the demands of telecommunications communication.

[0003] However, indiscriminately installing precise synchronization control hardware, such as high-precision time protocol (PTP) circuitry, in telecommunications devices would increase hardware costs and lead to excessive hardware design complexity. Furthermore, network devices in different application scenarios may not require precise synchronization control. If the aforementioned hardware with precise synchronization control is not directly adopted, hardware that does not require precise synchronization control must be redesigned, such as a separate circuit board for non-precision synchronization protocols, thus increasing circuit board design costs. Currently, there is no universal circuit board that can simultaneously support both high-precision and non-high-precision time protocols.

[0004] In view of the above-mentioned difficulties, there is a lack of solutions in the field that can support both synchronous and asynchronous control and reduce the difficulty of operation and design. Summary of the Invention

[0005] An embodiment provides a network switch including a high-precision time protocol module and a circuit board. The high-precision time protocol module is used to provide a first clock signal and includes a predetermined interface. The circuit board includes a slot, an oscillator, and a selection unit. The slot is used to insert the predetermined interface to receive the first clock signal. The oscillator is used to provide a second clock signal. The selection unit includes a first terminal, a second terminal, an output terminal, and a selection terminal, wherein the first terminal is used to receive the first clock signal when the predetermined interface is inserted into the slot, the second terminal is used to receive the second clock signal, the output terminal is used to output one of the first clock signal and the second clock signal, and the selection terminal is used to receive a selection signal to control the output terminal to output the first clock signal or the second clock signal.

[0006] Another embodiment provides a circuit board including a slot, a first oscillator, and a selection unit. The slot is used to insert a predetermined interface of a high-precision timing module to receive a first clock signal. The first oscillator is used to provide a second clock signal. The selection unit includes a first terminal, a second terminal, an output terminal, and a selection terminal, wherein the first terminal is used to receive the first clock signal when the predetermined interface is inserted into the slot, the second terminal is used to receive the second clock signal, the output terminal is used to output one of the first clock signal and the second clock signal, and the selection terminal is used to receive a selection signal to control the output terminal to output the first clock signal or the second clock signal. Simple Explanation of the Diagram

[0007] Figures 1, 2, and 4 are schematic diagrams of network switches in different embodiments. Figure 3 is a schematic diagram of the logic unit in the embodiment. Implementation

[0008] Figure 1 is a schematic diagram of a network switch 100 in an embodiment. The network switch 100 may include a precision time protocol (PTP) module 110 and a circuit board 120. The PTP module 110 may include a predetermined interface 112 and can be used to provide a first clock signal Sc1. For example, the circuit board 120 may include a printed circuit board (PCB) and components disposed on the PCB. The circuit board 120 may include a slot 122, an oscillator 123, and a selection unit 124. The slot 122 can be used to insert the predetermined interface 112 to receive the first clock signal Sc1. The oscillator 123 can be used to provide a second clock signal Sc2. The selection unit 124 may include a first terminal, a second terminal, an output terminal, and a selection terminal. The first terminal can be used to receive a first clock signal Sc1 when the predetermined interface 112 is inserted into the slot 122. The second terminal is used to receive a second clock signal Sc2. The output terminal can be used to output one of the first clock signal Sc1 and the second clock signal Sc2. The selection terminal can be used to receive a selection signal Ssel to control the output terminal to output the first clock signal Sc1 or the second clock signal Sc2.

[0009] As shown in Figure 1, the selection unit 124 can output a first clock signal Sc1 or a second clock signal Sc2 to the clock fan-out and attenuator circuit 126 on the circuit board 120, thereby providing a processed clock signal to the core switch chip 128 and the programmable unit 129.

[0010] For example, the core switch chip 128 may be an application-specific integrated circuit (ASIC). The programmable unit 129 may include a field-programmable gate array (FPGA) and / or a complex programmable logic device (CPLD). As shown in Figure 1, a controller 125 may be provided on the circuit board 120 to control the core switch chip 128 and the programmable unit 129.

[0011] According to an embodiment, the first clock signal Sc1 can be used to support high-precision time protocols, and the second clock signal Sc2 can be used to support non-high-precision time protocols. For example, the first clock signal Sc1 can support high-speed applications such as 5G and / or 6G communications, while the second clock signal Sc2 can support Ethernet applications.

[0012] As shown in Figure 1, when the predetermined interface 112 of the high-precision time protocol module 110 is not yet inserted into the slot 122 of the circuit board 120, the oscillator 123 of the circuit board 120 can provide a second clock signal Sc2 to the selection unit 124, so that the output terminal of the selection unit 124 outputs the second clock signal Sc2. When the predetermined interface 112 of the high-precision time protocol module 110 is inserted into the slot 122 of the circuit board 120, the high-precision time protocol module 110 can provide a first clock signal Sc1 to the selection unit 124, so that the output terminal of the selection unit 124 outputs the first clock signal Sc1.

[0013] Figure 2 is a schematic diagram of the network switch 100 in Figure 1 in the embodiment. As shown in Figure 2, the high-precision time protocol module 110 may include an oscillator 114 and a phase-locked loop circuit 116. The oscillator 114 can be used to provide a synchronous oscillation signal So, and the phase-locked loop circuit 116 can be used to generate a first clock signal Sc1 according to the synchronous oscillation signal So.

[0014] As shown in Figure 2, the high-precision timing module 110 may further include a reference voltage terminal for receiving a reference voltage signal Vr. The reference voltage signal Vr may have a fixed level. For example, the reference voltage signal Vr may be a ground voltage signal with a voltage level of 0 volts. When the predetermined interface 112 is inserted into the slot 122, the slot 122 can receive the first clock signal Sc1 and the reference voltage signal Vr. As shown in Figure 2, the circuit board 120 may further include a logic unit 127. When the predetermined interface 112 is inserted into the slot 122, the logic unit 127 can receive the reference voltage signal Vr from the slot 122 to adjust the level of the selection signal Ssel, thereby controlling the output of the selection unit 124 to output the second clock signal Sc2.

[0015] Figure 3 is a schematic diagram of the logic unit 127 in the embodiment. As shown in Figure 3, the logic unit 127 may include an inverter 310 and a mutual exclusion (XOR) gate 320. As shown in Figures 2 and 3, when the predetermined interface 112 is inserted into the slot 122, the inverter 310 may receive a reference voltage signal Vr to generate an inverted signal Vr'. The reference voltage signal Vr may have a first level, and the inverted signal Vr' may have a second level, wherein the first level and the second level may be inverted from each other. The mutual exclusion gate 320 may include a first terminal, a second terminal, and an output terminal, wherein the first terminal can be used to receive the inverted signal Vr', the second terminal can be used to receive an internal control signal Vi, and the output terminal can be used to output a selection signal Ssel. For example, the internal control signal Vi may be generated and output by the programmable unit 129.

[0016] Here, the operation of logic unit 127 is illustrated using the first level of the reference voltage signal Vr as the low level and the second level of the inverted signal Vr' as the high level. For example, the reference voltage signal Vr can be a ground signal, corresponding to the low level of logic 0. Therefore, when the predetermined interface 112 is inserted into slot 122, inverter 310 can receive the reference voltage signal Vr to generate the inverted signal Vr', where the inverted signal Vr' can correspond to the high level of logic 1. The internal control signal Vi can be selected with an appropriate level, for example, the low level of logic 0. Therefore, when the first terminal of the XOR gate 320 receives the inverted signal Vr' corresponding to the low level of logic 1, the selection signal Ssel can have an appropriate level (e.g., the low level of logic 0) so that the output terminal of selection unit 124 outputs the first clock signal Sc1. The signal levels described here are only examples and can be adjusted according to design requirements.

[0017] Figure 4 is a schematic diagram of the network switch 100 of Figure 1 in another embodiment. Figure 4 may be similar to Figure 2; however, as shown in Figure 4, the circuit board 120 may further include an oscillator 114 to provide a synchronous oscillation signal So. The high-precision timing module 110 of Figure 4 may include a phase-locked loop circuit 116 to receive the synchronous oscillation signal So and generate a first clock signal Sc1 based on the synchronous oscillation signal So when the predetermined interface 112 is inserted into the slot 122.

[0018] In Figure 2, the oscillator 114 and phase-locked loop circuit 116 supporting high-precision time protocol can be integrated into the high-precision time protocol module 120. Therefore, the relevant circuits of high-precision time protocol can be effectively integrated into the module, which can significantly reduce the cost and complexity of the circuit board 120. In Figure 4, because the oscillator 114 is set on the circuit board 120, the size of the high-precision time protocol module 110 can be reduced.

[0019] In Figures 1, 2, and 4, oscillator 123 can be a general oscillator. In Figures 2 and 4, oscillator 114 can include at least one of an oven-controlled crystal oscillator (OCXO) and a temperature-compensated crystal oscillator (TCXO).

[0020] According to the embodiment, the first clock signal Sc1 generated by the oscillator 114 supporting a high-precision time protocol and the second clock signal Sc2 generated by the oscillator 123 on the circuit board 120 are different. The oscillator 123 on the circuit board 120 can be a general oscillator, which is relatively inexpensive. The oscillator 114 can be an oscillator supporting a high-precision time protocol, which is relatively expensive. By using the architecture of Figures 1, 2, and 4, network switches that do not need to support high-precision time protocol functions can use the same motherboard (e.g., circuit board 120) because the network switch can use the clock signal (e.g., the second clock signal Sc2) generated by the cheaper oscillator (e.g., oscillator 123) on the motherboard.

[0021] Therefore, circuit board 120 can be a general-purpose circuit board, flexibly supporting both high-precision time protocol functions and non-high-precision time protocol functions, with or without the high-precision time protocol module 110. As shown in Figures 1, 2, and 4, circuit board 120 may include controller 125. When the predetermined interface 112 of the high-precision time protocol module 110 is inserted into the slot 122 of circuit board 120, controller 125 can be used to execute a control program to perform synchronous control operations, wherein the control program may correspond to oscillator 114 and phase-locked loop circuit 116. For example, controller 125 may perform control related to oscillator 114 and phase-locked loop circuit 116 through suitable software and / or firmware. For example, controller 125 may be a central processing unit (CPU).

[0022] As shown in Figures 1, 2, and 4, the high-precision timing module 110 may further include a memory 118 for storing identification data. The controller 125 may also be used to read the identification data. When the controller 125 determines that the identification data is correct, it can execute the relevant control program for synchronization control. For example, the memory 118 may include electrically-erasable programmable read-only memory (EEPROM).

[0023] Since both the oscillator 114 and the phase-locked loop circuit 116 supporting high-precision time protocols must pass relevant certifications, and the oscillators 114 and phase-locked loop circuits 116 provided by different suppliers must be controlled by specific programs, they must cooperate with each other during operation. If the oscillator 114 and the phase-locked loop circuit 116 are selected separately, the complexity and difficulty of design and control will increase. In addition, it will be difficult to design a circuit board that can support both high-precision and non-high-precision time protocols. By integrating the relevant components of the high-precision time protocol into the high-precision time protocol module 110 as shown in Figures 1, 2 and 4, the complexity and difficulty of design and use can be effectively reduced.

[0024] By using the architecture shown in Figures 1, 2, and 4, asynchronous control using non-high-precision time protocols can be supported when the predetermined interface 112 of the high-precision time protocol module 110 is not yet inserted into the slot 122 of the circuit board 120. When the predetermined interface 112 of the high-precision time protocol module 110 is inserted into the slot 122 of the circuit board 120, synchronous control using high-precision time protocols can be supported. The architecture disclosed in this embodiment provides a universal motherboard design that can be used for both Telco and 5G edge network switches that require high-precision time protocol functionality, and enterprise-level network switches or data center switches that do not require high-precision time protocol functionality, without the need to design a separate motherboard supporting non-high-precision time protocols (non-PTP). Therefore, this embodiment of the invention can significantly simplify design and operational complexity. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0025] 100: Network Switch 110: High-precision time agreement module 112: Reservation Interface 114, 123: Oscillators 116: Phase-locked loop circuit 118: Memory 120: Circuit board 122: Slot 124: Select Unit 125: Controller 126: Clock fan-out and attenuator circuit 127: Logic Unit 128: Core Switch Chip 129: Programmable Unit 310: Inverter 320: Mutual Exclusion or Gate Sc1: First clock signal Sc2: Second clock signal Ssel: Select Signal So: Synchronous oscillation signal Vi: Internal Control Signals Vr: Reference voltage signal Vr': Inverted signal

Claims

1. A network switch, comprising: a high-precision time protocol module for providing a first clock signal, comprising: a predetermined interface; a second oscillator for providing a synchronous oscillation signal and supporting a high-precision time protocol; and a phase-locked loop circuit for generating the first clock signal based on the synchronous oscillation signal; and a circuit board comprising: a slot for inserting the predetermined interface to receive the first clock signal; a first oscillator for providing a second clock signal; and a selection unit comprising a first terminal for receiving the first clock signal when the predetermined interface is inserted into the slot, a second terminal for receiving the second clock signal, an output terminal for outputting one of the first clock signal and the second clock signal, and a selection terminal for receiving a selection signal to control the output terminal to output the first clock signal or the second clock signal.

2. The network switch as described in claim 1, wherein: The first clock signal is used to support the high-precision time protocol; and the second clock signal is used to support a non-high-precision time protocol.

3. The network switch as described in claim 1, wherein: The high-precision timing module further includes a reference voltage terminal for receiving a reference voltage signal, wherein the reference voltage signal has a fixed level; the slot is further used to receive the reference voltage signal when the predetermined interface is inserted; and the circuit board further includes a logic unit for receiving the reference voltage signal from the slot when the predetermined interface is inserted into the slot to adjust the level of the selection signal, so as to control the output terminal of the selection unit to output the second clock signal.

4. The network switch as claimed in claim 3, wherein the logic unit comprises: an inverter for receiving the reference voltage signal to generate an inverted signal when the predetermined interface is inserted into the slot; and a mutex gate including a first terminal for receiving the inverted signal, a second terminal for receiving an internal control signal, and an output terminal for outputting the selection signal.

5. The network switch as claimed in claim 4, wherein the reference voltage signal has a first level and the inverted signal has a second level, and the first level and the second level are inverted.

6. A network switch, comprising: a high-precision time protocol module for providing a first clock signal, comprising: a predetermined interface and a phase-locked loop circuit for generating the first clock signal according to a synchronous oscillation signal when the predetermined interface is inserted into a slot; and a circuit board comprising: the slot for inserting the predetermined interface to receive the first clock signal; a first oscillator for providing a second clock signal; a selection unit comprising a first terminal for receiving the first clock signal when the predetermined interface is inserted into the slot, a second terminal for receiving the second clock signal, an output terminal for outputting one of the first clock signal and the second clock signal, and a selection terminal for receiving a selection signal to control the output terminal to output the first clock signal or the second clock signal; and a second oscillator for providing the synchronous oscillation signal; wherein the second oscillator supports a high-precision time protocol.

7. The network switch as claimed in claim 1 or 6, wherein the second oscillator comprises at least one of an Oven Controlled Crystal Oscillator (OCXO) and a Temperature Compensated Crystal Oscillator (TCXO).

8. The network switch as claimed in claim 1 or 6, wherein the circuit board further includes: a controller for executing a control program to perform a synchronization control operation; wherein the control program corresponds to the second oscillator and the phase-locked loop circuit.

9. The network switch as described in claim 8, wherein: The high-precision time agreement module further includes a memory for storing identification data; the controller is further used to read the identification data, and when the identification data is correct, the controller executes the control program.

10. A circuit board comprising: a slot for inserting a predetermined interface of a high-precision timing module to receive a first clock signal and for receiving a reference voltage signal when the predetermined interface is inserted; a first oscillator for providing a second clock signal; a selection unit comprising a first terminal for receiving the first clock signal when the predetermined interface is inserted into the slot, a second terminal for receiving the second clock signal, an output terminal for outputting one of the first clock signal and the second clock signal, and a selection terminal for receiving a selection signal to control the output terminal to output the first clock signal or the second clock signal; and a logic unit for receiving the reference voltage signal from the slot when the predetermined interface is inserted into the slot to adjust the level of the selection signal to control the output terminal of the selection unit to output the second clock signal.

11. The circuit board as claimed in claim 10, wherein: The first clock signal is used to support a high-precision time protocol; and the second clock signal is used to support a non-high-precision time protocol.

12. The circuit board of claim 10, wherein the logic unit comprises: an inverter for receiving the reference voltage signal to generate an inverted signal when the predetermined interface is inserted into the slot; and a mutex gate comprising a first terminal for receiving the inverted signal, a second terminal for receiving an internal control signal, and an output terminal for outputting the selection signal.

13. The circuit board as claimed in claim 10, wherein: The circuit board further includes a second oscillator for providing a synchronous oscillation signal; and when the predetermined interface is inserted into the slot, the circuit board provides the synchronous oscillation signal to the predetermined interface and receives the first clock signal from the predetermined interface; wherein the second oscillator supports a high-precision time protocol.

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