Display devices and electronic devices

Abstract

A display device with minimal chromaticity variation and high grayscale control is provided. This display device enables a light-emitting device to emit or de-emitter light using PAM and PWM (Pulse Width Control) with amplitude variation. The display device writes the same input signal (data potential) to both a first node and a second node, emitting light based on the potential of the first node and generating a pulse signal based on the potential of the second node. The potential of the first node can be reset according to the generated pulse signal. Therefore, the light-emitting device can emit light at a desired intensity for a desired duration.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above-described technical field. The technical field of one embodiment of the invention disclosed in this specification relates to an object, method, or manufacturing method. Furthermore, one embodiment of the present invention relates to a process, machine, manufacture, or composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, energy storage devices, memory devices, imaging devices, methods of operating these devices, or methods of manufacturing these devices.

[0003] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Transistors and semiconductor circuits are one embodiment of a semiconductor device. Additionally, memory devices, display devices, imaging devices, and electronic devices sometimes include semiconductor devices. Prior Technology

[0004] Display devices and lighting equipment incorporating micro light-emitting diodes (hereinafter referred to as Micro LEDs) have been proposed (e.g., Patent Document 1). Display devices incorporating Micro LEDs can achieve high brightness and have high reliability, and are expected to become the next generation of displays.

[0005] In addition, the technology of using metal oxides formed on a substrate to construct transistors has attracted attention. For example, Patent Documents 2 and 3 disclose a technology that uses transistors using zinc oxide, In-Ga-Zn type oxides as switching elements for pixels in a display device.

[0006] [Patent Document 1] U.S. Patent Application Publication No. 2014 / 0367705 [Patent Document 2] Japanese Patent Application Publication No. 2007-123861 [Patent Document 3] Japanese Patent Application Publication No. 2007-96055 Summary of the Invention

[0007] In display devices that use light-emitting devices (also known as light-emitting elements), brightness can be changed by controlling the current flowing through the light-emitting device. However, LEDs, as one type of light-emitting device, have the characteristic that their colorimetry is easily changed according to current density.

[0008] Therefore, when using pulse amplitude modulation (PAM) to control the brightness of an LED, color reproducibility sometimes decreases. Therefore, it is preferable to use pulse width modulation (PWM) control, which controls brightness based on the duty cycle, for driving the LED. Since PWM control can maintain a constant current density, brightness can be adjusted without causing chromaticity shift.

[0009] On the other hand, based on the transistors driving the LED and the LED's response characteristics, there is a lower limit to the operating ratio that can be stably controlled. Therefore, PWM control of LEDs has the problem of difficulty in controlling the low grayscale side with a small operating ratio.

[0010] In view of the above problems, one objective of an embodiment of the present invention is to provide a display device with small chromaticity variation and high grayscale controllability. Another objective of an embodiment of the present invention is to provide a display device including a pixel circuit that generates pulse signals. Another objective of an embodiment of the present invention is to provide a display device including a pixel circuit capable of PAM control and PWM control. Another objective of an embodiment of the present invention is to provide a display device with good display characteristics. Furthermore, one objective of an embodiment of the present invention is to provide a display device with a narrow bezel.

[0011] Furthermore, one objective of one embodiment of the present invention is to provide a low-power display device. Another objective of one embodiment of the present invention is to provide a highly reliable display device. Another objective of one embodiment of the present invention is to provide a novel display device, etc. Another objective of one embodiment of the present invention is to provide a method of operating the above-described display device. Furthermore, one objective of one embodiment of the present invention is to provide a novel semiconductor device, etc.

[0012] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the present invention does not need to achieve all of the above objectives. Note that objectives other than those described above can be derived from the description in the specification, drawings, claims, etc.

[0013] One embodiment of the present invention relates to a display device including a pixel circuit capable of PAM control and PWM control.

[0014] A first aspect of the present invention is a display device comprising a pixel including a pulse signal generating unit, a light-emitting device, a first node, and a second node. The first node is electrically connected to the input unit of the pulse signal generating unit, and the second node is electrically connected to the output unit of the pulse signal generating unit. The first node and the second node are electrically connected via a transistor. The pixel causes the light-emitting device to emit light in response to a data potential input to the second node. The pulse signal generating unit generates a pulse signal in response to a data potential input to the first node, and the pixel resets the potential of the second node in response to the pulse signal, thereby stopping the light-emitting device from emitting light.

[0015] A second aspect of the present invention is a display device comprising a pixel including a pulse signal generating unit, a first node, a second node, a first transistor, a second transistor, a third transistor, a first capacitor, and a light-emitting device. The first node is electrically connected to one of the source and drain electrodes of the first transistor, one of the source and drain electrodes of the second transistor, and the input portion of the pulse signal generating unit. The second node is electrically connected to the other of the source and drain electrodes of the second transistor, the gate electrode of the third transistor, one electrode of the first capacitor, and the output portion of the pulse signal generating unit. One of the source and drain electrodes of the third transistor is electrically connected to one electrode of the light-emitting device, and the other of the source and drain electrodes of the third transistor is electrically connected to the other electrode of the first capacitor.

[0016] The pulse signal generation unit includes a fourth to a ninth transistor and a second capacitor. The fourth transistor has a first gate and a second gate. The first gate of the fourth transistor and one of the source and drain of the fifth transistor are electrically connected to a first node. One of the source and drain of the fourth transistor is electrically connected to the gate of the sixth transistor and one of the source and drain of the seventh transistor. The second gate of the fourth transistor is electrically connected to one of the source and drain of the eighth transistor and one electrode of the second capacitor. The other electrode of the second capacitor is electrically connected to one of the source and drain of the ninth transistor. The other of the source and drain of the ninth transistor is electrically connected to the other of the source and drain of the fourth transistor. One of the source and drain of the sixth transistor is electrically connected to a second node.

[0017] The signal potential of another input ramp waveform in the source and drain of the fourth transistor.

[0018] The first, second, fourth, fifth, eighth, and ninth transistors are all n-channel transistors, while the third, sixth, and seventh transistors are all p-channel transistors.

[0019] n-channel transistors preferably contain metal oxides in the channel formation region, while p-channel transistors preferably contain silicon in the channel formation region.

[0020] In the second aspect of the present invention, the data potential of the first node corresponding to the pixel causes the light-emitting device to emit light, the pulse signal generation unit generates a pulse signal corresponding to the data potential of the second node, and the potential of the first node is reset by the pulse signal corresponding to the pixel, thereby causing the light-emitting device to stop emitting light.

[0021] Micro LED is the preferred light-emitting device.

[0022] By using one embodiment of the present invention, a display device with small color variation and high grayscale controllability can be provided. Furthermore, by using one embodiment of the present invention, a display device including a pixel circuit for generating pulse signals can be provided. Furthermore, by using one embodiment of the present invention, a display device including a pixel circuit capable of PAM control and PWM control can be provided. Furthermore, by using one embodiment of the present invention, a display device with excellent display characteristics can be provided. In addition, by using one embodiment of the present invention, a display device with a narrow bezel can be provided.

[0023] Furthermore, by using one embodiment of the present invention, a low-power display device can be provided. Furthermore, by using one embodiment of the present invention, a highly reliable display device can be provided. Furthermore, by using one embodiment of the present invention, a novel display device, etc., can be provided. Furthermore, by using one embodiment of the present invention, an operating method for the above-mentioned display device can be provided. In addition, by using one embodiment of the present invention, a novel semiconductor device, etc., can be provided. Simple Explanation of the Diagram

[0024] [Figure 1] is a diagram illustrating the pixel circuit. [Figure 2A] is a diagram illustrating the pixel circuit. [Figure 2B] is a timing diagram illustrating the operation of the pixel circuit. [Figure 2C] is a diagram illustrating the ramp potential. [Figure 2D] is a diagram illustrating the transistor. [Figure 3A] and [Figure 3B] are diagrams illustrating the stacked structure of the display device. [Figure 4A] and [Figure 4B] are diagrams illustrating the operation of pixels. [Figure 5A] and [Figure 5B] are diagrams illustrating the operation of pixels. [Figure 6A] and [Figure 6B] are diagrams illustrating the operation of pixels. [Figure 7] is a timing diagram illustrating the operation of the pixel. [Figure 8A] and [Figure 8B] are diagrams illustrating the operation of pixels. [Figure 9A] and [Figure 9B] are diagrams illustrating the operation of pixels. [Figure 10] is a timing diagram illustrating the operation of the pixel. [Figure 11A] and [Figure 11B] are figures illustrating examples of pixel deformation. [Figure 12A] and [Figure 12B] are figures illustrating examples of pixel deformation. [Figure 13A] is a diagram illustrating the pixel circuit. [Figure 13B] is a timing diagram illustrating the operation of the pixel. [Figure 14A] and [Figure 14B] are diagrams illustrating the operation of pixels. [Figure 15A] and [Figure 15B] are diagrams illustrating the operation of pixels. [Figure 16A] is a graph showing the relationship between grayscale and brightness. [Figure 16B] is a graph illustrating the operation of a light-emitting device with corresponding brightness based on the luminous intensity and luminous time. [Figure 17A] and [Figure 17B] are diagrams illustrating the range of chromaticity shift. [Figure 18] is a block diagram illustrating the display device. [Figure 19A] and [Figure 19B] are diagrams illustrating the display device. [Figure 20] is a diagram illustrating the display device. [Figure 21] is a diagram illustrating the display device. Figures 22A and 22B are illustrations of the display device. Figures 23A to 23D are illustrations of the electronic device. Implementation

[0025] The embodiments are described in detail using drawings. Note that the invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited only to the contents described in the embodiments shown below. Note that in the structure of the invention described below, the same element symbols are used in different drawings to represent the same parts or parts having the same function, and repeated descriptions are omitted. Note that sometimes the shading of the same components is appropriately omitted or changed in different drawings.

[0026] Furthermore, even if something is considered a single element on a circuit diagram, it can be constructed using multiple elements if there are no functional problems. For example, multiple transistors used as switches can sometimes be connected in series or parallel. Additionally, capacitors are sometimes segmented and configured in multiple locations.

[0027] Furthermore, sometimes a single conductor serves multiple functions, such as wiring, electrodes, and terminals. In this specification, multiple names are sometimes used for the same element. Additionally, even when elements are shown as directly connected in a circuit diagram, they are sometimes actually connected by multiple conductors. Such structures are also included in the scope of direct connections in this specification.

[0028] Implementation Method 1 In this embodiment, a display device according to one embodiment of the present invention will be described with reference to the drawings.

[0029] One embodiment of the present invention is a display device capable of emitting or de-emitting light using PAM+PWM control (pulse width control with amplitude variation). This display device writes the same input signal (data potential) to a first node and a second node, emitting light based on the potential of the first node and generating a pulse signal based on the potential of the second node. Furthermore, the potential of the first node is reset based on the generated pulse signal. Thus, the light-emitting device can emit light at a desired intensity for a desired period of time.

[0030] Note that in this embodiment, PAM control refers to controlling brightness by fixing the emission time (equivalent to the width of the pulse signal generated by the pixel) and changing the emission intensity (equivalent to the current flowing through the light-emitting device). PWM control, on the other hand, refers to controlling brightness by fixing the emission intensity and changing the emission time. Furthermore, PAM+PWM control controls brightness by changing both the emission intensity and the emission time.

[0031] LEDs, as light-emitting devices, have the characteristic that their color intensity changes according to current density, making them sometimes unsuitable for PAM control. On the other hand, PWM control suffers from difficulties in controlling low grayscale levels due to the influence of the driving transistors and the response characteristics of the LEDs. One embodiment of the present invention provides a display device that combines PWM control and PAM control to alleviate these problems.

[0032] For example, display operation can be performed using PAM control on the low grayscale side and the high grayscale side, while display operation on the intermediate grayscale side can be performed using PAM+PWM control. Through this operation, the amount of chromaticity change from the intermediate grayscale to the high grayscale can be reduced while improving controllability on the low grayscale side. Note that the display device of one embodiment of the present invention is not limited to this; LED illumination can be performed using only PAM control or only PWM control over a wide grayscale range.

[0033] Figure 1 is a circuit diagram of a pixel 10a included in a display device according to an embodiment of the present invention. Pixel 10a includes a pulse signal generation unit 11 and nodes N and A for maintaining data potential VDATA.

[0034] The data potential VDATA is a potential based on image data, and the same data potential VDATA is supplied to both node N and node A. The light-emitting device 110 can emit light according to the data potential VDATA supplied to node A (PAM control). Furthermore, the input of the pulse signal generation unit 11 is electrically connected to node N, and the output of the pulse signal generation unit 11 is electrically connected to node A. Therefore, the potential of node A can be reset according to the pulse signal generated by the pulse signal generation unit 11, thereby stopping the light-emitting device 110 from emitting light (PWM control).

[0035] Pixel 10a may include transistor 101, transistor 102, transistor 103, light-emitting device 110, capacitor 111, and pulse signal generation unit 11. Light-emitting device 110 is preferably an LED (e.g., Micro LED or Mini LED). Alternatively, organic EL elements may also be used for light-emitting device 110.

[0036] Here, transistors 101 and 102 are used as switches. Transistor 103 is a p-channel transistor and is used as the driving transistor for the light-emitting device 110. Capacitor 111 is used as the storage capacitor for node A. Note that although an example of using n-channel transistors 101 and 102 is shown, p-channel transistors can also be used as switches.

[0037] One of the source and drain electrodes of transistor 101 is electrically connected to one of the source and drain electrodes of transistor 102 and the input section of pulse signal generation unit 11. The other of the source and drain electrodes of transistor 102 is electrically connected to the output section of pulse signal generation unit 11, one electrode of capacitor 111, and the gate electrode of transistor 103. One of the source and drain electrodes of transistor 103 is electrically connected to one electrode (anode) of light-emitting device 110. The other of the source and drain electrodes of transistor 103 is electrically connected to the other electrode of capacitor 111.

[0038] Here, the point (wiring or electrode, etc.) connecting one of the source and drain terminals of transistor 101, one of the source and drain terminals of transistor 102, and the input terminal of pulse signal generation unit 11 is denoted as node N. Furthermore, the point (wiring or electrode, etc.) connecting the other of the source and drain terminals of transistor 102, the output terminal of pulse signal generation unit 11, one electrode of capacitor 111, and the gate terminal of transistor 103 is denoted as node A.

[0039] The connection relationships between each transistor and the wiring are as follows: the other of the source and drain of transistor 101 is electrically connected to wiring 121; the other of the source and drain of transistor 103 is electrically connected to wiring 125; the other electrode (cathode) of the light-emitting device 110 is electrically connected to wiring 129; the gate of transistor 101 is electrically connected to wiring 131; and the gate of transistor 102 is electrically connected to wiring 132.

[0040] Wiring 121 is the source wiring used to supply the data potential VDATA. Wiring 121 can be electrically connected to the source driver. Wirings 125 and 129 are power lines; wiring 125 can be a high-potential power line, and wiring 129 can be a low-potential power line. Wirings 131 and 132 are gate wirings used to control the conduction of each transistor, and they can be electrically connected to the gate driver.

[0041] Figure 2A shows a specific circuit structure example of the pulse signal generation unit 11. The pulse signal generation unit 11 may include transistors 104, 105, 106, 107, 108, 109, capacitor 112, and capacitor 113.

[0042] Here, transistor 104 is an n-channel transistor, including a first gate and a second gate. The first gate serves as the front gate, and the second gate serves as the back gate. Transistors 106 and 107 can be p-channel transistors. Note that although an example of using an n-channel transistor as another transistor is shown in Figure 2A, it can also be a p-channel transistor.

[0043] The first gate of transistor 104 is electrically connected to node N, one of the source and drain terminals of transistor 105, and one electrode of capacitor 112. In other words, the wiring or electrode connecting the first gate of transistor 104, one of the source and drain terminals of transistor 105, and one electrode of capacitor 112 can also be referred to as the input section of pulse signal generation unit 11. Alternatively, node N can be referred to as the input section of pulse signal generation unit 11.

[0044] One of the source and drain of transistor 104 is electrically connected to the gate of transistor 106 and one of the source and drain of transistor 107.

[0045] One of the source and drain terminals of transistor 106 is electrically connected to node A. That is, the wiring or electrode connecting one of the source and drain terminals of transistor 106 to node A can also be referred to as the output of pulse signal generation unit 11. Alternatively, node A can be referred to as the output of pulse signal generation unit 11.

[0046] The second gate of transistor 104 is electrically connected to one of the source and drain of transistor 108 and one electrode of capacitor 113.

[0047] The other electrode of capacitor 113 is electrically connected to the other of the source and drain electrodes of transistor 105 and one of the source and drain electrodes of transistor 109.

[0048] Here, the point (wiring or electrode, etc.) connecting one of the source and drain terminals of transistor 104, the gate terminal of transistor 106, and one of the source and drain terminals of transistor 107 is denoted as node W. Additionally, the point (wiring or electrode, etc.) connecting the second gate terminal of transistor 104, one of the source and drain terminals of transistor 108, and one electrode of capacitor 113 is denoted as node BG. Furthermore, the point (wiring or electrode, etc.) connecting the other electrode of capacitor 113, the other of the source and drain terminals of transistor 105, and one of the source and drain terminals of transistor 109 is denoted as node BS.

[0049] The connections between each transistor and the wiring are as follows: the other of the source and drain of transistor 104 and the other of the source and drain of transistor 109 are electrically connected to wiring 122; the other of the source and drain of transistor 106 is electrically connected to wiring 124; the other of the source and drain of transistor 107 is electrically connected to wiring 123; the other of the source and drain of transistor 108 is electrically connected to wiring 128; the gate of transistor 105 is electrically connected to wiring 133; the gate of transistor 107 is electrically connected to wiring 134; the gate of transistor 108 is electrically connected to wiring 135; the gate of transistor 109 is electrically connected to wiring 136; and the other electrode of capacitor 112 is electrically connected to wiring 127.

[0050] Wiring 122 is used to supply the ramp potential SLO. In this specification, ramp potential refers to a type of signal potential with a ramp waveform, meaning a signal potential that changes from high to low or from low to high over a period of time. Alternatively, it refers to a signal potential that changes with a gradient relative to the time axis.

[0051] Wiring 123 is used to supply the reset potential VRESW to node W. Wiring 124 is used to supply the reset potential VRESA to node A. Wiring 127 is a fixed potential line, such as a GND line or a low-potential power line. Wiring 128 is used to supply the potential VSBG to node BG. Potential VSBG is a fixed potential supplied as the initial back gate potential.

[0052] Here, the reset potential VRESW supplied to wiring 123 can be set to a high potential. Additionally, the reset potential VRESA supplied to wiring 124 can be set to a high potential. The potential VSBG supplied to wiring 128 can be set to a low potential (e.g., a negative potential). Details regarding the ramp potential SLO supplied to wiring 122 will be explained later.

[0053] Transistors 106 and 107 are used as switches. Transistors 104, 105, 108, and 109 have the function of determining the width of the generated pulse signal. Capacitor 112 is used as a storage capacitor for node N. Capacitor 113 is used as a storage capacitor for node BG.

[0054] In the pulse signal generation unit 11, under certain conditions, transistor 104 is turned on, the potential of node W decreases, and transistor 106 can be turned on. By turning on transistor 106, the potential of node A can be changed to the reset potential VRESA. In other words, the pulse signal generation unit 11 generates a pulse signal and can control the period during which node A maintains the data potential VDATA according to the pulse signal.

[0055] As for the transistors 101 to 109 in pixel 10a, transistors containing silicon in the channel forming region (hereinafter referred to as Si transistors) or transistors containing metal oxides in the channel forming region (hereinafter referred to as OS transistors) may be used. Alternatively, both Si transistors and OS transistors may be used.

[0056] For example, in the circuit structure shown in Figure 2A, it is preferable to use Si transistors as transistors 103, 106, and 107, and OS transistors as the other transistors. OS transistors can be placed in the fabrication process of the wiring layer on top of the Si transistors, thus increasing the integration density.

[0057] Transistors 103, 106, and 107 are preferably Si transistors, which are readily capable of forming p-channel transistors. Furthermore, since transistors 106 and 107 preferably possess fast charging characteristics, they are also preferred transistors with high transconductance (gm). Si transistors have high mobility and can therefore be used as transistors with high gm.

[0058] Furthermore, due to the large bandgap in the semiconductor layer of the OS transistor, it exhibits extremely low off-state current characteristics, only a few μA / μm (current value per channel width of 1 μm). This low off-state current enhances the node's potential retention capability, allowing for appropriate image display even at lower frame frequencies. For example, using a first frame frequency (e.g., 60Hz or higher) when displaying moving images, and switching to a second frame frequency (e.g., around 1 to 10Hz) lower than the first frame frequency when displaying static images, can achieve low power consumption in the display device.

[0059] As semiconductor materials for OS transistors, metal oxides with band gaps of 2 eV or higher, preferably 2.5 eV or higher, and more preferably 3 eV or higher can be used. Typical examples include indium-containing oxide semiconductors, such as CAAC-OS or CAC-OS mentioned later. CAAC-OS has stable atoms constituting the crystal, making it suitable for transistors where reliability is critical. CAC-OS exhibits high mobility characteristics, making it suitable for transistors used in high-speed driving.

[0060] Unlike transistors that contain silicon in the channel formation region (hereinafter referred to as Si transistors), OS transistors do not experience impact ionization, sudden collapse, short-channel effects, etc., and therefore can form highly reliable circuits.

[0061] Examples of metal oxides that can be used as semiconductor layers in OS transistors include indium oxide, gallium oxide, and zinc oxide. Preferably, the metal oxide comprises two or three elements selected from indium, element M, and zinc. Element M is selected from one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Particularly preferred is element M selected from one or more of aluminum, gallium, yttrium, and tin.

[0062] In particular, as the metal oxide used for the semiconductor layer, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also denoted as IGZO). Alternatively, it is preferable to use an oxide containing indium, tin, and zinc (also denoted as ITZO). Alternatively, it is preferable to use an oxide containing indium, gallium, tin, and zinc. Alternatively, it is preferable to use an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also denoted as IAZO). Alternatively, it is preferable to use an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also denoted as IAGZO).

[0063] When the metal oxide used for the semiconductor layer is an In-M-Zn oxide, the number of In atoms in the In-M-Zn oxide is preferably greater than or equal to the number of M atoms. Examples of such In-M-Zn oxide atomic ratios include In:M:Zn = 1:1:1 or similar, In:M:Zn = 1:1:1.2 or similar, In:M:Zn = 1:3:2 or similar, In:M:Zn = 1:3:4 or similar, In:M:Zn = 2:1:3 or similar, In:M:Zn = 3:1:2 or similar, and In:M: Compositions with Zn ratios of 4:2:3 or similar, In:M:Zn ratios of 4:2:4.1 or similar, In:M:Zn ratios of 5:1:3 or similar, In:M:Zn ratios of 5:1:6 or similar, In:M:Zn ratios of 5:1:7 or similar, In:M:Zn ratios of 5:1:8 or similar, In:M:Zn ratios of 6:1:6 or similar, and In:M:Zn ratios of 5:2:5 or similar, etc. Note that "simultaneous" composition includes a range of ±30% of the desired atomic ratio.

[0064] For example, when the atomic number ratio is described as In:Ga:Zn = 4:2:3 or similar, the following cases are included: when In is 4, Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. Furthermore, when the atomic number ratio is described as In:Ga:Zn = 5:1:6 or similar, the following cases are included: when In is 5, Ga is greater than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. Moreover, when the atomic number ratio is described as In:Ga:Zn = 1:1:1 or similar, the following cases are included: when In is 1, Ga is greater than 0.1 and 2 or less, and Zn is greater than 0.1 and 2 or less.

[0065] Alternatively, the semiconductor layer may also comprise two or more metal oxide layers with different compositions. For example, a preferred structure is a stacked structure comprising a first metal oxide layer with an In:M:Zn ratio of 1:3:4 or similar, and a second metal oxide layer disposed on the first metal oxide layer with an In:M:Zn ratio of 1:1:1 or similar. Furthermore, gallium or aluminum is particularly preferred as the element M.

[0066] Alternatively, for example, a stacked structure selected from any one of indium oxide, indium gallium oxide and IGZO and any one of IAZO, IAGZO and ITZO (registered trademark) may be used.

[0067] Note that the present invention is not limited to the above description, and an oxide semiconductor with an appropriate composition can be used according to the desired semiconductor characteristics and electrical characteristics (field-effect mobility, critical voltage, etc.) of the transistor. Furthermore, it is preferable to appropriately set the carrier concentration, impurity concentration, defect density, ratio of metal elements to oxygen atoms, interatomic distance, density, etc., of the semiconductor layer to obtain the desired semiconductor characteristics of the transistor.

[0068] When the oxide semiconductor constituting the semiconductor layer contains silicon or carbon, which are elements of Group 14, the oxygen defects increase, causing the semiconductor layer to become n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 2 × 10¹⁸ atoms / cm³ or less, preferably 2 × 10¹⁷ atoms / cm³ or less.

[0069] In addition, carriers are sometimes generated when alkali metals and alkaline earth metals bond with oxide semiconductors, which increases the off-state current of the transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 1×10¹⁸ atoms / cm³ or less, preferably 2×10¹⁶ atoms / cm³ or less.

[0070] Furthermore, when the oxide semiconductor constituting the semiconductor layer contains nitrogen, electrons are generated as carriers, increasing the carrier concentration and making it easier to form an n-type transistor. As a result, transistors with nitrogen-containing oxide semiconductors tend to become normally-on. Therefore, the nitrogen concentration of the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is preferably 5 × 10¹⁸ atoms / cm³ or less.

[0071] Furthermore, when the oxide semiconductor constituting the semiconductor layer contains hydrogen, the hydrogen reacts with the oxygen bonded to the metal atoms to form water, thus sometimes creating oxygen vacancies in the oxide semiconductor. When the channel-forming region in the oxide semiconductor contains oxygen vacancies, the transistor tends to have always-on characteristics. Moreover, sometimes hydrogen entering the defects in the oxygen vacancies acts as a donor, generating electrons as carriers. Additionally, sometimes a portion of the hydrogen bonds with the oxygen bonded to the metal atoms, generating electrons as carriers. Therefore, transistors using oxide semiconductors containing more hydrogen tend to have always-on characteristics.

[0072] Defects where hydrogen enters oxygen vacancies can be used as donors in oxide semiconductors. However, it is difficult to quantitatively evaluate these defects. Therefore, in oxide semiconductors, evaluation is sometimes based on carrier concentration rather than donor concentration. Consequently, in this specification and the like, carrier concentration, which is assumed to be in a state where no electric field is applied, is sometimes used as a parameter for oxide semiconductors instead of donor concentration. That is to say, the "carrier concentration" described in this specification and the like can sometimes be referred to as "donor concentration".

[0073] Therefore, it is preferable to minimize the amount of hydrogen in the oxide semiconductor. Specifically, in the oxide semiconductor, the hydrogen concentration, as measured by secondary ion mass spectrometry (SIMS), is less than 1 × 10²⁰ atoms / cm³, more preferably less than 1 × 10¹⁹ atoms / cm³, even more preferably less than 5 × 10¹⁸ atoms / cm³, and further preferably less than 1 × 10¹⁸ atoms / cm³. By using oxide semiconductors with sufficiently reduced impurities such as hydrogen in the channel formation region of transistors, stable electrical properties can be imparted.

[0074] Furthermore, the semiconductor layer can also have a non-single-crystal structure. Non-single-crystal structures include, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) with c-axis alignment, polycrystalline structures, microcrystalline structures, or amorphous structures. Among non-single-crystal structures, amorphous structures have the highest defect state density, while CAAC-OS has the lowest.

[0075] Amorphous oxide semiconductor films, for example, have a disordered atomic arrangement and lack crystalline components. Alternatively, amorphous oxide films can be, for example, completely amorphous structures without crystalline regions.

[0076] Furthermore, the semiconductor layer can also be a mixture of two or more regions having an amorphous structure, a microcrystalline structure, a polycrystalline structure, a CAAC-OS region, and a single-crystal structure. The mixture sometimes has, for example, a single-layer structure or a stacked structure including two or more of the aforementioned regions.

[0077] The following describes the configuration of CAC (Cloud-Aligned Composite)-OS in one embodiment of a non-single-crystal semiconductor layer.

[0078] CAC-OS, for example, refers to a composition in which elements are non-uniformly distributed within an oxide semiconductor, wherein the size of the material containing the non-uniformly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or approximately. Note that, below, the state in which one or more metal elements are non-uniformly distributed within an oxide semiconductor, and the regions containing those metal elements are mixed with sizes of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or approximately, is also referred to as mosaic or patch-like.

[0079] The oxide semiconductor preferably contains at least indium. In particular, it preferably contains both indium and zinc. In addition, it may also contain one or more of the following: aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0080] For example, CAC-OS in In-Ga-Zn oxide (in particular, In-Ga-Zn oxide can be called CAC-IGZO) refers to a material composed of indium oxide (hereinafter referred to as InO X1 (X1 is a real number greater than 0)) or indium zinc oxide (hereinafter referred to as In X2Zn Y2O Z2 (X2, Y2 and Z2 are real numbers greater than 0)) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter referred to as Ga X4Zn Y4O Z4 (X4, Y4 and Z4 are real numbers greater than 0)) etc., forming a mosaic pattern, and the mosaic-shaped InO X1 or In X2Zn Y2O Z2 is uniformly distributed in the film (hereinafter also referred to as cloud-like).

[0081] In other words, CAC-OS is a composite oxide semiconductor composed of regions with GaO X3 as the main component and regions with In X2Zn Y2O Z2 or InO X1 as the main components. In this specification, for example, when the ratio of the number of In atoms to the number of M atoms in the first region is greater than that in the second region, the In concentration in the first region is higher than that in the second region.

[0082] Note that IGZO is a general term, sometimes referring to compounds containing In, Ga, Zn, and O. As a typical example, one could cite... InGaO3(ZnO) m1 (m1 is a natural number) or In (1+x0)Ga (1-x0)O 3(ZnO) m0 (-1≤x0≤1, m0 is any number) represents a crystalline compound.

[0083] The aforementioned crystalline compounds have single-crystal, polycrystalline, or CAAC structures. The CAAC structure is a crystalline structure in which multiple IGZO nanocrystals have c-axis orientation and are connected in a non-oriented manner on the ab plane.

[0084] On the other hand, CAC-OS is related to the material composition of oxide semiconductors. CAC-OS refers to a material composition containing In, Ga, Zn, and O, in one part of which nanoparticle-like regions with Ga as the main component are observed, and in another part, nanoparticle-like regions with In as the main component are observed to be randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0085] CAC-OS does not contain stacked structures consisting of two or more different membranes. For example, it does not contain a structure consisting of two layers: one with In as the main component and the other with Ga as the main component.

[0086] Note that sometimes it is not possible to observe a clear boundary between regions with GaO X3 as the main component and regions with In X2Zn Y2O Z2 or InO X1 as the main components.

[0087] In the case where CAC-OS contains one or more of aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium to replace gallium, CAC-OS refers to a composition in which nanoparticle-like regions with the metal element as the main component are observed in one part, and nanoparticle-like regions with In as the main component are observed to be randomly dispersed in a mosaic pattern in another part.

[0088] CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gases, and nitrogen gases can be used as the deposition gas. Furthermore, the lower the oxygen gas flow rate in the total flow rate of the deposition gas during film formation, the better; for example, the oxygen gas flow rate ratio should be set to 0% or more and less than 30%, preferably 0% or more and less than 10%.

[0089] CAC-OS has the following characteristics: when measured using the out-of-plane method, one of the X-ray diffraction (XRD) methods, with θ / 2θ scanning, no clear peak is observed. In other words, according to X-ray diffraction, there is no alignment in the ab plane direction and the c-axis direction in the measurement region.

[0090] Furthermore, in the electron diffraction pattern of CAC-OS obtained by irradiating it with an electron beam with a diameter of 1 nm (also known as a nano-beam), a bright annular region and multiple bright spots within that annular region were observed. Therefore, based on the electron diffraction pattern, it can be concluded that the crystal structure of CAC-OS possesses an nc (nano-crystal) structure without alignment in either the planar or cross-sectional directions.

[0091] Furthermore, for example, in CAC-OS of In-Ga-Zn oxides, based on EDX surface analysis (mapping) images obtained by Energy Dispersive X-ray spectroscopy (EDX), it can be confirmed that there is a non-uniformly distributed mixture of regions with GaO X3 as the main component and regions with In X2Zn Y2O Z2 or InO X1 as the main components.

[0092] The structure of CAC-OS differs from that of IGZO compounds, where metallic elements are uniformly distributed, and thus exhibits different properties. In other words, CAC-OS has a mosaic-like structure with regions dominated by GaO X3 and others dominated by In X2Zn Y2O Z2 or InO X1, and the regions dominated by each element are separated.

[0093] Here, the conductivity of regions with InX2ZnY2OZ2 or InOX1 as the main components is higher than that of regions with GaOX3 as the main component. In other words, when carriers flow through regions with InX2ZnY2OZ2 or InOX1 as the main components, they exhibit the conductivity of oxide semiconductors. Therefore, when regions with InX2ZnY2OZ2 or InOX1 as the main components are distributed in a cloud-like pattern in an oxide semiconductor, a high field-efficiency mobility (μ) can be achieved.

[0094] On the other hand, regions with GaO X3 as the main component have higher insulation properties than regions with In X2ZnY2OZ2 or InO X1 as the main components. In other words, when regions with GaO X3 as the main component are distributed in oxide semiconductors, leakage current can be suppressed and good switching operation can be achieved.

[0095] Therefore, when CAC-OS is used in semiconductor devices, high on-state current (Ion) and high field-effect mobility (μ) can be achieved through the complementary effect of the insulation caused by GaO X3 and the conductivity caused by In X2Zn Y2O Z2 or InO X1.

[0096] Furthermore, semiconductor devices using CAC-OS exhibit high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0097] Alternatively, any one or more of transistors 102 to 105 may be formed of an OS transistor. Or, any one or more of transistors 102 to 105 may also be formed of a transistor (hereinafter, Si transistor) whose channel forming region contains silicon.

[0098] The channel forming region of a Si transistor can be made of amorphous silicon, microcrystalline silicon, polycrystalline silicon, monocrystalline silicon, etc. Note that when placing the transistor on an insulating surface such as a glass substrate, polycrystalline silicon is preferred.

[0099] High-quality polycrystalline silicon can be easily obtained using processes such as laser crystallization. Furthermore, high-quality polycrystalline silicon can also be obtained through solid-state growth methods that involve adding metal catalysts such as nickel or palladium to amorphous silicon and then heating it. Additionally, laser irradiation of polycrystalline silicon formed using solid-state growth methods with metal catalysts can further improve its crystallinity. Note that since the metal catalyst remains in the polycrystalline silicon, it degrades the electrical properties of the transistor. Therefore, it is preferable to create a region outside the channel formation region where phosphorus or a rare gas is added, and to trap the metal catalyst in that region.

[0100] Note that, in order to achieve the effect of one embodiment of the present invention, the structure is not limited to the above description, and all transistors included in the pixel can also be formed using Si transistors. Alternatively, one or more transistors included in the pixel can also be formed using p-channel transistors.

[0101] Figure 3A is a diagram showing an example of a display device with a stacked structure, and Figure 3B is an unfolded view and an enlarged view of a portion thereof. The display device with the stacked structure can be stacked in the following order: a layer 310 including a silicon substrate, a layer 320 including wiring, and a layer 330 including light-emitting devices. In this stacked structure, circuits can be overlapped, thus allowing for a narrow bezel in the display device.

[0102] Layer 310 may include Si transistors 311 as components of pixel circuitry and functional circuitry 312. Note that Si transistors 311 may be configured in an area that does not affect the functional circuitry 312. Si transistors 311 are, for example, equivalent to transistors 103, 106, and 107 in FIG. 2A. Layer 320 may include OS transistors 321 as components of pixel circuitry. Layer 330 may include an LED array 331.

[0103] LED array 331 employs an LED configuration in a matrix structure. For example, Micro LEDs with a diameter or one side less than 50 μm can be used, or Mini LEDs with a diameter or one side greater than 50 μm and less than 200 μm can be used.

[0104] As a functional circuit 312, one or more of the following can be provided: a source driver, a gate driver, a memory circuit, an arithmetic circuit, and a power supply circuit. Additionally, as a functional circuit 312, a pulse signal generation unit included in pixel 10a can also be provided. Note that part or all of the gate driver and memory circuit can also be formed using an OS transistor. Details of the stacked structure will be described in Embodiment 2.

[0105] Next, the operation of transistor 104 will be described with reference to Figures 2B to 2D. Transistor 104 includes a first gate and a second gate, and the threshold voltage (Vth) can be shifted by supplying an appropriate potential to the second gate. Transistor 104 can shift Vth in response to the data potential VDATA supplied as image data, and the turn-on timing can be controlled by the ramp potential SLO supplied to the source.

[0106] In other words, transistor 104 can change its conduction timing according to the magnitude of the data potential VDATA. This allows, for example, PAM control to be used at low and high grayscale levels, while switching to PAM+PWM control at intermediate grayscale levels. The specific effects of the grayscale-based switching control method will be explained later.

[0107] Figure 2B is a timing diagram illustrating the potential (Vbg) applied to the second gate (node ​​BG) of transistor 104. Here, the ramp potential SLO supplied to wiring 122 is a signal potential that varies from the upper end (SLO_H) to the lower end (SLO_L) over time, as shown in Figure 2C. The data potential VDATA supplied to wiring 121 is related to the ramp potential SLO in the order SLO_H > VDATA > SLO_L.

[0108] First, a high potential is supplied to wiring 131, 133, and 135 to turn on the transistors, thereby turning on transistors 101, 105, and 108.

[0109] At this time, the potential of node BS becomes VDATA, and the potential of node BG becomes VSBG. In addition, wiring 122 is in a standby state ready to supply the upper potential SOL_H of the ramp potential SLO, and the second gate-source voltage (Vbgs) of transistor 104 becomes VSBG-SLO_H.

[0110] Next, transistors 101, 105, and 108 are made non-conductive, and a high potential is supplied to wiring 136 to make the transistors conduct, thereby turning on transistor 109.

[0111] When the ramp potential SLO is supplied simultaneously, the potential of node BS becomes SLO. At this time, the potential of node BG is VSBG-VDATA+SLO due to the capacitive coupling of capacitor 113. The potential of node BG in the initial stage of the ramp potential SLO supply can be VSBG-VDATA+SLO_H.

[0112] Subsequently, the potential of node BG decreases with the ramp potential SLO. As shown in Figure 2D, the source of transistor 104 is also supplied with a ramp potential SLO. Therefore, the Vbgs of transistor 104 is VSBG - VDATA + SLO - SLO = VSBG - VDATA, which is constant regardless of the magnitude of the ramp potential SLO that changes over time.

[0113] Therefore, the Vth of transistor 104 can be shifted by a certain amount according to the magnitude of the data potential VDATA. In the pulse signal generation unit 11, the width of the generated pulse signal can be controlled by the Vth shift corresponding to the magnitude of the data potential VDATA.

[0114] Next, proceed with the operation of pixel 10a according to the grayscale specifications. Furthermore, for the data potentials VDATA described below, VDATA1 is used for low grayscale, VDATA2 for intermediate grayscale, and VDATA3 for high grayscale. Furthermore, since the transistor 103 driving the light-emitting device 110 is a p-channel type transistor, the potential magnitudes are VDATA1>VDATA2>VDATA3.

[0115] For example, VDATA1 is a data potential used to make the light-emitting device 110 emit light in an 8-bit grayscale range from grayscale 0 to a grayscale smaller than the lower end of the intermediate grayscale. VDATA2 is a data potential used to make the light-emitting device 110 emit light in the range from the lower end to the upper end of the intermediate grayscale. VDATA3 is a data potential used to make the light-emitting device 110 emit light in the range from grayscale greater than the upper end of the intermediate grayscale to grayscale 255. Here, the range of the intermediate grayscale can be set arbitrarily; for example, it can be set to a range from grayscale 32 to grayscale 127, etc.

[0116] Figure 4A shows the characteristics of transistor 104 and its drain current-gate voltage (I dV g) when the light-emitting device 110 is emitted at a low gray level using VDATA1 as the data potential.

[0117] First, when node BG of transistor 104 is supplied with potential VSBG and becomes Vbgs = VSBG - SLO_H, the IdVg curve of transistor 104 drifts positively from its initial position (not shown) towards the position indicated by the dashed line. Then, due to the capacitive coupling of capacitor 113, when Vbgs becomes VSBG - VDATA1, the IdVg curve of transistor 104 drifts negatively towards the position indicated by the solid line and remains fixed. The changes in Vbgs will be explained in detail in the subsequent description of the operation of pixel 10a.

[0118] Figure 4A shows the data potential VDATA1 and the threshold voltage (V th1) applied to the first gate of transistor 104 at this time, and shows that transistor 104 turns on when V gs becomes larger than +V gs1.

[0119] In transistor 104, the potential applied to the first gate is fixed at VDATA1, and Vgs is changed by supplying a ramp potential SLO to the source to scan the potential from high to low.

[0120] Figure 4B is a graph illustrating the relationship between the ramp potential SLO, the data potential VDATA1, and the light emission period of the light-emitting device 110.

[0121] The data potential VDATA1 is a value near the upper end (SLO_H) of the ramp potential SLO. When SLO = VDATA1, Vgs = 0. Based on this, when the ramp potential SLO decreases by increasing Vgs + Vgs1, the Vg of transistor 104 reaches Vth1, and transistor 104 becomes conductive.

[0122] The light-emitting device 110 begins to emit light after resetting nodes N and W and writing the data potential DATA1 to node A. It continues to emit light until transistor 104 becomes conductive. When transistor 104 becomes conductive, the potential of node W decreases, and transistor 107 becomes conductive, thereby changing the potential of node A from DATA1 to the reset potential VRESA. At this point, the light-emitting device 110 stops emitting light.

[0123] As shown in Figure 4B, the ramp potential SLO turns on transistor 104 just before it reaches the lower end SLO_L. By adjusting the relationship between the ramp potential SLO, the data potential VDATA1, and the drift of Vth1 in such a way that the light-emitting device 110 can emit light during almost all frame periods. In other words, it can also be said that PAM control is performed when VDATA1 is used as the data potential.

[0124] Figure 5A shows the characteristics of transistor 104 and its drain current-gate voltage (I dV g) when the light-emitting device 110 is illuminated by using VDATA2 as the data potential with an intermediate gray level.

[0125] First, when node BG of transistor 104 is supplied with potential VSBG and becomes Vbgs = VSBG - SLO_H, the IdVg curve of transistor 104 drifts positively from its initial position (not shown) towards the position indicated by the dashed line. Then, due to the capacitive coupling of capacitor 113, when Vbgs becomes VSBG - VDATA2, the IdVg curve of transistor 104 drifts negatively towards the position indicated by the solid line and remains fixed.

[0126] Figure 5A shows the data potential VDATA2 and the threshold voltage (V th2) applied to the first gate of transistor 104 at this time, and shows that transistor 104 turns on when V gs becomes larger than +V gs2.

[0127] In transistor 104, the potential applied to the first gate is fixed at VDATA2, and Vgs is changed by supplying a ramp potential SLO to the source to scan the potential from high to low.

[0128] Figure 5B is a graph illustrating the relationship between the ramp potential SLO, the data potential VDATA2, and the light emission period of the light-emitting device 110.

[0129] The data potential VDATA2 is a smaller value than VDATA1. When SLO = VDATA2, Vgs = 0. Based on this, when SLO decreases in the manner of Vgs increasing + Vgs2, the Vg of transistor 104 reaches Vth2, and transistor 104 becomes conductive.

[0130] The light-emitting device 110 begins to emit light after resetting nodes N and W and writing the data potential DATA2 to node A. It continues to emit light until transistor 104 becomes conductive. When transistor 104 becomes conductive, the potential of node W decreases, and transistor 107 becomes conductive, thereby changing the potential of node A from DATA2 to the reset potential VRESA. At this point, the light-emitting device 110 stops emitting light.

[0131] As shown in Figure 5B, transistor 104 is turned on during the decrease of the ramp potential SLO. By adjusting the relationship between the ramp potential SLO, the data potential VDATA2, and the drift of Vth2 in such a manner, the light-emitting device 110 can be made to stop emitting light midway through the frame period. In other words, in addition to emitting light using the data potential DATA2, the emitting period can also be controlled to be shorter. Therefore, it can be said that PAM+PWM control is performed when VDATA2 is used as the data potential.

[0132] Figure 6A shows the characteristics of transistor 104 and its drain current-gate voltage (I dV g) when the light-emitting device 110 is illuminated at a low gray level using VDATA3 as the data potential.

[0133] First, when node BG of transistor 104 is supplied with potential VSBG and becomes Vbgs = VSBG - SLO_H, the IdVg curve of transistor 104 drifts positively from its initial position (not shown) towards the position indicated by the dashed line. Then, due to the capacitive coupling of capacitor 113, when Vbgs becomes VSBG - VDATA1, the IdVg curve of transistor 104 drifts negatively towards the position indicated by the solid line and remains fixed.

[0134] Figure 6A shows the data potential VDATA3 and the threshold voltage (V th3) ​​applied to the first gate of transistor 104 at this time, and shows that transistor 104 turns on when V gs becomes greater than +V gs3.

[0135] In transistor 104, the potential applied to the first gate is fixed at VDATA3, and Vgs is changed by supplying a ramp potential SLO to the source to scan the potential from high to low.

[0136] Figure 6B is a graph illustrating the relationship between the ramp potential SLO, the data potential VDATA3, and the light emission period of the light-emitting device 110.

[0137] The data potential VDATA3 is a value near the upper end (SLO_H) of the ramp potential SLO. When SLO = VDATA1, Vgs = 0. Based on this, when the ramp potential SLO decreases in the manner of Vgs rising + Vgs3, the Vg of transistor 104 reaches Vth3, and transistor 104 becomes conductive.

[0138] The light-emitting device 110 begins to emit light after resetting nodes N and W and writing the data potential DATA3 to node A. It continues to emit light until transistor 104 becomes conductive. When transistor 104 becomes conductive, the potential of node W decreases, and transistor 107 becomes conductive, thereby changing the potential of node A from DATA3 to the reset potential VRESA. At this point, the light-emitting device 110 stops emitting light.

[0139] As shown in Figure 6B, the ramp potential SLO turns on transistor 104 just before it reaches the lower SLO_L. By adjusting the relationship between the ramp potential SLO, the data potential VDATA3, and the drift of Vth3 in such a way, the light-emitting device can emit light during almost all frame periods. In other words, it can be said that PAM control is performed when VDATA3 is used as the data potential.

[0140] Next, referring to the timing chart shown in FIG. 7 and the diagrams illustrating the operation of the circuit in FIGS. 8A to 9B, the operation of pixel 10a when using the data potential VDATA2 of the intermediate gray scale will be described. Note that the dashed arrows shown in FIGS. 8A to 9B indicate the potentials supplied to the inside of the circuit, and the dotted arrows indicate the current (ILED) flowing through the light emitting device 110.

[0141] First, at time T1, a low potential ("L") is supplied to wirings 131, 132, 133, 134, 135, 136. At this time, transistor 107 is turned on, and the reset potential VRESW (low potential) supplied to wiring 123 is supplied to node W (refer to FIG. 8A). This operation is the reset operation of node W, and at this time, transistor 106 becomes non-conductive.

[0142] At time T2, a high potential ("H") is supplied to wirings 131, 132, 133, 134, 135, and a low potential ("L") is supplied to wiring 136. At this time, transistor 107 becomes non-conductive. In addition, transistors 101, 102, 105 are turned on, and the data potential VDATA2 is supplied to node N, node BS, and node A. And, transistor 103 is turned on, and the light emitting device 110 emits light according to the data potential VDATA2 (refer to FIG. 8B).

[0143] In addition, transistor 108 is turned on, and the potential VSBG (low potential) supplied to wiring 128 is supplied to node BG. At this time, wiring 122 is supplied with the same potential as the upper end (SLO_H) of the ramp potential SLO, and the Vbgs of transistor 104 becomes VSBG - SLO_H. Here, since VSBG < SLO_H, the Id-Vg characteristics of transistor 104 are greatly positively shifted as shown by the dashed Id-Vg curve in FIG. 5A.

[0144] At time T3, a low potential ("L") is supplied to wirings 131, 132, 133, 135, and a high potential ("H") is supplied to wirings 134, 136. At this time, transistors 101, 102, 105, 108 become non-conductive, and transistor 109 is turned on (refer to FIG. 9A).

[0145] In addition, from time T3 to time T10, the ramp potential SLO is supplied to wiring 122. Here, since the potential of node BS is rewritten from VDATA2 to SLO, the potential of node BG becomes VSBG - VDATA2 + SLO due to the capacitive coupling of capacitor 113.

[0146] Furthermore, a ramp potential SLO is also supplied to the source of transistor 104. Therefore, the Vbgs of transistor 104 becomes VSBG - VDATA2 + SLO - SLO = VSBG - VDATA2, and remains a fixed value unaffected by the ramp potential SLO. Thus, the Id-Vg characteristic of transistor 104 drifts negatively and remains fixed, as shown by the solid line in Figure 5A.

[0147] Transistor 104 will not turn on until the increase in V gs due to the decrease in ramp potential SLO reaches +V gs2 (see Figures 5A and 5B). Figure 9A shows the state before the increase in V gs reaches +V gs2 (VDATA2-SLO<+V gs2), during which time the light-emitting device 110 continues to emit light.

[0148] Figure 9B shows an example where the increase in V gs at time T8 is greater than the +V gs2 state (VDATA2-SLO>+V gs2). Transistor 104 turns on, the potential of node W drops to SLO, and transistor 106 turns on. Furthermore, the reset potential VRESA (high potential) supplied to wiring 124 is supplied to node A, transistor 103 becomes non-conductive, and the light-emitting device 110 stops emitting light.

[0149] As described above, PAM+PWM control can be performed by using the data potential DATA2, which stops the light-emitting device 110 from emitting light midway through the slope potential SLO.

[0150] Figure 10 is a timing diagram illustrating the operation of pixel 10a when using a low grayscale data potential VDATA1 or a high grayscale data potential VDATA3.

[0151] Figure 10 differs from Figure 7 in that it uses VDATA1 or VDATA3 as the data potential. When the ramp potential SLO reaches the lower end of SLO_L or its vicinity, the stop crystal 104 remains on while the light-emitting device 110 continues to emit light. Therefore, the light-emitting device 110 emits light for most of the frame, which can be said to be PAM control.

[0152] Note that pixel 10a differs from the above-mentioned operation; it can be controlled by PAM or PWM across the entire grayscale.

[0153] For example, by supplying a reset potential VRESA to node A without turning on transistor 102, the light-emitting device 110 can be made to emit light simply by PWM control.

[0154] Furthermore, by replacing the ramp potential SLO to continuously supply a high potential (e.g., a potential of the same level as SLO_H) to prevent the transistor 104 from becoming conductive, the transistor 106 remains in a non-conductive state. Thus, the light-emitting device 110 can emit light using only PAM control.

[0155] Alternatively, the pixel in one embodiment of the present invention can also adopt the structure of pixel 10b shown in FIG11A. The structure shown in FIG11A differs from pixel 10a shown in FIG2A in that another of the source and drain electrodes of transistor 108 is electrically connected to wiring 122.

[0156] While pixel 10a shows an example of supplying VSBG from wiring 128 to node BG as an initial back gate potential, pixel 10b supplies a ramp potential SLO. In this case, it is preferable that the initial ramp potential is a low potential that does not cause transistor 104 to become conductive. By employing this structure, wiring 128 can be reduced.

[0157] Additionally, as shown in FIG11B, wirings 131, 132, 133, and 135 can also be connected to the common gate line GL. As shown in the timing diagrams of FIG7 and FIG10, these wirings can be supplied with the same potential at the same timing, thereby allowing them to share wiring. Furthermore, although FIG11B shows a structural example of pixel 10a, pixels with other structures shown in this embodiment can also use the common gate line GL.

[0158] Alternatively, as shown in pixel 10c of FIG12A, one electrode (anode) of the light-emitting device can be electrically connected to wiring 125, and the other electrode (cathode) can be electrically connected to another of the source and drain electrodes of transistor 103. The structures of pixels 10a and 10c can be distinguished according to the specifications of the terminals of the light-emitting device 110 used.

[0159] Furthermore, in the structures of pixels 10a, 10b, and 10c, when using OS transistors as n-channel transistors, as shown in Figure 12B, transistors 101, 102, 105, 108, and 109 can also be used with a back gate. By supplying the back gate with the same potential as the front gate, the on-state current can be increased. Alternatively, a structure with a constant potential supplied to the back gate can also be used. By supplying a constant potential to the back gate, the threshold voltage can be controlled.

[0160] In addition, in order to improve the display quality of the display device, the Vth of the transistor 103, which drives the light-emitting device 110, can also be calibrated.

[0161] For example, as shown in FIG13A, the internal correction of V th of transistor 103 can be performed by adding transistor 115, transistor 116 and capacitor 114 to the structure shown in FIG1.

[0162] One of the source and drain terminals of transistor 115 is electrically connected to the other of the source and drain terminals of transistor 103 and one electrode of capacitor 114. The other of the source and drain terminals of transistor 115 is electrically connected to the other electrode of capacitor 114 and wiring 125. The gate of transistor 115 is electrically connected to wiring 137.

[0163] One of the source and drain terminals of transistor 116 is electrically connected to one of the source and drain terminals of transistor 103. The other of the source and drain terminals of transistor 116 is electrically connected to wiring 139. The gate of transistor 116 is electrically connected to wiring 138.

[0164] Wiring 137 and 138 function as gate lines for controlling the conduction of each transistor. Wiring 139 is a discharge path and can be set as a low-potential line. The high power supply potential supplied to wiring 125 is denoted as LVDD. Wiring 121 is alternately supplied with data potential VDATA and potential V0 for a certain period. Potential V0 can be any potential at which transistor 103 conducts when its source potential is LVDD and its gate potential is V0; for example, it can be set to a low potential such as 0V.

[0165] Transistor 115 serves as a switch to temporarily fix the source potential of transistor 103. Transistor 116 functions as a switch connecting transistor 103 to wiring 139, which is the discharge path, when Vth is obtained. Although Figure 13A shows an example using an n-channel transistor for transistors 115 and 116, a p-channel transistor can also be used. Capacitor 114 is a storage capacitor for the source potential of transistor 103 and has a capacitance sufficiently large than that of capacitor 111.

[0166] The Vth correction operation of transistor 103 will be explained with reference to the timing diagram shown in Figure 13B and the circuit diagrams illustrating the operation in Figures 14A to 15B. Note that the explanation of the operation related to the light emission of light-emitting device 110 is the same as the previous explanation and is omitted.

[0167] First, at time T1, a high potential (“H”) is supplied to wiring 137 to turn on transistor 115. At this time, the source potential of transistor 103 becomes LVDD (see Figure 14A).

[0168] At the start of time T2, a potential V0 is supplied to wiring 121. During this timing sequence, high potentials (“H”) are supplied to wirings 131 and 138. Additionally, a low potential (“L”) is supplied to wiring 137. At this time, transistors 101 and 102 are turned on, and the gate of transistor 103 is supplied with potential V0. Furthermore, transistor 115 is in a non-conducting state while transistor 116 is turned on, and transistor 103 is turned on, causing the source potential to begin to decrease. Then, as the source potential discharges from LVDD to V0-Vth, transistor 103 becomes non-conducting (see Figure 14B).

[0169] Between time T2 and time T3, the potential supplied to wiring 121 switches from V0 to VDATA. During this timing, a high potential (“H”) is supplied to wiring 132. Conversely, a low potential (“L”) is supplied to wiring 138, causing transistor 116 to become non-conductive. At this time, the gate of transistor 103 is supplied with the data potential VDATA.

[0170] Here, since capacitor 114 has a sufficiently large capacitance than capacitor 111, the source potential of transistor 103 is substantially maintained at V0-Vth (see Figure 15A). Therefore, the Vgs of transistor 103 at this time is VDATA-V0+Vth.

[0171] At time T3, a high potential (“H”) is supplied to wiring 137, and a low potential (“L”) is supplied to wirings 131 and 132. At this time, transistors 101 and 102 become non-conductive, and the source potential of transistor 103 becomes LVDD. Furthermore, according to Vgs = VDATA - V0 + Vth held by capacitor 111, transistor 103 becomes conductive, and current ILED flows through the light-emitting device 110 (see Figure 15B).

[0172] The ILED follows the mathematical formula Id = β / 2(Vgs - Vth)², which governs the drain current flowing through transistor 103. Here, β is a coefficient. When Vgs = VDATA - V0 + Vth is substituted into the above formula, the term containing Vth is eliminated, meaning the drain current is unaffected by Vth. In other words, the ILED is unaffected by deviations in Vth of transistor 103, thereby improving the display quality of the display device.

[0173] Next, the effect of switching between PAM control and PAM+PWM control, which can be implemented in one embodiment of the present invention, will be explained.

[0174] Figure 16A is a graph showing the relationship between grayscale (8-bit input value) and brightness (output value) according to the γ curve (γ value = 2). Pixels 10a to 10c of one embodiment of the present invention can perform the input and output shown in Figure 16A, and the operating method can be switched within a desired grayscale range.

[0175] For example, the low-brightness 32 grayscale levels (equivalent to grayscale levels 0 to 31) and high-brightness 128 grayscale levels (equivalent to grayscale levels 128 to 255) operate using PAM control, while the intermediate 96 grayscale levels (equivalent to grayscale levels 32 to 127) operate using PWM+PWM control. This allows for the display of images with minimal color shift. Note that this is not a limitation; the operating method and switching timing can be arbitrarily set. Alternatively, the entire area can operate using either PAM control or PWM control.

[0176] Figure 16B illustrates the above operation using the luminous intensity and emission time of the light-emitting device. The values ​​indicated by the inside of the markings or arrows are the grayscale input values.

[0177] Low-brightness 32-grayscale and high-brightness 128-grayscale devices operate under PAM control for a relatively long emission time to make the light-emitting device emit light. PAM control can control the light intensity of the light-emitting device by controlling the amplitude, so even low brightness, which is difficult to control in PWM control, can be precisely controlled.

[0178] In the middle 96 gray levels, PAM+PWM control is performed by varying both the luminous intensity and the pulse signal width within a moderate range, thereby causing the light-emitting device to emit light. Since the middle 96 gray levels do not require an extremely short emission period (an extremely short pulse signal), PWM control can still be used effectively. Because control in the middle 96 gray levels is achieved by changing both the luminous intensity and the emission time, it can be called PAM+PWM control.

[0179] Figure 17A is an example illustrating the peak wavelength change when the brightness of the light-emitting device is changed in PAM control. The difference between the minimum and maximum values ​​in the above characteristics represents the range of chromaticity shift (R1). The chromaticity shift is larger when the light-emitting device is operated by PAM control from low to high brightness, which sometimes leads to a decrease in display quality.

[0180] Figure 17B is a diagram illustrating an example of peak wavelength variation when changing the brightness of the light-emitting device during the operation described with reference to Figures 16A and 16B. PAM+PWM control is performed within the range near the minimum value in Figure 17A, thus minimizing the peak wavelength variation within that range. Consequently, the range of chromaticity shift (R2) can be made smaller than R1. In other words, by using a display device according to one embodiment of the present invention and performing the above example, the degradation of display quality can be mitigated.

[0181] Figure 18 is a block diagram illustrating a display device according to one embodiment of the present invention. The display device includes a pixel array 13, a source driver 20, and a gate driver 30. The pixel array 13 includes pixels 10 arranged in the column direction and the row direction. Pixels 10a to 10c, as described in this embodiment, can be used as pixels 10. Note that wiring is simply shown, and wiring is provided to connect to the components included in the pixel 10 of the above-described embodiment of the present invention.

[0182] In addition, the display device includes a ramp potential supply circuit 40, which is electrically connected to the pixel 10. The ramp potential supply circuit 40 is also electrically connected to the ramp potential generation circuit 50.

[0183] Timing circuits such as shift registers can be used as source driver 20, gate driver 30, and ramp potential supply circuit 40. Note that source driver 20 can supply data potential VDATA to pixel 10.

[0184] Note that the source driver 20, gate driver 30, and ramp potential supply circuit 40 can be formed in layer 310 shown in Figures 3A and 3B. Additionally, they can be disposed in IC chips connected via COF (chip on film), COG (chip on glass), TCP (tape carrier package), or other methods.

[0185] This example shows a gate driver 30 configured on one side of the pixel array 13, but two gate drivers 30 can also be arranged opposite each other across the pixel array 13 and the drive rows can be divided.

[0186] This embodiment can be implemented by appropriately combining the structures described in other embodiments.

[0187] Implementation Method 2 In this embodiment, the stacked structure of a display device according to an embodiment of the present invention shown in FIG3A and FIG3B will be described.

[0188] Figure 19A shows a cross-sectional view of a display device 100A according to an embodiment of the present invention. The display device 100A has a structure in which a layer 310, in which a transistor including a driving circuit of a pixel circuit is disposed, a layer 320, in which a transistor including a pixel circuit and wiring are disposed, and a layer 330, in which a light-emitting device such as an LED included in the pixel circuit is disposed, are stacked in sequence.

[0189] Note that in this embodiment, the display device is described in multiple layers for ease of understanding, but the boundaries between layers are not strictly defined. For example, even a component described as a component of layer 310 can be considered a component of layer 320 if it is located near the boundary between layer 310 and layer 320. Furthermore, a component can be located in a layer other than layer 310 as long as its function is not impaired. Additionally, in one embodiment of the invention, other insulating and conductive layers besides the insulating and conductive layers included in each layer may be provided as needed. Furthermore, a portion of the insulating and conductive layers included in each layer may be omitted as needed.

[0190] Layer 310 includes, for example, a transistor 140 comprising components such as a pixel circuit driving circuit (one or both of a gate driver and a source driver), a memory circuit, an arithmetic circuit, etc. Because the transistor 140 needs to operate at high speed, it is preferable to use a transistor (hereinafter, Si transistor) that includes silicon (monocrystalline silicon, polycrystalline silicon, or amorphous silicon, etc.) in the channel formation region. Figure 19A shows an example of using monocrystalline silicon as a substrate 150, in which the transistor 140 includes a channel formation region.

[0191] A portion of the driving circuit for the pixel circuit can also be housed within an external IC chip connected to the pixel circuit.

[0192] Transistor 140 includes a conductive layer 145, an insulating layer 144, an insulating layer 146, and a pair of low-resistance regions 143. The conductive layer 145 serves as the gate. The insulating layer 144 is located between the conductive layer 145 and the substrate 150 and serves as the gate insulating layer. The insulating layer 146 is disposed covering the sides of the conductive layer 145 and serves as a sidewall. The pair of low-resistance regions 143 are doped regions in the substrate 150, one of which serves as the source of the transistor, and the other as the drain of the transistor. Additionally, a component separation layer 142 is disposed around the transistor.

[0193] An insulating layer 149 is provided over the transistor 140, and a conductive layer 148 is provided on the insulating layer 149. Furthermore, a conductive layer 147 is embedded in an opening provided in the insulating layer 149. The conductive layer 148 is electrically connected to one of a pair of low-resistance regions 143 via the conductive layer 147. Additionally, an insulating layer 151 is provided over the conductive layer 148. The conductive layer 148 serves as wiring. This wiring allows other transistors, pixel circuits, or other circuits in a circuit that includes the transistor 140 as a component to be electrically connected to each other.

[0194] Layer 320 includes a transistor 160, insulating layers 152, 162, 163, 181, 182, 183, conductive layers 184a, 184b, 185, 186, 187, conductive layers 192, 195, 196, and 197, which are components of the pixel circuit. One or more of these components are sometimes considered components of the transistor, but in this embodiment, they are not included in the description of transistor components. The conductive and insulating layers included in layer 320 are not limited to a single-layer structure and can also be in a stacked structure.

[0195] An insulating layer 152 is disposed on layer 310. The insulating layer 152 serves as an oxygen barrier layer to prevent impurities such as water and hydrogen from diffusing from layer 310 to transistor 160 and to prevent oxygen from detaching from the metal oxide layer 165 included in transistor 160 to the side of layer 310. As the insulating layer 152, for example, a film that is less susceptible to hydrogen and oxygen diffusion than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

[0196] Transistor 160 includes conductive layer 161, insulating layer 163, insulating layer 164, metal oxide layer 165, a pair of conductive layers 166, insulating layer 167, and conductive layer 168.

[0197] Transistor 160 is preferably a transistor (OS transistor) that includes a metal oxide layer 165 in the channel forming region. The metal oxide layer 165 has a first region overlapping one of a pair of conductive layers 166, a second region overlapping the other of the pair of conductive layers 166, and a third region between the first region and the second region.

[0198] OS transistors do not require bonding processes and can be formed in areas overlapping with Si transistors, separated by insulating layers. Therefore, multilayer devices can be manufactured with simple processes, thereby reducing manufacturing costs.

[0199] Furthermore, compared to transistors using amorphous silicon, OS transistors offer advantages such as high mobility enabling high-speed operation and high reliability. Additionally, the metal oxides used in OS transistors can be formed during the film deposition process, eliminating the need for laser devices required in the crystallization process of polycrystalline silicon. Therefore, by using OS transistors, inexpensive and highly reliable display devices can be manufactured.

[0200] A conductive layer 161 and an insulating layer 162 are disposed on the insulating layer 152, and an insulating layer 163 is disposed covering the conductive layer 161 and the insulating layer 162. An insulating layer 164 is disposed on the insulating layer 163, and a metal oxide layer 165 is disposed on the insulating layer 164.

[0201] Conductive layer 161 is used as a gate electrode, and insulating layers 163 and 164 are used as gate insulating layers. Conductive layer 161 has a region that overlaps with metal oxide layer 165 through insulating layers 163 and 164. Insulating layer 163 is preferably formed using the same material used as a barrier layer as insulating layer 152. Insulating layer 164 in contact with metal oxide layer 165 is preferably an oxide insulating film such as silicon oxide film.

[0202] A pair of conductive layers 166 are separately disposed on the metal oxide layer 165. One of the pair of conductive layers 166 is used as the source of a transistor, and the other is used as the drain. An insulating layer 181 is disposed covering the metal oxide layer 165 and the pair of conductive layers 166, and an insulating layer 182 is disposed on the insulating layer 181.

[0203] Openings extending to the metal oxide layer 165 are provided in insulating layers 181 and 182, and insulating layers 167 and 168 are embedded within these openings. These openings are located at a position overlapping a third region of the metal oxide layer 165. Insulating layer 167 has regions overlapping with the sides of insulating layers 181 and 182. Conductive layer 168 has regions overlapping with the sides of insulating layers 181 and 182, separated by insulating layers 167.

[0204] The conductive layer 168 is used as the gate electrode, and the insulating layer 167 is used as the gate insulating layer. The conductive layer 168 has a region that overlaps with the metal oxide layer 165 through the insulating layer 167.

[0205] Furthermore, insulating layers 183 and 185 are provided on the top surface covering insulating layers 182, 167 and conductive layers 168.

[0206] Insulating layers 181 and 183 are preferably formed using the same material as insulating layer 152, which is used as a barrier layer. By covering a pair of conductive layers 166 with insulating layer 181, oxidation of the pair of conductive layers 166 due to oxygen contained in insulating layer 182 can be suppressed.

[0207] A plug electrically connected to one of a pair of conductive layers 166 and conductive layer 195 is embedded in an opening provided in insulating layers 181, 182, 183, and 185. The plug may include a conductive layer 184b in contact with the side of the opening and the top surface of one of the pair of conductive layers 166, and a conductive layer 184a embedded inside the conductive layer 184b. The conductive layer 184b is preferably formed using a conductive material that does not readily diffuse hydrogen and oxygen.

[0208] The insulating layer 185 has a conductive layer 192, a conductive layer 195, and an insulating layer 186. Additionally, the insulating layer 186 has a conductive layer 196, a conductive layer 197, and an insulating layer 187. The conductive layer 195 is electrically connected to the conductive layer 196 via a plug. The conductive layer 192 is electrically connected to the conductive layer 197 via a plug.

[0209] Here, insulating layer 186 may have a planarization function. Insulating layer 187, conductive layer 196, and conductive layer 197 are used as bonding layers. Conductive layer 196 and conductive layer 197 have areas embedded in insulating layer 187. The surfaces of conductive layer 196, conductive layer 197, and insulating layer 187 are planarized in a manner that is consistent in height.

[0210] Layer 330 includes a light-emitting device 110 disposed on the support layer 118. The side surface of the light-emitting device 110 is sealed by an insulating layer 189, and the top surface of the light-emitting device 110 is provided with an insulating layer 188, a conductive layer 198, and a conductive layer 199. The conductive layer 198 is electrically connected to one electrode of the light-emitting device 110, and the conductive layer 199 is electrically connected to the other electrode of the light-emitting device 110. Preferably, an insulating resin layer or the like is used as the insulating layer 189.

[0211] Here, insulating layer 188, conductive layer 198, and conductive layer 199 are used as bonding layers. Conductive layer 198 and conductive layer 199 have areas embedded in insulating layer 188. The surfaces of conductive layer 198, conductive layer 199, and insulating layer 188 are planarized in a manner that is consistent in height.

[0212] The surfaces of layer 330 (insulating layer 188, conductive layer 198, and conductive layer 199) are bonded to the surfaces of layer 320 (insulating layer 187, conductive layer 196, and conductive layer 197). Here, insulating layer 188 and insulating layer 187 are bonded together. Conductive layer 198 and conductive layer 196 are bonded together and electrically connected. Conductive layer 199 and conductive layer 197 are bonded together and electrically connected.

[0213] Insulating layers 188 and 187 are preferably composed of the same composition. Furthermore, conductive layers 198 and 196 are preferably formed of a metal with the same main component. Additionally, conductive layers 199 and 197 are preferably formed of a metal with the same main component.

[0214] For example, insulating layers 187 and 188 are preferably formed by using one or more single layers or stacks of inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, hafnium oxide, and titanium nitride.

[0215] Alternatively, copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold can be used for conductive layers 196 to 199. Copper, aluminum, tungsten, or gold are preferred for ease of bonding.

[0216] Transistor 160 can be used as a transistor constituting a pixel circuit. Transistor 140 can be used as a transistor constituting a driving circuit (one or both of a gate driver and a source driver) used to drive the pixel circuit. Note that transistor 140 can also be a transistor constituting a pixel circuit. Furthermore, transistors 140 and 160 can also be used as transistors constituting various circuits such as arithmetic circuits and memory circuits.

[0217] By adopting this structure, in addition to forming components such as transistors included in the pixel circuit, components such as transistors included in the driving circuit can also be formed directly below the light-emitting device. Therefore, compared with the case where the driving circuit is set on the outside of the display section, the display device can be miniaturized. In addition, a display device with a narrow bezel (narrow non-display area) can be realized.

[0218] The light-emitting device 110 includes a semiconductor layer 173, a light-emitting layer 174, and a semiconductor layer 175, which are sequentially disposed on a support layer 118 in the aforementioned order. Additionally, a conductive layer 176 is provided on the semiconductor layer 173. The stack of the light-emitting layer 174 and the semiconductor layer 175, as well as the conductive layer 176, are covered by an insulating layer 117. The semiconductor layer 175 is electrically connected to the conductive layer 198 through a first opening in the insulating layer 117. The conductive layer 176 is electrically connected to the conductive layer 199 through a second opening in the insulating layer 117.

[0219] For example, gallium nitride or similar material formed on a sapphire substrate by epitaxial growth is used as a support layer 118, and semiconductor layers 173, 174, 175, insulating layers 117, and conductive layers 176 are formed on the support layer 118 to form multiple light-emitting devices 110. The multiple light-emitting devices formed by this process can be referred to as light-emitting devices formed with a monolithic structure.

[0220] Next, an insulating layer 189 and an adhesive layer are formed on the light-emitting device 110, and multiple light-emitting devices 110 are bonded to layer 320 in the same process. Then, a process of peeling off the sapphire substrate is performed to obtain the structure shown in the display device 100A.

[0221] A light-emitting layer 174 is sandwiched between semiconductor layers 173 and 175. In the light-emitting layer 174, electrons and holes bond to emit light. One of semiconductor layers 173 and 175 can be an n-type semiconductor layer, and the other can be a p-type semiconductor layer. Alternatively, the light-emitting layer 174 can be an n-type, i-type, or p-type semiconductor layer.

[0222] The stacked structure, including semiconductor layer 173, light-emitting layer 174, and semiconductor layer 175, is formed to emit light in the form of red, green, blue, blue-violet, purple, or ultraviolet light. For example, compounds containing Group 13 and Group 15 elements (also called Group 3-5 compounds) can be used as this stacked structure. Examples of Group 13 elements include aluminum, gallium, and indium. Examples of Group 15 elements include nitrogen, phosphorus, arsenic, and antimony.

[0223] For example, light-emitting devices that emit light can be manufactured by forming pn junctions or pin junctions using gallium-phosphorus compounds, gallium-arsenic compounds, gallium-aluminum-arsenic compounds, aluminum-gallium-indium-phosphorus compounds, gallium nitride, indium-gallium nitride compounds, selenium-zinc compounds, etc. Alternatively, compounds other than those mentioned above can also be used.

[0224] Furthermore, the pn junction or pin junction included in the light-emitting device 110 can be a homogeneous junction, a heterogeneous junction, or a double heterogeneous junction. In addition, light-emitting devices with quantum well junctions or light-emitting devices using nanopillars can also be used.

[0225] For example, materials such as gallium nitride can be used as light-emitting devices that emit light in the ultraviolet to blue wavelength region. Materials such as indium gallium nitride compounds can be used as light-emitting devices that emit light in the ultraviolet to green wavelength region. Materials such as aluminum-gallium-indium-phosphorus compounds or gallium-arsenide compounds can be used as light-emitting devices that emit light in the infrared wavelength region.

[0226] When multiple light-emitting devices 110 arranged on the same surface have structures with different light-emitting colors such as R (red), G (green), and B (blue), color images can be displayed.

[0227] Alternatively, all light-emitting devices 110 disposed on the same surface may also have a structure that emits light of the same color. In this case, the light emitted from the light-emitting layer 174 is extracted to the outside of the display device through one or both of the color conversion layer and the color layer. This structure will be described in detail in Embodiment 3 of the display device.

[0228] Alternatively, the display device of this embodiment may also include a light-emitting device that emits infrared light. The light-emitting device that emits infrared light can, for example, be used as a light source for an infrared light sensor.

[0229] Note that although Figure 19A shows the way layer 330 is attached to layer 320, a single light-emitting device 110 can also be mounted using a flip-chip bonding machine and sealed by an insulating layer 189, as shown in the display device 100B in Figure 19B.

[0230] This embodiment can be implemented by appropriately combining the structures described in other embodiments.

[0231] Implementation Method 3 In this embodiment, a structure in which a color conversion layer is provided on the light-emitting side of the light-emitting device of the display device described in Embodiment 2 will be explained. Note that detailed descriptions of components identical to those in Embodiment 2 are omitted.

[0232] Figure 20 shows a cross-sectional view of the display device 100E. The display device 100E includes a pixel 20R that emits red light, a pixel 20G that emits green light, and a pixel 20B that emits blue light. In addition, a layer 340 is provided on the layer 330 on which the light-emitting devices are disposed. The layer 340 is provided with a color conversion layer, a color layer, and a light-shielding layer, etc.

[0233] Pixel 20R includes a light-emitting device 110R. Pixel 20G includes a light-emitting device 110G. Pixel 20B includes a light-emitting device 110B. Light-emitting devices 110R, 110G, and 110B all emit light of the same color. In other words, light-emitting devices 110R, 110G, and 110B can all adopt the same structure.

[0234] Specifically, light-emitting devices 110R, 110G, and 110B preferably all emit blue light. When constructing a color image, pixels emitting the three primary colors of red (R), green (G), and blue (B) light can be used. In the display device described in this embodiment, the pixels use a color conversion layer to convert the light emitted by the light-emitting devices into light of the desired color before emitting it to the outside. Here, since a color conversion layer is not required for blue-light-emitting pixels when using blue-light-emitting devices, manufacturing costs can be reduced.

[0235] A color conversion layer 360R and a color layer 361R are provided in the area of ​​the red pixel 20R overlapping the light-emitting device 110R. The light emitted by the light-emitting device 110R is converted from blue to red in the color conversion layer 360R, and the purity of the red light is increased in the color layer 361R, and this light is emitted to the outside of the display device 100E. Alternatively, the color layer 361R may be omitted.

[0236] A color conversion layer 360G and a color layer 361G are provided in the area of ​​the green pixel 20G overlapping the light-emitting device 110G. The light emitted by the light-emitting device 110G is converted from blue to green in the color conversion layer 360G, and the purity of the green light is increased in the color layer 361G, and this light is emitted to the outside of the display device 100E. Alternatively, the color layer 361G may be omitted.

[0237] A color layer 361B is provided in the area of ​​the blue pixel 20B that overlaps with the light-emitting device 110B. The blue light emitted by the light-emitting device 110B has its purity enhanced in the color layer 361B, and this light is emitted to the outside of the display device 100E. Alternatively, the color layer 361B can be omitted. As described above, the color conversion layer can be omitted in the blue pixel 20B.

[0238] Because only one type of light-emitting device needs to be manufactured on the substrate in the display device 100E, the manufacturing equipment and process can be simplified compared to manufacturing multiple light-emitting devices.

[0239] A light-shielding layer 350 is provided between pixels of each color. The light-shielding layer 350 is positioned to at least block light emitted by the light-emitting device 110 in the lateral direction. If necessary, it may also be positioned to block light emitted by the light-emitting device 110 in the oblique direction. In addition, a light-shielding layer 351 covering the area around the pixels is provided on the support layer 118.

[0240] By providing light-shielding layers 350 and 351, light emitted by the light-emitting device can be suppressed from entering adjacent pixel areas of other colors, thereby preventing color mixing. Therefore, the display quality of the display device can be improved. Alternatively, one of light-shielding layers 350 and 351 may also be provided.

[0241] There are no particular limitations on the materials constituting the light-shielding layer 350 and the light-shielding layer 351. For example, inorganic materials such as metal materials or organic materials such as resin materials containing pigments (such as carbon black) or dyes can be used. In addition, the light-shielding layer 351 can also be formed by layering different colored layers. For example, it can be formed by layering red, green and blue colored layers.

[0242] Furthermore, light-emitting devices 110R, 110G, and 110B can each emit light with a wavelength whose photon energy is higher than that of blue light. For example, light-emitting devices capable of emitting blue-violet, violet, or ultraviolet light (UV light) can be used. By using light with high photon energy, color conversion can be performed efficiently in the color conversion layer.

[0243] In this case, as shown in the display device 100F in FIG21, a color conversion layer 360B and a color layer 361B are provided in the area of ​​the blue pixel 20B overlapping the light-emitting device 110B. The light emitted by the light-emitting device 110B is converted from blue-violet, violet or ultraviolet to blue in the color conversion layer 360B, and the purity of the blue light is increased in the color layer 361B, and the light is emitted to the outside of the display device 100E. Alternatively, the color layer 361B may be omitted.

[0244] Phosphors or quantum dots (QDs) are preferred as color conversion layers. In particular, quantum dots have narrow emission spectrum peaks, thus resulting in high color purity light emission. Therefore, the display quality of the display device can be improved.

[0245] Color conversion layers are formed by droplet jetting (e.g., inkjet printing), coating, imprinting, and various printing methods (screen printing, offset printing). Alternatively, color conversion films such as quantum dot films can also be used.

[0246] When processing the film that serves as the color conversion layer, photolithography can be used. For example, a photoresist mask can be formed on the film to be processed, the film can be processed by etching, and then the photoresist mask can be removed. Alternatively, a method can be used to process the film into the desired shape by exposure and development after forming a photosensitive film. For example, an island-shaped color conversion layer can be formed by forming a film using a photosensitive material made of mixed quantum dots and processing the film by photolithography.

[0247] There are no particular limitations on the materials used to construct quantum dots. Examples include elements from Group 14, Group 15, and Group 16; compounds containing multiple elements from Group 14; compounds of elements from Groups 4 to 14 and Group 16; compounds of elements from Groups 2 and 16; compounds of elements from Groups 13 and 15; compounds of elements from Groups 13 and 17; compounds of elements from Groups 14 and 15; compounds of elements from Groups 11 and 17; iron oxides; titanium oxides; spinel; and various semiconductor clusters.

[0248] Specifically, examples include cadmium selenide, cadmium sulfide, cadmium telluride, zinc selenide, zinc oxide, zinc sulfide, zinc telluride, mercuric sulfide, mercuric selenide, mercuric telluride, indium arsenide, indium phosphide, gallium arsenide, gallium phosphide, indium nitride, gallium nitride, indium antimonide, gallium antimonide, aluminum phosphide, aluminum arsenide, aluminum antimonide, lead selenide, lead telluride, lead sulfide, indium selenide, indium telluride, indium sulfide, gallium selenide, arsenic sulfide, arsenic selenide, arsenic telluride, antimony sulfide, antimony selenide, antimony telluride, bismuth sulfide, bismuth selenide, bismuth telluride, silicon, silicon carbide, germanium, tin, selenium, tellurium, boron, carbon, phosphorus, boron nitride, boron phosphide, boron arsenide, aluminum nitride, aluminum sulfide, barium sulfide, barium selenide, barium telluride, calcium sulfide, and selenium. Calcium sulfide, calcium telluride, beryllium sulfide, beryllium selenide, beryllium telluride, magnesium sulfide, magnesium selenide, germanium sulfide, germanium selenide, germanium telluride, tin sulfide, tin selenide, tin telluride, lead oxide, copper fluoride, copper chloride, copper bromide, copper iodide, copper oxide, copper selenide, nickel oxide, cobalt oxide, cobalt sulfide, iron oxide, iron sulfide, manganese oxide, molybdenum sulfide, vanadium oxide, tungsten oxide, tantalum oxide, titanium oxide, zirconium oxide, silicon nitride, germanium nitride, aluminum oxide, barium titanate, compounds of zinc cadmium selenide, zinc cadmium selenide, cadmium arsenide, cadmium selenide, cadmium selenide, tellurium cadmium selenide, indium gallium arsenide, indium gallium selenide, indium selenide, copper indium sulfide, and combinations thereof. In addition, so-called alloy-type quantum dots with compositions expressed in arbitrary ratios can also be used.

[0249] Quantum dots can have various structures, including core-shell, core-multishell, and core-multishell types. Furthermore, due to the high proportion of surface atoms, quantum dots exhibit high reactivity and are prone to aggregation. Therefore, to prevent aggregation and improve dispersibility in the dispersion medium, it is preferable that the surface of the quantum dots is coated with a protective agent or has a protective group. Additionally, this can reduce reactivity and improve electrical stability.

[0250] The smaller the size of a quantum dot, the larger its band gap. Therefore, by appropriately adjusting its size, light of the desired wavelength can be obtained. As the crystal size decreases, the emission of quantum dots shifts towards the blue side (i.e., towards the high-energy side). Therefore, by changing the size of the quantum dots, the emission wavelength can be tuned in a wavelength range covering the ultraviolet, visible, and infrared regions of the spectrum. Commonly used quantum dot sizes (diameters) are, for example, 0.5 nm or more and 20 nm or less, preferably 1 nm or more and 10 nm or less. The smaller the size distribution of quantum dots, the narrower the emission spectrum, thus achieving high color purity emission. Furthermore, there are no particular limitations on the shape of quantum dots; they can be spherical, rod-shaped, disk-shaped, or other shapes. Quantum rods made of rod-shaped quantum dots have the function of directional light emission.

[0251] A color layer is a colored layer that allows light in a specific wavelength range to pass through. For example, color filters that allow light in the red, green, blue, or yellow wavelength range to pass through can be used. Examples of materials that can be used for color layers include metallic materials, resin materials, and resin materials containing pigments or dyes.

[0252] Note that although the basic structure of display devices 100E and 100F is shown using the structure of display device 100A, it can also be used for display device 100B shown in embodiment 2.

[0253] This embodiment can be implemented by appropriately combining the structures described in other embodiments.

[0254] Implementation Method 4 In this embodiment, a display device according to an embodiment of the present invention will be described with reference to Figures 22A and 22B.

[0255] The display device in this embodiment can be a high-definition display device. Therefore, for example, the display device in this embodiment can be used as the display unit of information terminal devices (wearable devices) such as watch-type and bracelet-type devices, as well as the display unit of wearable devices that can be worn on the head, such as VR (Virtual Reality) devices such as head-mounted displays (HMDs) and AR (Augmented Reality) devices such as glasses-type devices.

[0256] [Display Module] Figure 22A is a perspective view of display module 280. Display module 280 includes display device 100A and FPC 290 described in the previous embodiments. Note that the display device included in display module 280 is not limited to display device 100A, but may be any one of display device 100B, display device 100E, and display device 100F.

[0257] The display module 280 includes a substrate 291 and a substrate 292. The display module 280 includes a display section 281. The display section 281 is the image display area in the display module 280, and can display light from each pixel disposed in the pixel section 284.

[0258] Figure 22B is a perspective view of one side of the structure of the substrate 291. A circuit section 282, a pixel circuit section 283 on the circuit section 282, and a pixel section 284 on the pixel circuit section 283 are stacked on the substrate 291. Furthermore, a terminal section 285 for connecting to the FPC 290 is provided on a portion of the substrate 291 that does not overlap with the pixel section 284. The terminal section 285 is electrically connected to the circuit section 282 via a wiring section 286 composed of multiple wirings.

[0259] The pixel unit 284 includes a plurality of pixels 284a arranged periodically. An enlarged view of a pixel 284a is shown on the right side of FIG22B. Pixel 284a includes a plurality of sub-pixels (sub-pixels 10R, 10G, 10B) that emit different colors. The sub-pixels can adopt various structures described in the previous embodiments.

[0260] The pixel circuit section 283 includes a plurality of pixel circuits 283a arranged periodically.

[0261] A pixel circuit 283a controls the driving of multiple elements included in a pixel 284a. A pixel circuit 283a can be composed of three circuits controlling the emission of light from a light-emitting device. For example, the pixel circuit 283a can be structured with at least one select transistor, one current control transistor (driving transistor), and a capacitor for each light-emitting device. In this case, the gate of the select transistor is input with a gate signal, and the source is input with a source signal. This realizes an active matrix display device.

[0262] The circuit section 282 includes circuitry for driving each pixel circuit 283a of the pixel circuit section 283. For example, it preferably includes one or both of a gate line driving circuit and a source line driving circuit. Furthermore, it may also include at least one of an arithmetic circuit, a memory circuit, and a power supply circuit.

[0263] The FPC290 is used for wiring to supply video signals or power potentials to the circuit section 282 from the outside. Additionally, ICs can be mounted on the FPC290.

[0264] The display module 280 can adopt a structure in which one or both of the pixel circuit section 283 and the circuit section 282 are stacked on the lower side of the pixel section 284, so that the display section 281 can have an extremely high aperture ratio (effective display area ratio). For example, the aperture ratio of the display section 281 can be 40% or more and less than 100%, preferably 50% or more and less than 95%, and more preferably 60% or more and less than 95%. In addition, the pixels 284a can be arranged in an extremely high density, thereby enabling the display section 281 to have extremely high resolution. For example, the display section 281 preferably has a resolution of 2000 ppi or more, more preferably 3000 ppi or more, further preferably 5000 ppi or more, and even more preferably 6000 ppi or more and less than 20000 ppi or less or less than 30000 ppi.

[0265] This high-definition display module 280 is suitable for use in VR devices such as HMDs or AR devices such as glasses. For example, because the display module 280 has an extremely high-definition display section 281, even when the display section of the display module 280 is magnified through a lens, the user cannot see any pixels, thereby achieving a highly immersive display. Furthermore, not limited to this, the display module 280 can also be applied to electronic devices with relatively small display sections. For example, it is suitable for use in the display section of wearable electronic devices such as watch-type devices.

[0266] This embodiment can be implemented by appropriately combining the structures described in other embodiments.

[0267] Implementation Method 5 In this embodiment, an electronic device according to one embodiment of the present invention will be described using Figures 23A to 23D.

[0268] The electronic device of this embodiment includes a display device according to one embodiment of the present invention in its display section. The display device according to one embodiment of the present invention is easily made to achieve high definition and high resolution. Therefore, it can be used in the display sections of various electronic devices.

[0269] Because the display device of one embodiment of the present invention can improve clarity, it can be suitable for use in electronic devices that include a small display section. Examples of such electronic devices include watch-type and bracelet-type information terminal devices (wearable devices), wearable devices that can be worn on the head, VR devices such as head-mounted displays, AR devices such as glasses, and MR (Mixed Reality) devices.

[0270] A display device according to one embodiment of the present invention preferably has extremely high resolution, such as HD (1280×720 pixels), FHD (1920×1080 pixels), WQHD (2560×1440 pixels), WQXGA (2560×1600 pixels), 4K (3840×2160 pixels), 8K (7680×4320 pixels), etc. In particular, it is preferred to set the resolution to 4K, 8K, or higher. Furthermore, the pixel density (clarity) in the display device according to one embodiment of the present invention is preferably 100 ppi or higher, preferably 300 ppi or higher, more preferably 500 ppi or higher, further preferably 1000 ppi or higher, even more preferably 2000 ppi or higher, even more preferably 3000 ppi or higher, still more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display device with one or both of the aforementioned high resolution and high definition, realism and depth can be further enhanced in portable or home-use electronic devices. Furthermore, there is no particular limitation on the screen aspect ratio (vertical-to-horizontal ratio) of the display device according to one embodiment of the present invention. For example, the display device can accommodate various screen aspect ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0271] The electronic device in this embodiment may also include a sensor (which has the function of sensing, detecting, and measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation).

[0272] The electronic device of this embodiment can have various functions. For example, it can have the following functions: displaying various information (still images, moving images, text images, etc.) on the display unit; touch panel function; displaying calendar, date or time, etc.; executing various software (programs); performing wireless communication function; reading programs or data stored in the storage medium; etc.

[0273] Figures 23A to 23D illustrate an example of a wearable device that can be worn on the head. These wearable devices have at least one of the following functions: displaying AR content, displaying VR content, displaying SR (Substitutional Reality) content, and displaying MR content. When an electronic device has the function of displaying at least one of AR, VR, SR, MR, etc., the user's sense of immersion can be enhanced.

[0274] The electronic device 700A shown in Figure 23A and the electronic device 700B shown in Figure 23B both include a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical components 753, an eyeglass frame 757, and a pair of nose pads 758.

[0275] The display panel 751 can be used with a display device according to one embodiment of the present invention. Therefore, an electronic device capable of displaying with extremely high clarity can be realized.

[0276] Furthermore, when the display device includes a light-receiving device, this device can be used to capture images of the pupil for iris recognition. Additionally, the light-receiving device can be used for gaze tracking. By performing gaze tracking, the object and its location being viewed can be determined, thus enabling the selection of functions within the electronic device and the execution of software.

[0277] Both electronic devices 700A and 700B can project images displayed on the display panel 751 onto the display area 756 in the optical component 753. Because the optical component 753 is light-transmitting, the user can see the image displayed on the display area by superimposing it with the image seen through the optical component 753. Therefore, both electronic devices 700A and 700B are capable of AR display.

[0278] The electronic devices 700A and 700B can also be equipped with cameras capable of capturing images of the front as imaging units. In addition, by installing accelerometers such as gyroscopes in the electronic devices 700A and 700B, the orientation of the user's head can be detected and the image corresponding to that orientation can be displayed on the display area 756.

[0279] The communications unit includes a wireless communication device, through which image signals can be supplied. Additionally, in addition to the wireless communication device, a connector capable of connecting cables that supply image signals and power can also be included.

[0280] In addition, electronic devices 700A and 700B are equipped with batteries that can be charged wirelessly or via wired means or both.

[0281] The electronic device 800A shown in Figure 23C and the electronic device 800B shown in Figure 23D both include a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0282] The display unit 820 can be equipped with a display device according to one embodiment of the present invention. Therefore, an electronic device capable of displaying extremely high clarity can be realized. As a result, the user can experience a high degree of immersion.

[0283] The display unit 820 is located inside the housing 821 in a position visible through the lens 832. Furthermore, by displaying different images between a pair of display units 820, three-dimensional display utilizing parallax can be achieved.

[0284] Both electronic devices 800A and 800B can be referred to as VR-oriented electronic devices. Users who install electronic devices 800A or 800B can see the image displayed on the display unit 820 through the lens 832.

[0285] Electronic devices 800A and 800B preferably have a mechanism that allows adjustment of the left and right positions of the lens 832 and the display unit 820 to position them in the most suitable way according to the user's eye position. Furthermore, it is preferable to have a mechanism that adjusts the focus by changing the distance between the lens 832 and the display unit 820.

[0286] The user can use the mounting part 823 to attach the electronic device 800A or electronic device 800B to their head. In Figure 23C, etc., the mounting part 823 is shown to have a shape similar to the temple of an eyeglass (also called a temple wire, etc.), but it is not limited to this. As long as the user can attach it, the mounting part 823 can have, for example, a helmet-shaped or strap-shaped shape.

[0287] The imaging unit 825 has the function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, multiple cameras can be set to support various viewing angles such as telephoto and wide-angle.

[0288] Note that the example shown here includes an imaging unit 825, which can be a range sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object. In other words, the imaging unit 825 is one implementation of the detection unit. For example, an image sensor or a distance image sensor such as LiDAR (Light Detection and Ranging) can be used as the detection unit. By using images acquired by the camera and images acquired by the distance image sensor, more information can be obtained, and more precise attitude control can be achieved.

[0289] The electronic device 800A may also include a vibration mechanism used as a bone conduction headphone. For example, the structure including this vibration mechanism may be adopted as one or more of the display unit 820, housing 821, and mounting unit 823. Thus, there is no need to separately install audio equipment such as headphones, earphones, or speakers; one can enjoy images and sound simply by installing the electronic device 800A.

[0290] Both electronic devices 800A and 800B may include input terminals. Cables supplying image signals from image output devices and power for charging batteries installed in the electronic devices can be connected to the input terminals.

[0291] An electronic device according to one embodiment of the present invention may also have the function of wirelessly communicating with an earphone 750. The earphone 750 includes a communication unit (not shown) and has wireless communication functionality. The earphone 750 can receive information (e.g., audio data) from the electronic device via the wireless communication function. For example, the electronic device 700A shown in FIG. 23A has the function of transmitting information to the earphone 750 via wireless communication. Additionally, for example, the electronic device 800A shown in FIG. 23C has the function of transmitting information to the earphone 750 via wireless communication.

[0292] Alternatively, the electronic device may also include an earphone unit. The electronic device 700B shown in Figure 23B includes an earphone unit 727. For example, a structure can be adopted in which the earphone unit 727 and the control unit are connected by a wire. A portion of the wiring connecting the earphone unit 727 and the control unit can also be disposed inside the housing 721 or the mounting portion 723.

[0293] Similarly, the electronic device 800B shown in FIG23D includes an earphone unit 827. For example, a structure in which the earphone unit 827 and the control unit 824 are connected by a wire can be adopted. A portion of the wiring connecting the earphone unit 827 and the control unit 824 can also be disposed inside the housing 821 or the mounting part 823. In addition, the earphone unit 827 and the mounting part 823 can also include magnets. Thus, the earphone unit 827 can be fixed to the mounting part 823 by magnetic force, making storage easier, which is preferable.

[0294] Electronic devices may also include an audio output terminal capable of connecting to headphones or headsets. Additionally, electronic devices may include one or both of an audio input terminal and an audio input mechanism. For example, a microphone or other sound-receiving device can be used as an audio input mechanism. By incorporating an audio input mechanism into the electronic device, it can be made to function as a so-called headset.

[0295] Thus, as an embodiment of the present invention, both eyeglass type (electronic device 700A and electronic device 700B, etc.) and goggle type (electronic device 800A and electronic device 800B, etc.) are preferred electronic devices.

[0296] In addition, the electronic device of one embodiment of the present invention can transmit information to the earphone in a wired or wireless manner.

[0297] Furthermore, in an electronic device that can utilize a display device according to one embodiment of the present invention, it can also be connected to an external server via a network. Alternatively, high-performance processing can be performed on a network-connected server instead of on the electronic device. This processing is also known as a thin client, where only limited processing is performed on the user-side (client-side) terminal (here, the electronic device), while advanced processing such as application execution and management is performed on the server side, thus reducing the processing scale of the client-side terminal. Therefore, the electronic device does not require a high-performance computing device, making it easier to achieve low cost, lightweight design, and miniaturization. Furthermore, in an electronic device according to one embodiment of the present invention, the aforementioned thin client can be combined with high-performance processing on the electronic device side for processing.

[0298] This embodiment can be implemented by appropriately combining the structures described in other embodiments.

[0299] BG: Nodes BS: Node GL: Gate line SLO: Slope Potential VDATA: Data Potential VRESA: Reset potential VRESW: Reset potential VSBG: Potential 10a: pixels 10B: Subpixel 10b: pixels 10c: pixels 10G: Subpixel 10R: Subpixel 10 pixels 11: Pulse signal generation unit 13: Pixel Array 20B: pixels 20G: pixels 20R: pixels 20: Source Driver 30: Gate driver 32: Grayscale 40: Slope potential supply circuit 50: Slope potential generation circuit 100A: Display device 100B: Display device 100E: Display device 100F: Display device 101: Transistor 102: Transistor 103: Transistor 104: Transistor 105: Transistor 106: Transistor 107: Transistor 108: Transistor 109: Transistor 110B: Light-emitting device 110G: Light-emitting device 110R: Light-emitting device 110: Light-emitting devices 111: Capacitor 112: Capacitor 113: Capacitor 114: Capacitor 115: Transistor 116: Transistor 117: Insulation layer 118: Support layer 121: Wiring 122: Wiring 123: Wiring 124: Wiring 125: Wiring 127: Wiring 128: Wiring 129: Wiring 131: Wiring 132: Wiring 133: Wiring 134: Wiring 135: Wiring 136: Wiring 137: Wiring 138: Wiring 139: Wiring 140: Transistor 142: Component Separation Layer 143: Low resistance region 144: Insulation layer 145: Conductive layer 146: Insulation layer 147: Conductive layer 148: Conductive layer 149: Insulation layer 150:Substrate 151: Insulation layer 152: Insulation layer 160: Transistor 161: Conductive layer 162: Insulation layer 163: Insulation layer 164: Insulation layer 165: Metal oxide layer 166: Conductive layer 167: Insulation layer 168: Conductive layer 173: Semiconductor layer 174: Emissive Layer 175: Semiconductor layer 176: Conductive layer 181: Insulation layer 182: Insulation layer 183: Insulation layer 184a: Conductive layer 184b: Conductive layer 185: Insulation layer 186: Insulation layer 187: Insulation layer 188: Insulation layer 189: Insulation layer 192: Conductive layer 195: Conductive layer 196: Conductive layer 197: Conductive layer 198: Conductive layer 199: Conductive layer 255: Grayscale 280: Display Module 281: Display Section 282: Circuit Section 283a: Pixel Circuit 283: Pixel Circuit Section 284a: pixels 284: Pixels 285: Terminal section 286: Wiring Department 290:FPC 291:Substrate 292:Substrate 310: Floor 311:Si transistor 312: Functional Circuit 320: Floor 321:OS transistor 330: Floor 331: LED Array 340: Floor 350: Light-shielding layer 351: Light-shielding layer 360B: Color Conversion Layer 360G: Color Conversion Layer 360R: Color Conversion Layer 361B: Color Layer 361G: Color Layer 361R: Color Layer 700A: Electronic Device 700B: Electronic Devices 721:Case 723: Installation Department 727: Headphone Department 750: Headphones 751: Display Panel 753: Optical components 756: Display area 757: Framework 758: Nose pad 800A: Electronic device 800B: Electronic Device 820: Display Unit 821: Outer shell 822: Communications Department 823: Installation Department 824: Control Department 825: Imaging Unit 827: Headphone Department 832: Lens

Claims

1. A display device, comprising: The system includes a pixel comprising a pulse signal generating unit, a light-emitting device, a first node, and a second node. The first node is electrically connected to the input unit of the pulse signal generating unit, and the second node is electrically connected to the output unit of the pulse signal generating unit. The first node and the second node are electrically connected via a transistor. The pixel emits light from the light-emitting device in response to a data potential input to the second node. The pulse signal generating unit generates a pulse signal in response to the data potential input to the first node. Furthermore, the pixel resets the potential of the second node in response to the pulse signal, thereby stopping the light-emitting device from emitting light.

2. A display device, comprising: The pixel includes a pulse signal generation unit, a first node, a second node, a first transistor, a second transistor, a third transistor, a first capacitor, and a light-emitting device. The first node is electrically connected to one of the source and drain electrodes of the first transistor, one of the source and drain electrodes of the second transistor, and the input part of the pulse signal generation unit. The second node is electrically connected to the other of the source and drain electrodes of the second transistor, the gate electrode of the third transistor, one electrode of the first capacitor, and the output part of the pulse signal generation unit. One of the source and drain electrodes of the third transistor is electrically connected to one electrode of the light-emitting device, and the other of the source and drain electrodes of the third transistor is electrically connected to the other electrode of the first capacitor.

3. The display device of claim 2, wherein the pulse signal generating unit includes a fourth to a ninth transistor and a second capacitor, the fourth transistor having a first gate and a second gate, the first gate of the fourth transistor and one of the source and drain of the fifth transistor being electrically connected to the first node, one of the source and drain of the fourth transistor being electrically connected to the gate of the sixth transistor and one of the source and drain of the seventh transistor, the second gate of the fourth transistor being electrically connected to one of the source and drain of the eighth transistor and one electrode of the second capacitor, the other electrode of the second capacitor being electrically connected to one of the source and drain of the ninth transistor, the other of the source and drain of the ninth transistor being electrically connected to the other of the source and drain of the fourth transistor, and one of the source and drain of the sixth transistor being electrically connected to the second node.

4. The display device as claimed in claim 3, wherein the other of the source and drain terminals of the fourth transistor is input with a ramp waveform signal potential.

5. The display device as claimed in claim 3, wherein the first transistor, the second transistor, the fourth transistor, the fifth transistor, the eighth transistor and the ninth transistor are all n-channel transistors, and the third transistor, the sixth transistor and the seventh transistor are all p-channel transistors.

6. The display device of claim 5, wherein the n-channel transistor comprises a metal oxide in the channel forming region and the p-channel transistor comprises silicon in the channel forming region.

7. The display device of claim 2, wherein the pixel causes the light-emitting device to emit light by corresponding input of the data potential of the first node, the pulse signal generating unit generates a pulse signal corresponding to input of the data potential of the second node, and the pixel resets the potential of the first node in response to the pulse signal to stop the light-emitting device from emitting light.

8. The display device as claimed in claim 1 or 2, wherein the light-emitting device is a Micro LED.

9. An electronic device comprising: Such as the display device requested in item 1 or 2; And a camera.

Images