Display device and tiled display device including the same

Abstract

The present invention provides a display device, comprising: a substrate; a transistor layer located on a first surface of the substrate; a pad portion; a first via layer located on the transistor layer and spaced apart from the pad portion; a second via layer located on the first via layer and exposing the upper surface of the first via layer; a third via layer located on the second via layer and exposing the upper surface of the second via layer; a display element layer located on the third via layer; a lead located on a second surface of the substrate; a side connection line located on the first surface, the second surface, and the side surface between the first surface and the second surface, the side connection line electrically connecting the pad portion to the lead line; and a cover layer covering the side connection line and overlapping the exposed upper surface of the first via layer.

Description

Display Device and Tiled Display Device Comprising the Same Aspects of embodiments of the present disclosure relate to a display device and a tiled display device comprising the same. Recently, with the increasing interest in information display, research and development of display devices have been continuously carried out. For example, in order to manufacture a large-screen display device, a tiled display device in which a plurality of display devices are connected to each other has been in actual use, and the tiled display device realizes a large screen by connecting a plurality of display panels having a predetermined size to each other. The above information disclosed in this prior art section is intended to deepen the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art. One or more embodiments of the present disclosure relate to a display device including a cover layer, the cover layer including a black pigment, and the cover layer may completely cover the entire side connection line and the exposed upper surface of the first via layer exposed from the second via layer. One or more embodiments of the present disclosure relate to a tiled display device including the display device. However, aspects and features of the present disclosure are not limited to the above, and various extensions can be made without departing from the spirit and scope of the present disclosure. According to one or more embodiments of the present invention, a display device includes: a substrate including a display area and a non-display area surrounding the display area; a transistor layer located on a first surface of the substrate, the transistor layer including a transistor of a pixel circuit located in the display area; a pad portion located in the non-display area, and the pad portion is electrically connected to the pixel circuit; a first via layer located on the transistor layer, and the first via layer is spaced apart from the pad portion; a second via layer located on the first via layer, and the second via layer has a step difference from the first via layer to expose a part of the upper surface of the first via layer; a third via layer located on the second via layer, and the third via layer has a step difference from the second via layer to expose a part of the upper surface of the second via layer; a display element layer located on the third via layer in the display area, the display element layer including a light-emitting element electrically connected to the transistor; a lead located on a second surface of the substrate; a side connection line located on the first surface of the substrate, on the second surface of the substrate, and on a side surface between the first surface and the second surface of the substrate, the side connection line electrically connecting the pad portion and the lead to each other; and a cover layer covering the entire side connection line, and the cover layer overlaps with the upper surface of the first via layer exposed from the second via layer. In an embodiment, an end of the cover layer may face an end of the second via layer. In one embodiment, the cover layer may overlap at least a portion of the upper surface of the exposed second via layer, and one end of the cover layer may face one end of the third via layer. In one embodiment, the cover layer may include an insulating layer that is in direct contact with the side connection line and contains a black pigment. In one embodiment, the transistor layer may further include an interlayer insulating layer located on the transistor, the interlayer insulating layer being in contact with the first via layer, and the interlayer insulating layer may include a portion that is exposed to the first via layer and the pad portion. In one embodiment, the display element layer may further include: a pixel electrode located on the third via layer, and the pixel electrode is electrically connected to the light-emitting element; and a protective layer located on the pixel electrode and the pad portion, and the protective layer exposes a portion of the upper surface of the pixel electrode and a portion of the upper surface of the pad portion, and the protective layer may contact the exposed portions of the interlayer insulating layer, the first via layer, the second via layer, and the third via layer. In one embodiment, the side connection line may be located on the protective layer, and the side connection line may overlap the exposed portion of the interlayer insulating layer. In one embodiment, one end of the cover layer may face one end of the second via layer, and the protective layer is inserted between the end of the cover layer and the end of the second via layer. In one embodiment, the end of the second via layer may have a shape that extends linearly in a first direction in a plan view. In one embodiment, the cover layer may overlap at least a portion of the upper surface of the exposed second via layer, and one end of the cover layer may face one end of the third via layer, and the protective layer is inserted between the end of the cover layer and the end of the third via layer. In one embodiment, the end of the second via layer may have a shape that extends linearly in a first direction in a plan view. In one embodiment, the display device may further include: a first source metal layer located on the transistor layer, and the first source metal layer is covered by the first via layer of the display area; a second source metal layer located on the first via layer of the display area, and the second source metal layer is covered by the second via layer; and a third source metal layer located on the second via layer of the display area, and the third source metal layer is covered by the third via layer. In one embodiment, the pad portion may include: a first pad electrode formed together with the first source metal layer; a second pad electrode formed together with the second source metal layer, and the second pad electrode is directly located on the first pad electrode; a third pad electrode formed together with the third source metal layer, and the third pad electrode is directly located on the second pad electrode; and a fourth pad electrode formed together with the pixel electrode, and the fourth pad electrode is directly located on the third pad electrode. A plurality of exposed portions of the first pad electrode to the fourth pad electrode may contact the protective layer. In one embodiment, the display element layer may further include: a black anisotropic conductive film located on a part of the cover layer and the protective layer in the display area. The black anisotropic conductive film includes a black pigment and a plurality of conductive particles, and the light-emitting element and the pixel electrode may be electrically connected to each other through the conductive particles. In one embodiment, the display device may further include: a second surface electrode located on the second surface of the substrate; and a flexible film electrically connected to the second surface electrode through a conductive adhesive, and the side connection line may be electrically connected to the second surface electrode through the lead wire. According to one or more embodiments of the present disclosure, a tiled display device includes: a plurality of display devices; and a coupling area located between the plurality of display devices and connecting the plurality of display devices to each other. At least one of the plurality of display devices includes: a substrate including a display area and a non-display area surrounding the display area; a transistor layer located on a first surface of the substrate, and the transistor layer includes a transistor of a pixel circuit in the display area; a pad portion located in the non-display area and electrically connecting the pixel circuit; a first via layer located on the transistor layer and spaced apart from the pad portion; a second via layer located on the first via layer and having a step difference from the first via layer to expose a part of an upper surface of the first via layer; a third via layer located on the second via layer and having a step difference from the second via layer to expose a part of an upper surface of the second via layer; a display element layer located on the third via layer in the display area, and the display element layer includes a light-emitting element electrically connected to the transistor; a lead wire located on a second surface of the substrate; a side connection line located on the first surface of the substrate, the second surface of the substrate, and a side surface between the first surface and the second surface of the substrate, and the side connection line electrically connects the pad portion and the lead wire to each other; and a cover layer covering the entire side connection line, and the cover layer overlaps the upper surface of the first via layer exposed from the second via layer, and the cover layer includes a black pigment. In one embodiment, an end of the covering layer may face an end of the second via layer. In one embodiment, the covering layer may overlap at least a portion of the upper surface of the exposed second via layer, and an end of the covering layer faces an end of the third via layer. In one embodiment, the display element layer may further include: a pixel electrode located on the third via layer, and the pixel electrode is electrically connected to the light-emitting element; and a protective layer located on the pixel electrode and the pad portion, and the protective layer exposes a portion of the upper surface of the pixel electrode and a portion of the upper surface of the pad portion, and the protective layer may contact the exposed portions of the first via layer, the second via layer, and the third via layer. In one embodiment, an end of the covering layer may face an end of the second via layer, and the protective layer is inserted between the end of the covering layer and the end of the second via layer. In one embodiment, the light-emitting element may include: a flip chip type micro light-emitting diode element. According to one or more embodiments of the present disclosure, a display device and a tiled display device including the same may include a covering layer that completely covers the side connection lines. By the step difference between a plurality of via layers disposed in a step shape on the substrate, the covering layer can be formed while being blocked by a dam. Therefore, an end of the covering layer can be uniformly extended in one direction while being blocked by the step difference between a plurality of via layers in the non-display area on the substrate, and the process capability (e.g., process dispersion, or process deviation) of the covering layer can be improved. For example: the process capability of the covering layer formed by a printing process can be improved, and the process capability of the display device including the same can be improved. Therefore, the reliability of the manufacturing method and the image quality of the display device and the tiled display device including the same can be improved. However, the aspects and features of the present disclosure are not limited to the above aspects and features, and various extensions can be made without departing from the spirit and scope of the present invention. In the following, embodiments will be described in more detail with reference to the drawings, in which the same reference numerals throughout the drawings represent the same elements. However, the present disclosure may be implemented in various different forms and should not be construed as limited only to the embodiments shown herein. On the contrary, these embodiments are provided by way of example to make the present disclosure clear and complete, and to fully convey the aspects and features of the present disclosure to those of ordinary skill in the art to which the present invention pertains. Therefore, processes, elements, and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, the same reference numerals described throughout the drawings and the specification represent the same elements, and thus, their redundant descriptions may not be repeated. When a particular embodiment can be implemented differently, the specific processing sequence may be different from the described sequence. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or may be performed in an order opposite to the described order. In the drawings, for clarity, the relative sizes of elements, layers, and regions may be exaggerated and / or simplified. Spatial relative terms, such as "beneath", "below", "under", "above", "upper", etc. may be used herein for illustrative purposes to explain the relationship between one element and another element shown in the drawings. Spatial relative terms are intended to encompass different orientations of a device in use, operation, and / or manufacture in addition to the orientation depicted in the drawings. For example, if the device in the drawings is flipped, an element described as "below", "beneath", or "under" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "below" or "under" may include both the above and below orientations. In addition, the device may be oriented in other ways (e.g., rotated 90 degrees or other orientations), and thus, the spatial relative descriptors used herein should also be interpreted accordingly. In the drawings, the x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system and may be interpreted more broadly. For example, the x-axis, y-axis, and z-axis may be perpendicular or substantially perpendicular to each other, or may represent different directions that are not perpendicular to each other. It should be understood that although the terms "first", "second", "third", etc. may be used in this specification to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, without departing from the teachings of this specification, the "first element", "component", "region", "layer" or "section" discussed below may be referred to as a second element, component, region, layer or part. It should be understood that when an element, layer, region or component is referred to as "formed on", "on", "connected to" or "coupled to" another element, layer, region or component, it can be directly formed on, on, connected to or coupled to the other element, layer, region or component, or indirectly formed on, on, connected to or coupled to the other element, layer, region or component such that one or more intermediate elements, layers, regions or components may be present. Similarly, when a layer, region or component is referred to as "electrically connected to" or "electrically coupled to" another layer, region or component, it can be directly electrically connected or coupled to the other layer, region or component, and / or intermediate layers, regions or components may be present. In addition, it should also be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present. The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used herein, the singular forms "a" and "an" are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises", "comprising", "includes", "including", "has", "have", "having" specify the presence of the feature, integer, step, operation, element and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof. As used in this specification, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example: "A and / or B" can be understood to mean "A, B or A and B". Expressions such as "at least one of" when placed before a list of elements modify the entire list of elements rather than each individual element of the list of elements. For example: the expressions "at least one of a, b and c" and "at least one selected from the group consisting of a, b and c" mean only a, only b, only c, both a and b, a and c, b and c, all of a, b and c, or variants thereof. As used herein, the terms "substantially", "about" and similar terms are used as approximate terms rather than terms of degree, and are intended to account for the inherent deviations of measured or calculated values that would be recognized by one of ordinary skill in the art to which the present invention pertains. In addition, "may" as used in describing embodiments of the disclosure refers to "one or more embodiments of the disclosure". As used herein, the terms "use", "using" and "used" may be considered respectively synonymous with the terms "utilize", "utilizing" and "utilized". In addition, the term "exemplary" is intended to refer to an example or illustration. The electronic or electrical devices and / or any other related devices or components according to the embodiments of the present invention described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software and firmware and / or hardware. For example, various components of these devices can be formed on one integrated circuit (IC) chip or on separate IC chips. In addition, various components of these devices can be implemented on a flexible printed circuit film, tape carrier package (TCP), printed circuit board (PCB), or formed on a substrate. In addition, various components of these devices can be processes or threads that run on one or more processors, in one or more computer devices, execute computer program instructions, and interact with other system components to perform various functions described herein. The computer program instructions are stored in a memory, which can be implemented in a computer device using standard memory devices, such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as CD-ROM, flash memory drive, etc. In addition, those of ordinary skill in the art to which the present invention pertains should understand that the functions of various computer devices can be combined or integrated into a single computer device, or the functions of a particular computer device can be distributed over one or more other computer devices without departing from the spirit and scope of the exemplary embodiments of the present invention. Unless otherwise defined, all terms used herein (including technical and scientific terms) can be understood by those of ordinary skill in the art according to the specific context. Unless clearly defined otherwise herein, all terms should be construed as having the same meaning as in a common dictionary and interpreted consistently with the meaning of the term in the relevant field, and should not be idealized or interpreted too formally. FIG. 1 shows a schematic diagram of a display device according to an embodiment of the present invention, FIG. 2 shows a schematic diagram of an example of a pixel included in the display device of FIG. 1, and FIG. 3 shows schematic diagrams of other examples of pixels included in the display device of FIG. 1. Referring to FIGS. 1, 2, and 3, the display device 10 may include pixels PX. The display device 10 is a device for displaying videos and / or static images. The display device 10 can be used as a display screen for various suitable products, such as portable electronic devices, such as mobile phones, smartphones, tablet personal computers (PCs), smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs), as well as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices. The display device 10 (or display panel) can be formed in a rectangular plane having a long side extending along a first direction DR1 and a short side extending along a second direction DR2 intersecting the first direction DR1. The angle formed by the intersection of the long side extending along the first direction DR1 and the short side extending along the second direction DR2 can be formed as a rounded corner with an appropriate curvature (e.g., a predetermined curvature), or can be formed as a right angle. The planar shape of the display device 10 is not limited to a quadrilateral, and can also be formed as another suitable polygon, circle, or ellipse. The display device 10 can be a flat or substantially flat display device, but the present disclosure is not limited thereto. For example, the display device 10 can include curved portions formed at the left and right ends and having a constant or varying curvature. The display device 10 can be flexibly formed as crooked, curved, bent, folded, or rolled. Each of the pixels PX can be represented as a unit pixel UP. For example, as shown in FIGS. 2 and 3, each unit pixel UP can include first, second, and third sub-pixels SP1, SP2, and SP3. FIGS. 2 and 3 show that the unit pixel UP includes three sub-pixels SP1, SP2, and SP3, but the present disclosure is not limited thereto. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can emit light having different colors from each other. Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have a planar shape of a rectangle, a square, or a rhombus. For example, as shown in FIG. 2, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have a planar shape of a rectangle having a short side extending along the first direction DR1 and a long side extending along the second direction DR2. As another example, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have a planar shape of a square or a rhombus. In one embodiment, as shown in FIG. 2, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be arranged along the first direction DR1. In another embodiment, the first sub-pixel SP1 and any one of the second sub-pixel SP2 and the third sub-pixel SP3 can be arranged along the first direction DR1, and the other of the second sub-pixel SP2 and the third sub-pixel SP3 can be arranged relative to the first sub-pixel SP1 along the second direction DR2. For example, as shown in FIG. 3, the second sub-pixel SP2 can be arranged relative to the first sub-pixel SP1 along the first direction DR1, and the third sub-pixel SP3 can be arranged relative to the first sub-pixel SP1 along the second direction DR2. The first pixel SP1 can emit a first light, the second pixel SP2 can emit a second light, and the third pixel SP3 can emit a third light. The first light can be light in the red wavelength band, the second light can be light in the green wavelength band, and the third light can be light in the blue wavelength band. The red wavelength band can be a band of approximately 600 nm to 750 nm, the green wavelength band can be a band of approximately 480 nm to 560 nm, and the blue wavelength band can be a band of approximately 370 nm to 460 nm, but the present invention is not limited thereto. Each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 can include an inorganic light-emitting element, which includes an inorganic semiconductor as the light-emitting element for emitting light. For example: The inorganic light-emitting element can be a flip chip type micro light-emitting diode (LED), but the present disclosure is not limited thereto. As shown in FIGS. 2 and 3, the area of the first pixel SP1, the area of the second pixel SP2, and the area of the third pixel SP3 can be the same as or substantially the same as each other, but the present disclosure is not limited thereto. The area of a pixel can be understood as the planar area of the light-emitting element (or light source) included in the corresponding pixel, or the planar area of the emission region of the light-emitting element. At least one of the area of the first pixel SP1, the area of the second pixel SP2, and the area of the third pixel SP3 can be different from other areas. As another example, any two of the area of the first pixel SP1, the area of the second pixel SP2, and the area of the third pixel SP3 can be the same as or substantially the same as each other, and the other one of them can be different from the areas of these two. As another example, the area of the first pixel SP1, the area of the second pixel SP2, and the area of the third pixel SP3 can be different from each other. FIG. 4 shows a schematic diagram of a tiled display device according to an embodiment of the present invention. Referring to FIG. 4, the tiled display device TD can include a plurality of display devices 10-1, 10-2, 10-3, and 10-4. The display devices 10-1, 10-2, 10-3, and 10-4 can be arranged in a grid shape, but the present disclosure is not limited thereto. Since the display devices 10-1, 10-2, 10-3, and 10-4 are connected to each other in the first direction DR1 or the second direction DR2, the tiled display device TD can have a suitable shape (for example: a specific or predetermined shape). For example: Each of the display devices 10-1, 10-2, 10-3, and 10-4 can have the same or substantially the same size as each other, but the present disclosure is not limited thereto. As another example, the size of at least a part of the display devices 10-1, 10-2, 10-3, and 10-4 can be different from that of other devices. The display devices 10-1, 10-2, 10-3, and 10-4 may include first to fourth display devices 10-1, 10-2, 10-3, and 10-4. The number of the display devices 10-1, 10-2, 10-3, and 10-4 and the coupling relationship therebetween are not limited to the embodiment shown in FIG. 4. The number of the display devices 10-1, 10-2, 10-3, and 10-4 may be determined according to the sizes of the display devices 10-1, 10-2, 10-3, and 10-4 and / or the tiled display device TD. The first to fourth display devices 10-1, 10-2, 10-3, and 10-4 may be fixed to a mounting frame (e.g., a predetermined mounting frame) to achieve a large-screen image. Each of the first to fourth display devices 10-1, 10-2, 10-3, and 10-4 may have a rectangular shape including a long side and a short side. The first to fourth display devices 10-1, 10-2, 10-3, and 10-4 may be arranged such that their long sides or short sides are connected to each other. A part of the first to fourth display devices 10-1, 10-2, 10-3, and 10-4 may be disposed at an edge of the tiled display device TD to form one side of the tiled display device TD. Another part of the first to fourth display devices 10-1, 10-2, 10-3, and 10-4 may be disposed at a corner of the tiled display device TD and may form two adjacent sides of the tiled display device TD. Still another part of the first to fourth display devices 10-1, 10-2, 10-3, and 10-4 may be disposed inside the tiled display device TD and may be surrounded by other display devices (e.g., around its periphery). Each of the first to fourth display devices 10-1, 10-2, 10-3, and 10-4 may include a display area DA and a non-display area NDA. The display area DA may include unit pixels UP and may display an image. Each unit pixel UP may include first, second, and third sub-pixels SP1, SP2, and SP3. Each of the first, second, and third sub-pixels SP1, SP2, and SP3 may include a micro LED. However, the present disclosure is not limited thereto, and each of the first, second, and third sub-pixels SP1, SP2, and SP3 may include an organic LED including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, or an inorganic LED including an inorganic semiconductor. Hereinafter, for the sake of convenience of explanation and description, it is assumed that each of the first, second, and third sub-pixels SP1, SP2, and SP3 includes a micro LED. The non-display area NDA may be disposed around the display area DA and may surround (e.g., around its periphery) at least a part of the display area DA. The non-display area NDA may not display a schematic image. The first to fourth display devices 10-1, 10-2, 10-3, and 10-4 may include first, second, and third pixel display regions DA of first, second, and third pixels SP1, SP2, and SP3 arranged along a plurality of rows and columns. Each of the first, second, and third pixels SP1, SP2, and SP3 may include an emission region, or an opening region defined by a pixel defining layer or a bank, and may emit light having a desired peak wavelength (e.g., a predetermined peak wavelength) through the emission region or the opening region. The emission region may be light generated by a light emitting element of each of the first, second, and third pixels SP1, SP2, and SP3 and emitted to the outside of the first to fourth display devices 10-1, 10-2, 10-3, and 10-4. The first, second, and third pixels SP1, SP2, and SP3 may be sequentially and repeatedly arranged along a first direction DR1 of the display region DA. The tiled display device TD may have an overall planar shape, but the present disclosure is not limited thereto. The tiled display device TD may have a three-dimensional shape to provide a three-dimensional effect to a user. For example, when the tiled display device TD has a three-dimensional shape, at least a part of the display devices 10-1, 10-2, 10-3, and 10-4 may have a curved shape. As another example, each of the first to fourth display devices 10-1, 10-2, 10-3, and 10-4 may have a planar shape and may be connected to each other at a suitable angle (e.g., a predetermined angle), and thus, the tiled display device TD may have a three-dimensional shape. The tiled display device TD may include a coupling region SM disposed between the display regions DA. The tiled display device TD may be formed by connecting non-display regions NDA of each adjacent display device. The first to fourth display devices 10-1, 10-2, 10-3, and 10-4 may be connected to each other by a coupling member or an adhesive member disposed at the coupling region SM (e.g., in or on the coupling region SM). The distance between the display regions DA of each of the first to fourth display devices 10-1, 10-2, 10-3, and 10-4 may be reduced or minimized such that the coupling region SM is not noticeable to a user. For example, a first horizontal pixel pitch HPP1 between pixels of the first display device 10-1 and pixels of the second display device 10-2 may be the same as or substantially the same as a second horizontal pixel pitch HPP2 between pixels of the second display device 10-2. A first vertical pixel pitch VPP1 between pixels of the first display device 10-1 and pixels of the third display device 10-3 may be the same as or substantially the same as a second vertical pixel pitch VPP2 between pixels of the third display device 10-3. Therefore, the tiled display device TD can improve (e.g., reduce) the sense of discontinuity between the first to fourth display devices 10-1, 10-2, 10-3, and 10-4, and can improve the immersion of the displayed schematic image by preventing or substantially preventing the coupling region SM between the first to fourth display devices 10-1, 10-2, 10-3, and 10-4 from being perceived by the user. FIG. 5 is a plan view showing an example of the display device of FIG. 1. Referring to FIGS. 4 and 5, the display device 10 may include a display area DA and a non-display area NDA. The first to fourth display devices 10-1, 10-2, 10-3, and 10-4 shown in FIG. 4 may have the same or substantially the same (or similar) configuration as the display device 10 shown in FIG. 5. In one embodiment, the display area DA may include a pixel circuit area CCA, a demultiplexing area DMA, a fan-out area FOA, and an electrostatic discharge area ESA. In one embodiment, the demultiplexing area DMA, the fan-out area FOA, and the electrostatic discharge area ESA may be provided at the edge of at least one side of the display area DA. In FIG. 5, the demultiplexing area DMA, the fan-out area FOA, and the electrostatic discharge area ESA are shown as being provided at the upper edge of the display area DA, but their installation positions are not limited thereto. As another example, at least one of the demultiplexing area DMA, the fan-out area FOA, and the electrostatic discharge area ESA may be further provided at at least one of the lower edge, the left edge, and the right edge of the display device 10. The non-display area NDA may include a plurality of pad portions PAD. In one embodiment, the pad portions PAD may electrically connect various driving circuits provided on the second surface (e.g., the rear surface) of the display device 10 to the circuits of the display area DA through signal lines (e.g., predetermined signal lines). The unit pixel UP may include first, second, and third sub-pixels SP1, SP2, and SP3. Each of the first, second, and third sub-pixels SP1, SP2, and SP3 may include a first pixel electrode ETL1 (e.g., an anode AND, or a pixel electrode) and a second pixel electrode ETL2 (e.g., a cathode CTD or a common electrode). For example, in each pixel row, the arrangement of the first and second pixel electrodes ETL1 and ETL2 of the first sub-pixel SP1, the first and second pixel electrodes ETL1 and ETL2 of the second sub-pixel SP2, and the first and second pixel electrodes ETL1 and ETL2 of the third sub-pixel SP3 may be repeated. The first pixel SP1 may include a first light-emitting element ED1 electrically connected to a first pixel electrode ETL1 and a second pixel electrode ETL2. In addition, the first pixel SP1 may further include a first pixel circuit PC1, and the first pixel circuit PC1 is electrically connected to the first light-emitting element ED1 through the first pixel electrode ETL1 included therein. The second pixel SP2 may include a second light-emitting element ED2 electrically connected to a first pixel electrode ETL1 and a second pixel electrode ETL2. The second pixel SP2 may further include a second pixel circuit PC2, and the second pixel circuit PC2 is electrically connected to the second light-emitting element ED2 through the first pixel electrode ETL1 included therein. The third pixel SP3 may include a third light-emitting element ED3 electrically connected to a first pixel electrode ETL1 and a second pixel electrode ETL2. The third pixel SP3 may further include a third pixel circuit PC3, and the third pixel circuit PC3 is electrically connected to the third light-emitting element ED3 through the first pixel electrode ETL1 included therein. In one embodiment, each of the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may be disposed on and overlap with its corresponding first pixel electrode ETL1 and second pixel electrode ETL2. The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may be disposed under (e.g., below) the first pixel electrode ETL1 and the second pixel electrode ETL2 corresponding to the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3. Hereinafter, for ease of explanation, the first and second pixel electrodes ETL1 and ETL2 and / or the first light-emitting element ED1 of the first pixel SP1 are shown as the first pixel SP1 in the drawings. Similarly, the first and second pixel electrodes ETL1 and ETL2 and / or the second light-emitting element ED2 of the second pixel SP2 are shown as the second pixel SP2, and the first and second pixel electrodes ETL1 and ETL2 and / or the third light-emitting element ED3 of the third pixel SP3 are shown as the third pixel SP3. In addition, it is assumed that each unit pixel UP has a configuration including the first, second, and third pixels SP1, SP2, and SP3 as described above. In addition, although one light-emitting element is shown as being disposed in one pixel in FIG. 5, the present disclosure is not limited thereto. For example, each of the first, second, and third pixels SP1, SP2, and SP3 may include at least two light-emitting elements. For example, each of the first, second, and third pixels SP1, SP2, and SP3 may include a main light-emitting element and a repair light-emitting element. The first, second, and third pixels SP1, SP2, and SP3 can be disposed in the electrostatic discharge area ESA, the fan-out area FOA, the demultiplexing area DMA, and the pixel circuit area CCA (e.g., therein or thereon). The unit pixels UP can be arranged to have a uniform or substantially uniform pixel pitch. For example, the pixel pitch (e.g., the horizontal distance) between the unit pixels UP adjacent to each other in the first direction DR1 can be uniform or substantially uniform. In addition, the pixel pitch (e.g., the vertical distance) between the unit pixels UP adjacent to each other in the second direction DR2 can be uniform or substantially uniform. The unit pixels UP can be arranged along a plurality of pixel rows and a plurality of pixel columns (e.g., unit pixel columns). For example, the first, second, and third pixels SP1, SP2, and SP3 can be arranged in the first to ninth pixel rows PROW1, PROW2, PROW3, PROW4, PROW5, PROW6, PROW7, PROW8, and PROW9. The first to ninth pixel rows PROW1, PROW2, PROW3, PROW4, PROW5, PROW6, PROW7, PROW8, and PROW9 can be arranged in sequence along the second direction DR2. Since the sense of difference of the image can be minimized or reduced when the first to ninth pixel rows PROW1, PROW2, PROW3, PROW4, PROW5, PROW6, PROW7, PROW8, and PROW9 including the actual light-emitting area are arranged at a uniform or substantially uniform distance, the first to ninth pixel rows PROW1, PROW2, PROW3, PROW4, PROW5, PROW6, PROW7, PROW8, and PROW9 can be arranged at the same or substantially the same distance from each other. In addition, as shown in FIG. 4, all the pixel rows can be arranged at a uniform or substantially uniform distance. The pixel circuit PC can be disposed at the pixel circuit area CCA (e.g., therein or thereon). The pixel circuit PC can include the first, second, and third pixel circuits PC1, PC2, and PC3. The first pixel circuit PC1 can provide a driving current to the first light-emitting element ED1 of the first pixel SP1, the second pixel circuit PC2 can provide a driving current to the second light-emitting element ED2 of the second pixel SP2, and the third pixel circuit PC3 can provide a driving current to the third light-emitting element ED3 of the third pixel SP3. The pixel circuits PC can be arranged along circuit rows. The first, second, and third pixel circuits PC1, PC2, and PC3 can be repeatedly arranged in the first to ninth circuit rows CROW1, CROW2, CROW3, CROW4, CROW5, CROW6, CROW7, CROW8, and CROW9 along the first direction DR1. The first to ninth circuit rows CROW1, CROW2, CROW3, CROW4, CROW5, CROW6, CROW7, CROW8, and CROW9 can be sequentially arranged along the second direction DR2. The first pixel row PROW1 can be set at the outermost end (e.g., the uppermost end) of the display area DA. The first pixel row PROW1 can be set at an edge or the upper edge of the display area DA. The electrostatic discharge circuit of the electrostatic discharge area ESA can be set in a layer different from (in or on) the layer of the first, second, and third pixels SP1, SP2, and SP3 (e.g., the first pixel electrode ELT1 and the second pixel electrode ELT2). In one embodiment, the first pixel row PROW1 can overlap with the electrostatic discharge area ESA. Thus, the area of the non-display area NDA can be minimized or reduced. The first pixel row PROW1 and the first circuit row CROW1 can be electrically connected to each other. For example, the pixels SP1, SP2, and SP3 of the first pixel row PROW1 can be respectively connected to the pixel circuits PC1, PC2, and PC3 of the first circuit row CROW1. In one embodiment, the first pixel row PROW1 and the first circuit row CROW1 can be spaced apart from each other in the second direction DR2 with a predetermined other configuration therebetween. For example, the second pixel row PROW2 can be set between the first pixel row PROW1 and the first circuit row CROW1. In addition, in one embodiment, the fan-out area FOA can be set between the first pixel row PROW1 and the first circuit row CROW1. The fan-out lines of the fan-out area FOA can be set in a layer different from (e.g., in or on) the layer of the first, second, and third pixels SP1, SP2, and SP3. In other words, in order to minimize the non-display area NDA, the fan-out area FOA can be set within (e.g., inside) the display area DA. The fan-out lines of the fan-out area FOA can be formed at the same layer as (e.g., in the same layer or on) the layer of the pixel circuit PC. For example, the fan-out lines can be formed in the space where the first circuit row CROW1 will be initially set in the display area DA (e.g., in or on). In addition, since the first pixel row PROW1 and the second pixel row PROW2 maintain or substantially maintain the same distance as other pixel rows, the first circuit row CROW1 can be set below (or inside) the second pixel row PROW2. The second pixel row PROW2 can be disposed within (e.g., inside) the display area DA and be more inward from the edge than the first pixel row PROW1. In one embodiment, the second pixel row PROW2 can overlap with the fan-out area FOA. The second pixel row PROW2 and the second circuit row CROW2 can be spaced apart from each other in the second direction DR2. In one embodiment, the first circuit row CROW1 and the third pixel row PROW3 can be disposed between the second pixel row PROW2 and the second circuit row CROW2. In one embodiment, the second circuit row CROW2 can be disposed between the third pixel row PROW3 and the fourth pixel row PROW4. The second pixel row PROW2 and the second circuit row CROW2 can be electrically connected to each other. For example, the pixels SP1, SP2, and SP3 of the second pixel row PROW2 can be respectively connected to the pixel circuits PC1, PC2, and PC3 of the second circuit row CROW2. In one embodiment, a demultiplexing area DMA including a demultiplexer (demux) DMX can be disposed between the second pixel row PROW2 and the first circuit row CROW1, and the demultiplexer DMX can provide data signals (or data voltages) provided from the fan-out lines to corresponding data lines by a time division method. The demultiplexer DMX can be formed at the same layer as the layer of the pixel circuit PC (e.g., within or on it). For example, the demultiplexer DMX can be formed in the space where the second circuit row CROW2 is initially disposed. In addition, since the second pixel row PROW2 and the third pixel row PROW3 maintain or substantially maintain the same distance from other pixel rows, the second circuit row CROW2 can be disposed below (or inside) the third pixel row PROW3. The third pixel row PROW3 can be disposed within (e.g., inside) the display area DA and be more inward from the edge than the second pixel row PROW2. The third pixel row PROW3 and the third circuit row CROW3 can be spaced apart from each other in the second direction DR2. The second circuit row CROW2 can be disposed between the third pixel row PROW3 and the third circuit row CROW3. The third pixel row PROW3 and the third circuit row CROW3 can be electrically connected to each other. For example, the pixels SP1, SP2, and SP3 of the third pixel row PROW3 can be respectively connected to the pixel circuits PC1, PC2, and PC3 of the third circuit row CROW3. The fourth and fifth pixel rows PROW4 and PROW5 can be disposed within (e.g., inside) the display area DA and be more inward from the edge than the third pixel row PROW3. The fourth pixel row PROW4 and the fourth circuit row CROW4 can be adjacent to each other in the second direction DR2, and the fifth pixel row PROW5 and the fifth circuit row CROW5 can be adjacent to each other in the second direction DR2. In one embodiment, the fourth and fifth circuit rows CROW4 and CROW5 can be disposed between the fourth pixel row PROW4 and the fifth pixel row PROW5 and be electrically connected thereto respectively. The sixth and seventh pixel rows PROW6 and POW7 can be disposed within (e.g., inside) the display area DA and be more inward from the edge than the fifth pixel row PROW5. The sixth and seventh pixel rows PROW6 and PROW7 can be disposed at the pixel circuit area CCA (e.g., in or on the pixel circuit area CCA). The sixth pixel row PROW6 and the sixth circuit row CROW6 can be adjacent to each other in the second direction DR2, and the seventh pixel row PROW7 and the seventh circuit row CROW7 can be adjacent to each other in the second direction DR2. The sixth and seventh circuit rows CROW6 and CROW7 can be disposed between the sixth pixel row PROW6 and the seventh pixel row PROW7 and be electrically connected thereto respectively. As described above, since each pixel row can maintain a uniform or substantially uniform distance from an adjacent pixel row, a space where two circuit rows can be disposed can be formed between the fifth pixel row PROW5 and the sixth pixel row PROW6, and signal lines (e.g., predetermined signal lines) can be arranged / extended in the corresponding space. For example, a stage of the gate driver can be disposed in the empty space between two pixel rows. The arrangement and configuration of the eighth and ninth pixel rows PROW8 and PROW9 and the eighth and ninth circuit rows CROW8 and CROW9 can be the same as or substantially the same as those of the sixth and seventh pixel rows PROW6 and PROW7 and the sixth and seventh circuit rows CROW6 and CROW7. In addition, a space where two circuit rows can be formed can be formed between the seventh pixel row PROW7 and the eighth pixel row PROW8. In one embodiment, a gate driver for outputting a gate signal for driving the pixel circuit PC can be disposed at the pixel circuit area CCA (e.g., in or on it). For example, a stage of the gate driver can be disposed in the empty space where the first, second, and third pixel circuits PC1, PC2, and PC3 are not disposed. As described above, since the positions of the first to third circuit rows CROW1, CROW2, and CROW3 in the display area DA of the display area DA change, the demultiplexing area DMA, the fan-out area FOA, and the electrostatic discharge area ESA can be included in the display device 10. Therefore, the non-display area NDA of the display device 10 can be minimized or reduced. In addition, the tiled display device TD can minimize or reduce the distance between the display devices 10 by reducing the non-display area NDA. Therefore, the pixel pitch between adjacent display devices 10 can be designed to be the same as or substantially the same as the pixel pitch inside each display device 10. Therefore, the user's perception of the coupling area SM between the display devices 10 can be prevented or minimized, and the disconnection feeling between the display devices 10 can be improved, thereby enhancing the immersion of the image. FIG. 6 and FIG. 7 are schematic diagrams showing examples of the connection relationship between the pixel circuit and the light-emitting element included in the display device of FIG. 5. Referring to FIG. 5, FIG. 6, and FIG. 7, the pixel SP may include a pixel circuit PC, a first pixel electrode ETL1, a second pixel electrode ETL2, and a light-emitting element ED. In one embodiment, the light-emitting element ED may contact the first pixel electrode ETL1 and the second pixel electrode ETL2, and may be disposed on the first pixel electrode ETL1 and the second pixel electrode ETL2. For example, the first pixel electrode ETL1 may be connected to the light-emitting element ED as an anode, and the second pixel electrode ETL2 may be connected to the light-emitting element ED as a cathode. In addition, the first pixel electrode ETL1 may be electrically connected to the pixel circuit PC. For example, the first pixel electrode ETL1 may be connected to the transistor TFT of the pixel circuit PC. The pixel circuit PC may include a plurality of transistors and at least one capacitor. For example, the pixel circuit PC may have the equivalent circuit shown in FIG. 21. In one embodiment, as shown in FIG. 6, when observed in a plan view, the pixel circuit PC may be disposed below the light-emitting element ED. For example, the pixel SP in FIG. 6 may be applied to the connection relationship between the fourth pixel row PROW4 and the fourth circuit row CROW4. In one embodiment, as shown in FIG. 7, when observed in a plan view, the pixel circuit PC may be disposed above the light-emitting element ED. For example, the pixel SP in FIG. 7 may be applied to the connection relationship between the fifth pixel row PROW5 and the fifth circuit row CROW5. FIG. 8 is a schematic diagram showing an example of a pixel circuit area, a demultiplexing area, a fan-out area, an electrostatic discharge area, and a non-display area included in the display device of FIG. 5. Please refer to FIGS. 5 and 8. Each display device 10 may include a display area DA and a non-display area NDA. For ease of illustration, pixel rows are not shown in FIG. 8. The display area DA may include an electrostatic discharge area ESA, a fan-out area FOA, a demultiplexing area DMA, and a pixel circuit area CCA. In one embodiment, the electrostatic discharge area ESA, the fan-out area FOA, and the demultiplexing area DMA may be disposed at the edge of at least one side of the display area DA. For example, the electrostatic discharge area ESA, the fan-out area FOA, and the demultiplexing area DMA may be disposed at the upper edge of the display area DA. As another example, the electrostatic discharge area ESA, the fan-out area FOA, and the demultiplexing area DMA may be disposed at the left and right edges or the upper and lower edges. As yet another example, at least one of the electrostatic discharge area ESA, the fan-out area FOA, and the demultiplexing area DMA may be disposed at at least one edge of the display device 10 (e.g., therein or thereon). The non-display area NDA may include a pad portion PAD. The electrostatic discharge area ESA may include an electrostatic discharge circuit ESD. In one embodiment, the electrostatic discharge circuit ESD may overlap at least a portion of the first, second, and third pixels SP1, SP2, and SP3 of the first pixel row PROW1. The electrostatic discharge circuit ESD can protect the fan-out lines FOL, the demultiplexer DMX, and the pixel circuit PC from static electricity. The electrostatic discharge circuit ESD can release the static electricity introduced from the outside to prevent or substantially prevent the static electricity from flowing into the display area DA. The fan-out area FOA may include fan-out lines FOL. In one embodiment, the fan-out lines FOL may overlap the first, second, and third pixels SP1, SP2, and SP3 of the second pixel row PROW2. In one embodiment, the fan-out lines FOL may extend from the pad portion PAD to the demultiplexer DMX. The fan-out lines FOL may provide the data voltage (e.g., data signal) received from the pad portion PAD to the demultiplexer DMX. In one embodiment, the fan-out lines FOL may extend from the pad portion PAD to the pixel circuit area CCA. The fan-out lines FOL may provide the clock signal received from the pad portion PAD to the clock line for driving the gate driver, and may provide the power voltage or control voltage received from the pad portion PAD to the voltage line (e.g., a predetermined voltage line) for driving the gate driver. The demultiplexing area DMA may include a demultiplexer DMX. The demultiplexer DMX may provide the data voltage received from the fan-out lines FOL to the first, second, and third data lines DL1, DL2, and DL3 in a time-division method. Since each of the display devices 10 includes the demultiplexer DMX, the number of fan-out lines FOL can be reduced, and the area of the fan-out area FOA can be reduced. The pixel circuit area CCA may include data lines DL. In addition, the pixel circuit area CCA may further include gate lines and a gate driver for driving the pixel circuit PC. The data lines DL may be connected between the demultiplexer DMX and the pixel circuit PC. The data lines DL may extend in a second direction DR2 and may be spaced apart from each other in a first direction DR1. The data lines DL may supply data voltages received from the demultiplexer DMX to the pixel circuit PC. The data lines DL may include first, second, and third data lines DL1, DL2, and DL3. The first data line DL1 may be connected to the first pixel circuit PC1 of each corresponding pixel column. The first data line DL1 may sequentially supply data voltages to the first pixel circuit PC1 provided in each corresponding pixel column. Here, the pixel column may correspond to an arrangement of unit pixels UP configured by first, second, and third sub-pixels SP1, SP2, and SP3 along the second direction DR2. The second data line DL2 may be connected to the second pixel circuit PC2 of each corresponding pixel column. The second data line DL2 may sequentially supply data voltages to the second pixel circuit PC2 provided in each corresponding pixel column. The third data line DL3 may be connected to the third pixel circuit PC3 of each corresponding pixel column. The third data line DL3 may sequentially supply data voltages to the third pixel circuit PC3 provided in each corresponding pixel column. FIG. 9 shows an enlarged view of an example of a part of the electrostatic discharge area and the fan-out area of FIG. 8. Referring to FIGS. 8 and 9, the fan-out line FOL connected to the pad portion PAD may include a first line resistor R1 and a second line resistor R2. In one embodiment, each of the first line resistor R1 and the second line resistor R2 may be formed in a zigzag pattern. The length of each of the first line resistor R1 and the second line resistor R2 may be designed differently according to the position of the fan-out line FOL. For example, by adjusting the lengths of the first line resistor R1 and the second line resistor R2 of the fan-out line FOL respectively, the fan-out line FOL may have the same or substantially the same resistance value. The electrostatic discharge circuit ESD may be provided adjacent to the fan-out line FOL. Some of the electrostatic discharge circuits ESD may be connected between the fan-out line FOL and the gate-off voltage line VGHL, while other electrostatic discharge circuits ESD may be connected between the fan-out line FOL and the gate-on voltage VGLL. The gate-off voltage line VGHL may be a transmission gate-off voltage to turn off the signal line of the transistor included in the display area DA. The gate-on voltage line VGLL may be a transmission gate-on voltage to turn on the signal line of the transistor included in the display area DA. When the gate-off voltage is at a logic high level, the gate-on voltage may be at a logic low level. Conversely, when the gate-off voltage is at a logic low level, the gate-on voltage may be at a logic high level. The electrostatic discharge circuit ESD may be connected to a portion between the first line resistor R1 and the second line resistor R2 of the fan-out line FOL, but the present disclosure is not limited thereto. The electrostatic discharge circuit ESD may release the electrostatic introduced from the outside to prevent or substantially prevent the electrostatic from flowing into the display area DA. FIG. 10 is a perspective view showing a display device according to an embodiment of the present invention, and FIG. 11 is a schematic view showing an example of a part of the second surface of the display device of FIG. 10. FIG. 10 schematically shows the structure of the pad portion PAD and the side connection line SCL. The following description is based on the structure of the pad portion PAD and the side connection line SCL. In addition, FIG. 11 shows an example of other configurations in which the side connection line SCL is connected to the back surface (e.g., the second surface) BS of the substrate SUB. Referring to FIGS. 5, 10, and 11, the display device 10 may include a substrate SUB having a display area DA and a non-display area NDA, a pad portion PAD provided on the upper surface (e.g., the first surface) US of the substrate SUB, a side connection line SCL provided on the upper surface US of the substrate SUB, a back surface BS, and a side surface SS between the upper surface US and the back surface BS. The upper surface US and the back surface BS of the substrate SUB may face each other in the third direction DR3. In one embodiment, the substrate SUB may include a chamfered surface CHM formed by chamfering the edges between the upper surface US and the side surface SS and the edges between the back surface BS and the side surface SS. The side surface SS of the substrate SUB may have an appropriate inclination (e.g., a predetermined inclination) through the chamfered surface CHM. Therefore, disconnection of the side connection line SCL around (e.g., around) the upper surface US, the side surface SS, and the back surface BS of the substrate SUB can be prevented or substantially prevented. The pad portion PAD can be arranged at (e.g., within or above) the non-display area NDA of the upper surface US of the substrate SUB. In FIG. 10, the pad portion PAD is shown as being disposed on one edge of the upper surface US of the substrate SUB, but the present disclosure is not limited thereto, and the pad portion PAD can be disposed on other edges of the upper surface US of the substrate SUB. In one embodiment, as described with reference to FIGS. 8 and 9, the pad portion PAD can be in contact with the side connection line SCL and can be connected to the fan-out line FOL extending to the display area DA, and each fan-out line FOL can be connected to one of the data line DL, power line, and clock line for driving the pixel SP. For example: the power line can include a power line for supplying various appropriate powers to the gate driver and / or the pixel SP, and the clock signal supplied to the gate driver can be provided to the clock line. The side connection line SCL can be connected to the pad portion PAD in a one-to-one manner, and the side connection line SCL can be physically and electrically connected to the pad portion PAD. In one embodiment, the side connection line SCL can completely cover the upper surface of the pad portion PAD. Therefore, the physical and electrical connection between the pad portion PAD and the side connection line SCL can be strengthened. The width of the side connection line SCL can be several tens of μm, and the distance between adjacent side connection lines SCL can be several tens of μm. In one embodiment, the width of the side connection line SCL can be greater than or equal to the distance between adjacent side connection lines SCL. As shown in FIG. 11, the lead LDL, the back surface electrode (e.g., the second surface electrode) BTE, and the flexible film FPCB can be disposed on the back surface (e.g., the second surface) BS of the substrate SUB. The lead LDL can be electrically and physically connected between the side connection line SCL and the back surface electrode BTE. One end of the lead LDL can be physically connected to the side connection line SCL extending to the back surface BS of the substrate SUB. In addition, the other end of the lead LDL can be physically connected to the back surface electrode BTE formed on the back surface (e.g., the second surface) BS of the substrate SUB. The back surface electrode BTE can supply the voltage or signal received from the flexible film FPCB to the side connection line SCL through the lead LDL. In one embodiment, the back surface electrode BTE and the flexible film FPCB can be electrically connected to each other through a conductive adhesive member (e.g., an anisotropic conductive film, etc.). For example: at least a part of the first surface of the flexible film FPCB can be attached to the back surface BS of the substrate SUB through a conductive adhesive member. Additionally, the second surface of the flexible thin film FPCB facing away from the first surface can be connected to the source circuit board, the driving chip, etc. FIG. 12 shows a cross-sectional view of an example of the display device of FIG. 10. Referring to FIGS. 10, 11, and 12, the display device 10 may include a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL. A stacked structure (e.g., a predetermined stacked structure) may be formed on each of the upper surface US and the back surface BS of the substrate SUB. For example, the pixel circuit layer PCL and the display element layer DPL may be disposed on the upper surface US of the substrate SUB. The pixel circuit layer PCL may include a light-shielding layer BML, a buffer layer BF, an active layer ACTL, a first gate insulating layer GI1, a first gate layer GTL1, a second gate insulating layer GI2, a second gate layer GTL2, an interlayer insulating layer ILD, a first source metal layer SDL1, a first via layer VIA1, a second source metal layer SDL2, a second via layer VIA2, a third source metal layer SDL3, and a third via layer VIA3. The display element layer DPL may include a fourth source metal layer SDL4, an anode layer ANDL, a fourth via layer VIA4, and a first protective layer PAS1. A second protective layer PAS2, a back surface electrode BTE, a lead wire LDL, a fifth via layer VIA5, a third protective layer PAS3, and a flexible film FPCB may be disposed on the back surface BS of the substrate SUB. In addition, a side connection line SCL may be disposed on the upper surface US and the back surface BS of the substrate SUB across the side surface SS of the substrate SUB. The substrate SUB may support the display device 10. The substrate SUB may be a base substrate or a base member. The substrate SUB may be a rigid substrate including a glass material. As another example, the substrate SUB may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate SUB may include an insulating material such as a polymer resin such as polyimide PI, but the present disclosure is not limited thereto. The light-shielding layer BML may be disposed on the substrate SUB. The light-shielding layer BML may be a single layer or a multi-layer formed of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. In one embodiment, the light-shielding layer BML may be connected to an electrode (e.g., a source electrode SE) of a transistor TFT (e.g., a driving transistor). As another example, the light-shielding layer BML may overlap at least a portion of the active layer ACTL of the transistor TFT and may block light incident on the active layer ACTL, thereby stabilizing the operating characteristics of the transistor TFT. The buffer layer BF can be disposed on the substrate SUB, and the buffer layer BF can include an inorganic material capable of preventing or substantially preventing the penetration of air and / or moisture. The buffer layer BF can include a plurality of inorganic layers stacked alternately. For example, the buffer layer BF can include multiple layers that alternately stack one or more inorganic layers among silicon nitride layer, silicon oxynitride layer, silicon oxide layer, titanium oxide layer, and aluminum oxide layer. The active layer ACTL can be disposed on the buffer layer BF, and the active layer ACTL can include the channel CH, source electrode SE, and drain electrode DE of the thin film transistor TFT. Here, the thin film transistor TFT can be a thin film transistor constituting the pixel circuit PC. The source electrode SE and the drain electrode DE can become conductive by performing heat treatment on the active layer ACTL. For example, the active layer ACTL can include polysilicon, single crystal silicon, low temperature polysilicon, amorphous silicon, or an oxide semiconductor. As another example, the active layer ACTL can include a first and a second active layer disposed in different layers (e.g., in different layers or on top of each other). In this case, the first active layer can include polysilicon, single crystal silicon, low temperature polysilicon, or amorphous silicon, while the second active layer can include an oxide semiconductor. The first gate insulating layer GI1 can be disposed on the active layer ACTL, and the first gate insulating layer GI1 can insulate the gate electrode GE and the channel CH of the thin film transistor TFT from each other. The first gate insulating layer GI1 can include an inorganic layer. For example, the first gate insulating layer GI1 can include one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. The first gate layer GTL1 can be disposed on the first gate insulating layer GI1, and the first gate layer GTL1 can include: the fan-out line FOL, the gate electrode GE of the thin film transistor TFT, and the first capacitor electrode (e.g., the bottom electrode) CE1 of the first capacitor C1 (e.g., see Figure 21). First, the gate layer GTL1 can be a single layer or multiple layers formed of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys. The fan-out line FOL can be connected to the pad portion PAD that passes through (e.g., penetrates) the interlayer insulating layer ILD and the second gate insulating layer GI2. In one embodiment, the fan-out line FOL can extend from the pad portion PAD to the display area DA, thereby reducing the size of the non-display area NDA. The second gate insulating layer GI2 can be disposed on the first gate layer GTL1, and the second gate insulating layer GI2 can insulate the first gate layer GTL1 and the second gate layer GTL2 from each other. The second gate insulating layer GI2 can include an inorganic layer. For example, the second gate insulating layer GI2 can include one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. The second gate layer GTL2 can be disposed on the second gate insulating layer GI2, and the second gate layer GTL2 can include a second capacitor electrode (or referred to as "upper electrode") CE2 of the first capacitor C1. The second gate layer GTL2 can be a single layer or a multi-layer formed of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys. The interlayer insulating layer ILD can be disposed on the second gate layer GTL2, and the interlayer insulating layer ILD can insulate the first source metal layer SDL1 and the second gate layer GTL2 from each other. The interlayer insulating layer ILD can include an inorganic layer. For example, the interlayer insulating layer ILD can include one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. The structure including the transistor TFT, the buffer layer BF, the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD can be understood as the transistor layer TL. For example, the uppermost layer of the transistor layer TL can be the interlayer insulating layer ILD. The transistor layer TL can be a part of the pixel circuit layer PCL. The first source metal layer SDL1 can be disposed on the interlayer insulating layer ILD of the transistor layer TL, and the first source metal layer SDL1 can include a connection electrode CCE. The connection electrode CCE can be connected to the anode connection line ACL passing through (e.g., penetrating) the first via layer VIA1, and the connection electrode CCE can be connected to the drain electrode DE of the transistor TFT by passing through (e.g., penetrating) the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1. Therefore, the connection electrode CCE can electrically connect the anode connection line ACL and the drain electrode DE to each other. The first pad electrode PAD1 can be formed together with the first source metal layer SDL1. In other words, the first pad electrode PAD1 can be disposed on the interlayer insulating layer ILD in the non-display area NDA. The first pad electrode PAD1 can be connected to the fan-out line FOL through a contact hole passing through (e.g., penetrating) the interlayer insulating layer ILD and the second gate insulating layer GI2. The first source metal layer SDL1 and the first pad electrode PAD1 can be a single layer or a multi-layer formed of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys. The first via layer VIA1 can be disposed on the first source metal layer SDL1, and the first via layer VIA1 can planarize or substantially planarize the upper end of the first source metal layer SDL1. The first via layer VIA1 can include an organic layer, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. In an embodiment, the first via layer VIA1 can be disposed at the display area DA (e.g., within or above the display area DA). The first via layer VIA1 can be spaced apart from the pad portion PAD, e.g., the first via layer VIA1 can be spaced apart from the first pad electrode PAD1. Thus, an interlayer insulating layer exposed area IEA can be formed between the first via layer VIA1 and the pad portion PAD (e.g., the first pad electrode PAD1). The interlayer insulating layer exposed area IEA can be the portion between the first via layer VIA1 and the pad portion PAD, where the upper surface of the interlayer insulating layer ILD is exposed from the first via layer VIA1. The second source metal layer SDL2 can be disposed on the first via layer VIA1, and the second source metal layer SDL2 can include an anode connection line ACL, and the anode connection line ACL can be connected to an anode connection electrode ACE that passes through (e.g., penetrates) the second via layer VIA2. The anode connection line ACL can be connected to the connection electrode CCE by passing through (e.g., penetrating) the first via layer VIA1. Thus, the anode connection line ACL can electrically connect the anode connection electrode ACE and the connection electrode CCE to each other. The second pad electrode PAD2 can be formed together with the second source metal layer SDL2, the second pad electrode PAD2 can be directly disposed on the first pad electrode PAD1, and the second pad electrode PAD2 can be formed at the non-display area NDA (e.g., within or above the non-display area NDA). The second source metal layer SDL2 and the second pad electrode PAD2 can be a single layer or multiple layers formed of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys. The second via layer VIA2 can be disposed on the first via layer VIA1 and the second source metal layer SDL2, the second via layer VIA2 can planarize or substantially planarize the upper end of the second source metal layer SDL2, and the second via layer VIA2 can include an organic layer, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. In one embodiment, the second via layer VIA2 may be disposed at the display area DA (e.g., within or above the display area DA), and the second via layer VIA2 may be spaced apart from the pad portion PAD. In addition, the second via layer VIA2 may form a step difference with the first via layer VIA1 to expose a part of the upper surface of the first via layer VIA1. The part of the first via layer VIA1 exposed from the second via layer VIA2 may be the first exposure area EA1. For example, the width of the first exposure area EA1 in the second direction DR2 may be approximately 10 μm. The third source metal layer SDL3 may be disposed on the second via layer VIA2. The third source metal layer SDL3 may include an anode connection electrode ACE. The anode connection electrode ACE may be connected to the first anode AND1 passing through (e.g., penetrating) the third via layer VIA3, and the anode connection electrode ACE may be connected to the anode connection line ACL by passing through (e.g., by penetrating) the second via layer VIA2. Therefore, the anode connection electrode ACE may electrically connect the anode AND and the anode connection line ACL to each other. The third pad electrode PAD3 may be formed together with the third source metal layer SDL3. The third pad electrode PAD3 may be directly disposed on the second pad electrode PAD2, and the third pad electrode PAD3 may be formed at the non-display area NDA (e.g., within or above the non-display area NDA). The third source metal layer SDL3 and the third pad electrode PAD3 may be a single layer or multiple layers formed of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys. The third via layer VIA3 may be disposed on the second via layer VIA2 and the third source metal layer SDL3. The third via layer VIA3 may planarize or substantially planarize the upper end of the third source metal layer SDL3. The third via layer VIA3 may include an organic layer, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. In one embodiment, the third via layer VIA3 may be disposed at the display area DA (e.g., within or above the display area DA). The third via layer VIA3 may be spaced apart from the pad portion PAD. In addition, the third via layer VIA3 may form a step difference with the second via layer VIA2 to expose a part of the upper surface of the second via layer VIA2. The part of the second via layer VIA2 exposed from the third via layer VIA3 may be the second exposure area EA2. For example, the width of the second exposure area EA2 in the second direction DR2 may be similar to or less than or equal to the width of the first exposure area EA1 in the second direction DR2. As described above, the first, second, and third via layers VIA1, VIA2, and VIA3 can be stacked and have a step shape. The fourth source metal layer SDL4 can be disposed on the third via layer VIA3. The fourth source metal layer SDL4 can include a first anode AND1 and a first cathode CTD1. The first anode electrode AND1 can be connected to the anode connection electrode ACE by passing through (e.g., penetrating) the third via layer VIA3. In FIG. 12, the anode AND and the cathode CTD are adjacent to each other in the second direction DR2 to show and describe the shape of the connection of the anode AND and the cathode CTD of the light-emitting element ED, and to detail the configuration of the light-emitting element ED. However, the arrangement of the anode AND and the cathode CTD is not limited thereto. For example, as shown in FIG. 6 and the like, the anode AND and the cathode CTD can be arranged to be adjacent to each other in the first direction DR1. The fourth pad electrode PAD4 can be formed together with the fourth source metal layer SDL4 and can be directly disposed on the third pad electrode PAD3. The fourth pad electrode PAD4 can be formed in the non-display area NDA (e.g., in or on the non-display area NDA). The fourth source metal layer SDL4 and the fourth pad electrode PAD4 can be a single layer or a multilayer formed of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys. The anode layer ANDL can be disposed on the fourth source metal layer SDL4. The anode layer ANDL can include a second anode AND2 and a second cathode CTD2. In one embodiment, the thickness of the second anode AND2 and the second cathode CTD2 can be less than the thickness of the first anode AND1 and the first cathode CTD1. The fifth pad electrode PAD5 can be formed together with the anode layer ANDL and can be directly disposed on the fourth pad electrode PAD4. For example, the fifth pad electrode PAD5 can contact the upper surface and the side surface of the fourth pad electrode PAD4 and can cover the fourth pad electrode PAD4. The thickness of the fifth pad electrode PAD5 can be less than the thickness of the fourth pad electrode PAD4. The anode layer ANDL and the fifth pad electrode PAD5 can include a transparent conductive material (TCO), such as ITO or IZO. The first anode AND1 and the second anode AND2 can form the anode AND (e.g., the first pixel electrode ETL1 shown in FIG. 5), and the first cathode CTD1 and the second cathode CTD2 can form the cathode CTD (e.g., the second pixel electrode ETL2 shown in FIG. 5). The first to fifth pad electrodes PAD1 to PAD5 can form the pad portion PAD. The pad portion PAD can be disposed on the interlayer dielectric layer ILD at the non-display area NDA (e.g., therein or thereon). The pad portion PAD can supply the voltage or signal received from the side connection line SCL to the fan-out line FOL. The fifth pad electrode PAD5 can be electrically connected to the lead LDL through the side connection line SCL. The fourth via layer VIA4 can be disposed on the third via layer VIA3 where the anode AND and the cathode CTD are not formed. The fourth via layer VIA4 can planarize or substantially planarize the upper end of the third via layer VIA3. The fourth via layer VIA4 can include an organic layer, e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. In one embodiment, the fourth via layer VIA4 can be disposed at the display area DA (e.g., within or above the display area DA). The fourth via layer VIA4 can be spaced apart from the pad portion PAD. In addition, the fourth via layer VIA4 can form a step difference with the third via layer VIA3 to expose a part of the upper surface of the third via layer VIA3. The part of the third via layer VIA3 exposed from the fourth via layer VIA4 can be the third exposed area EA3. For example, the width of the third exposed area EA3 in the second direction DR2 can be similar to or less than or equal to the width of the second exposed area EA2 in the second direction DR2. The first protective layer PAS1 can be disposed on the fourth via layer VIA4 and can cover a part of the anode AND, the cathode CTD, and the pad portion PAD. In addition, the first protective layer PAS1 can contact the interlayer dielectric layer ILD at the interlayer dielectric layer exposed area IEA (e.g., within or above the interlayer dielectric layer exposed area IEA) to cover the interlayer dielectric layer ILD of the interlayer dielectric layer exposed area IEA. In addition, the first protective layer PAS1 can contact the first via layer VIA1, the second via layer VIA2, and the third via layer VIA3. For example, the first protective layer PAS1 can contact the first via layer VIA1 at the first exposed area EA1 (e.g., within or above), contact the second via layer VIA2 at the second exposed area EA2 (e.g., within or above), and contact the third via layer VIA3 at the third exposed area EA3 (e.g., therein or thereon). The first protective layer PAS1 can include an inorganic layer. For example, the first protective layer PAS1 can include one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. The first protective layer PAS1 can not cover (and can expose) a part of the upper surface of the anode AND and a part of the upper surface of the cathode CTD. The light-emitting element ED can contact the anode AND and the cathode CTD not covered by the first protective layer PAS1. In one embodiment, the first protective layer PAS1 may cover all exposed portions of the first to fourth pad electrodes PAD1 to PAD4. For example, the first protective layer PAS1 may contact the exposed portions of the first to fourth pad electrodes PAD1 to PAD4. However, the first protective layer PAS1 may not cover and may expose a portion of the upper surface of the fifth pad electrode PAD5, and the side connection line SCL may contact the pad portion PAD not covered by the first protective layer PAS1. In one embodiment, an additional protective layer including an inorganic material may further include an inorganic material disposed at least at one of between the first via layer VIA1 and the second via layer VIA2, between the second via layer VIA2 and the third via layer VIA3, and between the third via layer VIA3 and the fourth via layer VIA4. The second protective layer PAS2 may be disposed on the back surface BS of the substrate SUB to planarize or substantially planarize the back surface BS of the substrate SUB. The second protective layer PAS2 may include an inorganic layer. For example, the second protective layer PAS2 may include one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. The back surface electrode BTE may be disposed on one surface (e.g., the back surface) of the second protective layer PAS2. The back surface electrode BTE may supply a voltage or signal received from the flexible film FPCB to the side connection line SCL through the lead line LDL, and the back surface electrode BTE may be electrically connected to the flexible film FPCB through the conductive adhesive member ACF. The back surface electrode BTE may include a first back surface electrode BTE1 and a second back surface electrode BTE2. The first back surface electrode BTE1 may be disposed on one surface (e.g., the back surface) of the second protective layer PAS2. The first back surface electrode BTE1 may be a single layer or a multi-layer formed of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. The second back surface electrode BTE2 may be disposed on one surface (e.g., the back surface) of the first back surface electrode BTE1. The second back surface electrode BTE2 may include a transparent conductive material (TCO), such as ITO or IZO. The lead line LDL may be disposed on one surface (e.g., the back surface) of the second protective layer PAS2. The lead line LDL may be formed of the same material as that of the first back surface electrode BTE1 and formed in the same layer (e.g., therein or thereon). The lead line LDL may supply a voltage or signal received from the back surface electrode BTE to the side connection line SCL. For example, as shown in FIG. 11, the lead line LDL may be physically connected to the back surface electrode BTE. The side connection line SCL can be disposed on the lower surface edge, side surface, and upper surface edge of the substrate SUB. One end of the side connection line SCL can be connected to the pad portion PAD, and the other end of the side connection line SCL can be connected to the lead LDL. In one embodiment, on the upper surface US of the substrate SUB, the side connection line SCL can overlap the entire pad portion PAD. For example, when observed in a plan view, the side connection line SCL can cover the entire pad portion PAD. In one embodiment, the side connection line SCL can overlap the interlayer insulation layer exposed area IEA. For example, the side connection line SCL can be disposed on the first protective layer PAS1 at (e.g., within or above) the interlayer insulation layer exposed area IEA. Additionally, on the back surface BS of the substrate SUB, the side connection line SCL can cover a portion of the lead-out line LDL. Therefore, the risk of electrical disconnection between the pad portion PAD and the lead LDL can be reduced. The side connection line SCL can extend across (or through) the side surfaces of the substrate SUB, buffer layer BF, first and second gate insulation layers GI1 and GI2, interlayer insulation layer ILD, and first protective layer PAS1. The side connection line SCL can be a single layer or a multi-layer formed of any one or more of silver (Ag), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys. For example, the side connection line SCL can be formed of silver. The fifth via layer VIA5 can cover at least a portion of the back surface of the back surface electrode BTE and the lead LDL. In addition, the fifth via layer VIA5 can cover a portion of the side connection line SCL. The fifth via layer VIA5 can planarize or substantially planarize the lower end of the substrate SUB. The fifth via layer VIA5 can include an organic layer, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The third protective layer PAS3 can be disposed on one surface (e.g., the back surface) of the fifth via layer VIA5 to protect the back surface electrode BTE and the lead LDL. The third protective layer PAS3 can include an inorganic layer. For example, the third protective layer PAS3 can include one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. The flexible film FPCB can be disposed on one surface (e.g., the rear surface) of the third protective layer PAS3. The flexible film FPCB can be attached to the rear surface of the third protective layer PAS3 using an adhesive member. One side of the flexible film FPCB can supply voltage or signals to the pad portion PAD through the rear surface electrode BTE, lead wire LDL, and side connection line SCL. The other side of the flexible thin film FPCB can be connected to a source circuit board (e.g., below) under the substrate SUB, etc. The flexible thin film FPCB can transmit signals provided from the source circuit board to the display device 10. The conductive adhesive member ACF can attach the flexible film FPCB to the rear surface of the rear surface electrode BTE. For example, the conductive adhesive member ACF can include an anisotropic conductive film. When the conductive adhesive member ACF includes an anisotropic conductive film, the conductive adhesive member ACF can have conductivity in the area where the rear surface electrode BTE and the flexible film FPCB are in contact with the conductive adhesive member ACF. Therefore, the flexible thin film FPCB can be electrically connected to the rear surface electrode BTE. The display device 10 can minimize or reduce the area of the non-display area NDA by including a flexible film FPCB disposed on the rear surface BS of the substrate SUB and a pad portion PAD disposed on the upper surface US of the substrate SUB. The rear surface electrode BTE, lead-out wire LDL, and side connection line SCL electrically connect the flexible film FPCB to the pad portion PAD. The cover layer OC can completely cover the side connection line SCL. For example, the cover layer OC can be formed as a pattern that covers all the plurality of side connection lines SCL. The cover layer OC can cover a part of the upper surface US and a part of the rear surface BS of the substrate SUB. The cover layer OC can be an insulating layer and can include an organic insulating material and / or an inorganic insulating material. The cover layer OC can prevent or substantially prevent contaminants from penetrating into the side surface SS and the edge portion of the display device 10 including the side connection line SCL, and can protect the side connection line SCL. In one embodiment, the cover layer OC can include a black pigment. Therefore, the cover layer OC can completely appear black. Therefore, the cover layer OC can prevent or reduce light reflection from the side connection line SCL, and thus, can improve visibility defects. The black pigment can include at least one of carbon black and titanium black. However, this is provided only as an example, and the black pigment contained in the cover layer OC is not limited thereto. In other words, the cover layer OC can be used as a light-shielding pattern and can be used as a protective layer that protects the side connection line SCL while insulating the side connection line SCL from other lines. In one embodiment, the cover layer OC can be formed on a part of the upper surface US, the side surface SS, and a part of the back surface BS of the upper surface of the substrate SUB by a pad printing process. For example: One end of the cover layer OC on the upper surface US of the substrate SUB and one end of the cover layer OC on the back surface BS of the substrate SUB can coincide or substantially coincide to contact a virtual axis parallel to or substantially parallel to the third direction DR3. The cover layer OC can have a thickness of about 5 to 15 μm. For example: The cover layer OC can have a thickness similar to that of the side connection line SCL. However, this is only provided as an example, and the thickness of the cover layer OC is not limited thereto. In one embodiment, the cover layer OC can overlap with the first exposed area EA1. In other words, the cover layer OC can overlap with at least a part of the upper surface of the first via layer VIA1 exposed from the second via layer VIA2. In addition, one end of the cover layer OC can face one end (e.g., the side surface) of the second via layer VIA2, and the first protective layer PAS1 is interposed between one end of the cover layer OC and one end of the second via layer VIA2. As described above, the second via layer VIA2 is formed with a step difference relative to the first via layer VIA1 and can be used as a dam to prevent or substantially prevent the cover layer OC from overflowing to the anode AND and the cathode CTD. The third and fourth via layers VIA3 and VIA4 can also be used as such dams. Therefore, the cover layer OC can have a uniform or substantially uniform end at the first exposed area EA1 (e.g., therein or thereon) through the dam formed by the second via layer VIA2, and the processability or process deviation of the cover layer OC can be improved. For example: The processability of the cover layer OC formed by the pad printing process can be improved, and the processability of the manufacturing method of the display device 10 including the cover layer process can be improved. Therefore, the reliability and image quality of the manufacturing method of the display device 10 can be improved. The light-emitting element ED can be disposed on the anode AND and the cathode CTD. In an embodiment, the light-emitting element ED can include a flip-chip type micro LED, which includes a first contact electrode CTE1 and a second contact electrode CTE2 facing the anode AND and the cathode CTD, respectively. The light-emitting element ED can be formed of an inorganic material such as GaN. Each dimension of the width, length, and height of the light-emitting element ED can be several to several hundred μm. For example: Each dimension of the width, length, and height of the light-emitting element ED can be about 100 μm or less. The light-emitting element ED can be formed by growing on a semiconductor substrate such as a silicon wafer. The light-emitting element ED can be directly transferred from the silicon wafer onto the anode AND and the cathode CTD of the substrate SUB. As another example, the light-emitting element ED can be transferred onto the anode AND and the cathode CTD of the substrate SUB by an electrostatic method using an electrostatic head or a transfer method using an elastic polymer material such as PDMS or silicone resin as a transfer substrate (stamp). The light-emitting element ED can include a base substrate SSUB, an n-type semiconductor NSEM, an active layer MQW, a p-type semiconductor PSEM, a first contact electrode CTE1, and a second contact electrode CTE2. The base substrate SSUB can be a sapphire substrate, but the present disclosure is not limited thereto. The n-type semiconductor NSEM can be disposed on one surface of the base substrate SSUB. For example, the n-type semiconductor NSEM can be disposed on the lower surface of the base substrate SSUB, and the n-type semiconductor NSEM can be formed of GaN doped with an n-type conductive dopant such as Si, Ge, Se, or Sn. The active layer MQW can be disposed on a part of one surface of the n-type semiconductor NSEM, and the active layer MQW can include materials having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes materials having a multi-quantum well structure, the active layer MQW can have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layer can be formed of InGaN, and the barrier layer can be formed of GaN or AlGaN, but is not limited thereto. As another example, the active layer MQW can have a structure in which a semiconductor material having a large bandgap and a semiconductor material having a small bandgap energy are alternately stacked according to the wavelength band of the emitted light, and can also include different group III-V semiconductor materials. The p-type semiconductor PSEM can be disposed on one surface of the active layer MQW, and the p-type semiconductor PSEM can be formed of GaN doped with a p-type conductive dopant such as Mg, Zn, Ca, Sr, or Ba. The first contact electrode CTE1 can be disposed on the p-type semiconductor PSEM, and the second contact electrode CTE2 can be disposed on another part of one surface of the n-type semiconductor NSEM. Another part of the surface of the n-type semiconductor NSEM provided with the second contact electrode CTE2 can be disposed to be spaced apart from a part of the surface of the n-type semiconductor NSEM provided with the active layer MQW. The first contact electrode CTE1 and the anode AND can be bonded to each other through a conductive bonding member such as an anisotropic conductive film or an anisotropic conductive paste. As another example, the first contact electrode CTE1 and the anode AND can be adhered to each other through a soldering process. In one embodiment, the second contact electrode CTE2 and the cathode CTD may be bonded to each other through a conductive bonding member such as an anisotropic conductive film or an anisotropic conductive paste. As another example, the second contact electrode CTE2 and the cathode CTD may be adhered to each other through a welding process. FIG. 13A is a perspective view showing an example of a side surface of a connection line and a via layer of the display device of FIG. 12, and FIG. 13B is a perspective view showing an example of the display device of FIG. 10. In FIG. 13B, compared with FIG. 10, the cover layer OC is further shown. For ease of explanation, the first protective layer PAS1 is not shown in FIGS. 13A and 13B. For example, in FIG. 13A, the first protective layer PAS1 may be inserted between the cover layer OC and the upper surface of the substrate SUB (for example, refer to FIG. 12). Referring to FIGS. 10, 12, 13A, and 13B, the cover layer OC may be integrally formed on a part of the non-display area of one side surface SS, the upper surface US connected to the side surface SS, and a part of the rear surface BS connected to the side surface SS of the display device 10. In addition, the cover layer OC may integrally cover all side connection lines SCL. As described above, the first, second, and third via layers VIA1, VIA2, and VIA3 may be stacked in sequence in the third direction DR3 while having a step difference therebetween. In one embodiment, each of an end EP1 (for example, one side surface of the first via layer VIA1) of the first via layer VIA1 and an end EP2 (for example, one side surface of the second via layer VIA2) may have a shape extending in a straight line or substantially in a straight line in the first direction DR1. For example, the end EP1 of the first via layer VIA1 and the end EP2 of the second via layer VIA2 may extend parallel or substantially parallel to each other. Therefore, the width of the first exposure area EA1 in the second direction DR2 may be uniform or substantially uniform. For example, the width of the first exposure area EA1 in the second direction DR2 may be about 10 μm. Similarly, an end EP3 (for example, one side surface of the third via layer VIA3) of the third via layer VIA3 may also have a shape extending in a straight line or substantially in a straight line in the first direction DR1. For example, the end EP3 of the third via layer VIA3 and the end EP2 of the second via layer VIA2 may extend parallel or substantially parallel to each other. Therefore, the width of the second exposure area EA2 in the second direction DR2 may be uniform or substantially uniform. The covering layer OC can be formed to cover at least a part of the first exposed area EA1. The second via layer VIA2 can be used as a dam, and the covering layer OC can be formed not to extend beyond (e.g., not to pass through) the upper surface of the second via layer VIA2. As described above, since the ends EP1, EP2, and EP3 of the first, second, and third via layers VIA1, VIA2, and VIA3 are formed as straight lines or substantially straight lines, the ends of the covering layer OC can be formed at consistent or substantially consistent positions. Therefore, the processability of the covering layer OC and the display device 10 including the same can be improved. In addition, through the dam functions of the second, third, and fourth via layers VIA2, VIA3, and VIA4, the covering layer OC can be prevented or substantially prevented from overflowing onto the anode AND and the cathode CTD. FIG. 14 shows a cross-sectional view of an example of the display device of FIG. 10. In FIG. 14, the same reference numerals are used for the same or substantially the same elements as those described above with reference to FIG. 12, and thus their redundant descriptions will not be repeated. Except that the black anisotropic conductive film BACF is further included in FIG. 14, the display device of FIG. 14 can be the same as or substantially the same as the display device of FIG. 12. Referring to FIGS. 10 and 14, the display device 10 can include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, a side connection line SCL, and a covering layer OC. In an embodiment, the display element layer DPL can further include a black anisotropic conductive film BACF, and the black anisotropic conductive film BACF can be disposed adjacent to the light-emitting element ED. For example, after forming the first protective layer PAS1 and the covering layer OC, the black anisotropic conductive film BACF can be disposed on the first protective layer PAS1 and the covering layer OC. The emission area of the pixel SP can be defined by the black anisotropic conductive film BACF, and the black anisotropic conductive film BACF can be configured to include at least one light-shielding material and / or reflective material to prevent or substantially prevent light leakage, where light (e.g., light rays) leaks between adjacent pixels SP (e.g., between adjacent light-emitting elements ED). The black anisotropic conductive film BACF can include an organic material, and the organic material increases the strength of the adhesion between the light-emitting element ED and the anode AND and the cathode CTD, while stably fixing the light-emitting element ED. In addition, the black anisotropic conductive film BACF can absorb external light rays to improve the contrast of the screen. In addition, the black anisotropic conductive film BACF can serve as a dam wall (e.g., as a pixel defining layer) for defining the emission area of adjacent pixels SP. For example, the black anisotropic conductive film BACF can include a black pigment and conductive fine particles FCP. The first contact electrode CTE1 and the anode AND can be electrically connected to each other through the conductive fine particles FCP that contact the first contact electrode CTE1 and the anode AND, and the second contact electrode CTE2 and the cathode CTD can be electrically connected to each other through the conductive fine particles FCP that contact the second contact electrode CTE2 and the cathode CTD. FIG. 15 shows a cross-sectional view of an example of the display device of FIG. 10. In FIG. 15, the same reference numerals are used for the same or substantially the same components as those described above with reference to FIG. 12, and thus their redundant descriptions will not be repeated. The display device of FIG. 15 can be the same as or substantially the same as the display device of FIG. 12, except that a cover layer COV is further included in FIG. 12. Referring to FIGS. 10 and 15, the display device 10 may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, a side connection line SCL, and a cover layer OC. In one embodiment, the display device 10 may further include a cover layer COV, and the cover layer COV may be disposed on the display element layer DPL using an intermediate layer CTL. For example, the cover layer COV may protrude beyond the side surface of the substrate SUB (or the non-display area NDA of the display device). The intermediate layer CTL may be a transparent adhesive layer (or an adhesive layer), such as an optically transparent adhesive layer, for strengthening the adhesion between the display element layer DPL and the cover layer COV, but the present invention is not limited thereto. According to one embodiment, the intermediate layer CTL may include a filler formed of an insulating material having insulating properties and adhesive properties. The cover layer COV may include a first layer FL and a second layer SL sequentially disposed on the intermediate layer CTL. The first layer FL may be a light transmittance control layer designed to reduce the transmittance of external light or light reflected from the display device 10, and can prevent or substantially prevent the distance between adjacent display devices 10 from being perceived from the outside through the first layer FL. The first layer FL may include a phase retardation layer, but the present disclosure is not limited thereto. The second layer SL may be an anti-glare layer designed to diffusely reflect external light to prevent or substantially prevent a reduction in the visibility of a schematic image due to the reflection of external light. The contrast of the image displayed by the display device 10 can be increased by the second layer SL. The second layer SL may include a polarizing plate, but the present disclosure is not limited thereto. FIG. 16 shows a cross-sectional view of an example of the display device of FIG. 10 In FIG. 16, the same reference numerals are used for the same or substantially the same components as described above with reference to FIG. 12, and thus their redundant descriptions will not be repeated. The display device of FIG. 16 may be the same as or substantially the same as the display device of FIG. 12, except that a chamfered surface CHM is further included in FIG. 16. Referring to FIGS. 10 and 16, the display device 10 may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, a side connection line SCL, and a cover layer OC. In one embodiment, the substrate SUB may include a chamfered surface CHM formed between the upper surface US and the side surface SS and / or between the rear surface BS and the side surface SS. The side surface SS of the substrate SUB may have an inclination (e.g., a predetermined inclination) caused by the chamfered surface CHM. Therefore, disconnection of the side connection line SCL around the upper surface US, the side surface SS, and the rear surface BS of the substrate SUB can be prevented or substantially prevented. In addition, when the display device 10 is implemented as a tiled display device TD, the chamfered surface CHM can prevent or substantially prevent the substrates SUB of the display devices 10 from colliding with each other and being damaged. FIG. 17 shows a cross-sectional view of an example of the display device of FIG. 10. In FIG. 17, the same reference numerals are used for the same or substantially the same components as described above with reference to FIG. 12, and thus their redundant descriptions will not be repeated. The display device of FIG. 17 may be the same as or substantially the same as the display device of FIG. 12, except that the cover layer OC formed at the end in FIG. 17 may be different. Referring to FIGS. 10 and 17, the display device 10 may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, a side connection line SCL, and a cover layer OC. In one embodiment, the cover layer OC may extend to the second exposed area EA2. For example, the cover layer OC may overlap with the upper surface of the second via layer VIA2 exposed from the third via layer VIA3, and one end of the cover layer OC may face one end (e.g., the side) of the third via layer VIA3, and the first protective layer PAS1 is interposed between one end of the cover layer OC and one end of the third via layer VIA3. The third via layer VIA3 can prevent or substantially prevent the cover layer OC from overflowing beyond the third via layer VIA3 during the pad printing process of the cover layer OC, and the cover layer OC may appear black. Considering the visibility of the front surface of the display device 10, the cover layer OC can be adjusted according to the product to extend from the upper surface US of the substrate SUB to the end of the display area DA. FIG. 18 is a schematic diagram showing an example of a method of forming a cover layer in the display device of FIG. 10, FIG. 19 is a schematic diagram showing an example of a cover layer formed in the display device of FIG. 10, and FIG. 20 is a schematic diagram showing an example of a method of forming a cover layer in the display device of FIG. 10. Referring to FIGS. 10, 12, 13B, 18, 19, and 20, the cover layer OC can be transferred to the substrate SUB by a printing technique using a stereoscopic pad. The stereoscopic pad may include a silicon mold SIM, but the present disclosure is not limited thereto. First, the cover layer material OCM can be transferred to the silicon mold SIM. The cover layer material OCM may include an organic material. For example, the cover layer material OCM may include a monomer (e.g., an epoxy resin-based material) that can be refluxed during the curing (e.g., high-temperature curing) of the cover layer OC. In addition, the cover layer material OCM may include a black pigment for exhibiting black. The black pigment may include carbon black, titanium black, etc. The cover layer material OCM may further include a dispersant for uniformly dispersing the black pigment in the organic insulating material. The silicon mold SIM may be a flexible pad. For example, the silicon mold SIM may have a certain degree of elastic force, and under this elastic force, its shape will be deformed due to an externally applied force and then return to its original shape when the force is removed. In one embodiment, as shown in FIG. 18, the silicon mold SIM may include a groove GRV corresponding to the shape of the cover layer OC. Through the process of picking up the cover material OCM using the silicon mold SIM, the cover material OCM can be transferred (e.g., applied) to the groove GRV of the silicon mold SIM (e.g., which may be a transfer area) from a pad image plate body (e.g., a predetermined pad image plate body) that provides the cover layer material OCM thereon. However, the present disclosure is not limited thereto, and as shown in FIG. 20, the transfer area where the cover layer material OCM is transferred to the silicon mold SIM may be a protrusion protruding relative to the periphery of the silicon mold SIM. A pad printing process can be performed. The silicon mold SIM is set with its side surface SS facing the substrate SUB, and then the silicon mold SIM is closely attached and pressed against the edge region of the upper surface US and the edge region of the back surface BS of the substrate SUB. Thus, as shown in Fig. 19, the covering layer OC can be formed to cover the side connection line SCL. In addition, the covering layer OC can be prevented or substantially prevented from overflowing beyond the second via layer VIA2 which serves as a dam, and the covering layer OC can be formed uniformly or substantially uniformly. Therefore, the process capability (e.g., process dispersion) of the pad printing process of the covering layer OC can be improved. Fig. 21 shows a circuit diagram of an example of the pixels included in the display device of Fig. 5, and Fig. 22 shows a layout diagram of an example of the pixel circuit included in the pixel of Fig. 21. Referring to Fig. 21 and Fig. 22, the pixel PX may include a pixel circuit PC and a light-emitting element ED. The light-emitting element ED may be an inorganic light-emitting diode of micron size or nano size. For example, the light-emitting element ED may be a flip-chip type micro light-emitting diode element. In one embodiment, the pixel circuit PC may include a pulse width modulation (PWM) circuit PWMC and a current generation circuit CGC. The current generation circuit CGC can generate a constant or substantially constant current (hereinafter referred to as a driving current) having a suitable or desired magnitude (e.g., a predetermined magnitude), and can supply the current to the light-emitting element ED. The PWM circuit PWMC can control the time for supplying the driving current to the light-emitting element ED based on the PWM data voltage V_PWM. As shown in Fig. 22, the initialization voltage line VIL, the initialization scan line GIL, the write scan line GWL, the PWM emission control line PWEL, the horizontal power line HVDL, the gate-off voltage line VGHL, the scan signal line SWPL, the control scan line GCL, the PAM emission control line PAEL, the test signal line TSTL, and the third power line VSL can extend in the first direction DR1 and can be spaced apart from each other in the second direction DR2. The initialization voltage line VIL, the initialization scan line GIL, the write scan line GWL, the PWM emission control line PWEL, the horizontal power line HVDL, the gate-off voltage line VGHL, the scan signal line SWPL, the control scan line GCL, the PAM emission control line PAEL, the test signal line TSTL, and the third power line VSL can be formed by the first source metal layer SDL1 provided on the interlayer insulating layer ILD. For example, the initialization scan line GIL, the write scan line GWL, the PWM emission control line PWEL, the control scan line GCL, the PAM emission control line PAEL, and the test signal line TSTL can be connected to the gate electrodes of the corresponding transistors through contact holes passing through (e.g., penetrating) the interlayer insulating layer ILD and the second gate insulating layer GI2. For example, the initialization voltage line VIL, the horizontal power line HVDL, the gate turn-off voltage line VGHL, the scan signal line SWPL, and the third power line VSL can be connected to the source electrode SE or the drain electrode DE of the corresponding transistors through contact holes passing through (e.g., penetrating) the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1. The data line DL, the vertical power line VVDL, and the PAM data line RDL can extend in the second direction DR2 and can be spaced apart from each other in the first direction DR1. The data line DL, the vertical power line VVDL, and the PAM data line RDL can be formed by the second source metal layer SDL2 provided on the first via layer VIA1. The data line DL and the PAM data line RDL can be connected to the source electrode SE or the drain electrode DE of the corresponding transistors through contact holes passing through (e.g., penetrating) the first via layer VIA1, the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1. In one embodiment, the vertical power line VVDL and the horizontal power line HVDL can be provided in different layers (e.g., within or above each other), and can be connected to each other through contact holes passing through (e.g., penetrating) the first via layer VIA1. The vertical power line VVDL and the horizontal power line HVDL can form the first power line VDL1. In one embodiment, the second power line VDL2 can be formed by the third source metal layer SDL3 provided on the second via layer VIA2. The second power line VDL2 can be connected to the sixth and seventh transistors T6 and T7 through contact holes passing through (e.g., penetrating) the second via layer VIA2 and the first via layer VIA1. Each of the first to nineteenth transistors T1 to T19 can be stacked in a structure similar to the structure of the transistor TFT described above with reference to FIG. 16. For example, each of the first to nineteenth transistors T1 to T19 can include a channel CH, a source electrode SE, and a drain electrode DE formed in the active layer ACTL, and a gate electrode GE formed in the first gate layer GTL1. For convenience of illustration, in FIG. 22, the gate electrode GE formed in the first gate layer GTL1 and the channel CH of the active layer ACTL overlapping with the gate electrode GE are defined as the transistors T1 to T19. It can be understood that the opposite sides of the channel CH of the active layer ACTL are the source electrode SE and the drain electrode DE (e.g., one electrode and the other electrode). In one embodiment, the active layer ACTL including the channels CH, source electrodes SE, and drain electrodes DE of the first to nineteenth transistors T1 to T19 may be integrally formed. Each of the first to third capacitors C1, C2, and C3 may be stacked in a structure similar to that of the first capacitor C1 described above with reference to FIG. 12. For example, each of the first to third capacitors C1, C2, and C3 may include a lower electrode CE1 formed in the first gate layer GTL1 and an upper electrode CE2 formed in the second gate layer GTL2. In one embodiment, the current generation circuit CGC may include the first to eleventh transistors T1 to T11, and the first capacitor C1. The first transistor T1 may serve as a driving transistor to generate a driving current supplied to the light-emitting element ED during the light-emitting period. The second transistor T2 may be connected between the PAM data line RDL and the second node N2. The gate electrode of the second transistor T2 may be connected to the write scan line GWL through a contact hole, and the second transistor T2 may be turned on in response to a write scan signal supplied to the write scan line GWL. The PAM data voltage V_PAM may be supplied to the PAM data line RDL, and the PAM data voltage V_PAM may determine the magnitude of the driving current. Unlike an organic light-emitting diode, the light-emitting brightness of the light-emitting element ED, which is an inorganic light-emitting diode, is not insensitive to changes in the driving current. Therefore, the light-emitting brightness of the light-emitting element ED may be controlled by the time of supplying the driving current rather than by the magnitude of the driving current. In one embodiment, the PAM data voltage V_PAM may be supplied to the same type of sub-pixels that emit the same color of light with the same or substantially the same amplitude, regardless of the gray level or the like. However, the present disclosure is not limited thereto, and the PAM data voltage V_PAM may be changed according to a reference (e.g., a predetermined reference). The third transistor T3 may be electrically connected between the gate electrode of the first transistor T1 (e.g., the first node N1) and the drain electrode of the first transistor T1 (e.g., the third node N3). The gate electrode of the third transistor T3 may be connected to the write scan line GWL. The third transistor T3 may be turned on together with the second transistor T2, and may diode-connect the first transistor T1, thereby compensating for the threshold voltage of the first transistor T1. In one embodiment, the third transistor T3 may have a form in which a plurality of transistors are connected in series and includes a commonly connected gate electrode. For example, as shown in FIG. 22, the gate electrode of the third transistor T3 may be divided into two branches, and each of the two branches may overlap the active layer ACTL. The fourth transistor T4 can be connected between the first node N1 and the initialization voltage line VIL to provide the voltage of the initialization power supply Vint. The gate electrode of the fourth transistor T4 can be connected to the initialization scan line GIL through a contact hole. The fourth transistor T4 can be turned on in response to the initialization scan signal provided to the initialization scan line GIL. When the fourth transistor T4 is turned on, the voltage of the initialization power supply Vint can be provided to the first node N1. In other words, the gate voltage of the first transistor T1 can be initialized. In one embodiment, the fourth transistor T4 can be in the form of multiple transistors connected in series, including gate electrodes connected together. For example, as shown in FIG. 22, the gate electrode of the fourth transistor T4 can be divided into two branches, and each of the two branches can overlap with the active layer ACTL. The voltage of the initialization power supply Vint can be low enough to turn on the transistor. The fifth transistor T5 can be connected between the third node N3 and the anode electrode of the light-emitting element ED (e.g., the fourth node N4). For example, the drain electrode of the fifth transistor T5 can be connected to the anode connection electrode ACE through a contact hole, and the anode connection electrode ACE can be connected to the anode AND in FIG. 16 through a contact hole. The gate electrode of the fifth transistor T5 can be connected to the PAM emission control line PAEL through a contact hole. The fifth transistor T5 can be turned on in response to the PAM emission control signal provided to the PAM emission control line PAEL. The sixth transistor T6 can be connected between the second power supply line VDL2 for providing the voltage of the second power supply VDD2 and the second node N2. The gate electrode of the sixth transistor T6 can be connected to the PWM emission control line PWEL through a contact hole. The sixth transistor T6 can be turned on in response to the PWM emission control signal provided to the PWM emission control line PWEL. In one embodiment, the PWM emission control signal and the PAM emission control signal can be provided at the same or substantially the same timing. The seventh transistor T7 can be connected between the second power supply line VDL2 and the second capacitor electrode CE2 of the first capacitor C1 (as shown in FIG. 16, for example, the upper electrode CE2). The second capacitor electrode CE2 of the first capacitor C1 can be formed in the second gate layer GTL2. The gate electrode of the seventh transistor T7 can be connected to the PWM emission control line PWEL through a contact hole. The seventh transistor T7 can be turned on in response to the PWM emission control signal. Therefore, the second capacitor electrode CE2 of the first capacitor C1 can be connected to the second power supply VDD2 during emission. The eighth transistor T8 can be connected between the first power supply line VDL1 for providing the voltage of the first power supply VDD1 and the second capacitor electrode CE2 of the first capacitor C1. For example, one electrode of the eighth transistor T8 can be connected to the first power supply line VDL1 through a contact hole, and the other electrode can be connected to the second capacitor electrode CE2 of the first capacitor C1 through a contact hole. The gate electrode of the eighth transistor T8 can be connected to the control scan line GCL through a contact hole, and the eighth transistor T8 can be turned on in response to the control scan signal. When the eighth transistor T8 is turned on, the voltage of the first power supply VDD1 can be supplied to the second capacitor electrode CE2 of the first capacitor C1. The voltage of the first power supply VDD1 and the voltage of the second power supply VDD2 can be the same or substantially the same, or they can be different. The write scan signal, the initialization scan signal, and the control scan signal can be provided during the non-emitting period. The initialization scan signal can be provided before the write scan signal is provided. In addition, the control scan signal can be provided at the same or substantially the same timing as the timing of the write scan signal. However, the present disclosure is not limited thereto, and the control scan signal can be provided after the write scan signal is provided. The first capacitor electrode CE1 of the first capacitor C1 can be connected to the gate electrode of the first transistor T1, or in other words, connected to the first node N1. For example, the first capacitor electrode CE1 of the first capacitor C1 and the gate electrode of the first transistor T1 can be integrally formed, and the overlapping portion of the gate electrode of the first transistor T1 and the second capacitor electrode CE2 of the first capacitor C1 can be understood as the first capacitor electrode CE1. The first capacitor C1 can be used as a storage capacitor for storing the PAM data voltage V_PAM. The ninth transistor T9 can be connected between the drain electrode of the fifth transistor T5 corresponding to the fourth node N4 and the initialization voltage line VIL, and one electrode of the ninth transistor T9 can be connected to the initialization voltage line VIL through a contact hole. The gate electrode of the ninth transistor T9 can be connected to the control scan line GCL through a contact hole. The ninth transistor T9 can supply the voltage of the initialization power supply Vint to the fourth node N4 in response to the control scan signal. Therefore, the voltage of the initialization power supply Vint can be supplied to the anode AND through the anode connection electrode ACE. The tenth transistor T10 can be connected between the fourth node N4 and the third power supply line VSL to provide the third power supply VSS, and the tenth transistor T10 can be turned on in response to the test voltage supplied to the test signal line TSTL. During the manufacturing process, before the light-emitting element ED and the pixel circuit PC are connected to each other, the tenth transistor T10 can be turned on according to a test voltage to check whether the pixel circuit PC is abnormal. One electrode of the tenth transistor T10 can be electrically connected to the anode connection electrode ACE through a contact hole, and the other electrode can be connected to the third power line VSL through a contact hole. The voltage of the third power supply VSS supplied to the third power line VSL can be lower than the voltages of the first power supply VDD1 and the second power supply VDD2. For example, the voltage of the third power supply VSS can correspond to the ground voltage. The gate electrode of the tenth transistor T10 can be connected to the test signal line TSTL through a contact hole. The eleventh transistor T11 can be connected between the third node N3 and the fifth transistor T5. For example, the eleventh transistor T11 can be formed between the first transistor T1 and the fifth transistor T5. The gate electrode of the eleventh transistor T11 can be connected to the lower electrode of the third capacitor C3. The gate electrode of the eleventh transistor T11 and the lower electrode of the third capacitor C3 can be connected to the ninth node N9. The eleventh transistor T11 can be turned on based on the voltage of the ninth node N9, and the turn-on time of the eleventh transistor T11 can correspond to the emission period of the light-emitting element ED (for example, the emission duty). The pulse width modulation PWMC circuit can control the turn-on time of the eleventh transistor T11 according to the PWM data voltage V_PWM. The PWM circuit PWMC can include the twelfth to nineteenth transistors T12 to T19, the second capacitor C2, and the third capacitor C3. The twelfth transistor T12 can be turned on during the emission period based on the PWM data voltage V_PWM and the scan voltage supplied to the scan signal line SWPL. The twelfth transistor T12 can be connected between the sixth node N6 and the seventh node N7. The gate electrode of the twelfth transistor 12 can correspond to the fifth node N5. The thirteenth transistor T13 can be connected between the data line DL and the sixth node N6 (for example, one electrode of the twelfth transistor T12). The gate electrode of the thirteenth transistor T13 can be connected to the write scan line GWL through a contact hole. The thirteenth transistor T13 can supply the PWM data voltage V_PWM to the sixth node N6 in response to the write scan signal. The fourteenth transistor T14 can be connected between the fifth node N5 and the seventh node N7. For example, the twelfth transistor T12 and the fourteenth transistor T14 can be connected to each other through a connection pattern (for example, a predetermined connection pattern) of the second source metal layer SDL2. The gate electrode of the fourteenth transistor T14 can be connected to the write scan line GWL through a contact hole. The fourteenth transistor T14 can compensate for the threshold voltage of the twelfth transistor T12 by diode - connecting the twelfth transistor T12 in response to a write scan signal, and the PWM data voltage V_PWM with the compensated threshold voltage can be provided to the fifth node N5. In one embodiment, the fourteenth transistor T14 can be in the form of multiple transistors connected in series and includes a commonly - connected gate electrode. For example, as shown in FIG. 22, the gate electrode of the fourteenth transistor T14 can be divided into two branches, and each of the two branches can overlap with the active layer ACTL. The fifteenth transistor T15 can be connected between the fifth node N5 and the initialization voltage line VIL. The gate electrode of the fifteenth transistor T15 can be connected to the initialization scan line GIL through a contact hole. The fifteenth transistor T15 can supply the voltage of the initialization power source Vint to the fifth node N5 in response to an initialization scan signal provided to the initialization scan line GIL. In one embodiment, the fifteenth transistor T15 can be in the form of multiple transistors connected in series and includes a commonly - connected gate electrode. For example, as shown in FIG. 22, the gate electrode of the fifteenth transistor T15 can be divided into two branches, and each of the two branches can overlap with the active layer ACTL. The sixteenth transistor T16 can be connected between the first power line VDL1 and the sixth node N6, and the gate electrode of the sixteenth transistor T16 can be connected to the PWM emission control line PWEL through a contact hole. The seventeenth transistor T17 can be connected between the seventh node N7 and the ninth node N9, and the gate of the seventeenth transistor T17 can be connected to the PWM emission control line PWEL through a contact hole. The sixteenth and seventeenth transistors T16 and T17 can be turned on in response to a PWM emission control signal. In other words, the sixteenth and seventeenth transistors T16 and T17 can provide a conductive path between the first power line VDL1 and the ninth node N9. The eighteenth transistor T18 can be connected between the eighth node N8 connected to the scan signal line SWPL and the gate - off voltage line VGHL for providing a gate - off voltage (e.g., a high - potential voltage) VGH. For example, one electrode of the eighteenth transistor T18 can be connected to the scan signal line SWPL through a contact hole, and the other electrode can be connected to the gate - off voltage line VGHL through a contact hole. The eighteenth transistor T18 can supply the high - potential voltage VGH to the eighth node N8 in response to a control scan signal. Therefore, when the fifteenth and eighteenth transistors T15 and T18 are turned on simultaneously (e.g., at the same time), the voltage difference between the gate-off voltage VGH and the voltage of the initialization power supply Vint can be stored at the opposite ends of the second capacitor C2. The nineteenth transistor T19 can be connected between the ninth node N9 and the initialization voltage line VIL. One electrode of the nineteenth transistor T19 can be connected to the gate of the eleventh transistor T11 through a contact hole and a connection pattern connected thereto, and the other electrode of the nineteenth transistor T19 can be connected to the initialization voltage line VIL through a contact hole. The gate of the nineteenth transistor T19 can be connected to the control scan line GCL through a contact hole, and the nineteenth transistor T19 can supply the voltage of the initialization power supply Vint to the ninth node N9 in response to the control scan signal. In addition, the third capacitor C3 can be connected between the ninth node N9 and the initialization voltage line VIL. For example, the lower electrode of the third capacitor C3 can be integrally formed with the gate electrode of the eleventh transistor T11, the upper electrode of the third capacitor C3 can overlap with the initialization voltage line VIL formed in the second gate layer GTL2, and the upper electrode of the third capacitor C3 can be connected to the initialization voltage line VIL through a contact hole. Therefore, the voltage of the initialization power supply Vint can be charged in the third capacitor C3, and the ninth node N9 can hold or substantially hold the voltage of the initialization power supply Vint. In one embodiment, the nineteenth transistor T19 can have a form in which multiple transistors are connected in series and includes a commonly connected gate electrode. For example, as shown in FIG. 22, the gate electrode of the nineteenth transistor T19 can have a curved shape, and its two parts can overlap with the active layer ACTL. When the fifth and sixth transistors T5 and T6 are turned on, a current path can be formed between the second power line VDL2 and the third power line VSL through the turned-on eleventh transistor T11, and the light-emitting element ED can emit light. For example, the emission of the light-emitting element ED can start in the off state of the twelfth transistor 12. The PWM circuit PWMC can control the emission time of the light-emitting element ED based on the voltage set at the fifth node N5. For example, the PWM circuit PWMC can control the supply of the drive current by controlling the operation of the eleventh transistor T11 based on the voltage set at the fifth node N5. In one embodiment, the PWM data voltage V_PWM may have a voltage range that turns off the twelfth transistor T12. For example, the PWM data voltage V_PWM may be determined within a voltage range of 10V to 15V. In this case, the voltage of the first power supply VDD1 may be approximately 10V. Therefore, when the sixteenth and seventeenth transistors T16 and T17 are turned on and the voltage of the first power supply VDD1 is supplied to the sixth node N6, the gate-source voltage of the twelfth transistor T12 is greater than or equal to the threshold voltage. Thus, the twelfth transistor T12 can be turned off. When the twelfth transistor T12 is turned off, the eleventh transistor T11 can be maintained or substantially maintained in the on state by the voltage of the initialization power supply Vint stored in the third capacitor C3, and the light emission time of the light emitting element ED can be maintained or substantially maintained. On the other hand, when the voltage of the fifth node N5 changes and the gate-source voltage of the twelfth transistor T12 drops to less than or equal to the threshold voltage, the twelfth transistor T12 can be turned on, and the voltage of the first power supply VDD1 can be supplied to turn off the eleventh transistor T11. Thus, the emission of the light emitting element ED can be stopped. More specifically, the scan voltage supplied to the scan signal line SWPL can change synchronously with the supply of the PAM emission control signal and the PWM emission control signal. For example, the scan voltage may have a triangular waveform that decreases during the period when the PAM emission control signal and the PWM emission control signal are supplied. For example, the scan voltage may be a voltage that linearly drops from 15V to 10V, but the present disclosure is not limited thereto. Since the change in the scan voltage is coupled to the fifth node N5 through the second capacitor C2, the voltage of the fifth node N5 can change according to the change in the scan voltage. Therefore, the time point when the twelfth transistor T12 is turned on can be determined according to the magnitude of the voltage set at the fifth node N5 by writing the PWM data voltage V_PWM, and the light emission time of the light emitting element ED can be controlled. The emission brightness can be adjusted by controlling the light emission time of the light emitting element ED. However, the structure of the pixel circuit is not limited to the structures shown in FIGS. 21 and 22, and various known pixel circuit structures can be implemented. FIG. 23 is a cross-sectional view showing an example of the connection between the display devices included in the tiled display device of FIG. 4. Referring to FIGS. 4, 12, 14, 15, 16, 17, and 23, the tiled display device TD may include a first display device 10-1 and a second display device 10-2 that are adjacent to each other and connected. The first display device 10-1 may include a first substrate SUB1, a light-emitting element ED, a first cover layer COV1, a first side connection line SCL1, and a first overcoat OC1. The first substrate SUB1, the light-emitting element ED, and the first cover layer COV1 may be stacked in sequence along a third direction DR3. The second display device 10-2 may include a second substrate SUB2, a light-emitting element ED, a second cover layer COV2, a second side connection line SCL2, and a second overcoat OC2. The second substrate SUB2, the light-emitting element ED, and the second cover layer COV2 may be stacked in sequence along the third direction DR3. Each of the first cover layer COV1 and the second cover layer COV2 may have the same or substantially the same configuration as the cover layer COV described above with reference to FIG. 15. Each of the first substrate SUB1 and the second substrate SUB2 may include the structure of the substrate SUB and the pixel circuit layer PCL described above with reference to FIGS. 12, 14, 15, 16, and 17. Each of the first display device 10-1 and the second display device 10-2 may include a chamfered surface CHM. When the first display device 10-1 and the second display device 10-2 are combined with each other, the chamfered surface CHM may prevent or substantially prevent the first substrate SUB1 and the second substrate SUB2 from colliding with and damaging each other. The first side connection line SCL1 and the first overcoat OC1 may be disposed at an edge EDG of the chamfered surface CHM including the first substrate SUB1. The first side connection line SCL1 and the first overcoat OC1 may extend to a part of the upper surface and a part of the rear surface of the first substrate SUB1, and the first overcoat OC1 may cover the entire first side connection line SCL1. The second side connection line SCL2 and the second overcoat OC2 may be disposed at an edge EDG of the chamfered surface CHM including the second substrate SUB2. The second side connection line SCL2 and the second overcoat OC2 may extend to a part of the upper surface and a part of the rear surface of the second substrate SUB2, and the second overcoat OC2 may cover the entire second side connection line SCL2. The light-emitting element ED and the barrier rib BNK located between the light-emitting elements ED may be disposed on each of the first substrate SUB1 and the second substrate SUB2, and the barrier rib BNK may be implemented by a black anisotropic conductive film BACF. The first cover layer COV1 may be disposed to cover the first substrate SUB1 and the light-emitting element ED mounted thereon to protect the first substrate SUB1 and the light-emitting element ED from external influences. The second cover layer COV2 can be arranged to cover the second substrate SUB2 and the light-emitting element ED mounted thereon to protect the second substrate SUB2 and the light-emitting element ED from external influences. The first cover layer COV1 and the second cover layer COV2 can reduce the visibility of the coupling region SM (e.g., seam) formed by the gap G formed between the first substrate SUB1 (or the first display device 10-1) and the second substrate SUB2 (or the second display device 10-2), and can improve the color deviation between the first display device 10-1 and the second display device 10-2. The first cover layer COV1 can protrude beyond the edge EDG of the first substrate SUB1, the second cover layer COV2 can protrude beyond the edge EDG of the second substrate SUB2, and the gap G between the first substrate SUB1 and the second substrate SUB2 can be greater than the gap between the first cover layer COV1 and the second cover layer COV2. In one embodiment, the first cover layer OC1 and the second cover layer OC2 can face each other in the gap G between the first substrate SUB1 and the second substrate SUB2. The first cover layer OC1 and the second cover layer OC2 presented in black can absorb the light incident on the gap G. In addition, the first cover layer OC1 and the second cover layer OC2 can block the light reflection from the gap G. The first and second side connection lines SCL1 and SCL2. The first cover layer OC1 and the second cover layer OC2 can prevent or substantially prevent foreign matter and / or moisture from entering each space between the first substrate SUB1 and the first cover layer COV1 and between the second substrate SUB2 and the second cover layer COV2. FIG. 24 is a block diagram illustrating an example of the tiled display device of FIG. 4. In FIG. 24, for ease of explanation, the first display device 10-1 and the host system HOST are shown. Referring to FIGS. 4 and 24, the tiled display device TD according to one embodiment may include a host system HOST, a broadcast tuning unit (e.g., broadcast tuner) 210, a signal processing unit (e.g., signal processor) 220, a display unit (e.g., display or display device) 230, a speaker 240, a user input unit (e.g., user input device or user input) 250, a storage unit (e.g., storage device or memory) 260, a network communication unit (e.g., network communication device or network communicator) 270, a user interface (UI) generation unit (e.g., UI generator) 280, and a control unit (e.g., controller) 290. The host system HOST can be implemented as a television system, a home theater system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer, a mobile phone system, a tablet computer, etc. The instructions of the user can be input into the host system HOST in various suitable formats. For example: The instructions input by the user's touch can be input into the host system HOST. Also for example: The instructions of the user can be input into the host system HOST by keyboard input or button input of a remote controller. The host system HOST can receive original video data corresponding to the original image from the outside, and the host system HOST can divide the original video data by the number of display devices. For example, in response to the first display device 10-1, the second display device 10-2, the third display device 10-3, and the fourth display device 10-4 being included in the tiled display device, the host system HOST can divide the original video data into first video data corresponding to the first image, second video data corresponding to the second image, third video data corresponding to the third image, and fourth video data corresponding to the fourth image. The host system HOST can transmit the first video data to the first display device 10-1, transmit the second video data to the second display device 10-2, transmit the third video data to the third display device 10-3, and transmit the third video data to the third display device 10-1. The fourth video data to the fourth display device 10-4. The first display device 10-1 can display the first image according to the first video data, the second display device 10-2 can display the second image according to the second video data, the third display device 10-3 can display the third image, the fourth display device 10-4 can display the fourth image according to the third video data, and the fourth display device 10-4 can display the fourth image according to the fourth video data. Therefore, the user can view the original image in which the first to fourth images displayed on the first to fourth display devices 10-1, 10-2, 10-3, and 10-4 are combined with each other. The first display device 10-1 can include a broadcast tuning unit 210, a signal processing unit 220, a display unit 230, a speaker 240, a user input unit 250, a storage unit 260, a network communication unit 270, a UI generation unit 280, and a control unit 290. The broadcast tuning unit 210 can tune the channel frequency (for example: a predetermined channel frequency) under the control of the control unit 290, and can receive the broadcast signal of the corresponding channel through the antenna. The broadcast tuning unit 210 can include a channel detection module (for example: a channel detector) and an RF demodulation module (for example: an RF demodulator). The broadcast signal demodulated by the broadcast tuning unit 210 is processed by the signal processing unit 220 and output to the display unit 230 and the speaker 240. Here, the signal processing unit 220 may include a demultiplexer 221, a video decoder 222, a video processing unit (such as a video processor) 223, an audio decoder 224, and an additional data processing unit (such as an additional data processor) 225. The demultiplexer 221 divides the demodulated broadcast signal into a video signal, an audio signal, and additional data. The divided video signal, audio signal, and additional data are respectively restored by the video decoder 222, the audio decoder 224, and the additional data processing unit 225. For example, the video decoder 222, the audio decoder 224, and the additional data processing unit 225 may be restored to a decoded format corresponding to the encoding format when the broadcast signal is sent. The decoded video signal is converted by the video processing unit 223 to be suitable for the vertical frequency, resolution, screen ratio, etc. corresponding to the output standard of the display unit 230, and the decoded audio signal is output to the speaker 240. The display unit 230 can display images. The user input unit 250 can receive signals sent from the host system HOST. The user input unit 250 may be provided to receive data for selecting instructions related to the user's communication with another display device and input data for input, as well as data related to channel selection sent by the host system HOST, and to select and operate the user interface (UI) menu. The storage unit 260 stores various software programs, including: OS programs, recorded broadcast programs, moving pictures, photos, and other data, and may be formed by a storage medium such as a hard disk or a non-volatile memory. The network communication unit 270 is used for short-distance communication with the host system HOST and another display device, can be implemented by a communication module including an antenna pattern, and can implement mobile communication, data communication, Bluetooth, RF, Ethernet, etc. The network communication unit 270 can send and receive wireless signals (GSM, CDMA, CDMA2000, EV-DO, WCDMA, HSDPA, HSUPA, LTE, LTE-A, 5G, etc.) with at least one of a base station, an external terminal, and a server in a mobile communication network constructed according to a technical standard or a communication method (such as: Global System for Mobile Communications) for mobile communication through the antenna pattern described in more detail below. The network communication unit 270 can send and receive wireless signals in the communication network according to the antenna pattern described in more detail below based on wireless Internet technology. The wireless Internet technology can include, for example, Wireless Local Area Network (WLAN), Wireless Fidelity (Wi-Fi), Wi-Fi Direct, Digital Living Network Alliance (DLNA), Wireless Broadband (WiBro), Worldwide Interoperability for Microwave Access (WiMAX), High-Speed Downlink Packet Access (HSDPA), High-Speed Uplink Packet Access (HSUPA), Long-Term Evolution (LTE), Long-Term Evolution-Advanced (LTE-A), etc. The antenna pattern is used to send and receive data according to at least one wireless Internet technology within the scope of Internet technologies not listed above. The UI generation unit 280 generates a UI menu for communicating with the host system HOST and another display device, and can be implemented by algorithm code and OSDIC. The UI menu for communicating with the host system HOST and other display devices can be a menu for specifying the target digital TV for communication and selecting desired functions. The control unit 290 is responsible for the overall control of the first display device 10-1, and is responsible for the communication control between the host system HOST and the second, third, and fourth display devices 10-2, 10-3, and 10-4, stores the corresponding algorithm code for control, and the control unit 290 can be implemented by a microcontroller unit (MCU) that executes the stored algorithm code. The control unit 290 controls the sending of corresponding control instructions and data to the host system HOST and the second, third, and fourth display devices 10-2, 10-3, and 10-4 through the network communication unit 270 according to the input and selection instructions of the user input unit 250. When control instructions (e.g., predetermined control instructions) and data are input from the host system HOST and the second, third, and fourth display devices 10-2, 10-3, and 10-4, operations are performed according to the corresponding control instructions. Since the block diagrams of each of the second, third, and fourth display devices 10-2, 10-3, and 10-4 are the same as or substantially the same as the block diagram of the first display device 10-1 described above with reference to Figure 24, the redundant description thereof will not be repeated. Although some embodiments have been described, those of ordinary skill in the art to which this invention pertains will readily understand that various modifications can be made to the embodiments without departing from the spirit and scope of this disclosure. It should be understood that the description of features or aspects in each embodiment is generally considered applicable to other similar features or aspects in other embodiments, unless otherwise stated. Therefore, it will be apparent to those of ordinary skill in the art to which this invention pertains that the features, characteristics, and / or elements described in connection with a particular embodiment can be used alone or in combination with the features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically stated. Accordingly, it should be understood that the foregoing is an illustration of various exemplary embodiments and should not be construed as limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined by the appended claims and their equivalents. 10: Display device 10-1~10-4: Display device 210: Broadcast tuning unit 220: Signal processing unit 221: Demultiplexer 222: Video decoder 223: Video processing unit 224: Audio decoder 225: Additional data processing unit 230: Display unit 240: Speaker 250: User input unit 260: Storage unit 270: Network communication unit 280: UI generation unit 290: Control unit ACE: Anode connection electrode ACF: Conductive adhesive member ACL: Anode connection line ACTL: Active layer AND: Anode AND1~AND2: First to second anodes ANDL: Anode layer BACF: Black anisotropic conductive film BF: Buffer layer BML: Light shielding layer BNK: Retaining wall BS: Back surface BTE: Back surface electrode BTE1~BTE2: First to second back surface electrodes C1~C3: First to third capacitors CCA: Pixel circuit area CCE: Connection electrode CE1~CE2: First to second capacitor electrodes CH: Channel CHM: Chamfered surface CGC: Current generation circuit COV1~COV2: First to second cover layers CROW1~CROW9: First to ninth circuit rows CTD: Cathode CTD1~CTD2: First to second cathodes CTE1~CTE2: First to second contact electrodes CTL: Intermediate layer DA: Display area DE: Drain electrode DMA: Demultiplexing area DPL: Display element layer DL1~DL3: First to third data lines DR1~DR3: First to third directions EA1~EA3: First to third exposed areas ED: Light-emitting element ED1~ED3: First to third light-emitting elements EDG: Edge ESA: Electrostatic discharge area ESD: Electrostatic discharge circuit ETL1~ETL2: First to second pixel electrodes FCP: Conductive particles FL: First layer FOA: Fan-out area FOL: Fan-out line FPCB: Flexible film G: Gap GCL: Control scan line GE: Gate electrode GI1~GI2: First to second gate insulating layers GIL: Initialization scan line GRV: Groove GTL1~GTL2: First to second gate layers HOST: Host system HPP1~HPP2: First to second horizontal pixel pitches HVDL: Horizontal power line IEA: Interlayer insulation layer exposed area ILD: Interlayer insulation layer LDL: Lead MQW: Active layer N1~N9: First to ninth nodes NDA: Non-display area NSEM: n-type semiconductor OC: Cover layer PAD: Pad portion PAD1~PAD5: First to fifth pad electrodes PAEL: PAM emission control line PAS1~PAS3: First to third protective layers PC: Pixel circuit PC1~PC3: First to third pixel circuits PCL: Pixel circuit layerPROW1~PROW9: The first to ninth pixel rows PSEM: p-type semiconductor PWEL: PWM emission control line PWMC: Pulse width modulation circuit PX: Pixel R1~R2: The first to second line resistors RDL: PAM data line SE: Source electrode SCL: Side connection line SDL1~SDL4: The first to fourth source metal layers SIM: Silicon mold SL: Second layer SM: Coupling region SP1~SP3: The first to third pixels SS: Side surface SSUB: Substrate base board SUB: Substrate SUB1~SUB2: The first to second substrates SWPL: Scan signal line T1~T19: The first to nineteenth transistors TD: Mosaic display device TFT: Transistor TL: Transistor layer TSTL: Test signal line UP: Unit pixel US: Upper surface V_PAM: PAM data voltage V_PWM: PWM data voltage VDD1~VDD2: The first to second power supplies VDL1: First power supply line VGHL: Gate-off voltage line VGLL: Gate-on voltage VIA1~VIA5: The first to fifth via layers VIL: Initialization voltage line Vint: Initialization power supply VPP1~VPP2: The first to second vertical pixel pitches VSL: Third power supply line VSS: Third power supply VVDL: Vertical power supply line Through the following detailed description of illustrative and non-limiting embodiments with reference to the drawings, the above and other aspects and features of the present disclosure will be more clearly understood, wherein: FIG. 1 shows a schematic diagram of a display device according to an embodiment of the present invention; FIG. 2 shows a schematic diagram of an example of a pixel included in the display device of FIG. 1; FIG. 3 shows schematic diagrams of other examples of pixels included in the display device of FIG. 1; FIG. 4 shows a schematic diagram of a tiled display device according to an embodiment of the present invention; FIG. 5 shows a plan view of an example of the display device of FIG. 1; FIGS. 6 to 7 show schematic diagrams of examples of the connection relationship between a pixel circuit and a light-emitting element included in the display device of FIG. 5; FIG. 8 shows a schematic diagram of an example of a pixel circuit region, a demultiplexing region (demux area), a fan-out region, an electrostatic discharge region, and a non-display region included in the display device of FIG. 5; FIG. 9 shows an enlarged view of an example of a part of the electrostatic discharge region and the fan-out region of FIG. 8; FIG. 10 shows a perspective view of a display device according to an embodiment of the present invention; FIG. 11 shows a schematic diagram of an example of a part of a second surface of the display device of FIG. 10; FIG. 12 shows a cross-sectional view of an example of the display device of FIG. 10; FIG. 13A shows a perspective view of an example of a side surface of a connection line and a via layer of the display device of FIG. 12; FIG. 13B shows a perspective view of an example of the display device of FIG. 10; FIG. 14 shows a cross-sectional view of an example of the display device of FIG. 10; FIG. 15 shows a cross-sectional view of an example of the display device of FIG. 10; FIG. 16 shows a cross-sectional view of an example of the display device of FIG. 10; FIG. 17 shows a cross-sectional view of an example of the display device of FIG. 10; FIG. 18 shows a schematic diagram of an example of a method of forming a cover layer in the display device of FIG. 10; FIG. 19 shows a schematic diagram of an example of a cover layer formed in the display device of FIG. 10; FIG. 20 shows a schematic diagram of an example of a method of forming a cover layer in the display device of FIG. 10; FIG. 21 shows a circuit diagram of an example of a pixel included in the display device of FIG. 5; FIG. 22 shows a layout diagram of an example of a pixel circuit included in the pixel of FIG. 21; FIG. 23 shows a cross-sectional view of an example of the connection between display devices included in the tiled display device of FIG. 4; and FIG. 24 shows a block diagram of an example of the tiled display device of FIG. 4. ACE: Anode connection electrode ACF: Conductive adhesive member ACL: Anode connection line ACTL: Active layer AND: Anode AND1~AND2: First to second anodes ANDL: Anode layer BF: Buffer layer BTE: Back surface electrode BTE1~BTE2: First to second back surface electrodes C1: First capacitor CCE: Connection electrode CE1~CE2: First to second capacitor electrodes CH: Channel CTD: Cathode CTD1~CTD2: First to second cathodes CTE1~CTE2: First to second contact electrodes DA: Display area DE: Drain electrode DPL: Display element layer DR1~DR3: First to third directions EA1~EA3: First to third exposed areas EOL: Fan-out line FPCB: Flexible film GE: Gate electrode GI1~GI2: First to second gate insulating layers GTL1~GTL2: First to second gate layers IEA: Interlayer insulation layer exposed area ILD: Interlayer insulation layer LDL: Lead MQW: Active layer NDA: Non-display area NSEM: n-type semiconductor OC: Cover layer PAD: Pad portion PAD1~PAD5: First to fifth pad electrodes PAS1~PAS3: First to third protective layers PCL: Pixel circuit layer PSEM: p-type semiconductor SE: Source electrode SCL: Side connection line SDL1~SDL4: First to fourth source metal layers SSUB: Substrate substrate TFT: Transistor TL: Transistor layer VIA1~VIA5: First to fifth via layers

Claims

1. A display device comprising: A substrate includes a display area and a non-display area surrounding the display area; a transistor layer located on a first surface of the substrate, the transistor layer including a transistor of a pixel circuit located in the display area; a bonding pad located in the non-display area and electrically connected to the pixel circuit; a first via layer located on the transistor layer and spaced apart from the bonding pad; a second via layer located on the first via layer and having a step difference from the first via layer to expose a portion of an upper surface of the first via layer; a third via layer located on the second via layer and having a step difference from the second via layer to expose a portion of an upper surface of the second via layer; a display element layer located on the third via layer in the display area, the display element layer including a light-emitting element electrically connected to the transistor; and a lead located on a second surface of the substrate. A side connection line is located on the first surface of the substrate, the second surface of the substrate, and one side surface between the first surface and the second surface of the substrate, the side connection line electrically connecting the pad portion and the lead to each other; and a cover layer covers the entire side connection line, and the cover layer overlaps with the upper surface of the first via layer exposed from the second via layer.

2. The display device according to claim 1, wherein one end of the cover layer faces one end of the second through-hole layer.

3. The display device according to claim 1, wherein the cover layer overlaps at least a portion of the upper surface of the exposed second through-hole layer, and wherein one end of the cover layer faces one end of the third through-hole layer.

4. The display device according to claim 1, wherein the cover layer includes an insulating layer that is in direct contact with the side connection line and contains a black pigment.

5. The display device according to claim 1, wherein the transistor layer further includes an interlayer insulating layer located on the transistor, the interlayer insulating layer being in contact with the first via layer, and wherein the interlayer insulating layer includes a portion exposed to the first via layer and the solder pad portion.

6. The display device according to claim 5, wherein the display element layer further comprises: A pixel electrode is located on the third via layer, and the pixel electrode is electrically connected to the light-emitting element; A protective layer is located on the pixel electrode and the solder pad, and the protective layer exposes a portion of an upper surface of the pixel electrode and a portion of an upper surface of the solder pad, and wherein the protective layer contacts the exposed portions of the interlayer insulating layer, the first via layer, the second via layer and the third via layer.

7. The display device according to claim 6, wherein the side connection line is located on the protective layer and the side connection line overlaps with the exposed portion of the interlayer insulation layer.

8. The display device according to claim 6, wherein one end of the cover layer faces one end of the second through-hole layer, and the protective layer is inserted between the end of the cover layer and the end of the second through-hole layer.

9. The display device according to claim 6, wherein the cover layer overlaps at least a portion of the upper surface of the exposed second through-hole layer, and wherein one end of the cover layer faces one end of the third through-hole layer, and the protective layer is inserted between the end of the cover layer and the end of the third through-hole layer.

10. The display device according to claim 6, further comprising: A first source metal layer is located on the transistor layer and is covered by the first via layer of the display area; a second source metal layer is located on the first via layer of the display area and is covered by the second via layer; and a third source metal layer is located on the second via layer of the display area and is covered by the third via layer.

11. The display device according to claim 10, wherein the solder pad portion includes: A first pad electrode is formed together with the first source metal layer; a second pad electrode is formed together with the second source metal layer and the second pad electrode is directly located on the first pad electrode; a third pad electrode is formed together with the third source metal layer and the third pad electrode is directly located on the second pad electrode; and a fourth pad electrode is formed together with the pixel electrode and the fourth pad electrode is directly located on the third pad electrode, wherein a plurality of exposed portions of the first pad electrode to the fourth pad electrode contact the protective layer.

12. The display device according to claim 6, wherein the display element layer further comprises: A black anisotropic conductive film is located on a portion of the cover layer and the protective layer of the display area. The black anisotropic conductive film includes a black pigment and a plurality of conductive microparticles, wherein the light-emitting element and the pixel electrode are electrically connected to each other through the conductive microparticles.

13. The display device according to claim 1, further comprising: A second surface electrode is located on the second surface of the substrate; And a flexible film electrically connected to the second surface electrode via a conductive adhesive, wherein the side connection line is electrically connected to the second surface electrode via the lead.

14. The display device according to claim 1, wherein the light-emitting element comprises: A flip-chip micro light-emitting diode device.

15. A splicing display device, comprising: Multiple display devices; The system also includes a coupling region located between the plurality of display devices, connecting the plurality of display devices to each other, wherein at least one of the plurality of display devices comprises: a substrate including a display area and a non-display area surrounding the display area; a transistor layer located on a first surface of the substrate, the transistor layer including a transistor of a pixel circuit located in the display area; a solder pad located in the non-display area, the solder pad being electrically connected to the pixel circuit; a first via layer located on the transistor layer, the first via layer being spaced apart from the solder pad; a second via layer located on the first via layer, the second via layer having a step difference from the first via layer to expose a portion of an upper surface of the first via layer; and a third via layer located on the second via layer, the third via layer having a step difference from the second via layer to expose a portion of an upper surface of the second via layer. A display element layer located on the third via layer of the display area, the display element layer including a light-emitting element electrically connected to a transistor; a lead located on a second surface of the substrate; a side connection line located on the first surface of the substrate, the second surface of the substrate, and a side surface between the first surface and the second surface of the substrate, the side connection line electrically connecting the pad portion and the lead to each other; and a cover layer covering the entire side connection line, and the cover layer overlapping the upper surface of the first via layer exposed from the second via layer, the cover layer including a black pigment.

16. The splicing display device according to claim 15, wherein one end of the cover layer faces one end of the second through-hole layer.

17. The splicing display device according to claim 15, wherein the cover layer overlaps at least a portion of the upper surface of the exposed second through-hole layer, and wherein one end of the cover layer faces one end of the third through-hole layer.

18. The splicing display device according to claim 15, wherein the display element layer further comprises: A pixel electrode is located on the third via layer, and the pixel electrode is electrically connected to the light-emitting element; A protective layer is located on the pixel electrode and the solder pad, and the protective layer exposes a portion of an upper surface of the pixel electrode and a portion of an upper surface of the solder pad, and wherein the protective layer contacts the exposed portions of the first via layer, the second via layer and the third via layer.

19. The splicing display device according to claim 18, wherein one end of the cover layer faces one end of the second through-hole layer, and the protective layer is inserted between the end of the cover layer and the end of the second through-hole layer.

20. The splicing display device according to claim 15, wherein the light-emitting element comprises: A flip-chip micro light-emitting diode device.

Images