Stiffener ring for packages with microcable / optical connectors, electronic data communication device, and method of assembling an electronic device

Abstract

A semiconductor package includes a package substrate, a semiconductor wafer disposed on the package substrate, and a reinforcement disposed on the package substrate. The reinforcement includes: an inner portion configured to surround the semiconductor wafer, the inner portion defining a space on the package substrate outside the inner portion and located between the inner portion and an outer edge of the package substrate; and a plurality of leg portions extending outward from the inner portion toward one or more of the outer edge of the package substrate and a corner of the package substrate.

Description

Encapsulation reinforcement ring with miniature cable / fiber optic connector Cross-reference to related applications: The scope of this application claims priority to U.S. Provisional Application No. 63 / 292,710, filed December 22, 2021. The entire disclosure of the above applications is incorporated herein by reference. This article relates to a reinforcement for semiconductor packages. The prior art description provided herein is intended to present the overall context of this specification. The work of the inventors currently named is neither expressly nor impliedly acknowledged as prior art to this specification, with regard to the extent described in the background section and to aspects that may not otherwise be described as prior art at the time of filing. Semiconductor packages (e.g., packages such as individual semiconductor wafers or dies, integrated circuit (IC) packages, etc.) typically comprise one or more circuits formed on a substrate. Various signals are transmitted between components on and / or through the substrate (e.g., through vias formed within the substrate). One or more semiconductor packages may be disposed on a printed circuit board (PCB) or other suitable substrate. In some embodiments, the semiconductor package is coupled to the PCB using a ball grid array (BGA). A semiconductor package includes a package substrate, a semiconductor wafer disposed on the package substrate, and a reinforcement disposed on the package substrate. The reinforcement includes: an inner portion configured to surround the semiconductor wafer, the inner portion defining a space on the package substrate outside the inner portion and located between the inner portion and an outer edge of the package substrate; and a plurality of leg portions extending outward from the inner portion toward one or more of the outer edge of the package substrate and a corner of the package substrate. Among other features, the packaging substrate is a laminated substrate, and the reinforcement is made of a material with greater rigidity than the laminated substrate. The reinforcement is made of metal. Multiple support portions include diagonal support portions extending from the corners of the inner portion toward the corners of the packaging substrate. Multiple support portions include lateral support portions extending from the sides of the inner portion toward the outer edge of the packaging substrate. The inner portion is rectangular. Among other features, the semiconductor package further includes circuit elements disposed on a package substrate within a space defined between an internal portion and the outer edge of the package substrate. The circuit elements are either cable connectors or silicon photonic packages. The semiconductor package is a serializer / deserializer (SerDes) device. Among other features, the electronic data communication device includes a printed circuit board and a semiconductor package mounted on the printed circuit board. The semiconductor package includes an array of electrical contact terminals and is surface-mounted to the printed circuit board to establish a plurality of electrical contacts via the array of electrical contact terminals. The electronic data communication device further includes a second semiconductor package, the second semiconductor package including a second packaging substrate, a second semiconductor wafer disposed on the second packaging substrate, and a second reinforcement disposed on the second packaging substrate. The second reinforcement includes: a second inner portion configured to surround the second semiconductor wafer, the second inner portion defining an outer portion on the second packaging substrate and located in a second space between the second inner portion and an outer edge of the second packaging substrate; and a second plurality of leg portions extending outward from the second inner portion toward one or more of the outer edge of the second packaging substrate and a corner of the second packaging substrate. Among other features, the electronic data communication device further includes: a first cable connector disposed on a package substrate in a space defined between an inner portion and an outer edge of the package substrate; a second cable connector disposed on a second package substrate in a space defined between a second inner portion and an outer edge of the second package substrate; and a cable coupling the first cable connector to the second cable connector. A method of assembling an electronic device includes: providing a package substrate; and attaching a reinforcement to the package substrate, the reinforcement including: an inner portion configured to surround a semiconductor wafer disposed on the package substrate, the inner portion defining a space on the package substrate outside the inner portion and located between the inner portion and an outer edge of the package substrate; and a plurality of leg portions extending outward from the inner portion toward one or more of the outer edge of the package substrate and a corner of the package substrate. Among other features, the method further includes attaching a semiconductor wafer to a package substrate within an internal portion. The method also includes attaching circuit elements to the package substrate within a space defined between the internal portion and the outer edge of the package substrate. Attaching the circuit elements includes attaching one of a cable connector and a silicon photonic package to the package substrate within the space defined between the internal portion and the outer edge of the package substrate. The method further includes attaching electronic equipment to a printed circuit board. Attaching electronic equipment to a printed circuit board includes attaching electronic equipment to an array of electrical contact terminals. The method further includes attaching a reinforcing member to the package substrate using epoxy resin. Other applications of this specification will become apparent from the specific embodiments, patent scope, and drawings. The specific embodiments and examples are for illustrative purposes only and are not intended to limit the scope of the invention. Semiconductor packages may include caps or reinforcements (e.g., reinforcing rings) disposed on a package substrate and surrounding one or more semiconductor wafers. The reinforcements are configured to maintain the flatness of the package substrate and the semiconductor package. For example, the reinforcements prevent bending or warping. The reinforcements may be made of stainless steel, copper (e.g., nickel-plated copper), or other suitable materials (e.g., other metals) that have greater rigidity and warp resistance than the material of the package substrate (e.g., organic or other laminated substrates). Therefore, the footprint of the package substrate may be larger than the footprint of the semiconductor wafer to accommodate the reinforcements on the package substrate. For example, the width of one peripheral side of the reinforcement (i.e., the distance from the inner edge to the outer edge) may be 10% or more of the total width of the package substrate. In some embodiments, it may be advantageous to arrange additional components (e.g., circuit elements) on the package substrate (e.g., rather than on a PCB or in a different semiconductor package on the PCB). For example, a semiconductor wafer may communicate with another component (e.g., a cable connector) arranged on the PCB. Thus, signals are transmitted from the wafer to other components via the package substrate, the ball grid array (BGA) coupling the package substrate to the PCB, and through the PCB. In other embodiments, the package substrate is coupled to the PCB using other types of connections (e.g., other types of electrical contact terminal arrays), including (but not limited to) other contact grid arrays (such as land grid arrays (LGAs), pin grid arrays (PGAs), etc.). When contact grid arrays such as BGAs, LGAs, and PGAs are used to mount semiconductor wafers to the package substrate and the package substrate to the PCB, warpage may make it difficult or even impossible to maintain adequate electrical contact between all contacts in the contact grid array. The negative effects of warpage increase as the pitch decreases. As an example, the transmission path from the semiconductor wafer through the BGA to other components on the PCB has associated signal loss. As signal transmission rates increase in certain applications (e.g., 200G or larger serializer / deserializer (SerDes) devices), signal integrity requirements also increase. Therefore, the signal loss associated with the transmission from the semiconductor wafer via the BGA to the associated cable connectors arranged on the PCB may not meet signal integrity requirements. In other words, the signal loss may exceed the maximum signal loss for 200G SerDes applications. Conversely, placing the cable connector on the same substrate as the semiconductor wafer reduces the transmission path length and significantly reduces losses associated with signal transmission to the cable connector. However, to accommodate such a cable connector, the footprint of the package substrate needs to be significantly increased. Furthermore, the placement of the cable connector is constrained by the location of the reinforcement. Typically, the reinforcement is placed at the outermost periphery of the package substrate to maintain the flatness of the outermost edge of the semiconductor package. Therefore, in a conventional arrangement, accommodating the cable connector arrangement between the reinforcement and the semiconductor wafer requires increasing the footprint of the package substrate, which increases the likelihood of warping. Conversely, extending the periphery of the package substrate beyond the reinforcement (i.e., accommodating additional components in the area of ​​the package substrate outside the reinforcement) increases the likelihood of warping at the outermost edge. Therefore, the semiconductor package and reinforcing element according to the invention are configured to increase the available space on the package substrate for elements such as cable connectors, while maintaining flatness and minimizing the possibility of warping. For example, in one embodiment, the reinforcing element includes: an inner portion or ring disposed on the package substrate surrounding a semiconductor wafer or die (e.g., directly adjacent to the semiconductor wafer or die or within 0 mm to 6 mm of the semiconductor wafer or die); and one or more leg portions extending radially outward from the inner portion. For example, the leg portions may extend diagonally outward from a corner of the inner portion toward a corresponding corner of the package substrate. Although described herein as a "ring," the inner portion may have a generally rectangular, square, or other shape suitable for surrounding one or more semiconductor wafers disposed on the package substrate. In this way, the reinforcement according to the invention maintains the flatness of the packaging substrate and prevents it from warping, while also providing space for components to be arranged on the packaging substrate outside the inner portion (e.g., between the inner portion and the outer edge of the packaging substrate). Figure 1 shows a top view (from top to bottom) of a semiconductor package 100 arranged on a PCB 104 according to the present invention. One or more additional semiconductor packages (108, 112, etc.) may be arranged on the PCB 104. Other semiconductor packages 108, 112 may have the same or different configurations relative to semiconductor package 100. For example, other semiconductor packages 108, 112 may include, but are not limited to: serializer / deserializer SerDes devices, copper Cu wire and optical PHY (Optical Physical Layer) devices, Ethernet switch devices, automotive PHY (Automotive Physical Layer) devices, memory devices, network processors and other processors, etc. Semiconductor package 100 includes a semiconductor die or wafer 116 arranged on a substrate such as package substrate 120. By way of example only, semiconductor wafer 116 includes a 20mm × 20mm die, and package substrate 120 is 55mm × 55mm. Various other suitable sizes are contemplated. A reinforcing member 124 is disposed on the packaging substrate 120. In some embodiments, the reinforcing member 124 is attached to the packaging substrate 120 using an epoxy resin (such as EA6700, SE4450, Sylgard 577, etc.) and cured at a high temperature (e.g., 150 degrees Celsius or higher for up to 3 hours). The reinforcing member 124 includes an inner portion 128 (e.g., a ring) and one or more foot portions 132. The inner portion 128 surrounds the semiconductor wafer 116. Although shown as generally rectangular or square, the inner portion 128 may have other suitable shapes. In one embodiment, the inner portion 128 is directly adjacent to the semiconductor wafer 116 or within 0 mm to 6 mm of the semiconductor wafer 116. The reinforcing member 124 may be made of stainless steel, copper (e.g., nickel-plated copper), or other suitable reinforcing materials having greater stiffness and warp resistance than the material of the packaging substrate 120. For example, the packaging substrate 120 is an organic or other type of laminated substrate. In one embodiment, the width W of a peripheral side of the reinforcement 124 (i.e., the distance from the inner edge 134-1 to the outer edge 134-2) can be 10% or greater of the total width of the package substrate 120. For example, the width W can be 2.0 mm to 6.0 mm. The width W can be the same or vary for different portions of the reinforcement 124 (e.g., the foot portion 132 can be wider or narrower than the side of the inner portion 128). The thickness (e.g., height) of the reinforcement 124 can be 0.5 mm to 4.0 mm. The thickness of different portions of the reinforcement 124 can vary (e.g., the foot portion 132 can be thicker or thinner than the side of the inner portion 128). As shown, the foot portion 132 extends radially outward from the inner portion 128. For example, the foot portion 132 extends diagonally outward from corner 136 of the inner portion 128 toward a corresponding corner 140 of the package substrate. Although four foot portions 132 are shown, in other embodiments, the reinforcement 124 may include fewer or more foot portions 132 in different configurations. Additional embodiment configurations are described in more detail below. Although the foot portions 132 are shown as generally rectangular (e.g., having square ends), in other embodiments, the foot portions 132 may have other shapes (e.g., tapered or rounded ends, curved or "S"-shaped, piecewise linear shapes with one or more angled bends, etc.). The foot portions 132 may each have the same dimensions (e.g., width and length) as shown, or they may have different dimensions. According to this disclosure, the reinforcing member 124 is configured to increase the space on the package substrate 120 for placing additional components outside the inner portion 128 (i.e., on the side of the inner portion 128 opposite to the semiconductor wafer 116), while maintaining flatness and minimizing the possibility of warping of the package substrate 120. For example, the occupied area of ​​the package substrate 120 is increased relative to the semiconductor wafer 116 such that the periphery or outer edge 144 of the package substrate 120 extends beyond the inner portion 128 of the reinforcing member 124, but the structural rigidity provided by the foot portion 132 is maintained. Therefore, space for additional components is defined on the package substrate 120 in the outer region 148 of the package substrate 120 located outside the inner portion 128 (i.e., between the inner portion 128 and the outer edge 144, and between adjacent foot portions 132). The support portion 132 extending to the outer edge 144 provides additional rigidity and structural support to the package substrate 120 to maintain flatness and prevent warping. In this way, the inner portion 128 is displaced inward toward the semiconductor wafer 116 to provide space for additional components without compromising the flatness of the package substrate 120. Furthermore, the inward position from the inner portion 128 toward the outer edge 144 provides access to the outer edge 144 and to components disposed on the package substrate 120 outside the inner portion 128. As one embodiment, the cable connector 152 (e.g., a biaxial microcable connector) can be surface-mounted or edge-mounted on the package substrate, as described in more detail below, close to or overlapping the outer edge 144. Because the cable connector 152 is located outside the inner portion 128 (i.e., closer to the outer edge 144 than the inner portion 128), the cable connector 152 is easily accessible for connecting or disconnecting cables. Other embodiment elements that may be located on the package substrate 120 outside the inner portion 128 include (but are not limited to) silicon photonic packages, co-packaged optics (CPOs), capacitors, or capacitor arrays, etc. Figure 2A shows a side view of semiconductor packages 200-1 and 200-2 (collectively referred to as semiconductor packages 200) arranged on PCB 204. Semiconductor package 200-1 shown in Figure 2A is a cross-sectional view taken along line AA shown in Figure 2B. Each semiconductor package 200 includes a semiconductor die or wafer 216 arranged on a package substrate 220. A reinforcement 224 according to the invention is arranged on the package substrate 220. The reinforcement 224 includes an internal portion 228 similar to that described above in Figure 1 and a foot portion 232. The foot portion 232 is not visible in the view shown in Figure 2A. In some embodiments, semiconductor wafer 216 transmits signals to other semiconductor wafers or components disposed on PCB 204 via package substrate 220 and BGA 236 coupling package substrate 220 to PCB 204. An embodiment of the transmission or signal path from semiconductor wafer 216 of semiconductor package 200-1 is shown at 240. In some embodiments, signals are transmitted to connectors disposed on PCB 204 via BGA (or other connection types, such as other contact grid arrays as described above), which has associated signal loss. As shown in Figures 2A and 2B, the reinforcement 224 according to the invention is configured to increase the available space on the package substrate 220 for components to be arranged outside the internal portion 228, while maintaining the flatness of the package substrate and minimizing the possibility of warping of the package substrate 220. For example, by reducing the possibility of warping, the connector 244 can be mounted on the package substrate 220 instead of on the PCB 204, thereby enabling improved connectivity between the semiconductor wafer and other components that can now be co-packaged (e.g., facilitating greater data transfer rates and / or bandwidth). In one embodiment, the semiconductor package 200-1 is a 200G or larger SerDes device, and the connector 244 is configured to transmit SerDes signals to and from the semiconductor package 200-1 (e.g., via a corresponding cable 248). For example, cable 248 couples together corresponding connectors 244 of semiconductor package 200 for transmitting signals between semiconductor package 200 and other components of PCB 204 and / or the outside of PCB 204. An embodiment of a signal path 252 (e.g., a signal trace) from semiconductor wafer 216 to connectors 244 arranged on substrate 220 is shown. Signal path 252 passes only through package substrate 220 (i.e., not through BGA 236, PCB 204, etc.), which typically has improved signal carrying characteristics compared to a PCB, but is also prone to warping for the same reason. Therefore, the length of signal path 252 is reduced (i.e., relative to the signal path from semiconductor wafer 216 to components arranged on PCB 204), and the loss associated with signal transmission from semiconductor wafer 216 and connectors 244 is reduced. Figures 3A, 3B, and 3C illustrate other embodiments of a semiconductor package 300 including a reinforcing member 304 according to the invention. In Figure 3A, the reinforcing member 304 includes a plurality of leg portions 316 and an inner portion 308 surrounding a semiconductor wafer 312. In this embodiment, the leg portions 316 include: diagonal leg portions 320 extending diagonally from the inner portion 308 to corresponding corners 324 of the package substrate 328; and lateral leg portions 332 extending laterally from the side of the inner portion 308 to the outer edge 336 of the package substrate 328. As shown, the lateral leg portions 332 extend from the corresponding center of each side of the inner portion 308. The lateral leg portions 332 extend in a direction perpendicular to a corresponding outer edge 336. The lateral leg portions 332 provide additional rigidity and prevent the package substrate 328 from warping (i.e., compared to embodiments with only diagonal leg portions 320). In addition, space is provided on the packaging substrate 328 between the inner portion 308 and the outer edge 336 to accommodate additional components such as connector 340. In the embodiment shown in FIG3B, the support portion 316 includes a diagonal support portion 320 and a rectangular foot 344 arranged at the respective ends of the diagonal support portion 320. The rectangular foot 344 is arranged in the respective corner 324 of the package substrate 328. In the embodiment shown in FIG3C, the support portion 316 includes only the lateral support portion 332 (i.e., the support portion 316 does not include the diagonal support portion 320 shown in FIG3B and FIG3C). The lateral support portion 332 may extend from the corner region of the inner portion 308 in a direction perpendicular to the respective outer edge 336 of the package substrate, as shown, and / or extend from the respective center of each side of the inner portion 308 as shown in FIG3A. Figure 4 illustrates the steps of an embodiment of method 400 for manufacturing or assembling an electronic device (e.g., an electronic data communication device) including a reinforcing member according to the invention. At 404, a package substrate is provided. For example, the package substrate is formed using one or more semiconductor materials (such as silicon). At 408, the reinforcing member according to the invention is attached to the package substrate. For example, as described above, the reinforcing member is attached to the package substrate using epoxy resin and cured. At 412, a semiconductor device or wafer is disposed on the package substrate within a periphery defined by the reinforcing member. The reinforcing member includes: an inner ring portion that surrounds the semiconductor wafer; and one or more leg portions that extend from the inner ring portion toward the outer edge of the package substrate. At 416, one or more additional elements (e.g., connectors) are optionally disposed on the package substrate outside the inner ring portion. At 420, the package substrate is attached to a PCB (e.g., via a contact grid array such as a BGA). For example, a contact grid array is formed on the PCB, and the package substrate is attached to the contact grid array. At 424, one or more additional semiconductor devices and the package substrate are optionally attached to the PCB. Figure 5 illustrates the manufacturing / assembly process of an embodiment of an electronic device including a reinforcement according to the invention. At 500, a package substrate 504 is shown. At 508, the reinforcement 512 according to the invention is attached to the package substrate 504. By way of example only, the reinforcement 512 is attached using epoxy resin, which is then cured as described above. Although the reinforcement 512 is described as being attached to the package substrate 504 before any other components, in other embodiments, the reinforcement 512 may be attached to the package substrate 504 after the other components. At 516, the semiconductor wafer 520 is attached to the package substrate 504 within the inner portion of the reinforcement 512. At 524, one or more additional components (e.g., a cable connector 528 as described above) are arranged on the package substrate 504 outside the inner portion of the reinforcement 512. At 532, a contact grid array such as a BGA 536 is formed on the PCB 540. At 544, the package substrate 504 is attached to the PCB 540 via the BGA 536. In other embodiments, the components of the semiconductor device may be assembled in a different order than that described above. For example, the package substrate 504 may be attached to the PCB 540 before attaching the semiconductor wafer 520 and / or the reinforcement 512. The foregoing description is illustrative in nature and is by no means intended to limit the invention, its application, or use. The extensive teachings of the invention can be implemented in various forms. Therefore, although the invention includes specific embodiments, its true scope should not be limited thereto, as other modifications will become apparent upon study of the drawings, specification, and claims. It should be understood that one or more steps within the method may be performed in different orders (or simultaneously) without altering the principles of the invention. Furthermore, although each embodiment is described above as having certain features, any one or more of those features described with respect to any embodiment of the invention may be implemented in and / or combined with features of any other embodiment, even if such combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and substitution of one or more embodiments for each other remains within the scope of the invention. Various terms are used to describe spatial and functional relationships between components (e.g., modules, circuit elements, semiconductor layers, etc.). Unless explicitly described as "direct," when describing a relationship between first and second components in the foregoing disclosure, the relationship can be a direct relationship in which no other intermediate components exist between the first and second components, or an indirect relationship in which one or more intermediate components (spatially or functionally) exist between the first and second components. As used herein, the phrases A, B, and C at least one should be interpreted as indicating logic using non-exclusive OR (A or B or C), and should not be interpreted as indicating "at least one of A, at least one of B, and at least one of C". In the diagrams, the direction of the arrows, as indicated by the arrows, typically represents the flow of information (such as data or instructions) of interest in the embodiment. For example, when components A and B exchange various information, but the information transmitted from component A to component B is relevant to the illustration, the arrow can point from component A to component B. This unidirectional arrow does not imply that no other information is transmitted from component B to component A. Furthermore, for information sent from component A to component B, component B can send a request for that information to component A or receive an acknowledgment of that information. 100: Semiconductor package; 104: PCB; 108, 112: Semiconductor package; 116: Semiconductor wafer; 120: Package substrate; 124: Reinforcement; 128: Internal portion; 132: Lead portion; 134-1: Inner edge; 134-2: Outer edge; 136, 140: Corner; 144: Outer edge; 148: Outer area; 152: Cable connector; 200, 200-1, 200-2: Semiconductor package; 204: PCB; 216: Wafer; 220: Package substrate; 224: Reinforcement; 228: Internal portion; 232: Lead portion; 236: BGA 244: Connector; 248: Cable; 252: Signal path; 300: Semiconductor package; 304: Reinforcement; 308: Internal portion; 312: Semiconductor wafer; 316: Lead portion; 320: Diagonal lead portion; 324: Corresponding corner portion; 328: Substrate; 332: Lateral lead portion; 336: Outer edge; 340: Connector; 344: Rectangular lead; 400: Method; 500, 504: Package substrate; 512: Reinforcement; 520: Semiconductor wafer; 528: Cable connector; 536: BGA; 540: PCB; W: Width Figure 1 is a top view (from top to bottom) of a semiconductor package including a reinforcing member according to the invention. Figure 2A is a side view of a semiconductor package arranged on a printed circuit board according to the present invention. Figure 2B is a plan view of one of the semiconductor packages in Figure 2A. Figures 3A, 3B, and 3C are plan views of reinforcements according to other embodiments of the present invention. Figure 4 shows the steps of an embodiment of a method for manufacturing or assembling a device including a reinforcing member according to the invention. Figure 5 shows the manufacturing process of an embodiment of a semiconductor device including a reinforcing member according to the present invention. In a diagram, symbols can be reused to identify similar and / or identical elements. 100: Semiconductor package 104:PCB 108, 112: Semiconductor packages 116: Semiconductor wafers 120: Packaging substrate 124: Reinforcing component 128: Internal Parts 132: Support Legs 134-1: Inner Edge 134-2: Outer edge 136,140: Corner 144: Outer edge 148: Outer Region 152: Cable Connector W: Width

Claims

1. A semiconductor package, comprising: One packaging substrate; A semiconductor wafer is disposed on the packaging substrate; And a reinforcing member disposed on the packaging substrate, the reinforcing member comprising: an inner portion configured to surround the semiconductor wafer, the inner portion being defined on the packaging substrate outside the inner portion and located in a space between the inner portion and an outer edge of the packaging substrate; and a plurality of leg portions extending outward from the inner portion toward (i) the outer edge of the packaging substrate and (ii) one or more corners of the packaging substrate. The plurality of support portions include lateral support portions extending from the side of the inner portion toward the outer edge of the package substrate.

2. The semiconductor package of claim 1, wherein the package substrate is a laminated substrate, and the reinforcement is made of a material with greater rigidity than the laminated substrate.

3. The semiconductor package as claimed in claim 2, wherein the reinforcement is made of metal.

4. The semiconductor package of claim 1, wherein the plurality of leg portions includes diagonal leg portions extending from a corner of the interior portion toward the corner of the package substrate.

5. The semiconductor package as claimed in claim 1, wherein the internal portion is rectangular.

6. The semiconductor package of claim 1, further comprising a circuit element disposed on the package substrate in the space defined between the inner portion and the outer edge of the package substrate.

7. The semiconductor package as claimed in claim 6, wherein the circuit element is one of a cable connector and a silicon photonic package.

8. A semiconductor package, comprising: One packaging substrate; A semiconductor wafer is disposed on the packaging substrate; and a reinforcing member disposed on the package substrate, the reinforcing member comprising: an inner portion configured to surround the semiconductor wafer, the inner portion defining an outer portion on the package substrate and located in a space between the inner portion and an outer edge of the package substrate; and a plurality of leg portions extending outward from the inner portion toward (i) the outer edge of the package substrate and (ii) one or more corners of the package substrate; wherein the semiconductor package is a serializer / deserializer (SerDes) device.

9. An electronic data communication device, comprising a printed circuit board and a semiconductor package as claimed in claim 1, the semiconductor package being mounted on the printed circuit board, the semiconductor package being a first semiconductor package.

10. The electronic data communication device of claim 9, wherein the first semiconductor package includes an array of electrical contact terminals and is surface-mounted to the printed circuit board to establish a plurality of electrical contacts via the array of electrical contact terminals.

11. The electronic data communication device as claimed in claim 9, further comprising a second semiconductor package, the second semiconductor package comprising: A second packaging substrate; A second semiconductor chip is disposed on the second packaging substrate; And a second reinforcement member disposed on the second packaging substrate, the second reinforcement member including: a second inner portion configured to surround the second semiconductor wafer, the second inner portion being defined on the second packaging substrate outside the second inner portion and located in a second space between the second inner portion and an outer edge of the second packaging substrate; And a second plurality of support portions extending outward from the second inner portion toward one or more of (i) the outer edge of the second packaging substrate and (ii) the corner of the second packaging substrate.

12. The electronic data communication device as claimed in claim 11, further comprising: A first cable connector is disposed on the packaging substrate in the space defined between the inner portion and the outer edge of the packaging substrate; A second cable connector is disposed on the second packaging substrate in the space defined between the second inner portion and the outer edge of the second packaging substrate; And a cable that couples the first cable connector to the second cable connector.

13. A method for assembling electronic devices, comprising: Provide a packaging substrate; And attaching a reinforcing member to the packaging substrate using an epoxy resin, the reinforcing member comprising: an inner portion configured to surround a semiconductor wafer disposed on the packaging substrate, the inner portion defining an outer portion on the packaging substrate and located in a space between the inner portion and an outer edge of the packaging substrate; and a plurality of leg portions extending outward from the inner portion toward (i) the outer edge of the packaging substrate and (ii) one or more corners of the packaging substrate.

14. The method of claim 13, further comprising: Within the internal portion, the semiconductor wafer is attached to the packaging substrate.

15. The method as described in claim 14, further comprising: A circuit element is attached to the package substrate within the space defined between the inner portion and the outer edge of the package substrate.

16. The method of claim 15, wherein attaching the circuit element comprises: In the space defined between the inner portion and the outer edge of the packaging substrate, one of a cable connector and a silicon photonic package is attached to the packaging substrate.

17. The method of claim 13 further includes attaching the electronic device to a printed circuit board.

18. The method of claim 17, wherein attaching the electronic device to the printed circuit board comprises: The electronic device is attached to an array of electrical contact terminals.

19. The semiconductor package of claim 1, wherein the plurality of legs extend and contact the outer edge of the package substrate.

20. The semiconductor package of claim 1, wherein the plurality of leg portions extend outward from the inner portion to the outer edge of the package substrate.

21. The semiconductor package as claimed in claim 1, further comprising an element wherein: The plurality of leg portions include: (i) a first leg portion extending laterally from one side of the inner portion; and (ii) a second leg portion extending diagonally from one corner of the inner portion, wherein the first leg portion and the second leg portion define the space on the package substrate; and the element is disposed in the space between the first leg portion and the second leg portion.

22. The semiconductor package as claimed in claim 1, further comprising an element wherein: The plurality of leg portions include: (i) a first leg portion extending diagonally from a first corner of the inner portion; and (ii) a second leg portion extending diagonally from a second corner of the inner portion, wherein the first leg portion and the second leg portion define the space on the package substrate; and the element is disposed in the space between the first leg portion and the second leg portion.

23. The semiconductor package as claimed in claim 1, further comprising an element wherein: The plurality of leg portions include: (i) a first leg portion extending laterally from one side of the inner portion; and (ii) a second leg portion extending laterally from the same side of the inner portion, wherein the first leg portion and the second leg portion define the space on the package substrate; and the element is disposed in the space between the first leg portion and the second leg portion.

24. The semiconductor package of claim 1, wherein the plurality of lead portions include: (i) A first leg portion extending laterally from a first side of the internal portion; (ii) a second leg portion extending laterally from a second side of the inner portion, wherein the second leg portion is perpendicular to the first leg portion.

25. The semiconductor package as claimed in claim 1, wherein: The internal portion is a ring and is disposed on the inner side of the outer edge of the packaging substrate; The plurality of leg portions are connected to each other at their first ends by means of the internal portion, and are not connected to each other at their second ends.

26. The semiconductor package of claim 1, wherein two of the plurality of leg portions extend to at least one outer edge of the package substrate and extend from at least one of: (i) a side of the inner portion and (ii) a corner of the inner portion adjacent to the same side.

27. The semiconductor package of claim 1, further comprising an element disposed in the space between two of the plurality of leg portions.

28. The electronic data communication device of claim 11, wherein the second semiconductor package is mounted on the printed circuit board and communicates with the first semiconductor package via the printed circuit board.

29. The electronic data communication device as claimed in claim 11, further comprising: A first cable connector, (i) disposed on the encapsulation substrate in the space defined between the inner portion and the outer edge of the encapsulation substrate, and (ii) disposed at the periphery of the first encapsulation substrate; a second cable connector, (i) disposed on the second encapsulation substrate in the space defined between the second inner portion and the outer edge of the second encapsulation substrate, and (ii) disposed at the periphery of the second encapsulation substrate; And a cable that couples the first cable connector to the second cable connector.

30. The method of claim 14, further comprising attaching a circuit element to the package substrate in the space defined between the inner portion and the outer edge of the package substrate, wherein attaching the circuit element includes attaching one of a cable connector and a silicon photonic package to the package substrate in the space defined between the inner portion and the outer edge of the package substrate.

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