Wafer bow compensation by patterned UV cure

Abstract

UV light can be guided through a patterned window to selectively expose certain areas of a substrate to UV light. The stress-tunable film deposited on the substrate can undergo localized stress variations due to this selective UV exposure. These localized stress variations in the stress-tunable film can alleviate wafer warpage in the substrate. The patterned window can be designed with UV-transparent and UV-opaque regions to facilitate targeted UV exposure of the stress-tunable film. In some embodiments, the patterned window may include a metallic coating, a ceramic cap, or a metal cap for selective UV exposure. In some embodiments, the patterned window may further include a transition region that allows partial transmission of UV light to limit stress variations in the corresponding areas of the stress-tunable film.

Description

[Technical Field]

[0001] This disclosure relates to apparatus and methods for selective UV exposure, and in particular to wafer warpage compensation by patterned UV curing. [Previous Technology]

[0002] Semiconductor manufacturing processes involve many deposition and etching operations that can significantly alter wafer warpage. For example, in the manufacture of 3D-NAND, which is gradually replacing 2D-NAND chips due to lower costs and higher reliability in many applications, multi-stacked films with thick, high-stress carbon-based hard masks and / or metallization lines can cause significant wafer warpage, resulting in mismatch in front-side lithography coverage or even wafer warpage exceeding the clamping limits of the electrostatic chuck.

[0003] The prior art provided herein is intended to generally present the context of the disclosure. The achievements of the inventors listed in this case within the scope of the prior art described herein, as well as embodiments of the specification that may not have been qualified as prior art at the time of application, are not intended or implied to be recognized as prior art against the disclosure herein. [Summary of the Invention]

[0004] This document provides an apparatus for selective UV exposure. The apparatus includes an ultraviolet (UV) light source and a process chamber. The process chamber includes a substrate support configured to support a semiconductor substrate, and one or more heating elements configured to control the temperature of the semiconductor substrate, wherein the semiconductor substrate includes a stress-tunable film. The apparatus further includes a window positioned between the substrate support and the UV light source, wherein the window is patterned to have one or more UV-transparent regions for selectively exposing one or more first regions of the stress-tunable film to UV light and one or more UV-opaque regions for selectively blocking UV light from one or more second regions of the stress-tunable film.

[0005] In some embodiments, the window system is patterned to have a metallic coating corresponding to one or more UV-opaque regions. In some embodiments, the metallic coating comprises silver, aluminum, or a combination thereof. In some embodiments, the window system is patterned to have a ceramic cover disposed on the window and corresponding to one or more UV-opaque regions. In some embodiments, the ceramic cover comprises aluminum nitride or aluminum oxide. In some embodiments, the window system is patterned to have a metallic cover disposed on the window and corresponding to one or more UV-opaque regions. In some embodiments, the window system is further patterned to have one or more transition regions with a perforated interface between one or more UV-transparent regions and one or more UV-opaque regions, wherein the one or more transition regions are translucent to UV light or contain a grid pattern of UV-transparent and UV-opaque materials. In some embodiments, the one or more transition regions contain a metallic layer having a thickness of less than about 100 nm. In some embodiments, the one or more transition regions are configured to provide a more gradual stress change at the interface between one or more first regions of the stress-tunable film and one or more second regions of the stress-tunable film. In some embodiments, one or more UV-transparent regions are configured to induce a stress shift equal to or greater than about 50% in one or more first regions of the stress-tunable film. In some embodiments, a UV light source is configured to direct UV light to the back side of a semiconductor substrate, wherein the stress-tunable film is formed on the back side of the semiconductor substrate. In some embodiments, a UV light source is configured to direct UV light to the front side of a semiconductor substrate, wherein the stress-tunable film is formed on the front side of the semiconductor substrate. The apparatus further includes a controller configured to have instructions for performing the following operations: providing the semiconductor substrate in a process chamber and selectively exposing one or more first regions of the stress-tunable film to UV light using a patterned window to locally modulate the stress on the stress-tunable film. In some embodiments, the stress-tunable film comprises silicon nitride, silicon oxide, silicon oxynitride, or silicon carbonitride, and the window comprises quartz.

[0006] This document also provides a method for selective UV exposure. The method includes providing a semiconductor substrate on a substrate support in a process chamber, wherein the semiconductor substrate includes a stress-tunable film, wherein a quartz window is positioned between the process chamber and an ultraviolet (UV) light source, and wherein the quartz window is patterned to have one or more UV-transparent regions and one or more UV-opaque regions. The method further includes selectively exposing one or more first regions of the stress-tunable film to UV light through the one or more UV-transparent regions of the quartz window, and selectively blocking UV light for one or more second regions of the stress-tunable film through the one or more UV-opaque regions of the quartz window.

[0007] In some embodiments, selectively exposing one or more first regions of the stress-tunable film involves locally modulating the stress in one or more first regions of the stress-tunable film. In some embodiments, the quartz window system is patterned to have a metallic coating corresponding to one or more UV-opaque regions. In some embodiments, the quartz window system is patterned to have a ceramic or metal cap disposed on the quartz window and corresponding to one or more UV-opaque regions. In some embodiments, the quartz window system is further patterned to have one or more transition regions between one or more UV-transparent regions and one or more UV-opaque regions, wherein the one or more transition regions are translucent to UV light. In some embodiments, the one or more transition regions comprise a metallic layer having a thickness of less than about 100 nm.

Implementation Method

[0024] In this disclosure, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially manufactured integrated circuit" are used interchangeably. Those skilled in the art will understand that the term "partially manufactured integrated circuit" can refer to a silicon wafer during any stage of the many stages of integrated circuit manufacturing. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, 300 mm, or 450 mm. The following detailed description assumes that this disclosure is implemented on a wafer. However, this disclosure is not limited to this. Workpieces can have many shapes, sizes, and materials.

[0025] Semiconductor manufacturing processes involve the formation of numerous structures, many of which may be two-dimensional. As semiconductor device sizes shrink and devices become smaller, the density of features across the semiconductor substrate increases, leading to the etching and deposition of three-dimensional material layers in various ways. For example, compared to other technologies like 2D-NAND, 3D-NAND is becoming increasingly prevalent due to its lower cost, increased memory density, and higher reliability in many applications. During the fabrication of 3D-NAND structures, wafer warpage can vary significantly. For instance, the deposition of thick, rigid masking materials and the etching along trenches on the wafer surface during the fabrication of 3D-NAND structures can cause wafer warpage.

[0026] When film layers are stacked on top of each other during manufacturing, more stress is introduced to the semiconductor wafer, causing warpage. Warpage can take many shapes. In a concave wafer, sometimes called a "smile wafer" or bow wafer, the lowest point is the center of the wafer and the highest point is the edge of the wafer. In a convex wafer, sometimes called a "sad wafer" or dome wafer, the lowest point is the edge of the wafer and the highest point is the center of the wafer.

[0027] Warpage can be measured using optical techniques. Wafer warpage can be measured or evaluated by acquiring a wafer map or stress map. Warpage can be quantified using warpage or twist values ​​as described herein, which are measurements of the vertical distance between the lowest point and the highest point on the semiconductor wafer. Twist values ​​can be along one or more axes; for example, an asymmetrically twisted wafer may have x-axis twist and / or y-axis twist.

[0028] In an arc-shaped wafer, the lowest point is the center of the wafer, and the highest point is the edge of the wafer. In a dome-shaped wafer, the lowest point is the edge of the wafer, and the highest point is the center of the wafer. Arc-shaped and dome-shaped wafers have symmetrical or substantially symmetrical warpage. Wafers can also have asymmetrical warpage. In asymmetrical warpage, the degree of twist is measured along the x-axis and y-axis. Asymmetrically warped wafers have different x-axis twist values ​​and y-axis twist values. In some cases, asymmetrically warped wafers have negative x-axis twist and positive y-axis twist. In some cases, asymmetrically warped wafers have positive x-axis twist and negative y-axis twist. In some cases, asymmetrically warped wafers have both positive x-axis twist and positive y-axis twist, but the twist values ​​are different. In some cases, asymmetrically warped wafers have both negative x-axis twist and negative y-axis twist, but the twist values ​​are different. An example of an asymmetrically warped wafer is a saddle-shaped wafer. In one example, the twist on the x-axis of a saddle-shaped wafer can be +200 μm and the twist on the y-axis can be -200 μm. A saddle-shaped wafer has two opposite edges that curve upwards while the other two opposite edges curve downwards. As used herein, twist can refer to any deviation in planarity exhibited by a wafer, with bow-shaped wafers, dome-shaped wafers, and saddle-shaped wafers being examples of different types of twist in wafers.

[0029] If the substrate is warped, the warping can cause numerous problems with subsequent processing. For example, during lithography, if the substrate is warped, the etching may be uneven. This can lead to problems associated with defocusing and coverage degradation, potentially resulting in significant yield losses. High warping can be caused by the deposition of thick, high-stress hard mask layers. Furthermore, due to the presence of multi-stacked films and thick, high-stress hard masks used in such manufacturing processes, etching can cause some asymmetric warping, and the deposition process can cause significant wafer warping ranging from +500 μm to -1300 μm. For example, ashingable hard masks can have stress values ​​up to -1000 MPa and warping values ​​up to -1000 μm. In some cases, high aspect ratio slot etching and metal filling (e.g., tungsten filling) can induce large anisotropic stresses on the semiconductor substrate.

[0030] Dealing with such wafer distortion can be challenging because subsequent or downstream processing may be affected by wafer distortion exceeding ±200μm, ±300μm, or ±500μm. For example, mechanical wafer handling may be affected due to wafer distortion, where uneven wafers may not be effectively gripped or supported by wafer robots or wafer handling mechanisms. Furthermore, wafer distortion can lead to process inhomogeneities, where downstream etching, deposition, or cleaning operations may be adversely affected by processing inhomogeneities across the wafer surface. In some cases, handling highly distorted wafers may cause further distortion. For example, etching trenches in one direction may cause distortion in asymmetrical warping due to asymmetrical stress on the wafer. Moreover, lithography operations may be adversely affected by wafer distortion because precise patterning cannot be formed. When using wafers in subsequent processes involving wafer clamping to an electrostatic chuck, highly distorted wafers may be unmanageable in some tools. Many electrostatic chucks have a "clamping limit," which is defined as the maximum allowable twist before the wafer can no longer be effectively clamped. For example, some electrostatic chucks have a clamping limit of approximately ±300 μm. In such cases, it may be impossible to handle wafers twisted beyond the clamping limit.

[0031] Figure 1 shows a perspective view of a warped semiconductor substrate, illustrating wafer warping in the x-axis and y-axis directions. The warped semiconductor substrate is superimposed in a three-dimensional (3D) coordinate system with a reference plane defined by the x-axis and y-axis directions, and a u-axis indicating the twist. As shown in Figure 1, the warped semiconductor substrate is asymmetrically warped, meaning that the x-axis twist value is different from the y-axis twist value. This produces a saddle-shaped warping. As discussed above, twist refers to any planarity deviation exhibited by the semiconductor substrate, where the saddle-shaped wafer represents an example of twist in the semiconductor substrate.

[0032] As 3D-NAND technology continues to scale up and high aspect ratio features become increasingly common, new challenges related to localized stress and inter-die stress variations on semiconductor substrates are emerging. Localized stress and inter-die stress variations can lead to lock-in bending, cell crosstalk, cell loss, and / or cell misalignment. Localized stress refers to stress changes occurring in a non-uniform manner within the wafer. Poorly compensated / corrected localized stress can lead to localized wafer topology changes, which in turn can result in misalignment during photolithography. Such misalignment is typically examined as in-plane distortion (IPD), which arises from the quantization of the vector displacement between alignment marks on the wafer topology and their intended positions. High IPD during photolithography can lead to undesirable changes in critical dimensions or any other features defined in the photolithography step, resulting in the aforementioned phenomena of lock-in bending, cell crosstalk, cell loss, and / or cell misalignment caused by photolithography errors.

[0033] Certain techniques exist for addressing symmetrical warpage of semiconductor wafers, and in some cases, the techniques can reduce warpage by altering the fabrication process of the desired layer in the substrate. Techniques for addressing symmetrical warpage of semiconductor substrates may involve the deposition of a warpage compensation layer on the back side of the semiconductor substrate. The application of warpage compensation layers on the back side of semiconductor substrates has historically been largely limited to monotonic global wafer warpage mitigation. In other words, such techniques for addressing semiconductor substrate warpage have historically been primarily limited to axisymmetric or multi-axis symmetric techniques. However, a few techniques exist for addressing asymmetric warpage, such as saddle-shaped warpage. The complexity of current techniques leads to more complex wafer warpage shapes, such as saddle-shaped warpage.

[0034] Among the few techniques used to address asymmetric warpage, one such technique may involve a precursor partition mask provided adjacent to the back side of a warped semiconductor substrate. For example, a support ring supporting the warped semiconductor substrate may be designed to have a support ring mask for masking certain areas of the warped semiconductor substrate during deposition. Another technique may involve a multi-gas-filled spray head to control the delivery of gas to different locations. For example, precursor material for depositing a compressed film may be delivered via a first region of the spray head platform and precursor material for depositing a stretched film may be delivered via a second region of the spray head platform.

[0035] Figure 2 shows a top view schematic diagram of an exemplary system for mitigating wafer warpage using a partition mask adjacent to a semiconductor substrate. A semiconductor substrate 203 may be provided in a process chamber. The semiconductor substrate 203 may be supported in the process chamber by a substrate holder 201. A partition mask 205 is positioned between the semiconductor substrate 203 and a gas distributor (e.g., a spray head stand) (not shown). The partition mask 205 may shield or block certain areas of the semiconductor substrate 203 during deposition. For illustrative purposes, the partition mask 205 is depicted as transparent to show the semiconductor substrate 203 below the partition mask 205. Only the upper right and lower left quadrants of the semiconductor substrate 203 are exposed to the deposited material. In some embodiments, the partition mask 205 may be a circular, planar block of material divided into four quadrants. The upper right and lower left quadrants of the partition mask 205 are exposed, while the upper left and lower right quadrants are not exposed.

[0036] Figure 3 shows a top schematic diagram of an exemplary system for mitigating wafer warpage using a multi-gas-filled spray head. The spray head 300 can be divided into four zones or regions 301, 302, 303, and 304, each capable of delivering different or the same gases for forming different or the same materials. In Figure 3, regions 301 and 303 are "opposite regions," and regions 302 and 304 are "opposite regions." For the deposition of a warpage compensation layer on an asymmetric warpage semiconductor substrate, the gases delivered to the first set of opposite regions (e.g., regions 301 and 303) can be the same, and the gases delivered to the second set of opposite regions (e.g., regions 302 and 304) can be the same. However, the gases delivered between the first and second sets can be different. For illustration, the gas for depositing a compressed silicon oxide film can be delivered via the first set of opposite regions, and the gas for depositing a stretched silicon nitride film can be delivered via the second set of opposite regions.

[0037] Local stress modulation can be achieved by using a partitioned mask, as shown in Figure 2, to deliver precursor material to certain areas or regions of a warped semiconductor substrate. Local stress modulation can also be achieved using a precursor partition with multiple gas filling sections, as shown in Figure 3, to control gas delivery to different locations. However, such techniques have been limited or ineffective due to high IPD coverage and associated problems with clamping the semiconductor substrate. High coverage error and vacuum clamping issues may result from abrupt changes in film stress between regions and difficulties in designing a region layout that minimizes local topological changes.

[0038] This disclosure provides a method and apparatus for mitigating asymmetric warpage in a warped semiconductor substrate by selective UV exposure. Instead of depositing compression and stretching films separately in different regions of the warped semiconductor substrate, a single compression or stretching film is deposited on the front or back side of the warped semiconductor substrate. This compression or stretching film is a stress-tunable film that undergoes stress modulation from UV exposure. The UV chamber is equipped with a UV light source, a substrate support for supporting the warped semiconductor substrate, and a window positioned between the substrate support and the UV light source. The window is patterned to have UV-transparent and UV-opaque regions to allow selective exposure of certain regions of the stress-tunable film for stress variation. In some embodiments, the window is patterned to have a metallic coating or a ceramic cap. In some embodiments, the window is further patterned to have a transition region that allows partial transmission of UV light, causing partial stress variation in the corresponding region of the stress-tunable film.

[0039] As used herein, a substrate holder is configured to support, hold, or otherwise cradle a substrate within a processing chamber. During the various processing steps performed within the processing chamber, the substrate is placed on or provided on the substrate holder. Thus, when the substrate undergoes processing (e.g., UV exposure), such as the substrate of a semiconductor wafer, it is positioned on the substrate holder within a UV chamber. In some embodiments, the substrate holder is a stage (e.g., a ceramic stage), an electrostatic chuck, a mechanical chuck, a plate, or other type of substrate holder.

[0040] As used herein, the window is a material element between the substrate support and the UV light source, or a material element that separates the UV light chamber from the substrate processing chamber, wherein the material element is transmissive or at least partially transmissive to the UV radiation system. Generally, the window is made of a glass material such as quartz glass. In some embodiments, the glass material is quartz glass, borosilicate glass, or phosphate glass.

[0041] As used herein, UV radiation or UV light can broadly include radiation from 150 nm to the infrared region (about 1 to 10 µm). In some embodiments, UV radiation or UV light is between about 150 nm and about 800 nm. UV radiation or UV light can be emitted from a UV source in a range or at a single wavelength.

[0042] FIG4A shows a schematic diagram of an exemplary apparatus for UV processing, the apparatus including a window positioned between a UV source and a semiconductor substrate. FIG4B shows a top view of the window transparent to the UV radiation of FIG4A. The apparatus 400 includes a process chamber 410 for processing or fabricating a substrate 412, and a UV light chamber 420 for housing a UV light source 422. The apparatus 400 includes a substrate holder 414 for supporting the substrate 412 in the process chamber 410. The apparatus 400 may include one or more heating elements 416 for controlling the temperature of the substrate 412. In some embodiments, the substrate holder 414 may be a pedestal equipped with one or more heating elements 416 for controlling the temperature of the substrate 412. In some embodiments, the substrate 412 may be in full contact with the pedestal or may be supported above the pedestal by means of an accessory (e.g., a pin). In some embodiments, the substrate holder 414 may clamp or hold the substrate 412 such that the back or front side of the substrate 412 faces the UV light source 422. The substrate 412 may be a warped semiconductor substrate, wherein the warped semiconductor substrate may have a stress-tunable film (not shown) deposited on the back or front side of the warped semiconductor substrate. The UV light source 422 may be configured to emit UV light to cure the stress-tunable film, thereby causing the stress-tunable film to undergo stress changes.

[0043] The UV light source 422 can be any suitable illumination source that emits UV radiation. The UV light source 422 may include a lamp, a light-emitting diode (LED), a bulb, a laser, or a combination thereof. In some cases, the UV light source 422 may emit UV light across a wide wavelength range from 170 nm to 400 nm, or it may emit UV light across a narrower wavelength range from 185 nm to 255 nm. For example, the UV light source 422 may relate to a broadband UV light source. The UV light source 422 and / or the UV light chamber 420 may be equipped with aperture and beamforming optics, such as lenses or mirrors. For example, the UV light chamber 420 may include a cold mirror for reflecting UV radiation. The UV light source 422 and / or the UV light chamber 420 may be equipped with filters, reflectors, gratings, prisms, or other wavelength-selective optics. For example, when the UV light source 422 is a broadband UV light source that generates a wide spectrum of radiation, optical components such as reflectors, filters, or a combination of reflectors and filters can be used to modulate the broadband spectrum reaching the substrate 412.

[0044] The apparatus 400 further includes a window 430 positioned between the UV light source 422 and the substrate holder 414. The window 430 can separate the UV light chamber 420 from the process chamber 410. The window 430 can be a quartz window that is transparent to UV radiation or at least substantially transparent. By changing the level of metallic impurities and water content in the quartz window, the window 430 can be manufactured to block radiation at unwanted wavelengths. High-purity silica with very few metallic impurities is more transparent in deeper ultraviolet spectra. As an example, quartz with a thickness of 1 cm will have a transmittance of about 50% at a wavelength of 170 nm, while it drops to only a few percent at 160 nm. The increased impurity level in the quartz will cause a reduction in UV transmission at lower wavelengths. Fused quartz has more metallic impurities, thus limiting its UV transmission wavelength to around 200 nm and longer. On the other hand, synthetic silica has higher purity and will shift down to 170 nm. For infrared radiation, the transmittance through quartz is determined by its water content. Higher water content in quartz means that infrared radiation is more easily absorbed. The water content in the quartz can be controlled through the manufacturing process. Therefore, the spectrum of radiation transmission through window 430 can be controlled to cut off or reduce UV transmission at shorter wavelengths and / or reduce infrared transmission at longer wavelengths. In Figures 4A and 4B, window 430 is unpatterned, allowing all or substantially all UV light from UV light chamber 420 to enter process chamber 410 through window 430.

[0045] The process chamber 410 may be configured to control the temperature of the substrate 412. One or more heating elements 416 may face the substrate 412 for substrate temperature control. As used herein, "heating element" refers to a component used to control the temperature of a workpiece or substrate. Heating elements may be embedded in a substrate holder 414, positioned adjacent to the substrate 412, positioned within the process chamber 410, or positioned outside the process chamber 410 for heating the substrate 412. In some embodiments, one or more heating elements 416 may be one or more LEDs, wherein the LEDs may be arranged in a plurality of independently controllable heating zones. Independently controllable heating zones facilitate temperature control in a plurality of areas of the substrate 412. In some embodiments, one or more heating elements 416 are resistance heaters. One or more heating elements 416 are configured to control the temperature of the substrate 412, wherein one or more heating elements 416 may allow the substrate temperature to be controlled in a range between about 5°C and about 675°C, or between about 50°C and about 500°C.

[0046] FIG5A shows a schematic diagram of an exemplary apparatus for UV processing, which, according to some embodiments, includes a patterned window positioned between a UV source and a semiconductor substrate. The apparatus 500 includes a process chamber 510 for processing or fabricating a substrate 512, and a UV light chamber 520 for housing a UV light source 522. The apparatus 500 includes a substrate holder 514 for supporting the substrate 512 within the process chamber 510. The apparatus 500 may include one or more heating elements 516 for controlling the temperature of the substrate 512. In some embodiments, the substrate holder 514 may clamp or hold the substrate 512 such that the back or front side of the substrate 512 faces the UV light source 522. Accordingly, in some cases the UV light source 522 may be configured to direct UV light to the back side of the substrate 512, or in other cases the UV light source 522 may be configured to direct UV light to the front side of the substrate 512. Various embodiments of one or more heating elements 516, substrate bracket 514, substrate 512, process chamber 410, UV light chamber 420, and UV light source 522 in FIG5A can be described based on the description of one or more heating elements 416, substrate bracket 514, substrate 512, process chamber 510, UV light chamber 520, and UV light source 522 in FIG4A.

[0047] The substrate 512 may be a warped semiconductor substrate, wherein the warped semiconductor substrate may have a stress-adjustable film (not shown) deposited on the back or front side of the warped semiconductor substrate. A warped semiconductor substrate refers to any semiconductor substrate having a surface deviating from a flat reference plane. In particular, the warped semiconductor substrate may have a twist exceeding ±300µm. In some embodiments, the warped semiconductor substrate may be asymmetrically warped.

[0048] A stress-tunable film can be deposited on the front or back side of the substrate 512 to have compressive or tensile film stress. The stress-tunable film is configured to undergo substantial stress changes in response to UV exposure, thermal exposure, or a combination thereof. Accordingly, the stress-tunable film can be a UV-curable film, a thermally curable film, or both. The stress-tunable film may include a dielectric material such as an ultra-low k dielectric material. In some embodiments, the stress-tunable film includes nitrides, oxides, or doped nitrides. Nitrides and oxides can undergo significant stress changes after UV curing. In some examples, the stress-tunable film includes silicon nitride, silicon oxide, silicon oxynitride, or silicon carbonitride. In some embodiments, the thickness of the stress-tunable film is between about 20 nm and about 150 nm, between about 25 nm and about 100 nm, or between about 30 nm and about 100 nm. The thickness of the stress-adjustable film is thin enough to allow complete UV radiation penetration and thick enough to induce stress on the underlying warped semiconductor substrate.

[0049] In some embodiments, any suitable deposition technique can be used to deposit a stress-tunable film on the substrate 512. In some embodiments, the stress-tunable film is deposited by chemical vapor deposition, such as plasma-enhanced chemical vapor deposition (PECVD). During PECVD, a silicon-containing precursor, such as silane, can be reacted with one or more reactive gases exposed to plasma to form a stress-tunable film, wherein the stress-tunable film is a silicon-containing film. For example, silane (SiH4) can be flowed into a deposition chamber containing ammonia (NH3) and / or nitrogen (N2) to deposit silicon nitride. Films deposited by PECVD typically contain a large amount of hydrogen. The amount of hydrogen in the film can affect the degree of stress in the stress-tunable film. In fact, the amount of hydrogen in the film can affect the degree of stress change that occurs after exposure to elevated temperatures or exposure to UV light. Specifically, nitride films, such as silicon nitride films, deposited via PECVD may contain Si-H and NH bonds in addition to Si-N bonds. Without any theoretical constraints, exposing the silicon nitride film to elevated temperatures or UV radiation causes the Si-H bonds to break, releasing hydrogen atoms from the silicon nitride film. With the breaking of Si-H bonds and the release of hydrogen atoms, the internal bonding structure within the silicon nitride film reorganizes. Silicon and nitrogen atoms rearrange and recombine within the film. This reorganization and rearrangement within the silicon nitride film can include stress changes leading to high stress displacement in response to thermosetting or UV curing.

[0050] The apparatus 500 further includes a window 530 positioned between the UV light source 522 and the substrate holder 514. The window 530 can separate the UV light chamber 520 from the process chamber 510. The window 530 can be patterned to define one or more UV transparent regions 532 and one or more UV opaque regions 534. Transparency, as used herein, can be defined as the transmittance of about 70% or more of UV light, for example, about 80% or more, or about 90% or more. That is, the amount of UV light passing through the window 530 of a certain thickness in one or more UV transparent regions 532 is equal to or greater than about 70%. One or more UV opaque regions 534 prevent or otherwise restrict the transmission of UV light through the window 530. In other words, one or more UV opaque regions 534 impede the transmission of UV light by reflecting or absorbing UV light, wherein opacity, as used herein, can be defined as the reflection or absorption of about 70% or more of UV light, for example, about 80% or more, or even about 90% or more. This can be achieved using materials that are opaque to or reflect UV light.

[0051] Window 530 is patterned to have a UV-transparent area 532 and a UV-opaque area 534 to provide a mask for selective UV exposure of substrate 512. The UV-opaque area 534 blocks or otherwise prevents UV light from reaching non-target areas of substrate 512, while the UV-transparent area 532 facilitates the transmission of UV light to target areas of substrate 512. Window 530 can be configured to cover substrate 512. The transparent and opaque portions of window 530 may correspond to areas of substrate without UV exposure and areas of substrate with UV exposure, respectively. The transparent and opaque portions of window 530 are positioned, sized, and shaped to accommodate areas of localized warping and stress in substrate 512. Thus, window 530 is patterned according to the target and non-target areas of substrate 512 for selective UV exposure. In some embodiments, window 530 is sized and shaped to fit the size and shape of substrate 512 to be processed.

[0052] During operation, the UV light source 522 emits UV light and passes through the patterned window 530 to selectively cure one or more regions of the stress-tunable film on the substrate 512. The stress-tunable film can be deposited on the substrate 512 with a tensile stress value (e.g., between about +0.1 MPa and about +2000 MPa) or with a compressive stress value (e.g., between about -0.1 MPa and about -2000 MPa). By way of example, a nitrogen-doped silicon carbide film may have a deposited stress value of about -400 MPa. In another example, a silicon nitride film may have a deposited stress value of about +700 MPa. In response to UV exposure, or both UV and thermal exposure, the stress-tunable film may undergo a stress shift equal to or greater than about 20%, equal to or greater than about 30%, equal to or greater than about 40%, or equal to or greater than about 50%. In some cases, stress shift can cause a stress-tunable film to change from a stretched film to a compressed film, or vice versa. The portion of the stress-tunable film selectively exposed to UV light undergoes stress variation, while the portion not exposed to UV light avoids stress variation. After selective UV exposure, the exposed portion becomes more stretched or more compressed. This allows the stress-tunable film to locally modulate stress at different locations, thereby mitigating warpage in warped semiconductor substrates.

[0053] The window 530 is patterned using a material opaque to UV light. In some embodiments, the window 530 is patterned as having a metal coating 540 corresponding to one or more UV-opaque areas 534. FIG5B shows a cross-sectional view of the patterned window 530 of FIG5A having a metal coating 540 according to some embodiments. The metal coating 540 shields certain areas of the window 530 so that UV light does not pass through the shielded areas. The metal coating 540 can help to increase the transmission efficiency of UV light through the UV transparent area 532 by reflecting UV light in the UV opaque area 534. Specifically, by reflecting UV light, UV light can be reflected by reflectors positioned at various points in the UV light chamber 520, thereby increasing the intensity of UV light passing through the UV transparent area 532. The metal coating 540 can be positioned directly on the surface of the window 530, on the surface of the window 530 facing the substrate bracket 514 or on the surface of the window 530 facing the UV light source 522. In some embodiments, the metal coating 540 comprises silver, aluminum, or a combination thereof. The metal coating 540 may even be a combination of multiple metal layers. The metal coating 540 may have a thickness sufficient to prevent UV light transmission. In some embodiments, the metal coating 540 has a thickness equal to or greater than 100 nm, for example, between about 100 nm and about 1000 nm.

[0054] In some embodiments, the window is patterned as a ceramic cover 550 having one or more UV-opaque areas 534. FIG. 5C shows a cross-sectional view of the patterned window 530 of FIG. 5A having a ceramic cover 550 according to some embodiments. The ceramic cover 550 is designed to shield an area of ​​the window 530 such that UV light does not pass through the shielded area. The ceramic cover 550 comprises a ceramic material that is opaque to UV light. Examples of such ceramic materials include, but are not limited to, aluminum nitride or aluminum oxide. The ceramic cover 550 has an opening 552 corresponding to a UV-transparent area 532 and a ceramic material block 554 corresponding to a UV-opaque area 534. The ceramic cover 550 may be customizable or configured to be placed in the device 500 such that the ceramic cover 550 is detachably inserted above or below the window 530. In some embodiments, the ceramic cover 550 is detachably positioned on the window 530. The structure and design of the window 530 may be manufactured independently of the ceramic cover 550. The ceramic cap 550 may have a thickness sufficient for handling and sufficient to prevent the transmission of UV light. In some embodiments, the ceramic cap 550 may have a thickness equal to or greater than about 0.1 mm, for example, between about 0.1 mm and about 10 mm.

[0055] In some alternative embodiments, the window is patterned as a metal cover (not shown) having corresponding one or more UV-opaque areas 534. The metal cover uses a metallic material, such as aluminum, instead of a ceramic material to shield the area of ​​window 530 so that UV light does not pass through the shielded area. The metallic material may absorb or reflect UV light from the UV light source 522.

[0056] Figure 6A shows a top view of a patterned window having UV-transparent and UV-opaque areas according to certain embodiments. The patterned window 610 can be any suitable shape for processing a semiconductor substrate. In some embodiments, the patterned window 610 is a circular block of material (one or more). UV light can pass through the patterned window 610 to expose the semiconductor substrate, wherein the patterned window can be made of a suitable material such as quartz. The patterned window 610 can be defined by multiple areas or regions 611, 612, 613, 614. Regions 611 and 613 are "opposite regions" and are used as UV-transparent areas 611 and 613, while regions 612 and 614 are "opposite regions" and are used as UV-opaque areas 612 and 614. Regions 612 and 614 can also be referred to as shielding areas or covering areas. In some embodiments, the UV-opaque areas 612 and 614 can use a metal coating, a metal cap, or a ceramic cap to block or reflect UV light. In Figure 6A, regions 611, 612, 613, and 614 are equal in area.

[0057] Figure 6B shows a top view of a patterned window having a UV-transparent area occupying a larger surface area compared to the UV-opaque area, according to some embodiments. The patterned window 620 can be any suitable shape for processing a semiconductor substrate. In some embodiments, the patterned window 620 is a circular block of material (one or more). UV light can pass through the patterned window 620 to expose the semiconductor substrate, wherein the patterned window can be made of a suitable material such as quartz. The patterned window 620 can be defined by a plurality of regions or areas 621, 622, 623, 624. Regions 621 and 623 are "opposite regions" and are used as UV-transparent regions 621 and 623, while regions 622 and 624 are "opposite regions" and are used as UV-opaque regions 622 and 624. In some embodiments, the UV-opaque regions 622 and 624 may use a metal coating, a metal cap, or a ceramic cap to block or reflect UV light. In Figure 6B, the UV transparent regions 621 and 623 occupy a larger surface area than the UV opaque regions 622 and 624. Specifically, the size and shape of the UV opaque regions 622 and 624 can be designed and configured based on the warp properties or the shape of the semiconductor substrate being processed. The geometrical patterning of the patterned window 620 allows for the targeted application of UV radiation to specific areas of the semiconductor substrate.

[0058] Selective UV exposure creates UV-exposed and UV-unexposed areas in a stress-tunable film to alleviate asymmetric warpage, where the stress variation between the UV-exposed and UV-unexposed areas can be quite large. When the stress variation is too large and sudden, peaks or ridges may form in the processed semiconductor substrate. In some cases, film bursting may even occur. By way of example, a deposited stress-tunable film may have a stress value of +500 MPa. After selective UV exposure, the UV-unexposed area maintains a stress value of +500 MPa while the UV-exposed area changes to a stress value of -500 MPa. A stress shift of 1000 MPa between the stretched and compressed regions of the stress-tunable film may be sudden. However, the distortion across the substrate surface is usually gradual and smooth, meaning that changes in local wafer topology occur smoothly and gradually rather than suddenly and incrementally. Therefore, stress variations occurring at the interface between the UV-exposed and UV-unexposed areas in the stress-tunable film may lead to peaks or ridges in the substrate. We aim to make the stress change at the interface between the UV-exposed and UV-unexposed areas of the stress-tunable film more gradual and smoother.

[0059] In some embodiments, the window (e.g., window 530) may be further patterned to have one or more transition regions for partial or restricted transmission of UV light through one or more transition regions of the window. For example, the transition regions may allow approximately 50% UV light transmittance, while UV-transparent regions may allow more than 90% UV light transmittance and UV-opaque regions may allow less than 5% UV light transmittance. One or more transition regions provide a portion of or reduce UV exposure of the corresponding transition region of the stress-tunable film. In this way, the corresponding transition region of the stress-tunable film undergoes a stress offset smaller than the stress offset of the UV-exposed region of the stress-tunable film. The corresponding transition region of the stress-tunable film provides an interface between the UV-exposed and UV-unexposed regions of the stress-tunable film such that the stress change between the UV-exposed and UV-unexposed regions is not abrupt. This mitigates film bursting and the formation of peaks or ridges in the substrate by making the stress change occur more gradually rather than abruptly.

[0060] In some embodiments, the window may include multiple transition regions with an interface laid between a UV transparent region and a UV opaque region. At least some of the multiple transition regions may allow varying UV light transmission to provide a more gradual stress variation in the corresponding regions of the stress-tunable film. For example, a first transition region may allow approximately 60% UV light transmittance, and a second transition region adjacent to the first transition region may allow approximately 30% UV light transmittance. The corresponding first transition region of the stress-tunable film may have a larger stress offset than the corresponding second transition region of the stress-tunable film, while the UV-exposed region of the stress-tunable film has the largest stress offset.

[0061] Figure 6C shows a top view of a patterned window having a UV transparent area, a UV opaque area, and a transition area that is semi-transparent to UV radiation, according to certain embodiments. As shown in Figures 6A and 6B, the patterned window 630 can be defined by multiple areas or regions 631, 632, 633, and 634. Regions 631 and 633 are "relative regions" and are used as UV transparent areas 631 and 633, while regions 632 and 634 are "relative regions" and are used as UV opaque areas 632 and 634. The patterned window 630 can be further defined by a transition area 635. The transition area 635 lays an interface between the UV transparent areas 631 and 633 and the UV opaque areas 632 and 634. In other words, the transition area 635 occupies a region of the patterned window 630 between the UV transparent areas 631 and 633 and the UV opaque areas 632 and 634. In Figure 6C, the transition region 635 is semi-transparent to the UV light system. The UV transparent regions 631 and 633 are transparent or at least substantially transparent to the UV light system, and the UV opaque regions 632 and 634 are opaque or reflective to the UV light system.

[0062] In some embodiments, the translucency of the transition region 635 may be achieved using a material that is partially transparent to UV light. By way of example, such a translucent material may include quartz.

[0063] In some embodiments, the translucency of the transition region 635 can be achieved using a metal or opaque ceramic material with reduced thickness. Typically, a metal coating with a thickness equal to or greater than about 100 nm is effective for reflecting UV light. The transition region 635 may include a metal layer with a thickness of less than 100 nm to allow partial transmission of UV light. Therefore, the transition region 635 may include a UV opaque material with a reduced thickness relative to the UV opaque regions 632, 634.

[0064] FIG. 6D shows a top view of a patterned window having a UV transparent area, a UV opaque area, and a transition area made of a mesh pattern, according to certain embodiments. As in FIGS. 6A and 6B, the patterned window 640 can be defined by multiple areas or regions 641, 642, 643, and 644. Regions 641 and 643 are "opposite areas" and are used as UV transparent areas 641 and 643, while regions 642 and 644 are "opposite areas" and are used as UV opaque areas 642 and 644. The patterned window 640 can be further defined by a transition area 645. As in FIG. 6C, the transition area 645 lays an interface between the UV transparent areas 641 and 643 and the UV opaque areas 642 and 644. In FIG. 6D, the transition area 645 uses a mesh pattern or mesh to partially transmit UV light. UV transparent regions 641 and 643 are transparent to or at least substantially transparent to the UV light system, while UV opaque regions 642 and 644 are opaque to or reflective of the UV light system.

[0065] In some embodiments, the grid pattern of the transition region 645 may include a mixture of UV-opaque and UV-transparent materials. For example, the grid pattern may include metallic lines or shapes on a quartz material, or it may include opaque ceramic lines or shapes on a quartz material. In this way, UV light passing through the grid pattern of the transition region 645 may be partially reflected or absorbed and partially transmitted.

[0066] A stress-tunable film can be deposited on the front or back side of a semiconductor substrate. Typically, the front side of a semiconductor substrate contains numerous circuits, transistors, or other device components. To mitigate warping in a warped semiconductor substrate, it is desirable to deposit a stress-tunable film on the back side of the semiconductor substrate to avoid deposition on the circuits, transistors, and other device components.

[0067] FIG7 shows a schematic diagram of an exemplary apparatus for UV backside processing, which, according to some embodiments, includes a patterned window positioned between a UV source and a semiconductor substrate. The apparatus 700 in FIG7A is similar to the apparatus 500 in FIG5A, except that it is oriented in an inverted direction, such that a process chamber 710 is positioned above a UV light chamber 720. The apparatus 700 includes a process chamber 710 for processing or fabricating a substrate 712, and a UV light chamber 720 for housing a UV light source 722. The apparatus 700 includes a substrate holder 714 for supporting the substrate 712 within the process chamber 710. In some embodiments, the substrate holder 714 may hold the substrate 712 by an edge, and the backside of the substrate 712 may face the UV light source 722. In some embodiments, the backside of the substrate 712 is not patterned. In some embodiments, the backside of the substrate 712 includes a stress-adjustable film. The apparatus 700 may include one or more heating elements 716 for controlling the temperature of the substrate 712. Various embodiments of one or more heating elements 716, substrate brackets 714, substrates 712, process chambers 410 / 510, UV light chambers 420 / 520, and UV light sources 422 / 522 in FIG7A can be described based on the descriptions of one or more heating elements 416 / 516, substrate brackets 414 / 514, substrates 712, process chambers 710, UV light chambers 720, and UV light sources 722 in FIG7A.

[0068] The apparatus 700 further includes a window 730 positioned between the UV light source 722 and the substrate holder 714. The window 730 can separate the UV light chamber 720 from the process chamber 710. The window 730 can be patterned to define one or more UV transparent areas 732 and one or more UV opaque areas 734. The window 730 is patterned to have UV transparent areas 732 and UV opaque areas 734 to provide a mask for selective UV exposure of the back side of the substrate 712. This allows target areas of the stress-tunable film deposited on the back side of the substrate 712 to undergo stress variation to obtain locally modulated stress, thereby alleviating warpage in the substrate 712. In some embodiments, the window 730 is patterned using a metal coating, a ceramic cap, or a metal cap. In some embodiments, the window 730 is further patterned to have one or more transition areas for partial or reduced transmission of UV light. In Figure 7, the UV light source 722 is configured to guide UV light to the back side of the substrate 712, wherein a stress-tunable film is formed on the back side of the substrate 712.

[0069] FIG8 illustrates a flowchart of an exemplary method of selective UV exposure according to certain embodiments. The operation of process 800 may be performed in different sequences and / or may have different, fewer, or additional operations. The operation of process 800 may be performed using the apparatus for UV treatment shown in FIG5A, FIG7, or FIG9. In some embodiments, the operation of process 800 may be implemented at least in part based on software stored in one or more non-transitory computer-readable media.

[0070] At block 810 of process 800, a semiconductor substrate is provided on a substrate support in a process chamber, wherein the semiconductor substrate includes a stress-tunable film. A quartz window is positioned between the process chamber and a UV light source, wherein the quartz window is patterned to have one or more UV-transparent regions and one or more UV-opaque regions. The semiconductor substrate may be a warped semiconductor substrate. A warped semiconductor substrate may be provided in the process chamber to perform at least a UV processing operation. However, it will be understood that in some embodiments, the process chamber may be configured to perform one or both of the UV processing and deposition operations. The semiconductor substrate may be a silicon wafer, such as a 200-mm wafer, a 300-mm wafer, or a 450-mm wafer, including a wafer having one or more layers of material deposited thereon, such as dielectric, conductive, or semiconductive materials. Some of the one or more layers may be patterned. Non-limiting examples of layers include dielectric layers and conductive layers, such as silicon oxide, silicon nitride, silicon carbide, metal oxides, metal nitrides, metal carbides, and metal layers. In many embodiments, the semiconductor substrate is patterned.

[0071] In some embodiments, the semiconductor substrate includes a patterned 3D-NAND structure and one or more etched trenches in the substrate. In some embodiments, the semiconductor substrate may be asymmetrically warped. The warped semiconductor substrate may have a twist of about +1000 μm. In some embodiments, the warped semiconductor substrate has a twist greater than about +300 μm. In some embodiments, the warped semiconductor substrate has a twist greater than about +300 μm and less than about +1000 μm. The twist may occur in one or more localized regions of the warped semiconductor substrate. The twist may have different values ​​between x-axis twist and y-axis twist. Thus, the twist along one axis may be more significant than that along the other axis.

[0072] The stress-tunable film can be deposited on the front or back side of the semiconductor substrate. In some embodiments, the stress-tunable film is deposited on the back side of the semiconductor substrate. In this way, the stress-tunable film is avoided from being deposited on circuits, transistors, or other device components on the front side of the semiconductor substrate. The stress-tunable film can be used as a warp compensation layer to alleviate warping in the semiconductor substrate.

[0073] The stress-tunable film may be one or both of a UV-curable film and a thermocurable film. The stress-tunable film undergoes stress changes upon exposure to either UV exposure or thermal exposure. In some embodiments, the stress-tunable film undergoes a stress shift equal to or greater than about 20%, equal to or greater than about 30%, equal to or greater than about 40%, or equal to or greater than about 50% upon exposure to UV light and / or increased temperature. In some embodiments, the stress-tunable film is a UV-curable film subjected to a stress value change greater than about 200 MPa, for example, between about 200 MPa and about 4000 MPa. This means that the deposited stress value of the stress-tunable film can vary by 200 MPa or more relative to the cured stress value. In some cases, the stress-tunable film can change from tension to compression, or from compression to tension.

[0074] In some embodiments, the stress-tunable film comprises a dielectric material, such as an ultra-low k dielectric material. In some embodiments, the stress-tunable film comprises a nitride, a doped nitride, or an oxide. In some examples, the stress-tunable film comprises silicon nitride. In some examples, the stress-tunable film comprises silicon carbonitride.

[0075] The quartz window between the substrate and the UV light source can be pre-patterned to allow UV light to selectively pass through the quartz window. By pre-patterning the quartz window, this avoids the need to introduce individual components or masks between the substrate and the light source. Fabricating individual components or masks may require additional steps in manufacturing, patterning, and insertion into the gap between the substrate and the light source. These additional steps can be time-consuming, cumbersome, and expensive. The quartz window is already a component of the UV processing chamber or apparatus. In some embodiments, the quartz window is patterned as a metallic coating having, for example, a silver or aluminum coating. The metallic coating may correspond to the UV-opaque area of ​​the quartz window. The metallic coating may have a thickness equal to or greater than about 100 nm, for example, between about 100 nm and about 1000 nm. In some embodiments, the quartz window is patterned as a ceramic cap having, for example, an aluminum nitride or aluminum oxide cap. The ceramic cap may correspond to the UV-opaque area of ​​the quartz window. The ceramic cap may have a thickness equal to or greater than about 1 mm, for example, between about 1 mm and about 100 mm. In some embodiments, the quartz window is patterned as a metal cover, such as an aluminum cap. The metal cap may correspond to the UV-opaque area of ​​the quartz window. The quartz window can be patterned to allow UV light transmission in the UV-transparent area and to block or reflect UV light in the UV-opaque area. In some embodiments, the quartz window may be patterned based on measurements of local stress on the semiconductor substrate. Measurements of local stress on the semiconductor substrate can be derived from a stress map.

[0076] At block 820 of process 800, one or more first regions of the stress-tunable film are selectively exposed to UV light through one or more UV-transparent regions of a quartz window, and one or more UV-opaque regions of the quartz window selectively block UV light for one or more second regions of the stress-tunable film. One or more first regions correspond to UV-transparent regions, and one or more second regions correspond to UV-opaque regions. The selective exposure of the one or more first regions to UV light locally modulates the stress of the stress-tunable film. After locally modulating the stress in the various regions of the stress-tunable film, the stress-tunable film helps to alleviate warpage in the semiconductor substrate.

[0077] The patterned quartz window selectively blocks UV exposure, allowing only certain areas of the semiconductor substrate to be exposed to UV radiation. In this way, one or more first regions represent UV-exposed areas subject to stress variation, while one or more second regions represent UV-unexposed areas without stress variation. Compared to one or more second regions, one or more first regions of the stress-tunable film can become more stretched or more compressed in stress. In the stress-tunable film after selective UV exposure, stress can be directed to one or more regions of the semiconductor substrate to alleviate warping in the semiconductor substrate. Localized stress in the stress-tunable film after selective UV exposure can be modulated to achieve a localized torsional topology.

[0078] Without any theoretical limitations, stress changes can evolve from the removal of hydrogen from the stress-tunable film during UV exposure. This can be observed in PECVD silicon nitride films. The loss of hydrogen and / or shrinkage of pores may lead to a reduction in volume in the stress-tunable film. However, the constraint of the semiconductor substrate prevents any lateral shrinkage, thereby imposing tensile strain in the exposed areas of the stress-tunable film. In some embodiments, selective exposure of one or more first regions of the stress-tunable film causes such regions to become more tensile in stress compared to the unexposed areas of the stress-tunable film.

[0079] In some embodiments, stress changes may occur in one or more first regions of the stress-tunable film upon exposure to an elevated temperature. Without any theoretical limitations, the elevated temperature may cause the removal of hydrogen from the stress-tunable film, resulting in a reduction in volume within the stress-tunable film. In some embodiments, the elevated temperature may be between about 200°C and about 800°C, or between about 300°C and about 700°C. One or more heating elements in the process chamber or substrate support may control the substrate temperature. The one or more heating elements may control the temperature in zones or regions independently, allowing elevated temperatures to be applied to certain areas of the stress-tunable film. Using one or more heating elements, stress changes may be introduced in a targeted manner in one or more first regions and / or one or more second regions of the stress-tunable film. In some cases, a combination of selective UV exposure and target temperature control may be used to locally modulate the stress in the stress-tunable film.

[0080] The degree of localized stress modulation in one or more first regions depends on the processing conditions during UV exposure and / or thermal exposure. In some embodiments, the degree of localized stress modulation in one or more first regions depends on the duration of UV exposure, substrate temperature, intensity of UV radiation, and / or wavelength of UV radiation. However, those skilled in the art will understand that other conditions during UV exposure and / or thermal exposure can be controlled to affect the degree of localized stress modulation. Nevertheless, by modulating one or more of the following: (1) the duration of UV exposure, (2) the substrate temperature during UV exposure, (3) the intensity of UV exposure, or (4) the wavelength of UV exposure, the amount of stress change induced in the exposed region relative to the unexposed region will be altered. For example, a longer UV exposure time results in a higher stress value, a higher substrate temperature results in a higher stress value, and a higher UV intensity results in a higher stress value. It will be understood that a longer UV exposure time, a higher substrate temperature, and a higher intensity may have certain limits in controlling the stress value. The aforementioned UV exposure conditions can be finely modulated to achieve specific levels of localized stress modulation in one or more first regions. The UV light source can be configured to control the UV exposure time (i.e., dose), UV exposure intensity, and UV exposure wavelength. The substrate support (i.e., stage) can be configured to control the substrate temperature.

[0081] In some embodiments, the UV exposure time is between about 0.5 minutes and about 120 minutes, between about 1 minute and about 60 minutes, or between about 2 minutes and about 30 minutes. The UV exposure time or period is sufficient to observe the desired stress change. In some embodiments, the temperature during UV exposure is between about 100°C and about 700°C, between about 150°C and about 550°C, or between about 200°C and about 500°C. The temperature range may be limited by thermal budget constraints, meaning that the substrate temperature during UV processing is affected by the devices and films on the semiconductor substrate. For example, the use of a nickel silicon silicide (NiSi) layer constrains the substrate temperature to less than 400°C, while the use of a nickel platinum silicon silicide (NiPtSi) layer constrains the substrate temperature to less than 480°C. In some embodiments, the intensity of UV exposure is between about 1 μW / cm² and about 10 W / cm², between about 10 μW / cm² and about 5 W / cm², or between about 50 μW / cm² and about 1 W / cm². The intensity of UV radiation provides sufficient energy to break certain bonds (e.g., Si-H and NH bonds) in the stress-tunable film.

[0082] In some embodiments, one or more first regions of the stress-tunable film may undergo stress variations equal to or greater than about 20%, equal to or greater than about 30%, equal to or greater than about 40%, or equal to or greater than about 50%. One or more first regions of the stress-tunable film may become more compressed or more stretched compared to one or more second regions of the stress-tunable film. It will be understood that the degree of stress modulation in one or more first regions may depend on the UV and heat treatment conditions. Processing conditions such as exposure time, substrate temperature, UV light intensity, and UV light wavelength can be controlled to vary the localized stress modulation.

[0083] For example, a silicon carbonitride film can be deposited on a semiconductor substrate by PECVD. The silicon carbonitride film can have a deposition compressive stress value of about 400 MPa (-400 MPa). As shown in Table 1 below, the first region of the silicon carbonitride film after selective UV exposure undergoes stress change to become tensile, such that the first region has a tensile stress value of about 400 MPa (+400 MPa). The second region of the silicon carbonitride film remains at a compressive stress value of about 400 MPa (-400 MPa). In another example, a silicon nitride film can be deposited on a semiconductor substrate by PECVD. The silicon nitride film can have a deposition tensile stress value of about 700 MPa (+700 MPa). As shown in Table 1 below, the first region of the silicon nitride film after selective UV exposure undergoes stress change to become more stretched, resulting in a tensile stress value of approximately 1600 MPa (+1600 MPa) in the first region. Membrane type Sedimentary stress Stress in the first zone after UV curing Stress in the second zone after UV curing Silicon carbonitride -400 MPa +400 MPa -400 MPa Silicon nitride +700 MPa +1600 MPa +700 MPa [Table 1]

[0084] In some embodiments, the quartz window is further patterned to have one or more transition regions between one or more UV-transparent regions and one or more UV-opaque regions. The one or more transition regions may be translucent to UV light. While UV light may selectively pass through the one or more UV-transparent regions, it may partially pass through the one or more transition regions. For example, the one or more transition regions may have UV light transmittance between about 10% and about 90%, between about 20% and about 80%, or between about 25% and about 75%. By reducing the transmission of UV light in the one or more transition regions where an interface can be laid between the UV-transparent and UV-opaque regions, the corresponding areas of the stress-tunable film exposed to reduced UV light transmission will experience a reduced amount of stress variation. This prevents abrupt changes in stress between one or more first regions and one or more second regions of the stress-tunable film.

[0085] In some embodiments, one or more transition regions may include a translucent material. In some embodiments where the UV-opaque region includes a metallic coating, one or more transition regions may include a metallic layer with a relatively small thickness. For example, one or more transition regions may include a metallic layer with a thickness of less than about 100 nm. In some embodiments, one or more transition regions include a grid pattern or mesh of UV-transparent and UV-opaque materials.

[0086] The disclosed embodiments can be performed in any suitable device or tool. The device or tool may include one or more process stations. Exemplary process stations and tools that may be used in some embodiments are described below.

[0087] FIG9 illustrates a schematic diagram of an exemplary apparatus for UV curing of stress-tunable films according to certain embodiments. Apparatus 901 is suitable for applications involving broadband UV sources. Apparatus 901 includes multiple curing stations 903 and 905, each accommodating substrates 913 and 915. Substrates 913 and 915 are positioned above pedestals 923 and 925. A gap 904 exists between the substrates and the pedestals. The substrates can be supported above the pedestals by means of attachments such as pins or by floating on gas. Parabolic or planar cold mirrors 953 and 955 are positioned above broadband UV source assemblies 933 and 935. UV light from luminaire assemblies 933 and 935 passes through windows 943 and 945. 943 and 945 can be patterned with metallic coatings, ceramic caps, metal caps, or other components to provide selective UV exposure to certain areas of substrates 913 and 915. In alternative embodiments, substrates 913 and 915 can be supported by pedestals 923 and 925, respectively. In such embodiments, the luminaire may or may not be equipped with a cold mirror. By ensuring full contact between the substrate and the pedestal, the substrate temperature can be maintained by using a heat-conducting gas at a sufficient pressure for heat transfer, such as helium or a mixture of helium and argon, with the sufficient pressure typically between about 20 and about 760 Torr, or between about 100 and about 600 Torr.

[0088] In operation, the substrate enters a chamber at station 903 where a first UV curing operation is performed. A window 943, which is pre-patterned, is provided between the substrate 913 and the UV source group 933. The stage temperature at station 903 is set to a first temperature, for example, between about 200°C and about 500°C, and the UV lamp above station 903 is set to a first intensity, for example, 100% of its maximum intensity, and a first wavelength of about 200 to 800 nm. In some embodiments, after sufficient curing time in station 903, the substrate 913 can be transferred to station 905 for further curing or removed from the device 901. A second window 945 may be provided between the substrate 915 and the UV source group 935. The stage temperature at station 905 is set to a second temperature, which may be the same as or different from that of the first station, and the UV intensity is set to a second intensity, for example, 90% of its maximum intensity. Additional stations may be used for additional UV curing under different conditions.

[0089] In order to irradiate a substrate with different wavelengths or wavelength ranges when using a broadband UV source that generates broadband radiation, optical components can be used in the radiation source to modulate a portion of the broadband spectrum reaching the substrate. For example, a reflector, a filter, or a combination of both can be used to subtract a portion of the spectrum from the radiation. Upon reaching the filter, the light can be reflected, absorbed into the filter material, or transmitted.

[0090] Long-pass filters provide sharp cutoff below a specific wavelength. They are useful for isolating specific regions of the spectrum. Long-pass filters are used to transmit or pass a range of wavelengths and to block or reflect other wavelengths on the shorter wavelength side of the passband. Long-wavelength radiation is transmitted while short-wavelength radiation is reflected. The region with high transmittance is called the passband, and the region with high reflectance is called the blocking or reflection band. The attenuation region separates the passband from the reflection band. The complexity of a long-pass filter depends primarily on the steepness of the transition region and also on the ripple specifications in the passband. At relatively high incident angles, polarization-dependent losses may occur. Long-pass filters are constructed from a hard, durable surface material covered with a dielectric coating. They are designed to withstand normal cleaning and handling.

[0091] Another type of filter is the UV cutoff filter. These filters do not allow UV transmission below a set value of, for example, 280 nm. These filters operate by absorbing wavelengths below the cutoff value. This helps to optimize the desired curing effect.

[0092] Another type of optical filter that can be used to select a wavelength range is the bandpass filter. Optical bandpass filters are designed to transmit a specific wavelength band. They are composed of many thin layers of dielectric material with different refractive indices to produce constructive and destructive interference in the transmitted light. In this way, optical bandpass filters can be designed to transmit only a specific wavelength band. The range limitation usually depends on the interference filter lens and the composition of the thin-film filter material. Incident light is passed through two coated reflective surfaces. The distance between the reflective coatings determines which wavelengths will be destructively interfered with and which wavelengths will be allowed to pass through the coated surfaces. If the reflected beams are in phase, the light will pass through both reflective surfaces. However, if the wavelengths are out of phase, destructive interference will block most of the reflection and almost no wavelengths will be allowed to pass through. In this way, interference filters can attenuate the intensity of transmitted light with wavelengths higher or lower than the desired range.

[0093] In addition to changing the wavelength by altering the radiation reaching the substrate, the radiation wavelength can also be controlled by modifying the properties of the light generator. Broadband UV sources can generate a wide spectrum of radiation from UV to infrared, but other light generators can be used to emit a smaller spectrum or increase the intensity of a narrower spectrum. Other light generators can be mercury vapor lamps, doped mercury vapor lamps, electrode lamps, excimer lamps, excimer lasers, pulsed xenon lamps, and doped xenon lamps. For example, an excimer laser emits radiation at a single wavelength. When dopants are added to mercury vapor and xenon lamps, the radiation in a narrow wavelength band can be made stronger. Common dopants are iron, nickel, cobalt, tin, zinc, indium, gallium, thallium, antimony, bismuth, or combinations of these dopants. For example, mercury vapor lamps doped with indium emit strongly in the visible spectrum at approximately 450 nm; iron at 360 nm; and gallium at 320 nm. The radiation wavelength can also be controlled by changing the lamp's filling pressure. For example, high-pressure mercury vapor lamps can emit wavelengths from 250 nm to 440 nm, with particularly strong emission at 310 nm to 350 nm. Low-pressure mercury vapor lamps emit at shorter wavelengths.

[0094] In addition to changing the properties of the light generator and the use of filters, reflectors that preferentially transmit one or more segments of the lamp's spectral output can be used. A common reflector is a cold mirror that allows infrared radiation to pass through but reflects other light. Other reflectors that preferentially reflect a spectral band of light can also be used. Thus, the substrate can be exposed to radiation of different wavelengths at different stations. Of course, the radiation wavelengths at the same station can be the same.

[0095] In Figure 9, pedestals 923 and 925 are stationary. The indicator 911 lifts and moves each substrate from one pedestal to another between each exposure cycle. The indicator 911 includes an indicator plate 921 attached to an actuation mechanism 931 having rotational and axial movement. An upward axial movement is applied to the indicator plate 921 to pick up the substrate from each pedestal. A rotational movement is used to advance the substrate from one station to another. The actuation mechanism then applies a downward axial movement to the indicator plate to place the substrate downwards onto the station.

[0096] Stands 923 and 925 are electrically heated and maintained at the required process temperature. Stands 923 and 925 may also be equipped with cooling lines for precise substrate temperature control. In alternative embodiments, a large heater block can be used to support the substrate instead of individual stands. A heat-conducting gas, such as helium, is used to achieve good thermal coupling between the stands and the substrate. In some embodiments, a cast stand with a coaxial heat exchanger can be used.

[0097] Figure 9 shows only an example of suitable equipment, and other equipment designed for use in other methods involved in previous and / or subsequent processes may be used. For example, in another embodiment using a broadband UV source, the substrate support is a rotary tray. Unlike a stationary pedestal substrate support, the substrate does not move relative to the rotary tray. After the substrate is positioned on the rotary tray, the tray rotates to expose the substrate to light from the UV lamp assembly if necessary. The rotary tray remains stationary during the exposure cycle. After the exposure cycle, the rotary tray rotates to advance each substrate for exposure to the next set of lamps. Heating and cooling elements may be embedded within the rotating rotary tray. Alternatively, the rotary tray may contact or hold the substrate such that the substrate is suspended above the heater plate.

[0098] In some embodiments, the substrate is exposed to UV radiation from a focused lamp rather than a floodlight. Unlike broadband source embodiments in which the substrate remains stationary during exposure (as in FIG. 9), there is relative movement between the substrate and the light source during exposure to the focused light when the substrate is scanned. In other embodiments, the substrate may be rotated relative to the light source to average out any intensity differences across the substrate.

[0099] FIG10 illustrates a schematic diagram of an exemplary process tool used to perform localized stress modulation operations according to certain embodiments. In FIG10, a multi-station process tool 1000 may include an inbound load lock 1002 and an outbound load lock 1004, either or both of which may include a plasma source and / or a UV source. A robot 1006 under atmospheric pressure is configured to remove a wafer from a cassette loaded into the inbound load lock 1002 via an atmospheric port (not shown) through a pod 1008. The robot 1006 places the wafer or substrate on a pedestal 1012 in the inbound load lock 1002, closes the atmospheric port, and evacuates the load lock. In cases where the inbound load lock 1002 includes a remote plasma source, the wafer may be exposed to remote plasma processing in the load lock before being introduced into one of the processing chambers, such as processing chamber 1014a. When the inbound loading lock 1002 includes a UV source, the wafer can be exposed to UV treatment in the loading lock before being introduced into one of the processing chambers, such as processing chamber 1014a. Furthermore, the wafer can also be heated in the inbound loading lock 1002 to, for example, remove moisture and adsorbed gases. Then, the chamber transfer port 1016 leading to processing chamber 1014a is opened, and another robot 1026 places the wafer into a reactor on a pedestal 1018 of the first station (labeled 1) of processing chamber 1014a, thus displaying it being processed in the reactor. Although the embodiment depicted in FIG. 10 includes a loading lock, it will be understood that in some embodiments, direct entry of the wafer into the process station may be provided.

[0100] For example, each of the depicted processing chambers, such as processing chamber 1014a, includes four process stations. Each station has a heating platform and a gas line inlet. It will be understood that in some embodiments, each process station may have different or multiple purposes. For example, one process station may be used to deposit tensile or compressive material as part of a warp compensation layer by means of a suitable deposition technique such as PECVD. Another process station may be used to process tensile or compressive material by means of selective UV curing. In some embodiments, deposition and UV treatment may occur in the same process station. Although the depicted processing chamber 1014a includes four stations, it will be understood that a processing chamber according to some of the disclosed embodiments may have any suitable number of stations. For example, in some embodiments, a processing chamber may have four or more stations, while in other embodiments, a processing chamber may have three or fewer stations. Furthermore, although the depicted processing tool 1000 has three processing chambers 1014a, 1014b, and 1014c, it will be understood that a processing tool according to some of the disclosed embodiments may have any suitable number of processing chambers.

[0101] Figure 10 depicts a wafer handling system 1090b for transferring wafers in a processing chamber 1014a. In some embodiments, the wafer handling system 1090b can transfer wafers between multiple process stations and between process stations and load locks. It will be understood that any suitable wafer handling system can be employed. Non-limiting examples include wafer rotary racks and wafer handling robots. Figure 10 also depicts an embodiment of a system controller 1050 for controlling process conditions and the hardware state of the process tool 1000. The system controller 1050 may include one or more memory devices 1056, one or more mass storage devices 1054, and one or more processors 1052. The processor 1052 may include a CPU or computer, analog and / or digital input / output connections, stepper motor control boards, etc.

[0102] In some embodiments, system controller 1050 controls all activities of process tool 1000. System controller 1050 executes system control software 1058, which is stored in mass storage device 1054, loaded into memory device 1056, and executed on processor 1052. Alternatively, the control logic may be hard-coded in controller 1050. Application-specific integrated circuits, programmable logic devices (e.g., field-programmable gate arrays, or FPGAs) and similar devices may be used for these purposes. In the following discussion, wherever "software" or "coding" is used, equivalent hard-coded logic can be used instead. System control software 1058 may include instructions for controlling the following: wafer transfer into and out of the process chamber, wafer rotation within the process chamber, wafer alignment with a spray head or quartz window in the process chamber, time for gas to exit a specific area of ​​the spray head, gas mixing, gas flow rate exiting a specific area of ​​the spray head, chamber and / or station pressure, backflow pressure exiting a specific area of ​​the spray head, chamber and / or reactor temperature, wafer temperature, bias power, target power level, RF power level and type (e.g., single-frequency or dual-frequency or high-frequency or low-frequency), stage, chuck and / or sensor position, UV wavelength, UV dose, UV intensity, and other parameters for specific processes performed by process tool 1000. System control software 1058 can be configured in any suitable manner. For example, various process tool component subroutines or control targets can be written to control the operation of process tool components used to perform various process tooling processes. The system control software 1058 can be coded in any suitable computer-readable programming language.

[0103] In some embodiments, the system control software 1058 may include input / output control (IOC) sequence instructions for controlling the aforementioned parameters. In some embodiments, other computer software and / or programs stored in a mass storage device 1054 and / or memory device 1056 associated with the system controller 1050 may be used. Examples of programs or program segments for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, electrostatic chuck power control programs, UV light control programs, and plasma control programs.

[0104] The substrate positioning program may include code for a process tool assembly used to load the substrate onto the stage 1018 and control the spacing between the substrate and other components of the process tool 1000. The UV light control program may include code for controlling UV light conditions (e.g., time, intensity, and wavelength as described herein). The pressure control program may include code for controlling pressure in the process station by adjusting, for example, a throttle valve in the exhaust system of the process station, airflow into the process station, gas pressure introduced to the back side of the wafer during adjustment operations, etc.

[0105] The heater control program may include coding for controlling the current supplied to the heating unit, which is used to heat the substrate for temperature control operations as described herein. Alternatively, the heater control program may control the delivery of a heat transfer gas (e.g., helium) to the substrate. The plasma control program may include coding for setting the RF power level applied to process electrodes in one or more process stations, according to embodiments herein. The pressure control program may include coding for maintaining pressure in the reaction chamber, according to embodiments herein.

[0106] In some embodiments, a user interface may be associated with the system controller 1050. The user interface may include a display screen, a graphical software display of device and / or process conditions, and a user input device, such as a pointer, keyboard, touch screen, microphone, etc.

[0107] In some embodiments, the parameters adjusted by the system controller 1050 may be related to process conditions. Non-limiting examples include the composition and flow rate of process gases, temperature, pressure, plasma conditions (e.g., RF bias power level), UV dose, UV intensity, UV wavelength, etc. These parameters may be provided to the user in the form of a recipe or input using a user interface.

[0108] Signals used for monitoring the process can be provided from various process tool sensors via analog and / or digital input connections of the system controller 1050. Signals used for controlling the process can be output to the analog and digital output connections of the process tool 1000. Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (e.g., manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms can be used with data from these sensors to maintain process conditions.

[0109] The system controller 1050 can provide programming instructions for implementing the above-described deposition process. The programming instructions can control various process parameters, such as UV dose, UV intensity, UV wavelength, pressure, temperature, etc. The instructions can control parameters to operate the UV treatment of the stress-adjustable film according to the various embodiments described herein.

[0110] The system controller 1050 will typically include one or more memory devices and one or more processors configured to execute instructions such that the device will perform the method according to the disclosed embodiments. Machine-readable media containing instructions for controlling process operations according to the disclosed embodiments may be coupled to the system controller 1050.

[0111] In some embodiments, the system controller 1050 is part of a system, which may be part of the above-described examples. Such a system may include semiconductor processing equipment, including: one or more processing tools, one or more chambers, one or more worktables for processing, and / or specific processing components (e.g., wafer pedestals, airflow systems, etc.). These systems may be integrated with electronic equipment for controlling the operation of the system before, during, and after the processing of a semiconductor wafer or substrate. The electronic equipment may be referred to as a "controller," and the controller may control various components or sub-components of the system or multiple systems. Depending on the processing conditions and / or the type of system, the system controller 1050 may be programmed to control any of the processes disclosed herein, including the delivery of process gases and / or inhibitor gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positioning and operation settings, wafer in / out tools, and other transfer tools and / or loading locks connected or interfaced with a specific system.

[0112] In general, the system controller 1050 can be defined as an electronic device having a plurality of integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, perform cleaning operations, perform endpoint measurements, and the like. The integrated circuits may include a chip in the form of firmware storing program instructions, digital signal processors (DSPs), a chip defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions transmitted to the system controller 1050 in the form of a plurality of individual settings (or program files), which define operational parameters for performing specific programming on, or for, a semiconductor wafer, or for the system. In some embodiments, the operational parameters may be part of a recipe defined by a process engineer to complete one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0113] In some embodiments, the system controller 1050 may be part of or coupled to a computer, the computer may be integrated with the system, coupled to the system, or network-connected to the system, or a combination thereof. For example, the system controller 1050 may be located in the "cloud" or may be all or part of the wafer fab's main computer system, allowing remote access to wafer processing. The computer may allow remote access to the system to monitor the current progress of manufacturing operations, view the history of past manufacturing operations, view trends or performance metrics from multiple manufacturing operations, change parameters of the current process, set processing steps to continue the current process, or initiate a new process. In some examples, the remote computer (e.g., a server) may use a network to provide process recipes to the system, the network may include a local area network or the Internet. The remote computer may include a user interface that allows the input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, system controller 1050 receives instructions in the form of data and specifies parameters for each processing step to be performed during one or more operations. It should be understood that these parameters may be specific to the type of process to be performed and the type of tool, and system controller 1050 is configured to interface with or control the tool. Therefore, as described above, system controller 1050 may be distributed, for example by including one or more distributed controllers networked together and operating for the same purpose, such as the process and control described herein. An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber communicating with one or more integrated circuits at a remote location (e.g., at the platform layer or as part of a remote computer), which together control the process on the chamber.

[0114] Numerous specific details have been set forth in the foregoing description to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be implemented without some or all of these specific details. In other respects, well-known process operations have not been described in detail in order not to unnecessarily obscure the disclosed embodiments. Although the disclosed embodiments have been described in conjunction with specific examples, it will be understood that they are not intended to be limiting.

[0115] Although the above embodiments have been described in some detail for clarity of understanding, it will be apparent that certain variations and modifications may be made within the scope of the appended claims. It should be noted that there are many alternative processes, systems, and apparatuses for implementing the embodiments of this application. Therefore, the embodiments of this application should be considered illustrative rather than restrictive, and these embodiments are not limited to the details given herein. [Simplified Explanation of the Diagram]

[0008] Figure 1 shows a perspective view of a warped semiconductor substrate, illustrating wafer warping in the x-axis and y-axis directions.

[0009] Figure 2 shows a top view of an exemplary system for mitigating wafer warping using partitioned masks of adjacent semiconductor substrates.

[0010] Figure 3 shows a top view schematic diagram of an exemplary system for mitigating wafer warping using a multi-inflatable spray head.

[0011] Figure 4A shows a schematic diagram of an exemplary apparatus for UV processing, the apparatus including a window positioned between a UV source and a semiconductor substrate.

[0012] Figure 4B shows a top view of the window that is transparent to UV radiation in Figure 4A.

[0013] Figure 5A shows a schematic diagram of an exemplary apparatus for UV processing, which, according to some embodiments, includes a patterned window positioned between a UV source and a semiconductor substrate.

[0014] FIG5B shows a cross-sectional view of the patterned window of FIG5A having a metallic coating according to certain embodiments.

[0015] FIG5C shows a cross-sectional view of the patterned window of FIG5A having a ceramic cover according to certain embodiments.

[0016] Figure 6A shows a top view of a patterned window having a UV transparent area and a UV opaque area according to certain embodiments.

[0017] Figure 6B shows a top view of a patterned window having a UV transparent area that occupies a larger surface area than the UV opaque area, according to some embodiments.

[0018] Figure 6C shows a top view of a patterned window having a UV transparent area, a UV opaque area, and a transition area that is semi-transparent to UV radiation, according to certain embodiments.

[0019] Figure 6D shows a top view of a patterned window having a UV transparent area, a UV opaque area, and a transition area made of a mesh according to certain embodiments.

[0020] Figure 7 shows a schematic diagram of an exemplary apparatus for UV back-side processing, the apparatus including a patterned window positioned between a UV source and a semiconductor substrate according to certain embodiments.

[0021] Figure 8 illustrates a flowchart of an exemplary method of selective UV exposure according to certain embodiments.

[0022] Figure 9 illustrates a schematic diagram of an exemplary apparatus for selective UV exposure of a stress-adjustable membrane according to certain embodiments.

[0023] Figure 10 illustrates a schematic diagram of an exemplary process tool used to perform selective UV exposure operations according to certain embodiments.

Claims

1. An apparatus for selective UV exposure, comprising: an ultraviolet (UV) light source; a process chamber including: a substrate support configured to support a semiconductor substrate, wherein the semiconductor substrate includes a stress-tunable film; and one or more heating elements configured to control the temperature of the semiconductor substrate; and a window positioned between the substrate support and the UV light source, wherein the window is patterned to have one or more UV-transparent regions for selectively exposing one or more first regions of the stress-tunable film to UV light and one or more UV-opaque regions for selectively blocking UV light from one or more second regions of the stress-tunable film.

2. The device of claim 1, wherein the window is patterned to have a metallic coating corresponding to the one or more UV opaque areas.

3. The device as claimed in claim 2, wherein the metal coating comprises silver, aluminum, or a combination thereof.

4. The device of claim 1, wherein the window is patterned as having a ceramic cover disposed on the window and corresponding to the one or more UV opaque areas.

5. The device as claimed in claim 4, wherein the ceramic cover comprises aluminum nitride or aluminum oxide.

6. The device of any one of claims 1 to 5, wherein the window is patterned as having a metal cover disposed on the window and corresponding to the one or more UV opaque areas.

7. The device of any one of claims 1 to 5, wherein the window is further patterned to have one or more transition areas having an interface laid between the one or more UV transparent areas and the one or more UV opaque areas, wherein the one or more transition areas are translucent to UV light or contain a grid pattern of UV transparent and UV opaque materials.

8. The device of claim 7, wherein the one or more transition regions comprise a metal layer having a thickness of less than about 100 nm.

9. The device of claim 7, wherein the one or more transition regions are configured to provide a more gradual stress change at the interface between the one or more first regions of the stress-adjustable membrane and the one or more second regions of the stress-adjustable membrane.

10. The apparatus of any one of claims 1 to 5, wherein the one or more UV transparent regions are configured to induce a stress shift equal to or greater than about 50% in the one or more first regions of the stress-tunable film.

11. The apparatus of any one of claims 1 to 5, wherein the UV light source is configured to direct UV light to a back side of the semiconductor substrate, wherein the stress-tunable film is formed on the back side of the semiconductor substrate.

12. The apparatus of any one of claims 1 to 5, wherein the UV light source is configured to direct UV light to a front side of the semiconductor substrate, wherein the stress-tunable film is formed on the front side of the semiconductor substrate.

13. The apparatus of any one of claims 1 to 5 further comprises: a controller configured to have instructions for performing the following operations: providing the semiconductor substrate in the process chamber; and selectively exposing the one or more first regions of the stress-tunable film to UV light using the patterned window to locally modulate the stress on the stress-tunable film.

14. The apparatus of any one of claims 1 to 5, wherein the stress-adjustable film comprises silicon nitride, silicon oxide, silicon oxynitride, or silicon carbonitride, and wherein the window comprises quartz.

15. A method of selective UV exposure, comprising: providing a semiconductor substrate on a substrate support in a process chamber, wherein the semiconductor substrate includes a stress-tunable film, wherein a quartz window is positioned between the process chamber and an ultraviolet (UV) light source, wherein the quartz window is patterned to have one or more UV-transparent regions and one or more UV-opaque regions; and selectively exposing one or more first regions of the stress-tunable film to UV light through the one or more UV-transparent regions of the quartz window, and selectively blocking UV light for one or more second regions of the stress-tunable film through the one or more UV-opaque regions of the quartz window.

16. The method of selective UV exposure as claimed in claim 15, wherein selectively exposing the one or more first regions of the stress-tunable film includes locally modulating the stress in the one or more first regions of the stress-tunable film.

17. The selective UV exposure method of claim 15, wherein the quartz window is patterned to have a metallic coating corresponding to the one or more UV-opaque areas.

18. A method of selective UV exposure as claimed in any of claims 15 to 17, wherein the quartz window is patterned to have a ceramic cover or a metal cover disposed on the quartz window and corresponding to the one or more UV-opaque areas.

19. A method of selective UV exposure as claimed in any of claims 15 to 17, wherein the quartz window is further patterned to have one or more transition regions between the one or more UV-transparent regions and the one or more UV-opaque regions, wherein the one or more transition regions are translucent to UV light.

20. The method of selective UV exposure as claimed in claim 19, wherein the one or more transition regions comprise a metal layer having a thickness of less than about 100 nm.