Package structure

Abstract

A packaging structure includes a substrate, a transistor assembly, and a packaging layer. The transistor assembly is formed on the substrate and includes a first transistor, a capacitor, a resistor, a first Zener diode, and a second Zener diode. The first transistor includes a gate, a drain, and a source. The capacitor and the resistor are electrically connected to the gate. The first Zener diode includes a first anode and a first cathode electrically connected to the gate. The second Zener diode includes a second anode electrically connected to the first anode and a second cathode electrically connected to the source. The packaging layer encapsulates the transistor assembly. The packaging structure includes a gate terminal, a drain terminal, and a source terminal for external interconnection.

Description

Packaging structure This disclosure relates to a packaging structure, and more particularly to a packaging structure that integrates a high electron mobility transistor (HEMT) and its protection circuitry. The gate-source voltage across a typical enhancement-mode high electron mobility transistor (E-Mode HEMT) (e.g., an enhancement-mode gallium nitride transistor) can withstand a maximum voltage of approximately -10V to 7V. However, the drive voltage output by a typical power conversion control circuit is approximately 0V to 20V. When the highest external drive voltage is applied directly to the E-Mode HEMT, it can easily damage the transistor. Therefore, a protection circuit is often placed between the E-Mode HEMT and the drive voltage to ensure its proper operation. However, additional protection circuitry requires additional circuit area and increases the complexity of the overall circuit design. Therefore, it is necessary to optimize high electron mobility transistors and their protection circuitry. This disclosure proposes a package structure that integrates a transistor and its protection circuitry. By integrating the transistor and its protection circuitry into the same package, the distance between the gate of the first transistor and the resistor, capacitor, and Zener diode is shortened, thereby reducing parasitic inductance and improving the transistor's robustness. Furthermore, the package structure that integrates the transistor and its protection circuitry disclosed in this disclosure can reduce the overall circuit area required on the circuit board, thereby increasing heat dissipation and reducing the defect rate in surface mount technology (SMT) processes, and may even reduce the complexity of circuit design. In view of this, this disclosure proposes a packaging structure including a substrate, a modular transistor, and a packaging layer. The modular transistor is formed on the substrate and includes a first transistor, a capacitor, a resistor, a first Zener diode, and a second Zener diode. The first transistor includes a gate, a drain, and a source. The capacitor and the resistor are electrically connected to the gate. The first Zener diode includes a first anode and a first cathode, wherein the first cathode is electrically connected to the gate. The second Zener diode includes a second anode and a second cathode, wherein the second anode is electrically connected to the first anode, and the second cathode is electrically connected to the source. The packaging layer encapsulates the modular transistor. The packaging structure includes a gate terminal, a drain terminal, and a source terminal for external interconnection. According to one embodiment of the present disclosure, the first transistor system is an enhanced high electron mobility transistor. According to one embodiment of this disclosure, the packaging structure further includes a first carrier plate, a second carrier plate, and a third carrier plate. The first carrier plate is formed on a substrate, wherein the second cathode and the source are electrically connected to each other via the first carrier plate. The second carrier plate is formed on the substrate, wherein the drain is electrically connected to the second carrier plate. The third carrier plate is formed on the substrate, wherein the gate is electrically connected to the third carrier plate. According to one embodiment of this disclosure, the packaging structure further includes a fourth carrier plate. The fourth carrier plate is formed on the substrate, wherein the gate and the first cathode are electrically connected to each other via the fourth carrier plate, and the capacitor and the resistor are electrically connected to the third carrier plate and the fourth carrier plate, respectively. According to one embodiment of the present disclosure, a first transistor and a second Zener diode are disposed on a first carrier plate, the first Zener diode is disposed on a fourth carrier plate, and a capacitor and a resistor are disposed between a third carrier plate and a fourth carrier plate. According to one embodiment of the present disclosure, the first carrier plate, the second carrier plate, the third carrier plate and the fourth carrier plate are each a conductive carrier plate, the gate is adjacent to the fourth carrier plate, the gate is electrically connected to the fourth carrier plate by a first metal wire, the first Zener diode is electrically connected to the second Zener diode by a second metal wire, and a capacitor and a resistor are respectively connected between the third carrier plate and the fourth carrier plate. According to one embodiment of this disclosure, the packaging structure further includes a first base plate, a second base plate, a third base plate, and a fourth base plate. The first base plate is disposed below the substrate and the first carrier plate. The second base plate is disposed below the substrate and the second carrier plate. The third base plate is disposed below the substrate and the third carrier plate. The fourth base plate is disposed below the substrate, the first carrier plate, and the first transistor. The first base plate, the second base plate, and the third base plate are electrically connected to the first carrier plate, the second carrier plate, and the third carrier plate, respectively, via individual connectors. According to one embodiment of this disclosure, the source end includes a first base plate, the drain end includes a second base plate, and the gate end includes a third base plate. According to one embodiment of the present disclosure, the first carrier plate is connected to the fourth base plate via a connector. According to one embodiment of the present disclosure, the substrate includes a plurality of through holes passing through the substrate, and connectors are respectively formed in the through holes. According to one embodiment of the present disclosure, the substrate includes a plurality of side surfaces, and a connector is formed on any one of the side surfaces. According to one embodiment of this disclosure, the packaging structure further includes a fifth carrier plate and a fifth base plate. The fifth carrier plate is formed on the substrate, wherein the fifth carrier plate and the first carrier plate are disposed separately on the substrate. The fifth base plate is disposed below the substrate and the fifth carrier plate. The fifth carrier plate is electrically connected to the fifth base plate via another connector. According to one embodiment of this disclosure, the third carrier plate includes a notch and / or the fourth carrier plate includes a notch. According to one embodiment of this disclosure, the notch of the third carrier plate is T-shaped and / or the notch of the fourth carrier plate is T-shaped. According to one embodiment of this disclosure, the packaging structure further includes an insulating plate, a sixth carrier plate, and a seventh carrier plate. The insulating plate is disposed on a substrate. The sixth carrier plate is disposed on the insulating plate. The seventh carrier plate is disposed on the insulating plate, wherein the sixth carrier plate is electrically connected to the gate terminal. The source and the second cathode are electrically connected to the substrate, and the capacitor and the resistor are both electrically connected to the sixth carrier plate and the seventh carrier plate. According to one embodiment of the present disclosure, a first Zener diode is disposed on a sixth carrier plate, and a capacitor and a resistor are disposed between the sixth carrier plate and a seventh carrier plate. According to one embodiment of this disclosure, the gate of the first transistor is adjacent to the sixth carrier plate, and the gate is connected to the sixth carrier plate by a metal wire. The following description is an embodiment of this disclosure. Its purpose is to illustrate the general principles of this disclosure and should not be regarded as a limitation thereof. The scope of this disclosure shall be defined by the claims. It is worth noting that the following disclosure provides multiple embodiments or examples for practicing different features of this disclosure. The specific element examples and arrangements described below are only for briefly illustrating the spirit of this disclosure and are not intended to limit its scope. Furthermore, the same element symbols or words may be repeated in multiple examples in the following description. However, the purpose of repetition is only to provide a simplified and clear explanation and is not intended to limit the relationship between the various embodiments and / or configurations discussed below. Moreover, descriptions in the following description of a feature being connected to, coupled to, and / or formed on another feature may actually encompass multiple different embodiments, including direct contact between the features, or additional features formed between the features, such that the features are not in direct contact. Furthermore, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the arrangement of the diagram is flipped so that it is upside down, the element depicted on the "lower" side will become the element on the "higher" side. It is understood that although terms such as "first," "second," and "third" may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or portions. Therefore, a first element, component, region, layer, and / or portion discussed below may be referred to as a second element, component, region, layer, and / or portion without departing from the teachings of some embodiments disclosed herein. This disclosure includes embodiments that can be understood in conjunction with the accompanying drawings, which are considered part of the description of these embodiments. It should be understood that the drawings are not drawn to scale with actual devices and components. The shape and thickness of the embodiments may be exaggerated in the drawings to clearly show the features of the disclosed embodiments. Furthermore, the structures and devices in the drawings are shown schematically to clearly demonstrate the features of the disclosed embodiments. Here, the terms "about," "approximately," and "roughly" generally indicate within 20%, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%, of a given value or range. The quantities given here are approximate quantities; that is, even without specific mention of "about," "approximately," or "roughly," the meaning of "about," "approximately," or "roughly" may still be implied. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure. In some embodiments disclosed herein, terms such as "connection" and "interconnection" used to refer to joining or linking, unless otherwise defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, with other structures disposed between them. Furthermore, these terms regarding joining or linking may also include situations where both structures are movable or both structures are fixed. In a diagram, similar elements and / or features may have the same element symbol. Various elements of the same type can be distinguished by adding letters or numbers after the element symbol to differentiate similar elements and / or similar features. Figure 1 shows a circuit diagram of an integrated circuit according to one embodiment of the present disclosure. As shown in Figure 1, the integrated circuit 100 includes a control circuit 110, a first transistor T1, a resistor R, a capacitor C, a first Zener diode ZD1, and a second Zener diode ZD2. As shown in Figure 1, the control circuit 110 is used to drive node ND and generate a drive signal SD. The first transistor T1 includes a gate G, a drain D, and a source S. According to some embodiments of this disclosure, the first transistor T1 is a high electron mobility transistor. According to one embodiment of this disclosure, the first transistor T1 may be an enhancement-mode high electron mobility transistor. According to another embodiment of this disclosure, the first transistor T1 may be an enhancement-mode gallium nitride transistor. A resistor R is electrically connected between the driving node ND and the gate G of the first transistor T1, and a capacitor C is electrically connected between the driving node ND and the gate G of the first transistor T1. The first Zener diode ZD1 includes a first anode NA1 and a first cathode NC1, wherein the first cathode NC1 is electrically connected to the gate G of the first transistor T1. The second Zener diode ZD2 includes a second anode NA2 and a second cathode NC2, wherein the second anode NA2 is electrically connected to the first anode NA1, and the second cathode NC2 is electrically connected to the source S of the first transistor T1. According to some embodiments disclosed herein, when the driving voltage of the drive signal SD exceeds the voltage range for normal operation of the first transistor T1, the resistor R, capacitor C, first Zener diode ZD1, and second Zener diode ZD2 are used to protect the first transistor T1 from burnout and maintain its normal operation. In other words, the resistor R, capacitor C, first Zener diode ZD1, and second Zener diode ZD2 can serve as a protection circuit for the first transistor T1. As shown in Figure 1, a first transistor T1, a resistor R, a capacitor C, a first Zener diode ZD1, and a second Zener diode ZD2 are packaged together to form a modular transistor TINT, wherein the modular transistor TINT includes a gate terminal TG, a drain terminal TD, and a source terminal TS. According to one embodiment of this disclosure, in the integrated circuit 100, the drive node ND is electrically connected to the gate terminal TG of the modular transistor TINT, the drain terminal D of the first transistor T1 is electrically connected to the drain terminal TD of the modular transistor TINT, and the source terminal S of the first transistor T1 is electrically connected to the source terminal TS of the modular transistor TINT. The packaging structure of the modular transistor TINT will be described in detail below. According to other embodiments of this disclosure, in the integrated circuit 100, other circuit elements, such as resistors and diodes, may be included between the drive node ND and the gate terminal TG of the integrated transistor TINT, to further protect the first transistor T1 from damage. Here, the resistor R, capacitor C, first Zener diode ZD1 and second Zener diode ZD2 are used as a protection circuit for the first transistor T1 for illustration and explanation only, and are not limited to this in any way. Figure 2A shows a top view of a package structure according to one embodiment of the present disclosure, wherein the package structure 200 corresponds to the integrated transistor TINT in Figure 1. According to one embodiment of the present disclosure, the package structure 200 may be a surface mount device (SMD) package structure. As shown in Figure 2A, the package structure 200 includes a substrate SUB, a first carrier CP1, a second carrier CP2, a third carrier CP3, and a fourth carrier CP4. According to some embodiments of the present disclosure, the substrate SUB includes an insulating material. According to one embodiment of the present disclosure, the substrate SUB may be a ceramic substrate, wherein the ceramic substrate is an insulating material. According to one embodiment of the present disclosure, the insulating material of the ceramic substrate may be made of alumina or aluminum nitride (AlN). The first carrier plate CP1 is formed on the substrate SUB, and the first transistor T1 and the second Zener diode ZD2 in Figure 1 are placed on the first carrier plate CP1. The second cathode NC2 of the second Zener diode ZD2 (not shown in Figure 2A) is electrically connected to the first carrier plate CP1 by direct or indirect contact. According to one embodiment of the present disclosure, the second cathode NC2 is fixed to the first carrier plate CP1 and electrically connected to it by solder. According to one embodiment of the present disclosure, the structure of the first transistor T1 includes an insulating substrate, a semiconductor epitaxial stack is located on the insulating substrate, and a gate G, a drain D, and a source S are located on the semiconductor epitaxial stack. The semiconductor epitaxial stack includes a channel layer and a barrier layer formed thereon. A two-dimensional electron gas (2DEG) is present in the channel layer near the interface between it and the barrier layer as a current conduction channel when the transistor is turned on (not shown in Figure 2A). The semiconductor epitaxial stack of the first transistor T1 may further include a nucleation layer formed on an insulating substrate and a buffer layer formed on the nucleation layer, with a channel layer and a barrier layer formed on the buffer layer. In one embodiment, the semiconductor epitaxial stack of the first transistor T1 may further include a capping layer formed on the barrier layer. In one embodiment, the first transistor T1 is a high electron mobility transistor. In one embodiment, the first transistor T1 is an enhancement-mode high electron mobility transistor. The enhancement-mode high electron mobility transistor may have a p-type doped semiconductor layer disposed between the gate and the barrier layer, whereby the p-type doped semiconductor layer depletes the two-dimensional electron gas (2DEG) in the channel layer below the gate, allowing the transistor to be turned off without a bias voltage applied to the gate. The p-type semiconductor layer includes a p-type III-V group semiconductor layer or a p-type II-VI group semiconductor layer, and the p-type III-V group semiconductor material includes p-type doped gallium nitride (p-GaN) and p-type doped boron nitride (p-BN). p-type II-VI semiconductors include p-type doped zinc oxide (p-ZnO). In another embodiment, the enhancement-mode high electron mobility transistor (EMHMT) may be a gate-recess E-mode HEMT, wherein the barrier layer below the gate has a recess, and the gate is filled into the recess. In one embodiment, the materials of the nucleation layer, buffer layer, channel layer, and barrier layer in the first transistor T1 include III-V compound semiconductor materials, such as III-nitride semiconductor materials. III-nitrides include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), or combinations thereof. The band gap of the barrier layer is larger than the band gap of the channel layer. In one embodiment, the capping layer may include a III-V compound semiconductor material, such as gallium nitride (GaN), or a dielectric material, such as silicon nitride. Since the gate (G), drain (D), and source (S) are all located on the same side of the first transistor T1, the source (S) of the first transistor T1 is electrically connected to the first substrate CP1 through a plurality of first bonding wires (BW1) of the package structure 200. According to one embodiment of this disclosure, the source (S) of the first transistor T1 is electrically connected to the second Zener diode ZD2 through the first substrate CP1 and the second cathode NC2. The second substrate CP2 is formed on the substrate SUB, wherein the drain (D) of the first transistor T1 is electrically connected to the second substrate CP2 through a plurality of second bonding wires (BW2) of the package structure 200. The third carrier plate CP3 and the fourth carrier plate CP4 are formed on the substrate SUB, and the first carrier plate CP1, the third carrier plate CP3, and the fourth carrier plate CP4 are adjacent to each other. A first Zener diode ZD1 is disposed on the fourth carrier plate CP4, and the first cathode NC1 (not shown in Figure 2A) of the first Zener diode ZD1 is electrically connected to the fourth carrier plate CP4 through direct or indirect contact. According to one embodiment of this disclosure, the first cathode NC1 is fixed to the fourth carrier plate CP4 and electrically connected to it by solder. The gate G of the first transistor T1 is electrically connected to the fourth carrier plate CP4 via a third metal wire BW3, and then electrically connected to the first Zener diode ZD1 via the fourth carrier plate CP4 and the first cathode NC1. As shown in Figure 2A, the capacitor C and resistor R in Figure 1 are electrically connected between the third carrier plate CP3 and the fourth carrier plate CP4, respectively. The first anode NA1 of the first Zener diode ZD1 (not shown in Figure 2A) is electrically connected to the second anode NA2 of the second Zener diode ZD2 (not shown in Figure 2A) through the fourth metal wire BW4. According to one embodiment of this disclosure, the first carrier plate CP1, the second carrier plate CP2, the third carrier plate CP3, and the fourth carrier plate CP4 are all conductive plates. According to another embodiment of this disclosure, the first carrier plate CP1, the second carrier plate CP2, the third carrier plate CP3, and the fourth carrier plate CP4 are separately disposed on the substrate SUB. According to other embodiments of this disclosure, the encapsulation structure 200 further includes an encapsulation layer (not shown in Figure 2A), wherein the encapsulation layer is used to encapsulate the integrated transistor TINT, the first carrier plate CP1, the second carrier plate CP2, the third carrier plate CP3, and the fourth carrier plate CP4 to form the encapsulation structure 200. The encapsulation layer comprises a resin material, such as epoxy resin. In one embodiment, the encapsulation layer may be black glue. According to one embodiment of this disclosure, as shown in Figure 2A, when the drive signal SD is provided to the gate G of the first transistor T1 through the third carrier CP3 of the package structure 200 via the resistor R, capacitor C, fourth carrier CP4 and third metal wire BW3, since the first Zener diode ZD1 is disposed between the resistor R, capacitor C and the third metal wire BW3 and is connected in reverse series with the second Zener diode ZD2, the drive signal SD will first be limited by the first Zener diode ZD1 and the second Zener diode ZD2 before being provided to the gate G of the first transistor T1. In other words, the first Zener diode ZD1 is located between the third metal wire BW3 and the resistor R and capacitor C, and is connected in reverse series with the second Zener diode ZD2. This ensures that the drive signal SD is first converted into a safe operating voltage range for the first transistor T1 by the first Zener diode ZD1 and the second Zener diode ZD2 before being provided to the first transistor T1, thereby protecting the first transistor T1 from burnout. As shown in Figure 2A, the package structure 200 further includes one or more connectors VIA extending from the upper surface to the lower surface of the substrate SUB. According to one embodiment of this disclosure, the connectors VIA are formed by first forming a plurality of through-holes penetrating the substrate SUB, and then forming a conductive layer, for example, by plating. The conductive layer can be a metal pillar structure filling the through-holes, or a metal film structure formed on the sidewalls of the through-holes but not filling them completely. Finally, the connectors VIA extend from the plurality of through-holes to the upper surface and / or lower surface of the substrate SUB. In one embodiment, the connectors VIA are respectively located under the first carrier plate CP1, the second carrier plate CP2, and the third carrier plate CP3, wherein the dashed circles in Figure 2A represent schematic diagrams of the positions of the connectors VIA penetrating the substrate SUB, exposed on the upper and lower surfaces, and covered by the first carrier plate CP1, the second carrier plate CP2, and the third carrier plate CP3. Figure 2B shows a bottom view of the package structure according to one embodiment of the present disclosure, wherein the package structure 200 corresponds to the integrated transistor TINT in Figure 1. As shown in Figure 2B, the package structure 200 further includes a first substrate PB1, a second substrate PB2, a third substrate PB3, and a fourth substrate PB4, wherein the first substrate PB1, the second substrate PB2, the third substrate PB3, and the fourth substrate PB4 are all formed below the substrate SUB. The first base plate PB1 corresponds to the first carrier plate CP1 and is located below the substrate SUB. The connector VIA shown in Figure 2A is located on the first base plate PB1, and the first base plate PB1 is electrically connected to the first carrier plate CP1 via the connector VIA. The number of first base plates PB1 can be designed as one or more according to user needs. In this embodiment, the number of first base plates PB1 is three. According to one embodiment of this disclosure, the first base plate PB1 can be used as an endpoint for electrical connection to the outside in, for example, an SMD package. In one embodiment, the first base plate PB1 is used to form the source terminal TS of the integrated transistor TINT in Figure 1. The second base plate PB2 corresponds to the second carrier plate CP2 and is located below the substrate SUB. The connector VIA is located on top of the second base plate PB2, and the second base plate PB2 is electrically connected to the second carrier plate CP2 via the connector VIA. The number of second base plates PB2 can be designed as one or more according to user needs. In this embodiment, the number of second base plates PB2 is four. According to one embodiment of this disclosure, the second base plate PB2 can be used as an endpoint for electrical connection to the outside in, for example, an SMD package. In one embodiment, the second base plate PB2 is used to form the drain terminal TD of the integrated transistor TINT in Figure 1. The third base plate PB3 corresponds to the third carrier plate CP3 and is located below the substrate SUB. The connector VIA is located on top of the third base plate PB3, and the third base plate PB3 is electrically connected to the third carrier plate CP3 via the connector VIA. The number of third base plates PB3 can be designed as one or more according to user needs. In this embodiment, the number of third base plates PB3 is one. According to one embodiment of this disclosure, the third base plate PB3 can be used as an endpoint for electrical connection to the outside in, for example, an SMD package. In one embodiment, the third base plate PB3 is used to form the gate terminal TG of the integrated transistor TINT in Figure 1. The fourth base plate PB4 is formed below the substrate SUB, corresponding to the positions of the first carrier plate CP1 and the first transistor T1. The connector VIA is located on the fourth base plate PB4, and the fourth base plate PB4 is electrically connected to the first carrier plate CP1 via the connector VIA. The number of fourth base plates PB4 can be designed as one or more according to user needs. In this embodiment, there is one fourth base plate PB4. According to one embodiment of this disclosure, the fourth base plate PB4 can be used as an endpoint for electrical connection to the outside in, for example, an SMD package. In one embodiment, the fourth base plate PB4 assists in heat dissipation of the first transistor T1 and helps the source terminal TS of the first transistor T1 to have better grounding performance. The first base plate PB1, the second base plate PB2, the third base plate PB3, and the fourth base plate PB4 can be made of the same or different metallic materials. The metallic materials include copper (Cu), silver (Ag), gold (Au), titanium (Ti), or nickel (Ni). The first carrier plate CP1, the second carrier plate CP2, the third carrier plate CP3, and the fourth carrier plate CP4 can be made of the same or different metallic materials. The metallic materials include copper (Cu), silver (Ag), gold (Au), titanium (Ti), or nickel (Ni). The connector VIA can be made of a metallic material. The metallic materials include copper (Cu), silver (Ag), gold (Au), titanium (Ti), or nickel (Ni). The aforementioned first base plate PB1, second base plate PB2, third base plate PB3, fourth base plate PB4, first carrier plate CP1, second carrier plate CP2, third carrier plate CP3, fourth carrier plate CP4, and connector VIA can be formed of the same or different metallic materials. In one embodiment, the aforementioned first base plate PB1, second base plate PB2, third base plate PB3, fourth base plate PB4, first carrier plate CP1, second carrier plate CP2, third carrier plate CP3, fourth carrier plate CP4, and connector VIA are formed of the same metal material, such as copper (Cu), silver (Ag), gold (Au), titanium (Ti), or nickel (Ni). Figure 3 shows a cross-sectional view of the packaging structure according to one embodiment of the present disclosure. Figure 3 is cut along the dashed line A-A' of Figure 2A. As shown in Figure 3, the first carrier plate CP1 and the second carrier plate CP2 of the packaging structure 200 are formed on the substrate SUB, and the first bottom plate PB1, the second bottom plate PB2 and the fourth bottom plate PB4 are located below the substrate SUB. As shown in Figure 3, the connector VIA includes a first connector VIA1 that electrically connects the first carrier plate CP1 and the first base plate PB1, a second connector VIA2 that electrically connects the first carrier plate CP1 and the fourth base plate PB4, and a third connector VIA3 that electrically connects the second carrier plate CP2 and the second base plate PB2. Figure 4 shows a top view of a package structure according to another embodiment of the present disclosure, wherein the package structure 400 corresponds to the integrated transistor TINT in Figure 1. According to one embodiment of the present disclosure, similar to the package structure 200 in Figure 2A, the package structure 400 may be a surface mount device package structure. Comparing the package structure 400 in Figure 4 with the package structure 200 in Figure 2A, in Figure 4, the area occupied by the first carrier CP1 on the substrate SUB is smaller than that in Figure 2A. Specifically, the shape of the first carrier CP1 in Figure 4 is more square, and there is no first carrier CP1 at the location of the first region AR1 on the substrate SUB. Furthermore, the third carrier CP3 and the fourth carrier CP4 further include notches N2 and N1, respectively. In one embodiment, the notch N2 of the third carrier CP3 may include a T-shaped notch, which includes a first gap D1 and a second gap D2. The notch N1 of the fourth carrier plate CP4 may include a T-shaped notch, which includes a third interval D3 and a fourth interval D4. In one embodiment, the first interval D1 is substantially perpendicular to the second interval D2, and the third interval D3 is substantially perpendicular to the fourth interval D4, but is not limited thereto. According to one embodiment of this disclosure, compared to the embodiment in Figure 2A, the first carrier CP1 of the packaging structure 400 has a smaller area. Reducing the size of the first carrier CP1 without affecting its function will help lower production costs. As shown in Figure 4, the first interval D1 is adjacent to the resistor R and the capacitor C, the second interval D2 is located between the resistor R and the capacitor C, the third interval D3 is located between the resistor R, the capacitor C, and the first Zener diode ZD1, and the fourth interval D4 is located between the resistor R and the capacitor C. According to one embodiment of this disclosure, when the resistor R and capacitor C are die-bonded to the third carrier CP3 and the fourth carrier CP4 using solder paste, the T-shaped notch of the third carrier CP3, which includes the first interval D1 and the second interval D2, and the T-shaped notch of the fourth carrier CP4, which includes the third interval D3 and the fourth interval D4, can serve as a channel for venting excess solder paste, preventing the solder paste from spreading to other components, such as the first Zener diode ZD1, so as to avoid electrical problems in the components and adverse effects, such as short circuits. As shown in Figure 4, when the drive signal is supplied to the gate G of the first transistor T1 through the third carrier CP3 of the package structure 400 via resistor R, capacitor C, fourth carrier CP4, and third metal wire BW3, the first Zener diode ZD1 is positioned between the third metal wire BW3 and resistor R and capacitor C, and is connected in reverse series with the second Zener diode ZD2. This forces the drive signal received by the third carrier CP3 to be limited by the voltage of the first Zener diode ZD1 and the second Zener diode ZD2 before being supplied to the gate G of the first transistor T1. Therefore, the first transistor T1 can operate normally. The package structure 400 may further include a first substrate PB1, a second substrate PB2, a third substrate PB3, and a fourth substrate PB4, wherein the first substrate PB1, the second substrate PB2, the third substrate PB3, and the fourth substrate PB4 are all formed below the substrate SUB (not shown in the figure). The bottom view of each substrate of the package structure 400 can be referred to the bottom view of Figure 2B, and will not be described again here. In one embodiment, the packaging structure 400 of Figure 4 may also have a connector VIA as shown in Figure 2A. Regarding the materials, functions, and connection methods of the first carrier CP1, second carrier CP2, third carrier CP3, fourth carrier CP4, first base plate PB1, second base plate PB2, third base plate PB3, fourth base plate PB4, and connector VIA of Figure 4, please refer to the descriptions of the embodiments in Figures 2A and 2B, which will not be repeated here. Figure 5A shows a top view of a package structure according to yet another embodiment of the present disclosure, and Figure 5B shows a bottom view of a package structure according to yet another embodiment of the present disclosure, wherein the package structure 500 corresponds to the integrated transistor TINT in Figure 1. According to one embodiment of the present disclosure, the package structure 500 may be a surface mount device package structure. The difference between the package structure 500 and the package structure 200 in Figure 2A is that the package structure 500 further includes a fifth carrier plate CP5 located on and adjacent to the substrate SUB. The source S of the first transistor T1 is electrically connected to the first carrier plate CP1 and the fifth carrier plate CP5 through a plurality of metal wires. Specifically, the source S of the first transistor T1 is electrically connected to the first carrier plate CP1 through a plurality of first metal wires BW1 and a plurality of fifth metal wires BW5, respectively. The source S of the first transistor T1 is also electrically connected to the fifth carrier plate CP5 through one or a plurality of sixth metal wires BW6. The drain D of the first transistor T1 is electrically connected to the second carrier plate CP2 through a plurality of second metal wires BW2, and the gate G of the first transistor T1 is electrically connected to the fourth carrier plate CP4 through a third metal wire BW3. As shown in Figure 5B, the difference between the package structure 500 and the package structure 200 in Figure 2B is that, in addition to the first substrate PB1, the second substrate PB2, the third substrate PB3, and the fourth substrate PB4, the package structure 500 also includes a fifth substrate PB5 formed below (on the lower surface) of the substrate SUB. The position of the fifth substrate PB5 corresponds to the fifth carrier CP5 being disposed below the substrate SUB. Figure 5C shows a perspective view of the packaging structure according to another embodiment of the present disclosure. Figure 5D shows a side view of the packaging structure according to another embodiment of the present disclosure. Figure 5E shows a perspective view of the packaging structure according to another embodiment of the present disclosure. Figure 5F shows a side view of the packaging structure according to another embodiment of the present disclosure. Referring to Figures 5A-5D, the substrate SUB has a first side surface S1 and a second side surface S2 located between an upper surface and a lower surface, with the first side surface S1 opposite to the second side surface S2. The packaging structure 500 further includes connectors C1, C2, C3, and C4 located on the first side surface S1 and the second side surface S2. A first base plate PB1 is located below the first carrier plate CP1 opposite to the substrate SUB. The first base plate PB1 and the first carrier plate CP1 are connected via connector C1 located on the first side surface S1 of the substrate SUB. A fifth base plate PB5 is located below the fifth carrier plate CP5. The fifth base plate PB5 and the fifth carrier plate CP5 are connected by a connector C2 located on the first side S1 of the substrate SUB. The third base plate PB3 is located below the third carrier plate CP3. The third base plate PB3 and the third carrier plate CP3 are connected by a connector C3 located on the first side S1 of the substrate SUB. Please refer to Figures 5A-5B and 5E-5F. The second base plate PB2 is located below the second carrier plate CP2. The second base plate PB2 and the second carrier plate CP2 are connected by a connector C4 located on the second side surface S2 of the substrate SUB. The first base plate PB1 corresponds to the first carrier plate CP1 and is located below the substrate SUB. The number of first base plates PB1 can be designed as one or more according to user needs. In this embodiment, there are two first base plates PB1. According to one embodiment of this disclosure, the first base plate PB1 can be used as an endpoint for external electrical connection in, for example, an SMD package. In one embodiment, the first base plate PB1 is used to form the source terminal TS of the integrated transistor TINT in Figure 1. The fifth base plate PB5 corresponds to the fifth carrier plate CP5 and is located below the substrate SUB. The number of fifth base plates PB5 can be designed as one or more according to user needs. In this embodiment, there is one fifth base plate PB5. According to one embodiment of this disclosure, the fifth base plate PB5 can be used as an endpoint for external electrical connection in, for example, an SMD package. In one embodiment, the fifth base plate PB5 is used to form the source terminal TS of the integrated transistor TINT in Figure 1. The third base plate PB3 corresponds to the third carrier plate CP3 and is located below the substrate SUB. The number of third base plates PB3 can be designed as one or more according to user needs. In this embodiment, the number of third base plates PB3 is one. According to one embodiment of this disclosure, the third base plate PB3 can be used as an endpoint for external electrical connection in, for example, an SMD package. In one embodiment, the third base plate PB3 is used to form the gate terminal TG of the integrated transistor TINT in Figure 1. The fourth base plate PB4 corresponds to the first carrier plate CP1 and the first transistor T1, and is located below the substrate SUB. The number of fourth base plates PB4 can be designed as one or more according to user needs. In this embodiment, there is one fourth base plate PB4. The fourth base plate PB4 can be connected to the first carrier plate CP1 via a connector VIA similar to that shown in Figure 2A (not shown in Figures 5A and 5B). According to one embodiment of this disclosure, the fourth base plate PB4 can be used as an endpoint for external electrical connection, for example, in an SMD package. In one embodiment, the fourth base plate PB4 is used to assist in heat dissipation of the first transistor T1 and to help the source terminal TS of the first transistor T1 have better grounding performance. The second base plate PB2 corresponds to the second carrier plate CP2 and is located below the substrate SUB. The number of second base plates PB2 can be designed as one or more according to user needs. In this embodiment, the number of second base plates PB2 is four. According to one embodiment of this disclosure, the second base plate PB2 can be used as an endpoint for external electrical connection in, for example, an SMD package. In one embodiment, the second base plate PB2 is used to form the drain terminal TD of the integrated transistor TINT in Figure 1. The first carrier plate CP1, the second carrier plate CP2, the third carrier plate CP3, the fourth carrier plate CP4, and the fifth carrier plate CP5 can be made of the same or different metal materials. The first base plate PB1, the second base plate PB2, the third base plate PB3, the fourth base plate PB4, and the fifth base plate PB5 can be made of the same or different metal materials. The connectors C1, C2, C3, and C4 can be made of the same or different metal materials. In one embodiment, the first carrier plate CP1, the second carrier plate CP2, the third carrier plate CP3, the fourth carrier plate CP4, the fifth carrier plate CP5, the first base plate PB1, the second base plate PB2, the third base plate PB3, the fourth base plate PB4, the fifth base plate PB5, and the connectors C1, C2, C3, and C4 are formed of the same metallic material. The aforementioned metallic material includes copper (Cu), silver (Ag), gold (Au), titanium (Ti), or nickel (Ni). According to one embodiment of this application, the first carrier plate CP1 and the fifth carrier plate CP5 are separated and disposed on the upper surface of the substrate SUB. Therefore, during four-wire measurement, the source S of the first transistor T1 is connected to the first carrier plate CP1 and the fifth carrier plate CP5 via a plurality of first metal wires BW1 and a sixth metal wire BW6, respectively. The first carrier plate CP1 can be used to apply a measurement current or a measurement voltage to the first transistor T1, and the fifth carrier plate CP5 can be used to receive the signal generated by the measured first transistor T1 and transmit the signal generated by the measured first transistor T1 to the circuit board for processing and analysis to obtain the current value or voltage value of the first transistor T1. This four-wire measurement method can make the measurement results more accurate. Figure 6A shows a top view of the packaging structure according to another embodiment of this disclosure, and Figure 6B is an enlarged schematic diagram of the stacked structure 600 shown in Figure 6A. The packaging structure 700 corresponds to the integrated transistor TINT in Figure 1. As shown in Figure 6A, the packaging structure 700 includes a base plate BP, a first lead frame LF1, a second lead frame LF2, and a third lead frame LF3, wherein the base plate BP is electrically connected to the first lead frame LF1. According to one embodiment of this disclosure, the base plate BP is a conductive plate and is connected to the first lead frame LF1, for example, by means of integral molding. In one embodiment, the base plate BP, the first lead frame LF1, the second lead frame LF2, and the third lead frame LF3 are integrally molded. The base plate BP, the first lead frame LF1, the second lead frame LF2, and the third lead frame LF3 may be made of the same or different metal materials. In one embodiment, the base plate BP, the first lead frame LF1, the second lead frame LF2, and the third lead frame LF3 contain the same metal material. The aforementioned metallic materials include copper (Cu), silver (Ag), gold (Au), titanium (Ti), or nickel (Ni). According to one embodiment of this disclosure, the package structure 700 may be a transistor outline (TO) package structure. As shown in Figures 6A and 6B, in this embodiment, the packaging structure 700 further includes a stacked structure 600 formed on the base plate BP. The stacked structure 600 includes an insulating plate PI, a sixth carrier plate CP6, and a seventh carrier plate CP7 formed on the insulating plate PI. The resistor R and capacitor C in Figure 1 are disposed on the sixth carrier plate CP6 and the seventh carrier plate CP7, and are electrically connected between the sixth carrier plate CP6 and the seventh carrier plate CP7. In one embodiment, both the sixth carrier plate CP6 and the seventh carrier plate CP7 are conductive plates, such as metal conductive plates. The sixth carrier plate CP6 and the seventh carrier plate CP7 may be made of the same or different metal materials. In one embodiment, the sixth carrier plate CP6 and the seventh carrier plate CP7 are formed of the same metal material, such as copper (Cu), silver (Ag), gold (Au), titanium (Ti), nickel (Ni), or alloys of the aforementioned materials. The sixth carrier plate CP6 and the seventh carrier plate CP7 may include a single layer or multiple layers of metal. In this embodiment, the sixth carrier CP6 and the seventh carrier CP7 may include copper (Cu) / gold (Au). According to one embodiment of this disclosure, the insulating plate PI may be a ceramic substrate, and the material may include alumina or aluminum nitride (AlN). As shown in Figure 6B, resistor R and capacitor C are soldered across the sixth carrier plate CP6 and the seventh carrier plate CP7, respectively. In one embodiment, the package structure 700 further includes a first insulating layer SP1 and a second insulating layer SP2. During soldering, the first insulating layer SP1 is formed at the non-soldering location between resistor R and capacitor C and the sixth carrier plate CP6, and the second insulating layer SP2 is formed at the non-soldering location between resistor R and capacitor C and the seventh carrier plate CP7. The first insulating layer SP1 and the second insulating layer SP2 can serve as solder resist layers. The material of the aforementioned solder resist layer may include epoxy resin, ethyl carbamate, or ethyl acetate resin. In this embodiment, the package structure 700 includes a first transistor T1 as shown in Figure 1 and a second Zener diode ZD2, which can be disposed on a base plate BP as shown in Figure 6A. The source S of the first transistor T1 is electrically connected to the base plate BP through a plurality of seventh metal wires BW7, and the drain D of the first transistor T1 is electrically connected to a third lead frame LF3 through a plurality of eighth metal wires BW8. The second cathode NC2 of the second Zener diode ZD2 (not shown in Figure 6A) is electrically connected to the base plate BP through direct or indirect contact. According to one embodiment of this disclosure, the second cathode NC2 is fixed to the base plate BP and electrically connected to it by soldering. As shown in Figure 1, the first Zener diode ZD1 is disposed on the sixth carrier plate CP6. The first cathode NC1 of the first Zener diode ZD1 (not shown in Figure 6A) is electrically connected to the sixth carrier plate CP6 by direct or indirect contact. According to one embodiment of this disclosure, the first cathode NC1 is fixed to the sixth carrier plate CP6 by soldering and electrically connected thereto. The gate G of the first transistor T1 is electrically connected to the sixth carrier plate CP6 through the third metal wire BW3, and then electrically connected to the first Zener diode ZD1 through the sixth carrier plate CP6 and the first cathode NC1. The first anode NA1 of the first Zener diode ZD1 (not shown in Figure 6A) is electrically connected to the second anode NA2 of the second Zener diode ZD2 (not shown in Figure 6A) through the fourth metal wire BW4. The seventh carrier plate CP7 is electrically connected to the second lead frame LF2 through a plurality of ninth metal wires BW9. In one embodiment, a metal structure, including titanium (Ti), nickel (Ni), silver (Ag), or an alloy of the above materials, may be disposed between the laminated structure 600 and the base plate BP. This metal structure may be a single layer or multiple layers and is used to fix the laminated structure 600 to the base plate BP. According to one embodiment of this disclosure, the fixing method includes welding. According to one embodiment of the present disclosure, the first lead frame LF1 forms the source terminal TS of the integrated transistor TINT in Figure 1, the second lead frame LF2 forms the gate terminal TG of the integrated transistor TINT in Figure 1, and the third lead frame LF3 forms the drain terminal TD of the integrated transistor TINT in Figure 1. According to one embodiment of this disclosure, the package structure 700 forms the integrated transistor TINT of Figure 1. As shown in Figure 7, the package structure 700 receives the drive signal SD from the second lead frame LF2 (i.e., the gate terminal TG of the integrated transistor TINT) and provides it to the gate G of the first transistor T1 via a resistor R, a capacitor C, a first Zener diode ZD1 (which may include a second Zener diode ZD2), and a third metal wire BW3. The encapsulation structure 700 may further include an encapsulation layer comprising a resin material, such as epoxy resin. In one embodiment, the encapsulation layer may be a black adhesive. In one embodiment, the encapsulation layer may completely enclose the base plate BP, the first transistor T1 on the base plate BP, the second Zener diode ZD2, the stacked structure 600, a portion of the first leadframe LF1, a portion of the second leadframe LF2, and a portion of the third leadframe LF3. Since the drive signal SD is first limited by the first Zener diode ZD1 and the second Zener diode ZD2 before being supplied to the gate G of the first transistor T1, the signal received by the gate G of the first transistor T1 can be ensured to be within the safe operating range of the first transistor T1. Furthermore, by reducing the distance between the gate G of the first transistor T1 and the sixth carrier CP6, the length of the third metal conductor BW3 can be shortened, thereby reducing the parasitic inductance caused by the third metal conductor BW3, and thus reducing the voltage fluctuation of the gate G of the first transistor T1. The tolerance of the first transistor T1 is also improved accordingly. According to one comparative example of this disclosure, a package structure contains only a transistor package and does not include resistors, capacitors, or Zener diodes. In an application circuit, the transistor package structure, resistors, capacitors, and Zener diodes are arranged on a circuit board in the layout of the circuit diagram of Figure 1. Since there are wires on the circuit board that electrically connect the resistors (or capacitors), Zener diodes, and transistor package structures, and these wires have a trace distance, parasitic inductance will be generated on the wires along this trace distance when the components are in operation. Furthermore, the lead frame used as the gate terminal of the transistor and the metal wires connecting the gate terminal and the gate of the transistor also have parasitic inductance, making the parasitic inductance from the Zener diode to the gate of the transistor in the comparative example much greater than the parasitic inductance between the first Zener diode ZD1 and the gate G of the first transistor T1 in the package structure 700 (i.e., the third metal wire BW3). As the parasitic inductance between the gate of the transistor and the Zener diode in the comparative example increases, the voltage fluctuation at the gate of the transistor becomes greater, and the gate of the transistor is more easily broken down. Conversely, referring to Figure 6A, the package structure 700 can shorten the length of the third metal conductor BW3 by adjusting the position of the gate G of the first transistor T1 and the sixth carrier CP6, thereby reducing the parasitic inductance between the gate G of the first transistor T1 and the first Zener diode ZD1. In other words, placing the protection circuit of the first transistor T1 (i.e., resistor R, capacitor C, first Zener diode ZD1, and second Zener diode ZD2) in the same package structure as the first transistor T1 helps improve the tolerance of the first transistor T1. Furthermore, the package structure 700 in Figure 6A helps reduce the overall required circuit area and the complexity of the circuit design. This disclosure proposes a package structure that integrates a transistor and its protection circuitry. By integrating the transistor and its protection circuitry into the same package, the distance between the gate of the first transistor and the resistor, capacitor, and Zener diode is shortened, thereby reducing parasitic inductance and improving the transistor's robustness. Furthermore, the package structure that integrates the transistor and its protection circuitry disclosed in this disclosure can reduce the overall circuit area required on the circuit board, thereby increasing heat dissipation and reducing the defect rate in surface mount technology (SMT) processes, and may even reduce the complexity of circuit design. While the embodiments and advantages of this disclosure have been disclosed above, it should be understood that anyone skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of this specification. Anyone skilled in the art can understand from the disclosure of some embodiments of this disclosure the current or future development of processes, machines, manufacturing, material composition, apparatus, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claim claims and embodiments. 100: Integrated Circuit 110: Control Circuit 200, 400, 500, 700: Package Structure 600: Stacked Structure T1: First Transistor R: Resistor C: Capacitor ZD1: First Zener Diode ZD2: Second Zener Diode ND: Drive Node SD: Drive Signal G: Gate D: Drain S: Source NA1: First Anode NA2: Second Anode NC1: First Cathode NC2: Second Cathode TINT: Integrated Transistor TG: Gate Terminal TD: Drain Terminal TS: Source Terminal SUB: Substrate CP1: First Carrier CP2: Second Carrier CP3: Third Carrier CP4: Fourth Carrier CP5: Fifth Carrier CP6: Sixth Carrier CP7: Seventh Carrier BW1: First Metal Wire BW2: Second Metal Wire BW3: Third Metal Wire BW 4: Fourth metal conductor BW5: Fifth metal conductor BW6: Sixth metal conductor BW7: Seventh metal conductor BW8: Eighth metal conductor BW9: Ninth metal conductor PB1: First base plate PB2: Second base plate PB3: Third base plate PB4: Fourth base plate PB5: Fifth base plate VIA: Connector VIA1: First connector VIA2: Second connector VIA3: Third connector D1: First gap D2: Second gap D3: Third gap D4: Fourth gap AR1: First area PI: Insulating plate SP1: First insulating layer SP2: Second insulating layer BP: Base plate LF1: First conductor frame LF2: Second conductor frame LF3: Third conductor frame C1, C2, C3, C4: Connector N1, N2: Notch S1: First side S2: Second side Figure 1 shows a circuit diagram of an integrated circuit according to one embodiment of the present disclosure; Figure 2A shows a top view of a package structure according to one embodiment of the present disclosure; Figure 2B shows a bottom view of a package structure according to one embodiment of the present disclosure; Figure 3 shows a cross-sectional view of a package structure according to one embodiment of the present disclosure; Figure 4 shows a top view of a package structure according to another embodiment of the present disclosure; Figure 5A shows a top view of a package structure according to yet another embodiment of the present disclosure; Figure 5B shows a bottom view of a package structure according to yet another embodiment of the present disclosure; Figure 5C shows a perspective view of a package structure according to yet another embodiment of the present disclosure; Figure 5D shows a side view of a package structure according to yet another embodiment of the present disclosure; Figure 5E shows a perspective view of a package structure according to yet another embodiment of the present disclosure; Figure 5F shows a side view of a package structure according to yet another embodiment of the present disclosure. Figure 6A shows a top view of the packaging structure according to yet another embodiment of the present disclosure; and Figure 6B is an enlarged schematic diagram of the stacked structure 600 shown in Figure 6A. 200: Package structure T1: First transistor R: Resistance C: Capacitor ZD1: First Zener Diode ZD2: Second Zener Diode SD: Drive signal G: Gate D: Jiji S: Source SUB:Substrate CP1: First carrier board CP2: Second carrier board CP3: Third carrier board CP4: Fourth Carrier BW1: First metallic conductor BW2: Second metal wire BW3: Third metal conductor BW4: Fourth Metal Wire VIA: Connector

Claims

1. A packaging structure, comprising: One substrate; An integrated transistor is formed on the substrate, comprising: a first transistor, including a gate, a drain and a source; A capacitor electrically connected to the gate; a resistor electrically connected to the gate; a first Zener diode including a first anode and a first cathode, wherein the first cathode is electrically connected to the gate; and a second Zener diode including a second anode and a second cathode, wherein the second anode is electrically connected to the first anode and the second cathode is electrically connected to the source; and a package layer encapsulating the transistor assembly; wherein the package structure includes a gate terminal, a drain terminal, and a source terminal for external connection; wherein the capacitor and the resistor are both coupled between the gate terminal and the gate.

2. The packaging structure as claimed in claim 1, wherein the first transistor system is an enhanced high electron mobility transistor.

3. As in the encapsulation structure of request item 1, it further includes: A first carrier plate is formed on the substrate, wherein the second cathode and the source are electrically connected to each other via the first carrier plate; A second carrier plate is formed on the substrate, wherein the drain is electrically connected to the second carrier plate; and a third carrier plate is formed on the substrate, wherein the gate is electrically connected to the third carrier plate.

4. As in the encapsulation structure of request item 3, it further includes: A fourth carrier plate is formed on the substrate, wherein the gate and the first cathode are electrically connected to each other via the fourth carrier plate, and the capacitor and the resistor are electrically connected to the third carrier plate and the fourth carrier plate, respectively.

5. The packaging structure as claimed in claim 4, wherein the first transistor and the second Zener diode are disposed on the first carrier plate, the first Zener diode is disposed on the fourth carrier plate, and the capacitor and the resistor are disposed between the third carrier plate and the fourth carrier plate.

6. The packaging structure of claim 5, wherein the first carrier, the second carrier, the third carrier and the fourth carrier are each a conductive carrier, the gate is adjacent to the fourth carrier, the gate is electrically connected to the fourth carrier via a first metal wire, the first Zener diode is electrically connected to the second Zener diode via a second metal wire, and the capacitor and the resistor are respectively connected across the third carrier and the fourth carrier.

7. As in the encapsulation structure of request item 3, it further includes: A first base plate is disposed below the substrate and the first carrier plate; a second base plate is disposed below the substrate and the second carrier plate; a third base plate is disposed below the substrate and the third carrier plate; and a fourth base plate is disposed below the substrate, the first carrier plate, and the first transistor; wherein the first base plate, the second base plate, and the third base plate are electrically connected to the first carrier plate, the second carrier plate, and the third carrier plate respectively via individual connectors.

8. The packaging structure as claimed in claim 7, wherein the source end includes the first base plate, the drain end includes the second base plate, and the gate end includes the third base plate.

9. The packaging structure as claimed in claim 7, wherein the first carrier board is connected to the fourth base plate via a connector.

10. The packaging structure of claim 9, wherein the substrate includes a plurality of through-holes passing through the substrate, and the connectors are respectively formed in the through-holes.

11. The packaging structure of claim 7, wherein the substrate includes a plurality of sides, and the connectors are formed on any of the sides.

12. The encapsulation structure as described in request item 11 further includes: A fifth carrier plate is formed on the substrate, wherein the fifth carrier plate and the first carrier plate are disposed separately on the substrate; A fifth base plate is disposed below the substrate and the fifth carrier plate; wherein the fifth carrier plate is electrically connected to the fifth base plate via another connector.

13. The packaging structure of claim 4, wherein the third carrier includes a notch and / or the fourth carrier includes a notch.

14. The packaging structure of claim 13, wherein the notch of the third carrier is T-shaped and / or the notch of the fourth carrier is T-shaped.

15. As in the encapsulation structure of request item 1, it further includes: An insulating plate is disposed on the substrate; A sixth carrier plate is disposed on the insulating plate; A seventh carrier plate is disposed on the insulating plate, wherein the sixth carrier plate is electrically connected to the gate terminal; wherein the source and the second cathode are electrically connected to the substrate, and the capacitor and the resistor are both electrically connected to the sixth carrier plate and the seventh carrier plate.

16. The packaging structure of claim 15, wherein the first Zener diode is disposed on the sixth carrier, and the capacitor and the resistor are disposed between the sixth carrier and the seventh carrier.

17. The package structure of claim 16, wherein the gate of the first transistor is adjacent to the sixth carrier, and the gate is connected to the sixth carrier by a metal wire.

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