Semiconductor package and method of forming the same

Abstract

A method for forming a semiconductor package according to an embodiment of the present invention includes forming a composite package substrate. Forming the composite package substrate includes: encapsulating interconnect dies in a first encapsulation, wherein the interconnect dies include a plurality of first through-holes; and forming a plurality of first redistribution lines and a plurality of second redistribution lines on opposite sides of the interconnect dies. The method further includes bonding an organic package substrate to the composite package substrate; and bonding a first package assembly and a second package assembly to the plurality of first redistribution lines. The first package assembly and the second package assembly are electrically interconnected through the interconnect dies and the plurality of first redistribution lines.

Description

Prior Art

[0001] Integrated circuits (ICs) are gaining increasing functionality. To integrate these functions, multiple device dies are manufactured and packaged together. These multiple device dies are electrically interconnected, enabling them to function together. As the size and complexity of the package increase, warpage also increases. Simple diagram description

[0002] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion. 1-16 illustrate cross-sectional views of intermediate stages in package formation according to some embodiments. FIG. 17 illustrates a cross-sectional view of a package according to some embodiments. 18-21 illustrate cross-sectional views of intermediate stages in package formation according to some embodiments. 22-23 illustrate cross-sectional views of intermediate stages in package formation according to some embodiments. 24-31 illustrate cross-sectional views of intermediate stages in package formation according to some embodiments. 32 to 37 illustrate cross-sectional views of some packages according to some embodiments. 38-43 illustrate cross-sectional views of intermediate stages in package formation according to some embodiments. 44-47 illustrate cross-sectional views of intermediate stages in package formation according to some embodiments. 48-50 illustrate cross-sectional views of some packages according to some embodiments. 51-60 illustrate cross-sectional views of intermediate stages in package formation according to some embodiments. 61-62 illustrate cross-sectional views of some packages according to some embodiments. 63-69 illustrate cross-sectional views of intermediate stages in package formation according to some embodiments. 70-71 illustrate cross-sectional views of some packages according to some embodiments. 72 to 75 illustrate cross-sectional views of some package components in a package according to some embodiments. FIG. 76 shows an enlarged view of a portion of a package according to some embodiments. FIG. 77 illustrates a cross-sectional view of an interconnect die in accordance with some embodiments. FIG. 78 illustrates a process flow for forming a package in accordance with some embodiments. Implementation Method

[0003] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature being formed over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features, thereby preventing the first and second features from directly contacting each other. Furthermore, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the sake of brevity and clarity and does not inherently indicate a relationship between the various embodiments and / or configurations discussed.

[0004] Furthermore, for ease of description, spatially relative terms, such as "underlying," "below," "lower," "overlying," "upper," and similar terms, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0005] A packaging process and the resulting package are provided. According to some embodiments, an integrated fan-out (InFO) package substrate (also known as a composite package substrate) is formed, in which a local silicon interconnect (LSI) die is embedded. The InFO package substrate can be a wafer-level package component comprising multiple identical InFO package substrates. The InFO package substrates are built layer by layer and extend laterally beyond the edges of their respective underlying device dies. The InFO package substrate can be bonded to another package component, such as an organic package substrate. Discrete package components, such as device dies, high-bandwidth memory (HBM), and chip-on-wafer (COW) packages can be directly bonded to the InFO package substrate. Because the LSI die is built into the InFO package substrate, rather than embedded in a chip-on-wafer-on-substrate (CWOS) package bonded to the package substrate, warpage of the resulting package is reduced, and manufacturing yield is improved. A CWOS package may include discrete device dies bonded to a wafer, followed by dicing the wafer to form discrete COW packages, which are then bonded to a packaging substrate to form a CWOS package. This enables the formation of very large packages (e.g., with a 6X mask or larger). Insertion loss is also reduced. The embodiments discussed herein are intended to provide examples for implementing or using the subject matter of the present disclosure, and those skilled in the art will readily appreciate modifications that can be made while remaining within the intended scope of the various embodiments. Throughout the various views and illustrative embodiments, like reference numerals are used to indicate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0006] 1 to 17 illustrate cross-sectional views of intermediate stages in the formation of a package including an LSI die according to some embodiments. The corresponding process is also schematically reflected in a process flow 200, as shown in FIG. 78 .

[0007] Referring to FIG. 1 , a carrier 20 is provided, and a release film 22 is coated on the carrier 20. The carrier 20 is formed of a transparent material, such as a glass carrier, a ceramic carrier, or the like. The release film 22 may be formed of a light-to-heat conversion (LTHC) coating material. The release film 22 may be applied to the carrier 20 by coating. According to some embodiments, the LTHC coating material can decompose under the heat energy of light / radiation (e.g., laser), thereby enabling the carrier 20 to be released from the structure formed thereon.

[0008] 1 , a dielectric layer 24 is formed on a release film 22. The dielectric layer 24 may be formed of or include a polymer, which may be a photosensitive polymer such as polybenzoxazole (PBO), polyimide, or benzocyclobutene (BCB).

[0009] Then, redistribution lines 26 are formed. Redistribution lines 26 include via portions extending into dielectric layer 24 and trace portions on dielectric layer 24. The corresponding process is shown as process 202 in process flow 200, as shown in FIG78. Formation of redistribution lines 26 may include patterning dielectric layer 24 to form openings (occupied by the via portions) and depositing a metal seed layer. The metal seed layer includes portions above dielectric layer 24 and portions extending into dielectric layer 24. According to some embodiments, the metal seed layer includes a titanium layer and a copper layer located above the titanium layer. The metal seed layer may be formed, for example, using physical vapor deposition (PVD), chemical vapor deposition (CVD), or the like. Next, a patterned plating mask (not shown) is used and patterned to form openings therein, exposing portions of the metal seed layer. The patterned plating mask may include photoresist. Metal material is then deposited on the exposed portions of the metal seed layer, and the plating mask is subsequently removed to expose portions of the metal seed layer below. Metal materials may include Cu, Al, Ti, W, Au, etc. The exposed portion of the metal seed layer is then removed, leaving behind redistribution circuit 26. It should be noted that while an interface exists between the via portion and the trace portion of redistribution circuit 26 as shown in the figure, this interface does not need to exist when using the above-described process.

[0010] After the redistribution lines 26 are formed, metal pillars 28 can be formed. The corresponding process is shown as process 204 in the process flow 200, as shown in Figure 78. It can be understood that although one redistribution line layer is used as an example, depending on the wiring requirements, more layers (for example, 2 layers, 3 layers, 4 layers or more layers) of redistribution lines can be formed before forming the metal pillars 28. The formation of the metal pillars 28 can include depositing a metal seed layer above the redistribution lines 26, and forming a patterned electroplating mask, the patterned electroplating mask exposing some portions of the metal seed layer. Then, an electroplating process is performed to electroplate the metal material into the openings in the electroplating mask. The electroplating mask is then removed, and the exposed portion of the metal seed layer is subsequently etched to form the metal pillars 28.

[0011] FIG2 illustrates the bonding of LSI die 30 to redistribution circuit 26. The corresponding process is shown as process 206 in process flow 200, as shown in FIG78. Although a single LSI die 30 is shown, multiple LSI dies 30 may be bonded. The multiple LSI dies 30 may have the same structure or different structures. LSI die 30 is schematically illustrated, and its detailed structure is shown in FIG28 according to some embodiments.

[0012] FIG77 illustrates an example LSI die 30 according to some embodiments. LSI die 30 includes a substrate 32, which may be a semiconductor substrate such as a silicon substrate. Substrate 32 may also be a dielectric substrate formed of a dielectric material such as silicon oxide or silicon nitride. According to some embodiments, a through-hole 34 is formed extending into substrate 32. Therefore, dashed lines are used to indicate that through-hole 34 may or may not be formed.

[0013] According to some embodiments, LSI die 30 does not include active components such as transistors and diodes. LSI die 30 may or may not include passive components such as capacitors, transformers, inductors, and resistors. According to some embodiments of the present disclosure, LSI die 30 includes some active components and / or passive components (not shown), and the active components may be formed on the top surface of semiconductor substrate 32.

[0014] LSI die 30 also includes an interconnect structure 31 above substrate 32. Interconnect structure 31 also includes a dielectric layer 35 and metal lines and vias 37 within the dielectric layer. Dielectric layer 35 may include an intermetallic dielectric (IMD) layer. According to some embodiments, some of dielectric layers 35 (e.g., lower dielectric layer 35) are formed from a low-k dielectric material having a dielectric constant (k value) less than 3.8, and the k value may be less than approximately 3.0 or approximately 2.5. Low-k dielectric layer 35 may be formed from carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. The formation of metal lines and vias 37 may include single and dual damascene processes. Electrical connections may be formed on the surface of LSI die 30, including metal pillars or metal pads (which may or may not include solder regions 36).

[0015] Referring back to FIG. 2 , according to some embodiments, the LSI die 30 and the redistribution line 26 may be joined by solder bonding or direct metal-to-metal bonding. For example, the joining may be performed through the solder region 38. After joining, the underfill 40 is dispensed in the gap between the LSI die 30 and the underlying redistribution line 26. The gap may have a height H1 in the range between about 80 μm and about 10 μm. According to some embodiments, the underfill 40 may include a substrate 40A ( FIG. 76 ) and filler particles 40B in the substrate 40A, and the substrate 40A may include a polymer, a resin, an epoxy resin, and / or the like. The filler particles 40B may be dielectric particles of silicon dioxide, aluminum oxide, boron nitride, or the like, and may have a spherical shape.

[0016] According to some embodiments, in addition to LSI die 30, additional device dies may also be bonded to redistribution line 26. For example, FIG. 17 illustrates device die 74D that is also bonded to redistribution line 26. According to some embodiments, device die 74D is an integrated passive component that may include capacitors, inductors, resistors, etc. According to some embodiments, there are no device dies that include bonded active and / or passive components. The bottom surface of device die 74D may be in contact with dielectric layer 44 (which is formed in the process shown in FIG. 5 ), or the bottom surface of device die 74D may be separated from dielectric layer 44 by some portion of encapsulation body 42.

[0017] 3 , a thinning process is performed to thin the substrate 32 in the LSI die 30. The remaining substrate 32 may have a thickness T1 less than approximately 200 μm. Thickness T1 may also be within a range between approximately 100 μm and approximately 200 μm. The thinning process can reduce the aspect ratio of the gaps between adjacent LSI dies 30 and metal pillars 28.

[0018] Next, as shown in FIG4 , an encapsulant 42 is dispensed to encapsulate the LSI die 30 and metal pillars 28 therein. The corresponding process is shown as process 208 in process flow 200 and is shown in FIG78 . Encapsulant 42 fills the gaps between adjacent metal pillars 28 and the gaps between the metal pillars 28 and the LSI die 30. Encapsulant 42 may include a molding compound, a molding underfill, an epoxy, and / or a resin. When the package is complete, the top surface of encapsulant 42 is higher than the tops of the metal pillars 28 and the top surface of the LSI die 30. Encapsulant 42 may include a substrate 42A ( FIG76 ) and filler particles 42B within the substrate. Substrate 42A may be a polymer, resin, epoxy, or the like. Filler particles 42B may be dielectric particles such as silicon dioxide, aluminum oxide, or boron nitride, and may have a spherical shape.

[0019] Then, a planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical polishing process, is performed until metal pillars 28 are exposed, thereby thinning package 42 and LSI die 30. The resulting structure is shown in FIG4 . Metal pillars 28 are hereinafter alternatively referred to as vias because they penetrate package 42. Vias 34 in LSI die 30 are also exposed by the planarization process.

[0020] FIG5 illustrates the formation of a patterned dielectric layer 44 according to some embodiments. The corresponding process is shown as process 210 in process flow 200, as shown in FIG78. Dielectric layer 44 may be or include an organic material such as a polymer, and may be a photosensitive polymer such as PBO or polyimide. Dielectric layer 44 may also be formed from or include an inorganic material such as silicon oxide or silicon nitride.

[0021] Dielectric layer 44 is patterned to form openings 46, through which metal pillars (vias) 28 are exposed. Openings 48 may also be formed to expose vias 34. Furthermore, dielectric layer 50 may (or may not) be formed in LSI die 30, wherein dielectric layer 50 contacts the backside of semiconductor substrate 32. Vias 34 extend through dielectric layer 50. Dielectric layer 50 may be formed of or include silicon oxide, silicon nitride, or the like. The formation process may include, before forming dielectric layer 44 and after planarization to expose vias 34, recessing semiconductor substrate 32 of LSI die 30 to form a recess, filling the recess with dielectric layer 50, and then performing another planarization process to expose vias 34 again.

[0022] FIG6 illustrates the formation of a redistribution wiring structure 52 on an LSI die 30. The corresponding process is shown as process 212 in the process flow 200, as shown in FIG78. According to some embodiments, the redistribution wiring structure 52 includes a dielectric layer 54A and a dielectric layer 54A above the dielectric layer 54B. The dielectric layer 54A and the dielectric layer 54B can be formed of different materials and have different thicknesses. For example, each of the dielectric layers 54A can be thicker than any of the dielectric layers 54B. According to some embodiments, the dielectric layer 54A is formed of a non-photosensitive material such as a molding compound, a molding underfill, silicon oxide, silicon nitride, etc. Conversely, the dielectric layer 54B can also be formed of a photosensitive material such as PBO, polyimide, BCB, etc. According to other embodiments, both the dielectric layers 54A and 54B are formed of a photosensitive material.

[0023] Redistribution lines 56A are formed in dielectric layer 54A, and redistribution lines 56B are formed in dielectric layer 54B. According to some embodiments, redistribution lines 56A are thicker and / or wider than redistribution lines 56B and can be used for long-distance electrical routing, while redistribution lines 56B can be used for short-distance electrical routing. Redistribution lines 56A and 56B are electrically connected to metal pillars (vias) 28 and vias 34. Surface conductive features 56BT are formed, which can be part of redistribution lines 56B or can be separately formed under-bump metallurgy (UBM).

[0024] According to some embodiments, redistribution lines 56A and 56B are electrically connected to redistribution lines 26 through both metal posts (vias) 28 and vias 34. According to some embodiments, metal posts (vias) 28 are not formed. Therefore, all connections from redistribution lines 56A and 56B to redistribution lines 26 are made through vias 34 in LSI die 30. Because vias 34 can be formed using the same process used to form device dies, vias 34 can be made smaller than metal posts (vias) 28. Therefore, by forming more / larger LSI dies 30 (and therefore more vias 34) to occupy the wafer area that would otherwise be occupied by metal posts (vias) 28, more electrical interconnections can be formed. According to other embodiments, the number of metal posts (vias) 28 can be minimized, and all signals can be transmitted through vias 34, while metal posts (vias) 28 can be used only for power transmission, such as VDD and VSS.

[0025] In the subsequent process, as shown in FIG7 , a carrier exchange process is performed. The corresponding process is shown as process 214 in process flow 200 , as shown in FIG78 . In the carrier exchange process, the redistribution wiring structure 52 is first connected to the carrier 58 via a release film 60 . The carrier 58 is formed of a transparent material and can be a glass carrier, a ceramic carrier, or the like. The release film 60 can be formed of an LTHC coating material. The carrier 20 is then separated from the redistribution wiring structure 52 . In the separation process, a light beam (which can be a laser beam) is projected onto the release film 22, and the light beam penetrates the transparent carrier 20. The release film 22 is thereby decomposed. The carrier 20 can be separated from the release film 132 , and the redistribution wiring structure 52 (together with the LSI die 30 ) is separated (disassembled) from the carrier 20 .

[0026] FIG8 illustrates the formation of a front-side interconnect structure and electrical connectors located above and connected to the redistribution wiring structure 52. The corresponding process is shown as process 216 in process flow 200, as shown in FIG78. The front-side interconnect structure includes a dielectric layer 62 and redistribution wiring 64 in the dielectric layer 62. According to some embodiments, the dielectric layer 62 is formed from or includes a polymer such as PBO, polyimide, or BCB. The formation process includes applying the dielectric layer 62 in a flowable form and then curing the dielectric layer 62. According to some embodiments of the present disclosure, the dielectric layer 62 is formed from an inorganic dielectric material such as silicon nitride or silicon oxide. The formation method may include CVD, atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), or other suitable deposition methods. The formation of the redistribution wiring 64 can be similar to the formation of the redistribution wiring 26 and will not be further described here.

[0027] FIG8 further illustrates the formation of dielectric layer 66, underbump metallurgy (UBM) 68, and electrical connector 70 according to some embodiments. Dielectric layer 66 may also be formed from a polymer such as polyimide, PBO, or the like. Underbump metallurgy (UBM) 68 extends into dielectric layer 66. To form UBM 68, an opening is formed in dielectric layer 66 to expose an underlying metal pad, which is part of redistribution trace 64. UBM 68 is then formed by a deposition process such as a PVD process. UBM 68 may be formed from or include nickel, copper, titanium, or multiple layers thereof.

[0028] Then, an electrical connector 70 is formed on the underbump metallurgy 68. The corresponding process is also shown as process 216 in the process flow 200, as shown in Figure 78. The electrical connector 70 can be formed by placing a solder ball on the exposed portion of the underbump metallurgy 68 and then reflowing the solder ball, so the electrical connector 70 is a solder area. According to other embodiments of the present disclosure, the formation of the electrical connector 70 includes performing an electroplating process to form a solder layer and then reflowing the solder layer. The electrical connector 70 can also include a non-solder metal pillar, or can have a composite structure including a metal pillar and a solder cap above the non-solder metal pillar, which can also be formed by electroplating. Throughout this specification, the structure above the release film 60 is referred to as the InFO package substrate 72. The InFO package substrate 72 can be a wafer-level package component that includes multiple identical InFO package substrates 72'.

[0029] Figures 9 through 16 illustrate the formation of a package by bonding the package components to opposite sides of an InFO package substrate 72. Details of the InFO package substrate 72 are not shown in these figures; reference is made to the previous figures for details. Surface conductive features 56BT, LSI die 30, and electrical connectors 70 are schematically illustrated to illustrate the front side (the side with electrical connectors 70) and back side (the side with conductive features 56BT) of the InFO package substrate 72. Figure 9 shows a simplified view of the structure shown in Figure 8, without showing details within the InFO package substrate 72.

[0030] Referring to FIG. 10 , multiple package components 74 are bonded to an InFO package substrate 72 . The corresponding process is shown as process 218 in process flow 200 , as shown in FIG. 78 . According to some embodiments, package components 74 include logic dies, which may be central processing unit (CPU) dies, graphics processing unit (GPU) dies, mobile application dies, microcontroller unit (MCU) dies, input / output (IO) dies, baseband (BB) dies, application processor (AP) dies, or combinations thereof. Package components 74 may also include memory dies, such as dynamic random access memory (DRAM) dies and static random access memory (SRAM) dies. Memory dies may be discrete memory dies or may be a die stack comprising multiple stacked memory dies. Package components 74 may also include system-on-chip (SOC) dies. Furthermore, package components 74 may include integrated passive device (IPD) dies, which may include passive components. Passive components may include capacitors, resistors, inductors, and the like.

[0031] Next, underfill 76 is dispensed into the gap between the package components 74 and the underlying InFO package substrate 72'. The corresponding process is shown as process 220 in process flow 200 and illustrated in FIG78 . According to some embodiments, multiple reinforcement rings 102 (not shown in FIG10 , see FIG37 ) may be attached to the InFO package substrate 72' via an adhesive film 104 (also shown in FIG37 ), each of the plurality of reinforcement rings 102 surrounding a group of package components 74. Each reinforcement ring 102 is positioned above one of the InFO package substrates 72'. The reinforcement rings 102 function to reduce warpage of the resulting package. According to some embodiments, the reinforcement rings are not yet attached.

[0032] Referring to FIG. 11 , package components 74 are encapsulated within an encapsulant 77 . The corresponding process is shown as process 222 in process flow 200 and as illustrated in FIG. 78 . Encapsulant 77 may be or may include a molding compound, a molding primer, an epoxy, a resin, and / or the like. Encapsulant 77 may include a substrate and filler particles within the substrate. The substrate may be a polymer, a resin, an epoxy, or the like. The filler particles may be dielectric particles such as silicon dioxide, aluminum oxide, or boron nitride, and may have a spherical shape. Encapsulant 77 fills the gaps between adjacent package components 74 . In some embodiments, no primer 76 is applied, and encapsulant 77 further fills the gaps between the InFO package base 72 and the upper package component 74 . In these embodiments, encapsulant 77 may be a molding primer.

[0033] Then, a planarization process is performed to flatten the top surface of encapsulant 77. According to some embodiments, after the planarization process, a portion or all of the back surface of package component 74 is exposed. This back surface may also be the back surface of the corresponding semiconductor substrate in package component 74. According to other embodiments, after the planarization process, a layer of encapsulant 77 remains to cover package component 74, and the top surface 77TS of encapsulant 77 is represented by a dotted line.

[0034] Next, a carrier separation process is performed. The corresponding process is shown as process 224 in process flow 200 and is shown in FIG78 . The InFO package substrate 72 is separated (disassembled) from the carrier 58. This separation can be achieved, for example, by projecting a light beam (which can be a laser beam) through the release film 60. The light beam penetrates the transparent carrier 58, thereby disintegrating the release film 60. The carrier 58 is separated from the release film 60, and the InFO package substrate 72 is thus separated (disassembled) from the carrier 58.

[0035] Next, the InFO package substrate 72 is placed on tape 80, which may be secured to a frame (not shown). The resulting structure is shown in FIG12 . The corresponding process is also shown as process 224 in process flow 200 , as shown in FIG78 . The backside of the package component 74 faces the tape 80 and may be in contact with the tape 80. The conductive features 56BT are exposed.

[0036] Referring to FIG. 13 , an electrical connector 82 , such as a solder area, is formed on the conductive feature 56BT. The conductive feature 56BT may be a metal pad, a metal pillar, an under-bump metallurgy, or the like. The corresponding process is shown as process 226 in process flow 200 , as shown in FIG. 78 . The electrical connector (such as the solder area) 82 is reflowed. Next, the device die 84 is bonded to the InFO package substrate 72 via some of the electrical connectors (such as the solder area) 82 . The corresponding process is shown as process 228 in process flow 200 , as shown in FIG. 78 . According to some embodiments, the device die 84 is an IPD die, which may include independent passive components such as capacitors, resistors, inductors, and / or the like. According to some embodiments, the device die 84 may include an active device.

[0037] FIG14 illustrates the bonding of a package substrate 86 to an InFO package substrate 72′ in the InFO package substrate 72. The corresponding process is shown as process 230 in process flow 200 and as shown in FIG78. Package substrate 86 may include an organic dielectric layer and may be referred to as an organic package substrate. Package substrate 86 may be a cored package substrate including a dielectric core or a coreless package substrate without a core. For example, package substrate 86 may include a dielectric core 88 (see FIG17 for details) and plated through holes (PTHs, i.e., conductive tubes) 90 therein. According to some embodiments, package substrate 86 is a discrete package substrate. According to some embodiments, package substrate 86 is in an unsawn wafer-level package substrate and is bonded to InFO package substrate 72 via wafer-to-wafer bonding. Package substrate 86 does not include active components such as transistors and diodes, nor may it include passive components such as capacitors, inductors, or resistors. Bonding may be achieved via electrical connectors (such as solder pads) 82. The backside (top side shown) of the device die 84 may be spaced apart from the corresponding underlying package substrate 86 or may be in contact therewith.

[0038] With further reference to FIG. 14 , an encapsulant 92 is dispensed to encapsulate the package substrate 86 therein. The corresponding process is shown as process 232 in process flow 200 , as shown in FIG. 78 . Encapsulant 92 fills the gap between adjacent package substrates 86 . Encapsulant 92 may include a molding underfill, which is also filled into the gap between the InFO package substrate 72 and the upper package substrate 86 . According to some embodiments, an underfill (not shown) may be dispensed to first fill the gap between the InFO package substrate 72 and the upper package substrate 86 , followed by dispensing encapsulant 92 , which may include a molding compound. Encapsulant 92 may include a base material and filler particles within the base material. The base material may be or may include a polymer, resin, epoxy, or the like. The filler particles may be dielectric particles such as silicon dioxide, aluminum oxide, boron nitride, or the like, and may have a spherical shape. Throughout this description, the structure above tape 80 is referred to as reconstituted wafer 96 .

[0039] FIG15 illustrates a singulation process for separating the reconstituted wafer 96 into discrete packages 96′. The corresponding process is shown as process 234 in process flow 200, as shown in FIG78. Throughout this description, the InFO package substrate 72′ and the corresponding overlying package substrate 86 are collectively referred to as a compound package substrate 98 because they include two types of package substrates, namely, the InFO package substrate 72′ and the package substrate 86. The InFO package substrate 72′ and the corresponding package substrate 86 are combined to serve as an integrated package substrate. The singulation process can be performed using a cutting tool or by a laser ablation process. According to some embodiments, in each package 96′, the encapsulant 92 may include portions that contact opposing sidewalls of the package substrate 86. According to some embodiments, the encapsulant 92 may also completely surround the package substrate 86.

[0040] FIG16 illustrates one of the packages 96′ according to some embodiments. As shown in FIG16 , a solder region 97 is formed on the package 96′. The solder region 97 can be electrically connected to an electrical connector (such as a solder region) 82 and an InFO package substrate 72′, and can also be electrically connected to the package assembly 74.

[0041] FIG17 shows a detailed view of package 96′ shown in FIG16 , according to some embodiments. In package 96′, compound encapsulation substrate 98 includes an InFO encapsulation substrate 72′ and an encapsulation substrate 86 bonded to each other. IPD die 84 may be bonded between InFO encapsulation substrate 72′ and encapsulation substrate 86. Encapsulation substrate 86 is encapsulated within encapsulation body 92. In other words, a portion of compound encapsulation substrate 98 is encapsulated within encapsulation body 92, while another portion of compound encapsulation substrate 98 (InFO encapsulation substrate 72′) is external to encapsulation body 92.

[0042] According to some embodiments, package assembly 74 includes package assembly (such as HBM) 74A, package assembly (such as package) 74B (which may also be or include a device die), and IPD die 74C. Each of package assembly (such as HBM) 74A, package assembly (such as package) 74B, and IPD die 74C may be directly bonded to InFO package substrate 72′.

[0043] According to some embodiments, the LSI die 30 is embedded in an InFO package substrate 72'. The LSI die 30 is used to electrically interconnect features above the LSI die 30 and features below the LSI die 30. The LSI die 30 is also used to electrically and signal interconnect package components 74. Embedding the LSI die 30 in the InFO package substrate 72' has several advantages. For example, if the LSI die 30 is built outside the InFO package substrate 72', the LSI die 30 will be built into a package that includes an interposer for bonding the LSI die 30 thereto. This allows the corresponding package components 74 interconnected by the LSI die 30 to be bonded to the interposer. The package components 74 electrically interconnected by the LSI die 30 will be at the same level and within the same package. Consequently, the package including the LSI die 30 and the interconnected package components 74 will be larger and occupy a larger die area. When this large package is bonded to the underlying package substrate, warpage of the resulting package will increase. Due to significant warping of large package components, the manufacturing yield of the resulting package will be reduced.

[0044] In contrast, when LSI die 30 is fabricated in an InFO package substrate 72' according to some embodiments of the present disclosure, each of the package components 74 (including package component (such as HBM) 74A, package component (such as package) 74B, and IPD die 74C) can be a discrete device die and / or a small package, and thus can be directly bonded to the underlying InFO package substrate 72'. For example, FIG. 17 illustrates five discrete small package components 74 bonded to the InFO package substrate 72'. Because the package components 74 are each small packages, the bonding yield is very high.

[0045] 17, the LSI die 30 has its upper side bonded to the front side redistribution trace 26 via solder regions 36. On the other hand, the lower side of the LSI die 30 is bonded to the underlying conductive features via no solder joints.

[0046] According to some embodiments, as shown in FIG. 17 , the singulation process ( FIG. 15 ) is performed by cutting through the middle portion of the portion of encapsulant 92 between adjacent package substrates 86 , thereby not cutting through package substrates 86 . Consequently, in package 96 ′, the remaining encapsulant 92 may form a complete ring that completely encapsulates package substrate 86 . According to these embodiments, the sidewalls / edges of package substrate 86 are laterally recessed from the corresponding sidewalls / edges of the upper package substrate 72 ′ and encapsulant 77 . Furthermore, InFO package substrate 72 ′ has a lateral dimension (length or width) L1, while package substrate 86 has a lateral dimension (length or width) L2 that is smaller than lateral dimension L1.

[0047] Figures 18 to 21 illustrate cross-sectional views of intermediate stages in the formation of packages according to some embodiments. These embodiments are similar to the embodiments of Figures 1 to 17 , but in the final package 96 ′, the encapsulant 92 has been removed from the sidewalls of the package substrate 86 . Unless otherwise noted, the materials and manufacturing processes of the components in these embodiments (as well as the embodiments of Figures 22 to 75 ) are substantially the same as those of the same components denoted by the same reference numerals in the aforementioned embodiments shown in Figures 1 to 17 . Therefore, details regarding the manufacturing processes and materials of the components shown in Figures 18 to 21 (as well as the embodiments of Figures 22 to 75 ) can be found in the discussion of the aforementioned embodiments.

[0048] The initial process for these embodiments is substantially the same as that shown in Figures 1 to 14. Figure 18 illustrates a reconstructed wafer 96 produced on tape 80. The illustrated reconstructed wafer 96 can be the same structure as that shown in Figure 14. The spacing between adjacent package substrates 86 can be small and can be smaller than the spacing in reconstructed wafer 96, as shown in Figure 14. Next, referring to Figure 19, a singulation process is performed. According to some embodiments, during the singulation process, the package substrates 86 are cut through, and edge portions of the package substrates 86 can be removed along with the encapsulant 92. In this way, portions of the encapsulant 92 between adjacent package substrates 86 are removed, and the sidewalls of the resulting package substrates 86 are exposed.

[0049] FIG20 illustrates a package 96' sawn from a reconstructed wafer 96 according to some embodiments. The detailed structure of the InFO package substrate 72' and the corresponding package 96' is shown in FIG21. According to some embodiments, as shown in FIG20 and FIG21, all portions of the encapsulant 92 surrounding the package substrate 86 are removed. Accordingly, the sidewalls of the package substrate 86 in the package 96' are fully exposed, and the exposed (four) sidewalls can form a complete ring. No portion of the encapsulant 92 remains on the sidewalls of the package substrate 86. According to these embodiments, the edges of the package substrate 86 are vertically aligned with the corresponding edges of the package substrate 72', the encapsulant 77, and the encapsulant 42. Furthermore, the InFO package substrate 72' has a lateral dimension L1, and the package substrate 86 has a lateral dimension L2 that is equal to the lateral dimension L1.

[0050] According to other embodiments, due to process variations, some portions of the encapsulant 92 surrounding the package substrate 86 are removed, while other portions may remain on the sidewalls of the package substrate 86. For example, the portion of the encapsulant 92 on the first sidewall (e.g., the left sidewall) of the package substrate 86 may be removed to expose the first sidewall of the package substrate 86. However, a portion of the package substrate 86 may remain on the second sidewall (e.g., the right sidewall) of the package substrate 86.

[0051] Figures 22 and 23 illustrate cross-sectional views of intermediate stages in package formation according to some embodiments of the present disclosure. These embodiments are similar to those of Figures 1 through 17 , except that a wafer-level package substrate, rather than a discrete package substrate, is first bonded to the InFO package substrate 72 , and the wafer-level package substrate is sawn into discrete package substrates.

[0052] The initial manufacturing process for these embodiments is essentially the same as that shown in Figures 1 to 13 . Next, as shown in Figure 22 , a wafer-level packaging substrate 86W is bonded to the InFO packaging substrate 72 . The wafer-level packaging substrate 86W can be a wafer or a packaging substrate strip comprising multiple packaging substrates 86 . Similar to the discrete packaging substrates 86 discussed in the previous embodiments, the packaging substrates 86 in the wafer-level packaging substrate 86W can also include organic dielectric layers and are sometimes referred to as organic packaging substrates. For example, the wafer-level packaging substrate 86W can include a dielectric core 88 (see also Figure 17 ) and a PTH (PTH) 90 therein. The dielectric core 88 and the dielectric layers above and below can extend continuously into each packaging substrate 86 without interruption or interfaces separating the dielectric portions of different packaging substrates 86 . The wafer-level packaging substrate 86W does not contain active components such as transistors or diodes, nor passive components such as capacitors. Furthermore, the packaging substrates 86 in the wafer-level packaging substrate 86W are identical to each other.

[0053] 22 , an encapsulant 92 is dispensed to encapsulate the wafer-level package substrate 86W therein. The encapsulant 92 may include a molding compound and may or may not include an underfill, thereby forming a reconstituted wafer 96 .

[0054] FIG23 illustrates a singulation process for separating reconstituted wafer 96 into discrete packages 96′. During the singulation process, portions of wafer-level package substrates 86W connecting adjacent package substrates 86 are severed, separating package substrates 86 from one another. The singulation process can be performed using a cutting tool or by a laser ablation process.

[0055] The resulting package 96' is substantially the same as that shown in FIG. 21 . According to these embodiments, all sidewalls of package substrate 86 in package 96' are exposed, and the exposed sidewalls can form a complete ring. Encapsulation body 92 does not include portions remaining on the sidewalls of package substrate 86. According to these embodiments, the edges of package substrate 86 are vertically aligned with corresponding edges of package substrate 72', encapsulation body 77, and encapsulation body 42. Furthermore, InFO package substrate 72' has a lateral dimension L1, and package substrate 86 has a lateral dimension L2 that is equal to lateral dimension L1.

[0056] Figures 24 through 31 illustrate cross-sectional views of intermediate stages in the formation of packages according to some embodiments of the present disclosure. These embodiments are similar to those of Figures 1 through 17 , except that the InFO package substrate 72 and the corresponding encapsulant 77 are sawn to form the package, and then the package is bonded to the package substrate 86 via die-to-wafer or die-to-die bonding. In contrast, in the previous embodiments, the InFO package substrate 72 and the corresponding encapsulant 77 are sawn after bonding to the package substrate 86, rather than before.

[0057] The initial manufacturing process for these embodiments is essentially the same as that shown in Figures 1 to 8 , in which an InFO package substrate 72 is formed. Figure 24 is a simplified diagram of the structure shown in Figure 8 , and therefore does not show the detailed structure of InFO package substrate 72. InFO package substrate 72 is located above carrier 58 . For details, refer to Figure 8 , for example. Surface conductive features 56BT, LSI die 30, and electrical connectors 70 are schematically illustrated to illustrate the front side (the side with electrical connectors 70) and back side (the side with conductive features 56BT) of InFO package substrate 72.

[0058] Referring to FIG. 25 , multiple package components 74 are bonded to an InFO package substrate 72 . While two package components 74 are shown as a group, each group may include more or fewer package components 74 . Next, underfill 76 is dispensed into the gaps between the package components 74 and the underlying InFO package substrate 72 ′. Underfills dispensed to different groups of package components 74 are separated from one another.

[0059] Next, referring to FIG. 26 , package component 74 is encapsulated in encapsulant 77, which may include a molding compound, an underfill, and the like. A planarization process is then performed to flatten the top surface of encapsulant 77. The top surface of encapsulant 77 thus formed may be flush with part or all of package component 74. According to some embodiments, a top surface 77TS of encapsulant 77 may be higher than the top surface of package component 74.

[0060] Next, the InFO package substrate 72 is separated (detached) from the carrier 58, for example by projecting a laser beam to decompose the release film 60. The InFO package substrate 72 is then placed on a tape 80, which may be secured to a frame (not shown). The resulting structure is shown in FIG27 . The backside of the package component 74 faces the tape 80 and may be in contact with it. The conductive features 56BT are exposed.

[0061] FIG28 illustrates forming electrical connections (such as solder areas) 82 on conductive features 56BT. Device die 84, which may be an IPD or may include an active device die, is then bonded to InFO package substrate 72 via electrical connections (such as solder areas 82). The resulting structure including InFO package substrate 72, package assembly 74, and encapsulant 77 is hereinafter referred to as reconstituted wafer 79.

[0062] Next, as shown in FIG29 , a singulation process is performed to saw the reconstructed wafer 79 to form discrete packages 79 ′. In subsequent processes, multiple packages 79 ′ are bonded to a wafer-level packaging substrate 86W (not shown), which may have the same structure as that shown in FIG22 . According to some embodiments, bonding is performed via die-to-wafer bonding, with the packages 79 ′ being in die form. After the bonding process, the packages 79 ′ are laterally separated from each other by gaps.

[0063] In subsequent manufacturing processes, underfill 81 ( FIG. 30 ) is dispensed into the gaps between package substrate 86 and the corresponding discrete packages 79 ′. A singulation process can then be performed to separate package substrates 86 from one another within wafer-level package substrate 86W. This results in packages 96 ′, as shown in FIG. 30 . In the resulting packages 96 ′, the edges of package substrate 86 extend laterally beyond the corresponding edges of package substrate 72 ′ and encapsulant 77 . Furthermore, InFO package substrate 72 ′ has a lateral dimension L1, and package substrate 86 has a lateral dimension L2 that is greater than lateral dimension L1.

[0064] FIG31 shows a cross-sectional view of a package 96′ according to some embodiments, wherein a reinforcement ring 102 is attached to the top surface of the package 96′ via an adhesive film 104. It should be understood that while the illustrated example package 96′ has a length L1 that is less than length L2, the package 96′ to which the reinforcement ring 102 is attached can have any of the configurations shown in the aforementioned embodiments, and the length L1 can be equal to or greater than the length L2. The reinforcement ring 102 functions to reduce warpage of the resulting package 96′. According to some embodiments, the reinforcement ring 102 is formed from a rigid metal material such as copper or stainless steel. According to some embodiments, the reinforcement ring 102 can have a top-view shape that is a complete ring without interruptions. The reinforcement ring 102 can also include four sections, each section being parallel to and adjacent to an edge of the package 79′. Alternatively, the reinforcement ring 102 can have a circular top-view shape.

[0065] Figures 32 and 33 illustrate cross-sectional views of intermediate stages in the formation of a package including a metal lid according to some embodiments of the present disclosure. Referring to Figure 32 , a package 96' is formed. While one embodiment is shown, package 96' can have any of the structures shown in the aforementioned embodiments. At least some (and possibly all) of the top surface of package component 74 is exposed. For example, the silicon substrate of package component 74 can be exposed.

[0066] Referring to FIG. 33 , a lid (heat sink) 106 is attached to package 96 ′. This attachment is achieved via a thermal interface material (TIM) 108 that contacts the top surface of package component 74 . TIM 108 is a highly thermally conductive adhesive having, for example, a thermal conductivity greater than approximately 1 W / (k*m), 5 W / (k*m), or even higher. Lid 106 may be formed from or include a metal such as copper, aluminum, stainless steel, or alloys thereof. According to some embodiments, package 96 ′ is a large package. Therefore, an adhesive film 110 may be applied to improve adhesion of lid 106 to package 96 ′. According to some embodiments, adhesive film 110 has stronger adhesion to package 96 ′ than TIM 108, but has a lower thermal conductivity than TIM 108. According to some embodiments, adhesive film 110 is applied to areas where package component 74 is not present. Thus, the entire adhesive film 110 can be separated from the entire package component 74. Furthermore, the adhesive film 110 may surround the thermal interface material 108, wherein the top view shape of the adhesive film 110 is a complete ring.

[0067] 33 , the adhesive film 110 may be separated from the thermal interface material 108 by a gap 112. According to some embodiments, the gap 112 forms a complete gap ring surrounding the thermal interface material 108 and surrounded by the adhesive film 110. This allows for process margins to be allocated for the adhesive film 110 and the thermal interface material 108.

[0068] FIG34 illustrates a package according to some embodiments of the present disclosure. The package in FIG34 is similar to the structure shown in FIG33 . According to these embodiments, adhesive film 110 is in physical contact with and surrounds thermal interface material 108, with no gap therebetween. Adhesive film 110 and thermal interface material 108 form an interface 111. In FIG33 and FIG34 , some device dies, such as IPD die 74C, are covered by the top surface layer of encapsulant 77. IPD die 74C may overlap one or both (partially overlap) of thermal interface material 108 and adhesive film 110.

[0069] FIG35 illustrates a cross-sectional view of a package 96′ according to some embodiments of the present disclosure. These embodiments are similar to the embodiment shown in FIG31 , with some details being described. The relative lateral dimensions L1 of the package 79′ and the lateral dimension L2 of the package substrate 86 differ from those shown in FIG31 . For example, in FIG35 , the InFO package substrate 72′ has a lateral dimension L1, while the package substrate 86 has a lateral dimension L2 that is smaller than the lateral dimension L1. In contrast, in the embodiment shown in FIG31 , the InFO package substrate 72′ has a lateral dimension L1, while the package substrate 86 has a lateral dimension L2 that is larger than the lateral dimension L1.

[0070] According to some embodiments, there are some device dies, such as IPD die 74C, that are covered by the top surface layer of encapsulant 77. According to some embodiments, stiffener ring 102 completely or partially overlaps IPD die 74C. According to some embodiments, stiffener ring 102 does not overlap any IPD die 74C.

[0071] 36 shows a cross-sectional view of a package 96' according to some embodiments of the present disclosure. These embodiments are similar to the embodiment shown in FIG17, except that the encapsulant 77 includes a top surface portion covering all package components 74 after being planarized.

[0072] FIG37 illustrates a cross-sectional view of a package 96′ according to some embodiments of the present disclosure. These embodiments are similar to the embodiment shown in FIG17 , but include a reinforcement ring 102. The reinforcement ring 102 can be attached to the InFO package substrate 72′ via an adhesive film 104. The attachment process can be performed after the process shown in FIG10 and before the process shown in FIG11 . According to some embodiments, during the planarization of the encapsulation 77, the reinforcement ring 102 is planarized and exposed after planarization, as shown in FIG37 . According to some embodiments, the reinforcement ring 102 is embedded in the encapsulation 77 after the planarization. Thus, a layer of the encapsulation 77 covers and overlaps the reinforcement ring 102.

[0073] Figures 38 to 43 illustrate cross-sectional views of intermediate stages in the formation of a package including through-holes for electrical connections according to some embodiments of the present disclosure. The through-holes are used to electrically connect the InFO package substrate 72' to other package components. These embodiments are similar to the embodiments of Figures 1 to 17, except that in these embodiments (Figures 38 to 43), the InFO package substrate 72 and the corresponding encapsulant 77 are first sawn to form discrete packages, which are then bonded to the package substrate 86 via die-to-wafer or die-to-die bonding. In contrast, in the embodiments of Figures 1 to 17, the InFO package substrate 72 and the corresponding encapsulant 77 are sawn after bonding to the package substrate 86, rather than before. Similar to the embodiments of Figures 24 to 30, additional through-holes are also formed in these embodiments (Figures 38 to 43).

[0074] Similarly, details of the InFO package substrate 72 are not shown in Figures 38 to 43 , but reference can be made to the embodiment shown in Figure 8 for details. Surface conductive features 56BT, LSI die 30, and electrical connectors 70 are schematically illustrated to illustrate the front side (the side with electrical connectors 70) and back side (the side with conductive features 56BT) of the InFO package substrate 72. Figure 38 shows a simplified view of the structure shown in Figure 8 , without showing details of the InFO package substrate 72. The InFO package substrate 72 is formed over a carrier 58 and a release film 60.

[0075] Referring to FIG39 , a plurality of through-holes 114 are formed above the InFO package substrate 72 and are electrically connected to the redistribution lines within the InFO package substrate 72. The formation of the through-holes 114 may include depositing a metal seed layer (not shown) on the exposed top surface layer and the exposed redistribution lines in the InFO package substrate 72, forming a patterned electroplating mask (not shown) such as a photoresist on the metal seed layer, and then performing a metal electroplating process to deposit a metal material on the exposed metal seed layer. According to some embodiments of the present disclosure, the metal seed layer includes a titanium layer and a copper layer above the titanium layer. The metal seed layer can be formed using a process such as PVD. Electroplating can be performed using an electrochemical plating process, for example. The patterned electroplating mask and the portion of the metal seed layer covered by the patterned electroplating mask are then removed, leaving the through-holes 114, as shown in FIG39 . The through-holes 114 are electrically connected to the redistribution lines within the InFO package substrate 72′.

[0076] According to some embodiments, instead of forming through-holes 114 in the InFO package substrate 72', a stiffener ring 102 (see also FIG. 37 ) is adhered to the InFO package substrate 72' at this time. Therefore, corresponding features are labeled 114 / 102 to indicate that these features can be through-holes 114 or stiffener rings 102. According to some embodiments, both through-holes 114 and stiffener rings 102 are formed / attached, with stiffener rings 102 surrounding through-holes 114. When stiffener rings 102 are used, adhesive film 104 is also used, whereas when through-holes 114 are formed, adhesive film 104 is not used.

[0077] With further reference to FIG. 39 , multiple package components 74 are bonded to the InFO package substrate 72 . Package components 74 may include logic dies, memory dies, IPD dies, packages, and the like. Bonding may be performed using solder bonding, direct metal-to-metal bonding, hybrid bonding, and the like. Next, underfill 76 is dispensed into the gaps between package components 74 and the underlying InFO package substrate 72 ′. During dispensing, underfill 76 may be spaced apart from the through-vias 114 .

[0078] According to some embodiments, there are multiple groups of identical package components 74, each spaced apart to allow space for placement of reinforcement rings 102 and / or formation of through-holes 114. The inter-group spacing between adjacent groups of package components 74 may be greater than the intra-group spacing between package components 74 within the same group. Each reinforcement ring 102 may surround a group of package components 74. When reinforcement rings 102 are used, the resulting structure is similar to that shown in FIG. 37 .

[0079] Referring to FIG. 40 , package components 74, through-holes 114, and stiffener rings 102 (if attached) are encapsulated in an encapsulant 77. Encapsulant 77 may be or include a molding compound, a molding underfill, an epoxy, a resin, and / or the like. Encapsulant 77 fills the gaps between adjacent package components 74, through-holes 114, and stiffener rings 102. A planarization process is then performed to flatten the top surface of encapsulant 77. In some embodiments, after the planarization process, the backside of package components 74 is exposed. In other embodiments, after the planarization process, a layer of encapsulant 77 remains covering package components 74, with the corresponding top surface 77TS of encapsulant 77 represented by a dashed line. Through-holes 114 (if formed) are exposed after the planarization process. If stiffener ring 102 is formed, it may also be exposed after the planarization process. Alternatively, stiffener ring 102 may still be covered by a thin layer of encapsulant 77 after the planarization process. In this way, a reconstructed wafer 79 is formed.

[0080] Next, the reconstituted wafer 79 is separated (disassembled) from the carrier 58. This separation process can be performed, for example, by projecting a beam (which can be a laser beam) through the release film 60, with the beam penetrating the transparent carrier 58. This decomposes the release film 60. The carrier 58 is separated from the InFO package substrate 72, and the InFO package substrate 72 is thus separated (disassembled) from the carrier 58. The InFO package substrate 72 is then placed on a tape 80, which can be secured to a frame (not shown). The resulting structure is shown in FIG41. The backside of the package component 74 faces the tape 80 and may be in contact with it. The conductive features 56BT are exposed.

[0081] Referring to FIG. 42 , electrical connectors (such as solder pads) 82 are formed on conductive features 56BT, and then reflow is performed. Next, device die 84 is bonded to InFO package substrate 72 via electrical connectors (such as solder pads 82 ). According to some embodiments, device die 84 is an IPD die, which may include passive components such as capacitors, resistors, inductors, and / or the like. According to some embodiments, device die 84 may include active devices. In this manner, reconstituted wafer 79 is formed.

[0082] Next, as also shown in FIG42 , the sawn reconstructed wafer 79 undergoes a singulation process to form discrete packages 79 ′. In subsequent processes, the plurality of packages 79 ′ are bonded to a wafer-level packaging substrate 86W (not shown; see FIG22 ), which includes a plurality of unsawn package substrates 86 . Bonding can be performed via die-to-wafer bonding, where each of the packages 79 ′ is die-bonded to one of the package substrates 86 in the wafer-level packaging substrate 86 ′. After bonding, the packages 79 ′ are laterally separated from each other by gaps.

[0083] In subsequent manufacturing processes, underfill 81 ( FIG. 43 ) is dispensed into the gaps between package substrate 86 and the corresponding discrete packages 79 ′. A singulation process can then be performed to separate package substrates 86 from each other within wafer-level package substrate 86W. This results in packages 96 ′, one of which is shown in FIG. In the resulting package 96 ′, the edges of package substrate 86 extend laterally beyond the corresponding edges of package substrate 72 ′ and encapsulation body 77 . Furthermore, InFO package substrate 72 ′ has a lateral dimension L1 , while package substrate 86 has a lateral dimension L2 that is greater than lateral dimension L1 . In FIG. 43 , features labeled 114 / 102 represent one or both of through-hole 114 and reinforcement ring 102 . Because adhesive film 104 is used to adhere reinforcement ring 102 , it is not formed when through-hole 114 is formed. Therefore, in FIG. 43 , adhesive film 104 is marked with a dashed line to indicate whether or not adhesive film 104 may be used.

[0084] Figures 44-47 illustrate cross-sectional views of intermediate stages of package formation according to some embodiments of the present disclosure, wherein through-holes 114 are formed for electrical connection purposes. Through-holes 114 are used to electrically connect the InFO package substrate 72' to other package components. These embodiments are similar to those shown in Figures 38-42, but in Figures 38-42, the InFO package substrate 72 and the corresponding encapsulant 77 are first sawn to form discrete packages, which are then bonded to the package substrate 86 via die-to-wafer or die-to-die bonding. In contrast, in the embodiments shown in Figures 44-47, the InFO package substrate 72 and the corresponding encapsulant 77 are sawn after bonding to the package substrate 86, rather than before.

[0085] The initial process of these embodiments is basically the same as that shown in Figures 38 to 42, but the segmentation process shown in Figure 42 is not performed. Therefore, according to this embodiment, the structure shown in Figure 42 (before being segmented) is the initial structure.

[0086] Next, FIG. 44 illustrates the bonding of multiple packaging substrates 86 to the InFO packaging substrate 72. The packaging substrates 86 may include an organic dielectric layer, sometimes referred to as organic packaging substrates. The packaging substrates 86 may be cored packaging substrates, including a core and PTHs. According to some embodiments, as shown in FIG. 44 , the packaging substrates 86 are discrete packaging substrates, physically separated from one another. According to some embodiments, the packaging substrates 86 are in an unsawn wafer 86W ( FIG. 22 ) and are bonded to the InFO packaging substrate 72 via wafer-to-wafer bonding.

[0087] With further reference to FIG. 44 , an encapsulant 92 is dispensed. Encapsulant 92 fills the gap between package substrate 86 and the underlying InFO package substrate 72. In some embodiments employing discrete package substrates 86, encapsulant 92 also fills the gap between adjacent package substrates 86. Encapsulant 92 may include a mold underfill, which also fills the gap between InFO package substrate 72 and the upper package substrate 86. In this manner, a reconstructed wafer 96 is formed.

[0088] FIG45 illustrates a singulation process for separating the reconstructed wafer 96 into discrete packages 96′. The InFO package substrate 72′ and the corresponding package substrate 86 are combined as an integrated package substrate. The singulation process can be performed using a cutter or by a laser ablation process. According to some embodiments, as shown in FIG45 , the singulation process is performed by cutting through the middle portion of the portion of the encapsulant 92 between adjacent package substrates 86 without cutting through the package substrate 86. Thus, in each package 96′, the encapsulant 92 can completely surround the package substrate 86. According to some embodiments, the singulation process is performed by cutting through the encapsulant 92 and the edge portion of the package substrate 86. Thus, in each package 96′, the encapsulant 92 can be removed from a sidewall of the package substrate 86, and the sidewall of the package substrate 86 is exposed after the singulation process.

[0089] FIG46 illustrates a cross-sectional view of one of the packages 96', according to some embodiments. The exemplary embodiment shown in FIG46 shows that the edge of package substrate 86 is laterally recessed from the corresponding edge of INFO package substrate 72'. Thus, in package 96', the remaining encapsulation body 92 may form a complete ring around package substrate 86. According to some embodiments, the edge of package substrate 86 may be vertically aligned with the corresponding edge of INFO package substrate 72'. Thus, in the structure shown in FIG46, INFO package substrate 72' has a lateral dimension L1, and package substrate 86 has a lateral dimension L2 that is smaller than lateral dimension L1.

[0090] 46 shows arrows 120 indicating that the edge of package substrate 86 may also extend to align vertically with the edge of InFO package substrate 72'. In the corresponding package 96', package substrate 86 would have a lateral dimension L2 equal to the lateral dimension L1 of InFO package substrate 72'.

[0091] FIG47 illustrates a cross-sectional view of an embodiment in which through-vias 114 are formed. Thus, according to some embodiments, package 96′ is bonded to package component 123. This bonding can be performed, for example, via solder regions 122. Solder regions 122 may be in physical contact with through-vias 114 and conductive features 124 within package component 123. Conductive features 124 may be or include metal pads, metal pillars, under-bump metallurgy, and the like. Underfill 125 may be dispensed between package 96′ and package component 123. According to some embodiments, package component 123 may include a memory die, a logic die, an IPD die, a package, or a combination thereof. Package component 123 may be electrically connected to package component 74 via through-vias 114 and redistribution traces in InFO package substrate 72′. Package component 123 may also be electrically connected to package substrate 86 via LSI die 30, and may also be electrically connected via metal pillars (through-vias) 28.

[0092] FIG48 shows a cross-sectional view of package 96′ according to some embodiments of the present disclosure. According to some embodiments, the edge of encapsulant 77 is laterally recessed from the edge of InFO package substrate 72′ to allow space for stiffener ring 102. This can be achieved, for example, by using a mold designed for dispensing encapsulant 77. Portions of the mold may occupy area (space) 127, so that encapsulant 77 does not fill area 127. After dispensing encapsulant 77, stiffener ring 102 is attached to InFO package substrate 72′ via adhesive film 104.

[0093] According to some embodiments, package component (such as a package) 74E is directly bonded to InFO package substrate 72′ along with other package components (e.g., package component (such as an HBM) 74A and device die 74D). According to some embodiments, package component 74E includes an interposer 74F and a package component (such as a package) 74B (e.g., a device die) bonded to interposer 74F. Interposer 74F may be a silicon interposer including a silicon substrate 126 and a through-via 128 extending through silicon substrate 126.

[0094] As shown in FIG48 (and in previous embodiments), LSI die 30 is built into InFO package substrate 72. LSI die 30 is used to electrically and signal interconnect package component 74. It will be appreciated that LSI die 30 is not within package component (such as package) 74E. Instead, LSI die 30 is within InFO package substrate 72′. In contrast, in a related configuration, LSI die 30 would be built into package component (such as package) 74E and bonded to the bottom side of interposer 74F. Package components electrically interconnected via LSI die 30 would be bonded to the top side of interposer 74F. For example, in a related configuration where LSI die 30 is not within InFO package substrate 72′, package component 74A would also be built into package component (such as package) 74E together with package component 74B, allowing LSI die 30 to electrically interconnect package components 74A and 74B. Consequently, package component (such as package) 74E would be larger. Due to the significant warpage of large package components, the bonding yield can be reduced.

[0095] FIG49 shows a cross-sectional view of a package 96′ formed according to some embodiments. This embodiment is similar to the embodiment shown in FIG48 , except that package substrate 86 is wider than and laterally extends beyond the edges of InFO package substrate 72′. According to some embodiments, the edges of encapsulation body 77 are laterally recessed from the edges of InFO package substrate 72′ to allow space for reinforcement ring 102. This can be achieved, for example, by using a mold having portions that occupy area (space) 127 (not intended to be filled with encapsulation body 77). Reinforcement ring 102 is attached to InFO package substrate 72′ via adhesive film 104 and is positioned in area 127.

[0096] FIG50 illustrates a cross-sectional view of a package 96' formed according to some embodiments. This embodiment is similar to the embodiment shown in FIG31, except that, whereas in the embodiment shown in FIG31, the lateral dimension L1 of the InFO package substrate 72' is smaller than the lateral dimension L2 of the package substrate 86, in the embodiment shown in FIG50, the lateral dimension L1 of the InFO package substrate 72' is larger than the lateral dimension L2 of the package substrate 86. FIG50 also shows arrows 120 to indicate that the edges of the package substrate 86 can be vertically aligned with corresponding edges of the InFO package substrate 72'. In FIG50, the four side portions of the reinforcement ring 102 can be parallel to and adjacent to the edges of the package 79', which includes the InFO package substrate 72' and the package assembly 74. The outer edges of the reinforcement ring 102 can be vertically aligned with the corresponding edges of the InFO package substrate 72' (or can be laterally recessed).

[0097] Figures 51 to 60 illustrate cross-sectional views of intermediate stages in the package formation process according to some embodiments of the present disclosure. These embodiments are similar to those shown in Figures 1 to 17 , but in the embodiments shown in Figures 51 to 60 , package component 74 is first encapsulated in encapsulation body 77 to form a reconstituted wafer, and the reconstituted wafer is then bonded to InFO package substrate 72 via wafer-to-wafer bonding. In contrast, in the aforementioned embodiments shown in Figures 1 to 17 , package component 74 is first bonded to InFO package substrate 72 via die-to-wafer bonding, and the bonded package component 74 is then encapsulated in encapsulation body 77.

[0098] Referring to FIG. 51 , a carrier 130 is provided, and a release film 132 is coated on the carrier 130. The carrier 130 is formed of a transparent material, such as a glass carrier, a ceramic carrier, or the like. The release film 132 may be formed of an LTHC coating material. The release film 132 may be applied to the carrier 130 by coating. According to some embodiments, the LTHC coating material can be decomposed by the heat energy of light / radiation (e.g., a laser beam), thereby allowing the carrier 130 to be released from the structure formed thereon.

[0099] Next, as also shown in FIG51 , package components 74 are placed on carrier 130. According to some embodiments, package components 74 are placed front-side up, with electrical connectors 70 ′, such as solder pads, metal pillars, metal pads, and / or the like, on the top surface of package components 74. Package components 74 may include logic dies, memory dies, IPD dies, etc. The spacing between package components 74 is aligned with the positions of electrical connectors 70 in InFO package substrate 72 ( FIG8 and FIG9 ), so that electrical connectors 70 ′ are aligned with electrical connectors 70 during the subsequent bonding process ( FIG54 ).

[0100] Referring to FIG. 52 , package components 74 are encapsulated in an encapsulant 77. Encapsulant 77 may be or include a molding compound, a molding primer, an epoxy, a resin, and / or the like. Encapsulant 77 may include a base material and filler particles within the base material. The base material may be a polymer, a resin, an epoxy, or the like. The filler particles may be dielectric particles such as silicon dioxide, aluminum oxide, or boron nitride and may have a spherical shape. Encapsulant 77 fills the gaps between adjacent package components 74. When encapsulant 77 is dispensed, the top surface of encapsulant 77 is higher than electrical connectors 70 ′. Next, encapsulant 77 is planarized in a planarization process such as a CMP process or a mechanical polishing process. Thus, electrical connectors 70 ′ are exposed after the planarization process. The resulting structure, including package components 74 and encapsulant 77, is collectively referred to as a reconstituted wafer 134 .

[0101] Next, the reconstructed wafer 134 is separated (disassembled) from the carrier 130. This separation can be achieved, for example, by projecting a light beam (such as a laser beam) through the release film 132. The light beam penetrates the transparent carrier 130, causing the release film 132 to decompose under the thermal energy of the light beam. The reconstructed wafer 134 is then removed from the carrier 130.

[0102] 53 , reconstituted wafer 134 is placed on tape 80 , which may be secured to a frame (not shown). The front side of package assembly 74 , including electrical connector 70 ′, faces tape 136 and may be in contact with tape 136 .

[0103] FIG53 further illustrates the singulation process used to separate reconstituted wafer 134 into discrete packages 134′. The singulation process can be performed using a cutter or by a laser ablation process. In each package 134′, encapsulant 77 can have a top surface coplanar with the back surface of package element 74 and a bottom surface coplanar with the bottom surface of electrical connector 70′.

[0104] FIG54 illustrates the bonding of package 134′ to InFO package substrate 72′ in InFO package substrate 72. InFO package substrate 72 can be placed on carrier 138 via release film 140. Carrier 138 can be a transparent carrier, such as a glass carrier. According to some embodiments, release film 140 can be a thermal release film, such as an LTHC film. Details of the materials, structure, and formation process of InFO package substrate 72 are not described here; for details, reference can be made to the embodiments shown in FIG1 through FIG8. Surface conductive features 56BT, LSI die 30, and electrical connector 70 are schematically illustrated to illustrate the front side (the side with electrical connector 70) and back side (the side with conductive features 56BT) of InFO package substrate 72.

[0105] The bonding of the package 134' to the InFO package substrate 72' can be achieved through the electrical connector 70. The solder in the electrical connector 70' (Figure 53) may be merged with the solder in the electrical connector 70, so the electrical connector 70' is not described separately. According to some embodiments, there is no underfill extending into the gap between the package component 74 and the InFO package substrate 72'. The entire bottom surface of the encapsulant 77 in the same package 134' can be coplanar and the entire bottom surface of the encapsulant 77 can physically contact the corresponding underlying InFO package substrate 72', or the entire bottom surface of the encapsulant 77 can be higher than and spaced apart from the corresponding underlying InFO package substrate 72'.

[0106] Next, referring to FIG. 55 , another encapsulation process is performed. Thus, package 134′ is encapsulated in encapsulant 142. Encapsulant 142 can also be a molding compound, molding primer, resin, epoxy, etc. Encapsulant 142 can also include a base material and filler particles within the base material. The base material can be a polymer, resin, epoxy, etc. The filler particles can be dielectric particles such as silicon dioxide, aluminum oxide, boron nitride, etc., and can have a spherical shape. Because encapsulant 77 has been sawn through the process shown in FIG. 53 , and some of the filler particles within encapsulant 77 have been sawn into partially spherical particles, a distinguishable interface exists between encapsulant 77 and encapsulant 142. In some embodiments, encapsulant 77 and encapsulant 142 are of the same type, for example, both using the same type of molding compound. In other embodiments, encapsulant 77 and encapsulant 142 are different, for example, using different types of base materials, filler particles of different materials, and / or filler particles of different sizes.

[0107] According to some embodiments, a stiffening ring is not used in package 134', as shown in FIG55. According to some embodiments, stiffening ring 102 may also be attached to InFO package substrate 72'. Stiffening ring 102 may be attached at some time after the structure shown in FIG54 is formed and before encapsulation 142 is dispensed. Thus, stiffening ring 102 will be encapsulated within encapsulation 142 and may be in contact with the sidewalls of encapsulation 77 or may be spaced apart from the sidewalls of encapsulation 77. The resulting package 96' is similar to that shown in FIG37, but both encapsulation 77 and encapsulation 142 are present, and stiffening ring 102 is encapsulated within encapsulation 142. According to some embodiments, encapsulation 142 is not dispensed, resulting in a structure similar to that shown in FIG48.

[0108] After encapsulant 142 is applied, a planarization process, such as a CMP process or a mechanical polishing process, may be performed to polish encapsulant 142. According to some embodiments, both encapsulant 77 and package component 74 are exposed after the planarization process. According to other embodiments, after the planarization process, a layer of encapsulant 142 may cover encapsulant 77 and package component 74, wherein the layer of encapsulant 142 has a top surface 142'. Throughout this description, the structure located above release film 140 and including package component 74, encapsulant 142, and InFO package substrate 72 may be collectively referred to as a reconstituted wafer 79.

[0109] Next, the reconstructed wafer 79 is separated (disassembled) from the carrier 138. This separation can be achieved, for example, by projecting a light beam (such as a laser beam) through the release film 140. The light beam penetrates the transparent carrier 138, thereby disintegrating the release film 140. Thus, the reconstructed wafer 79 can be separated (disassembled) from the carrier 138.

[0110] Reconstituted wafer 79 is then placed on tape 144, which may be secured to a frame (not shown). The resulting structure is shown in FIG56. According to some embodiments, package assembly 74 may be in contact with tape 144. Conductive features (such as metal pads) 56BT are exposed.

[0111] Referring to FIG. 57 , electrical connectors (such as solder areas) 82 are formed on conductive features 56BT. Conductive features 56BT may be metal pads, metal pillars, under-bump metallurgy (UBM), etc. Electrical connectors (such as solder areas) 82 are reflowed. Next, device die 84 is bonded to InFO package substrate 72 via some of the electrical connectors (such as solder areas) 82. According to some embodiments, device die 84 is an IPD die, which may include passive components such as capacitors, resistors, inductors, and / or the like. According to some embodiments, device die 84 may include active devices.

[0112] FIG58 illustrates the bonding of package substrate 86 to InFO package substrate 72. Package substrate 86 may include an organic dielectric layer, sometimes referred to as an organic package substrate. Package substrate 86 may be a cored package substrate including a core (including a dielectric core and PTHs), or a coreless package substrate lacking a core. In some embodiments, package substrate 86 is a discrete package substrate and is bonded to InFO package substrate 72 via die-to-wafer bonding. In some embodiments, package substrate 86 is located within an uncut wafer and is bonded to InFO package substrate 72 via wafer-to-wafer bonding. Active components such as transistors and diodes are absent from package substrate 86. Bonding may be achieved via electrical connectors (such as solder pads) 82. The backside (top side in the illustration) of device die 84 may be spaced apart from or in contact with the corresponding underlying package substrate 86.

[0113] With further reference to FIG. 58 , an encapsulant 92 is dispensed to encapsulate the package substrates 86 . Encapsulant 92 fills the gaps between adjacent package substrates 86 . Encapsulant 92 may include a mold underfill, which also fills the gaps between the InFO package substrate 72 and the upper package substrate 86 . Encapsulant 92 may include a base material, such as a polymer, resin, or epoxy resin, and filler particles within the base material. The filler particles may be dielectric particles such as silicon dioxide, aluminum oxide, or boron nitride, and may have a spherical shape. Throughout this description, the structure above tape 144 is referred to as a reconstituted wafer 96 .

[0114] FIG59 illustrates a singulation process for separating reconstituted wafer 96 into discrete packages 96′. The singulation process can be performed using a cutter or by a laser ablation process. According to some embodiments, in package 96′, some remaining portions of encapsulant 92 may remain on the sidewalls of package substrate 86, completely surrounding package substrate 86. According to some embodiments, encapsulant 92 and edge portions of package substrate 86 are cut through during the singulation process, and encapsulant 92 is removed from the sidewalls of package substrate 86. As a result, the sidewalls of package substrate 86 may be exposed.

[0115] According to some embodiments, as shown in FIG59 , the middle of encapsulant 142 is sawn, leaving portions of encapsulant 142 on opposite sides of the sawing line. Thus, in package 96 ′, encapsulant 142 is left. According to some embodiments, encapsulant 142 may form a complete ring surrounding encapsulant 77 . According to some embodiments, during the singulation process, encapsulant 142 may be completely removed, resulting in package 96 ′ without encapsulant 142.

[0116] FIG60 shows a cross-sectional view of package 96′ according to some embodiments. These embodiments are similar to the embodiment of FIG17 , but may include an encapsulation 142 and a reinforcement ring 102. Package 96′ may include encapsulation 77, and package 96′ may or may not include encapsulation 142. According to some embodiments, reinforcement ring 102 may be attached to the top of package 96′. According to yet other embodiments, reinforcement ring 102 is not employed. Therefore, reinforcement ring 102 on the top of package 96′ is shown as a dashed line to indicate that it may or may not be attached.

[0117] Furthermore, as described in the previous embodiments, the stiffener ring 102 may (or may not) be attached to the InFO package substrate 72' prior to dispensing the enclosure 142. Thus, according to some embodiments, the stiffener ring 102 may be within the enclosure 142. The stiffener ring 102 is also shown as a dashed line to indicate that it may or may not be employed.

[0118] FIG61 shows a cross-sectional view of package 96′ according to some embodiments. These embodiments are similar to those in FIG17 , but with the addition of a stiffening ring 102 and a heat sink 148. Heat sink 148 is attached to package 96′ via thermal interface material 146. Heat sink 148 may be formed from or include a metal material such as copper, stainless steel, nickel, aluminum, or alloys thereof. According to some embodiments, stiffening ring 102 may be attached to InFO package base 72 and may be in contact with thermal interface material 146. According to some embodiments, stiffening ring 102 is not attached.

[0119] FIG62 shows a cross-sectional view of a package 96′ according to some embodiments. These embodiments are similar to those of FIG17 , but the LSI die 30 is bonded to the upper structure not via solder pads. Instead, non-solder joints are formed via metal pillars 23. Thus, the LSI die 30 is bonded to both the upper and lower structures via non-solder joints.

[0120] 63 to 69 illustrate cross-sectional views of intermediate stages in the formation of the package 96' shown in FIG. 62, according to some embodiments. Unless otherwise noted, the features discussed below may be identical to those disclosed in FIG. 1 to 17. Therefore, the corresponding details are not repeated here.

[0121] Referring to Figure 63, a carrier 20 is provided, and a release film 22 is coated on the carrier 20. Then, a redistribution circuit 26 is formed on the release film 22. According to some embodiments, a buffer dielectric layer (such as PBO, polyimide, etc., not shown) may exist (or may not exist) above the release film 22, wherein the redistribution circuit 26 is formed above the buffer dielectric layer and in contact with the buffer dielectric layer. According to some embodiments, the redistribution circuit 26 includes a line portion and does not include a through-hole portion. The redistribution circuit 26 can be formed by electroplating. Alternatively, the redistribution circuit 26 can be formed by depositing a blanket metal layer and patterning the blanket metal layer. It should be understood that although a layer of redistribution circuit 26 is shown, multiple layers of redistribution circuit 26 can be formed.

[0122] After redistribution lines 26 are formed, metal pillars 28 can be formed. Forming metal pillars 28 may include depositing a metal seed layer above redistribution lines 26 and forming a patterned plating mask (not shown) that exposes portions of the metal seed layer. An electroplating process is then performed to electroplate metal material into the openings in the patterned plating mask. The patterned plating mask is then removed, followed by etching of the exposed portions of the metal seed layer. The electroplated metal material and the remaining portions of the metal seed layer combine to form metal pillars 28.

[0123] An LSI die 30 is placed on top of the release film 22. The front side of the LSI die 30 faces the release film 22, and the semiconductor substrate 32 of the LSI die 30 faces upward. Furthermore, the LSI die 30 is not placed on the redistribution trace 26. According to some embodiments, each LSI die 30 includes a metal pillar 23 and a dielectric layer 25 in which the metal pillar 23 is embedded. The dielectric layer 25 may be in contact with the release film 22 (or, if a buffer dielectric layer is used, with the buffer dielectric layer).

[0124] Referring to FIG. 64 , metal pillars 28 and LSI die 30 are encapsulated in encapsulation body 42. Encapsulation body 42 may include a molding compound, a molding underfill, an epoxy resin, and / or a resin. A planarization process, such as a CMP process or a mechanical polishing process, is then performed until metal pillars 28 are exposed, thereby thinning encapsulation body 42 and LSI die 30. Furthermore, through-holes 34 in LSI die 30 are exposed. The resulting structure is shown in FIG. 64 . Because metal pillars 28 penetrate encapsulation body 42, they are hereinafter alternatively referred to as metal pillars (through-holes) 28.

[0125] FIG65 illustrates forming a redistribution wiring structure 52 on an LSI die 30 and electrically connected to the LSI die 30. The process and detailed structure can be seen in the embodiments shown in FIG5 and FIG6. Thus, a portion of the InFO package substrate 72 is formed.

[0126] With further reference to FIG. 65 , electrical connectors (such as solder pads) 82 are formed on conductive features 56BT, which are surface conductive features of redistribution structure 52 . Next, device die 84 is bonded to InFO package substrate 72 via electrical connectors (such as solder pads 82 ). According to some embodiments, device die 84 is an IPD die, which may include passive components such as capacitors, resistors, inductors, and / or the like. According to some embodiments, device die 84 may also include an active die.

[0127] In the subsequent process, the carrier exchange process is performed. In this process, the structure above the release film 22 is first attached to the carrier 58 via the release film 60 (Figure 66). The carrier 20 is then separated from the redistribution structure 52. During the separation process, a light beam (which can be a laser beam) is projected onto the release film 22, penetrating the transparent carrier 20. This decomposes the release film 22. The carrier 20 can then be removed from the InFO package substrate 72, thereby separating (disassembling) the InFO package substrate 72 from the carrier 20. The resulting structure is shown in Figure 66.

[0128] According to some embodiments, dielectric layers and redistribution wiring are formed on the front side of LSI die 30. FIG67 illustrates the formation of front-side interconnect structure 39, which is located above LSI die 30 and connects to LSI die 30 and underlying redistribution wiring structure 52. Front-side interconnect structure 39 may include redistribution wiring and electrical connectors. Furthermore, front-side interconnect structure 39 may include one or more redistribution wiring layers. This completes the formation of InFO package substrate 72.

[0129] 67 , package component 74 is bonded to InFO package substrate 72. Next, underfill 76 is dispensed into the gap between package component 74 and underlying InFO package substrate 72. Package component 74 is then encapsulated in encapsulant 77, followed by a planarization process, after which package component 74 may be exposed or covered by encapsulant 77.

[0130] Next, the InFO package substrate 72 is separated (detached) from the carrier 58. In subsequent processing, as shown in FIG68 , the InFO package substrate 72 is placed on a tape 80 , which may be secured to a frame 83 . The backside of the package component 74 faces the tape 80 and may be in contact with it. Electrical connectors (such as solder pads) 82 and device die 84 are exposed. This creates a reconstructed wafer 79 . In subsequent processing, the reconstructed wafer 79 is singulated into packages 79 ′.

[0131] According to some embodiments, package 79' can be bonded to package substrate 86 via die-to-die bonding to form package 96' as shown in FIG69 . Bonding can be achieved via solder pads. The backside (bottom surface shown) of device die 84 can be spaced apart from the corresponding underlying package substrate 86 or can be in contact with the underlying package substrate 86. An underfill 81 is then dispensed between package 79' and package substrate 86. Solder pads 97 can be formed on package substrate 86 and electrically connected to upper package substrate 86 and InFO package substrate 72'. Solder pads 97 can be electrically connected to package assembly 74.

[0132] According to some embodiments, bonding is performed using die-to-wafer bonding, wherein a plurality of packages 79' are bonded to a wafer-level packaging substrate 86W (see FIG. 22 ). An underfill 81 is then dispensed between the plurality of packages 96' and the underlying wafer-level packaging substrate 86W. Solder regions 97 are formed on the wafer-level packaging substrate 86W and electrically connected to the package substrate 86 and the InFO packaging substrate 72'. Solder regions 97 can be electrically connected to the package components 74. A singulation process is then performed to separate the wafer-level packaging substrate 86W into discrete package substrates 86, thereby forming a plurality of packages 96'. One of the packages 96' is shown in FIG. 69 .

[0133] FIG70 shows a cross-sectional view of a package 96′ formed according to some embodiments. This embodiment is similar to the embodiment shown in FIG69 , but a reinforcement ring 102 is formed and embedded within the encapsulation body 77. According to some embodiments, the top surface of the reinforcement ring 102 may be lower than the top surface of the encapsulation body 77. The outer sidewall of the reinforcement ring 102 may be exposed. This can be achieved, for example, by cutting through the reinforcement ring 102 during a corresponding singulation process. Alternatively, the outer sidewall of the reinforcement ring 102 may not be exposed, but may instead be in contact with the encapsulation body 77.

[0134] FIG71 illustrates a cross-sectional view of a package 96′ formed according to some embodiments. This embodiment is similar to the embodiment shown in FIG70 , but the top surface of the stiffener ring 102 is exposed and coplanar with the top surface of the encapsulant 77. This can be achieved, for example, by controlling the planarization process of the encapsulant 77 until the stiffener ring 102 is exposed.

[0135] Package assembly 74 can take various forms. For example, Figures 72 to 75 illustrate some example package assemblies 74 according to some embodiments. Figure 72 illustrates a die-on-wafer package assembly (such as a package) 74E according to some embodiments. As shown in Figure 48 , an example die-on-wafer package assembly (such as a package) 74E is also illustrated in package 96 ′. Die-on-wafer package 74 includes an interposer 74F and package assemblies 74A and 74B bonded to interposer 74F. According to some embodiments, package 74A may include an HBM, while package 74B may include a logic die such as a CPU or GPU.

[0136] FIG73 illustrates an integrated fan-out (InFO) package assembly (such as package 74E) according to some embodiments. According to these embodiments, fan-out redistribution structure 150 is formed layer by layer starting from package assemblies 74A and 74B. Redistribution structure 150 includes multiple redistribution lines that interconnect package assemblies 74A and 74B.

[0137] FIG74 illustrates an example package assembly 74 according to some embodiments, wherein package assembly 74 includes an optical element die 152. According to some embodiments, optical element die 152 may include an electro-optical converter and / or an optical-electrical converter, such as an image sensor, a grating coupler, etc. Optical element die 152 may also include a waveguide 154. Furthermore, microlenses 160 may be formed in semiconductor substrate 153. Optical fibers 158 may be connected to optical element die 152 and aligned with microlenses 160.

[0138] FIG. 75 illustrates package assembly 74 formed via hybrid bonding, according to some embodiments. A device die or package (e.g., package assemblies 74A and 74B) can be bonded to device die 164 via hybrid bonding or direct metal-to-metal bonding. Gap filler material 166 is formed to fill the gap between package assemblies 74A and 74B. Gap filler material 166 may be formed of or include a silicon nitride etch stop layer and an oxide filler material. According to some embodiments, gap filler material 166 may include a molding compound, a molding underfill, or the like.

[0139] FIG76 illustrates an enlarged view of portion 170 of package 96′ shown in FIG17 . LSI die 30, dielectric layer 24, and dielectric layer 44 are shown. Encapsulation body 42 may include substrate 42A and filler particles 42B. Due to the grinding of encapsulation body 42 by the process shown in FIG4 , some filler particles 42B are ground into partial particles. Partial particles 42B may have a flat bottom surface in contact with dielectric layer 44. In contrast, filler particles 40B in contact with dielectric layer 24, metal pillars (vias) 28, and LSI die 30 are unground, completely spherical particles, and may have rounded top surfaces.

[0140] In the embodiments described above, processes and features for forming three-dimensional (3D) packages were discussed according to some embodiments. Other features and processes may also be included. For example, test structures may be included to facilitate verification testing of 3D packages or 3D IC devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which allow for testing of the 3D package or 3D IC using probes and / or a probe card. Verification testing can be performed on intermediate structures as well as final structures. Furthermore, the structures and methods disclosed herein can be combined with testing methods that incorporate intermediate verification of known-good dies to improve yield and reduce costs.

[0141] The disclosed embodiments have several advantageous features. By embedding the local interconnect die within the InFO package substrate, package components (e.g., device die and package) can be directly bonded to the InFO package substrate and electrically interconnected via the interconnect die. This reduces the size of the bonded package component because the local interconnect die is not included. This also reduces the size of the package bonded to the package substrate. This reduces warpage of the resulting package, improving manufacturing yield. Furthermore, insertion loss can be reduced. Furthermore, the compound package substrate includes the LSI die and can form another package substrate, and the IPD die can be bonded to the opposite side of the composite package substrate. This improves package design flexibility.

[0142] According to some embodiments of the present disclosure, a method includes forming a composite packaging substrate, which includes encapsulating an interconnection die in a first encapsulation body, wherein the interconnection die includes a plurality of first through-holes; forming a plurality of first redistribution lines and a plurality of second redistribution lines on opposite sides of the interconnection die; bonding an organic packaging substrate to the composite packaging substrate; bonding a first packaging component and a second packaging component to the plurality of first redistribution lines, wherein the first packaging component and the second packaging component are electrically interconnected through the interconnection die and the plurality of first redistribution lines.

[0143] In one embodiment, the plurality of first redistribution lines and the plurality of second redistribution lines are interconnected through the plurality of first through-vias. In one embodiment, the method further comprises forming a plurality of second through-vias, wherein the plurality of second through-vias are encapsulated in the first encapsulation body, and wherein the plurality of first redistribution lines and the plurality of second redistribution lines are further interconnected through the plurality of second through-vias. In one embodiment, the organic encapsulation substrate and the first encapsulation component are located on opposite sides of the composite encapsulation substrate. In one embodiment, the plurality of second redistribution lines are formed after the plurality of first redistribution lines are formed, and wherein the method further comprises bonding the interconnect die to the plurality of first redistribution lines.

[0144] In one embodiment, the interconnect die and the first encapsulant together form part of a reconstructed wafer, and the plurality of first redistribution lines and the plurality of second redistribution lines are formed from opposite sides of the reconstructed wafer. In one embodiment, the method further includes encapsulating the organic encapsulation substrate in a second encapsulant after the organic encapsulation substrate is bonded to the composite encapsulation substrate. In one embodiment, the method further includes encapsulating a reinforcement ring in the second encapsulant. In one embodiment, the method further includes attaching a reinforcement ring to the second encapsulant.

[0145] In one embodiment, the method further includes forming an additional plurality of through-holes in the plurality of first redistribution traces, wherein the additional plurality of through-holes are further encapsulated in the second encapsulant. In one embodiment, the method further includes bonding a passive device die to the composite encapsulation substrate before bonding the organic encapsulation substrate to the composite encapsulation substrate, wherein the passive device die is between the organic encapsulation substrate and the composite encapsulation substrate. In one embodiment, the organic encapsulation substrate is a cored substrate comprising a dielectric core and conductive tubes within the dielectric core.

[0146] According to some embodiments of the present disclosure, a package includes a composite packaging substrate, a first packaging component, a second packaging component, and a packaging substrate. The composite packaging substrate includes a plurality of first redistribution lines, an interconnection die, a first encapsulation package, and a plurality of second redistribution lines. The interconnection die is bonded to the plurality of first redistribution lines, and the interconnection die includes a semiconductor substrate and a plurality of first through-holes extending through the semiconductor substrate. The first encapsulation package encapsulates the interconnection die therein. The plurality of second redistribution lines are located on opposite sides of the first encapsulation, wherein the plurality of first redistribution lines are electrically connected to the plurality of second redistribution lines through the plurality of first through-holes. The first packaging component and the second packaging component are above the composite packaging substrate and bonded to the composite packaging substrate, wherein the first packaging component and the second packaging component are electrically interconnected through the interconnection die. The packaging substrate is below the composite packaging substrate and bonded to the composite packaging substrate.

[0147] In one embodiment, the package further comprises a plurality of second through-holes extending through the first encapsulant, wherein the plurality of first redistribution traces are further electrically connected to the plurality of second redistribution traces via the plurality of second through-holes. In one embodiment, the package further comprises a second encapsulant, wherein the second encapsulant comprises portions on opposing sidewalls of the encapsulation substrate. In one embodiment, the first sidewall of the encapsulation substrate is vertically aligned with the corresponding second sidewall of the composite encapsulation substrate. In one embodiment, the composite encapsulation substrate comprises a first sidewall that is laterally recessed from the corresponding second sidewall of the encapsulation substrate.

[0148] According to some embodiments of the present disclosure, a package includes a first device die and a second device die, a composite packaging substrate, a packaging substrate, and a solder region. The composite packaging substrate is below the first device die and the second device die. The composite packaging substrate includes an interconnect die that electrically interconnects the first device die and the second device die, and a molding compound that encapsulates the interconnect die. The packaging substrate is below the composite packaging substrate and bonded to the composite packaging substrate, wherein the packaging substrate is electrically connected to the first device die via the interconnect die. The solder region bonds the composite packaging substrate to the packaging substrate, wherein the solder region is in physical contact with the composite packaging substrate and the packaging substrate. In one embodiment, the package further includes a plurality of through-holes encapsulated in the molding compound, wherein the plurality of through-holes electrically connect a plurality of conductive features above the interconnect die to the packaging substrate. In one embodiment, the package further includes a stiffener ring attached to the composite packaging substrate.

[0149] The above summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0150] 20, 58, 130, 138: carrier board 22, 60, 132, 140: Release film 23, 28: Metal columns 24, 25, 35, 44, 50, 54A, 54B, 62, 66: dielectric layer 26: Rerouting 30:LSI chip 31:Internal structure 32: Base 34, 114, 128: perforation 36, 38, 97, 122: solder area 37:Through hole 39: Front inner connection structure 40, 76, 81, 125: Primer 40A, 42A: base material 40B, 42B: particles 42, 77, 92, 142: Encapsulation 46, 48: Opening 52, 150: Re-routing line structure 56A, 56B, 64: Rerouting 56BT, 124: conductive characteristics 68: Underbump Metal 70, 70', 82: electrical connectors 72, 72', 86, 86', 86W: Package substrate 74, 74A, 74B, 74E, 123: packaging components 74C:IPD die 74D, 84, 164: device chips 74E:Packaging components 74F: Intermediary 77TS: Top 79, 96, 134: Reconstructed wafer 79', 96', 134': Encapsulation 80, 136, 144: belt 83:Frame 88: Dielectric core board 90:Plated through hole 98: Compound encapsulation substrate 102: Reinforcement ring 104, 110: Adhesive membrane 106: Cover 108, 146: Thermal interface materials 111: Interface 112: Gap 120: Arrow 126:Silicon substrate 127: Area 142': Top 148:Heat sink 152: Optical component grain 153:Semiconductor substrate 154: Waveguide 158: Fiber Optic 160: Microlens 166: Gap filling material 170: Part 200:Process flow 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226, 228, 230, 232, 234: Process H1: Height L1, L2: lateral dimensions T1:Thickness

Claims

1. A method for forming a semiconductor package, comprising: Forming a composite package substrate includes: encapsulating an interconnect die in a first encapsulation, wherein the interconnect die includes a plurality of first through-holes; forming a plurality of first redistribution lines and a plurality of second redistribution lines on opposite sides of the interconnect die; bonding an organic package substrate to the composite package substrate; bonding a first package assembly and a second package assembly to the plurality of first redistribution lines, wherein the first package assembly and the second package assembly are electrically interconnected through the interconnect die and the plurality of first redistribution lines; forming a reinforcing ring on the first redistribution lines; and encapsulating the reinforcing ring, the first package assembly, and the second package assembly in a second encapsulation.

2. The method as described in claim 1, wherein the plurality of first redundancy lines and the plurality of second redundancy lines are interconnected through the plurality of first through-holes.

3. The method as described in claim 1 further includes: A plurality of second perforations are formed, wherein the plurality of second perforations are encapsulated in the first encapsulation body, and wherein the plurality of first re-laid lines and the plurality of second re-laid lines are further interconnected through the plurality of second perforations; and another reinforcing ring is formed on the second encapsulation body.

4. The method of claim 1, wherein the organic encapsulation substrate and the first encapsulation component are located on opposite sides of the composite encapsulation substrate.

5. The method of claim 1, wherein the plurality of second redistribution lines are formed after the plurality of first redistribution lines are formed, and wherein the method further comprises bonding the interconnect die to the plurality of first redistribution lines.

6. The method of claim 1, wherein the interconnect die and the first encapsulation together form part of a reconstructed wafer, and wherein the plurality of first redistribution lines and the plurality of second redistribution lines are formed from opposite sides of the reconstructed wafer.

7. A method for forming a semiconductor package, comprising: Forming a composite package substrate includes: forming a plurality of first redistribution lines; bonding interconnect dies to the plurality of first redistribution lines, wherein the interconnect die includes: a semiconductor substrate; and a plurality of first vias penetrating the semiconductor substrate; encapsulating the interconnect die in a first encapsulation; and forming a plurality of second redistribution lines, wherein the plurality of first redistribution lines are electrically connected to the plurality of second redistribution lines through the plurality of first vias; bonding a first package assembly and a second package assembly to the composite package substrate, wherein the first package assembly and the second package assembly are electrically interconnected through the interconnect die; forming a reinforcing ring on the first redistribution lines; encapsulating the reinforcing ring, the first package assembly, and the second package assembly in a second encapsulation to form a reconstructed wafer; dicing the reconstructed wafer into a plurality of individual packages, wherein the interconnect die is located in a discrete package of the plurality of individual packages; and bonding a package substrate to the discrete package.

8. The method of claim 7, further comprising encapsulating a plurality of second perforations in the first encapsulation, wherein the plurality of second perforations physically contact the first encapsulation, wherein the plurality of first overlay lines are further electrically connected to the plurality of second overlay lines through the plurality of second perforations.

9. A method for forming a semiconductor package, comprising: Forming a composite package substrate includes: forming a plurality of first redistribution lines; bonding interconnect dies to the plurality of first redistribution lines, wherein the interconnect die includes: a semiconductor substrate; and a plurality of first vias penetrating the semiconductor substrate; encapsulating the interconnect die in a first encapsulation package; and forming a plurality of second redistribution lines, wherein the plurality of first redistribution lines are electrically connected to the plurality of second redistribution lines through the plurality of first vias; bonding a first device die and a second device die to the composite package substrate, wherein the first device die and the second device die are electrically interconnected through the interconnect die; forming a reinforcing ring on the first redistribution lines; and encapsulating the reinforcing ring, the first device die, and the second device die with a molding compound.

10. The method of claim 9, further comprising encapsulating a plurality of perforations in the molding compound.

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