Electronic device

Abstract

An electronic device includes a substrate, a conductive structure disposed on the substrate, and a first insulating island disposed on the conductive structure. The conductive structure includes a first conductive element, a second conductive element, and a third conductive element. The third conductive element is disposed on and electrically connected to the first and second conductive elements. In a cross-sectional view of the electronic device, the width of the first insulating island is greater than the width of the third conductive element.

Description

electronic devices The present disclosure relates to an electronic device, and more particularly to an electronic device including a conductive structure and an insulating island. With the development of the electronics industry, the size of electronic devices continues to shrink, while the number of electronic units per unit area continues to increase. As the size of electronic devices decreases and the number of electronic units increases, the layout design and configuration of wires in electronic devices become more complex. Electronic devices are easily scratched by dropped foreign objects during the manufacturing process, causing them to fail. The present disclosure provides an electronic device comprising a substrate, a conductive structure disposed on the substrate, and a first insulating island disposed on the conductive structure. The conductive structure comprises a first conductive element, a second conductive element, and a third conductive element, wherein the third conductive element is disposed on and electrically connected to the first and second conductive elements. In a cross-sectional view of the electronic device, the width of the first insulating island is greater than the width of the third conductive element. The following is a detailed description of the elements of some embodiments of the present disclosure. It should be understood that the following description provides many different embodiments or examples for implementing different modes of some embodiments of the present disclosure. The specific elements and arrangements described below are only for the purpose of simply and clearly describing some embodiments of the present disclosure. Of course, these are only for illustrative purposes and are not limitations of the present disclosure. In addition, repeated numbers or markings may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing some embodiments of the present disclosure and do not represent any correlation between the different embodiments and / or structures discussed. Furthermore, when a first material layer is mentioned as being on or above a second material layer, this includes the situation where the first material layer is in direct contact with the second material layer. Alternatively, there may be a situation where there are one or more other material layers in between, in which case the first material layer and the second material layer may not be in direct contact. Herein, the terms "about," "approximately," and "substantially" generally mean within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. A given quantity is an approximate quantity, meaning that even without the specific wording "about," "approximately," or "substantially," the meaning of "about," "approximately," or "substantially" is implied. Herein, the term "a to b" means greater than or equal to a and less than or equal to b. Herein, the term "less than or equal to" includes values ​​up to and including a given value, while the term "greater than or equal to" includes values ​​above a given value. Conversely, the term "less than" includes values ​​less than a given value but excluding it, while the term "greater than" includes values ​​exceeding a given value but excluding it. For example, "greater than or equal to a" includes values ​​up to and including a, while "greater than a" includes values ​​exceeding a but excluding a. It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are merely used to distinguish different elements, components, regions, layers, and / or parts. Thus, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present disclosure. In some embodiments of the present disclosure, relative terms such as "lower," "upper," "horizontal," "vertical," "below," "above," "top," "bottom," etc. should be understood to refer to the orientations depicted in that section and the related drawings. Such relative terms are used for convenience of description only and do not imply that the device described must be manufactured or operated in a specific orientation. Terms related to joining and connection, such as "connect," "interconnect," etc., unless otherwise defined, may refer to two structures being in direct contact, or may refer to two structures not being in direct contact, with another structure disposed between the two structures. Furthermore, such terms related to joining and connection may also include situations where both structures are movable or both structures are fixed. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of this disclosure. The electronic device disclosed herein may include a display device, a backlight device, an antenna device, a sensing device, or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-luminous display device or a self-luminous display device. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device, and the sensing device may be a sensing device that senses capacitance, light, heat, or ultrasound, but is not limited thereto. The electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. The light-emitting diode may include an organic light-emitting diode or an inorganic light-emitting diode. The light-emitting diode may be, for example, an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro light-emitting diode (micro LED), or a quantum dot light-emitting diode (quantum dot LED), but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any combination of the aforementioned, but is not limited thereto. Some embodiments of the present disclosure can be understood in conjunction with the accompanying drawings, which are considered part of the description of the present disclosure. It should be understood that the drawings of the present disclosure are not drawn to scale relative to actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings to clearly illustrate the features of the present disclosure. Furthermore, the structures and devices in the drawings are schematically illustrated to clearly illustrate the features of the present disclosure. Figure 1 is a schematic top view of an electronic device 1 according to an embodiment of the present disclosure. In order to more clearly explain the structure of the electronic device 1, Figure 1 omits the conductive structure provided in the peripheral area PA. Referring to Figure 1, the present disclosure provides an electronic device 1, which includes a first substrate 11, a second substrate (not shown), a pixel unit 15, a second insulating island 17, and a fourth insulating island 19. The first substrate 11 and the second substrate are arranged opposite to each other, and the pixel unit 15, the second insulating island 17, and the fourth insulating island 19 can be arranged between the first substrate 11 and the second substrate. In addition, the first substrate 11 includes an active area AA and a peripheral area PA adjacent to the active area AA. The pixel unit 15 is located above the first substrate 11 and is correspondingly arranged in the active area AA of the first substrate 11. The second insulating island 17 is located in the active area AA of the first substrate 11, and the fourth insulating island 19 is located in the peripheral area PA of the first substrate 11. The first substrate 11 and the second substrate (not shown) may include a flexible substrate, a rigid substrate, or a combination thereof, but are not limited thereto. In some embodiments, the first substrate 11 may include a transparent substrate or a semi-transparent substrate. According to some embodiments, the material of the first substrate 11 may include glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. The electronic device 1 further includes data lines and scan lines (not shown) disposed on a substrate. The data lines and scan lines intersect to form a pixel region. Pixel units 15 may be disposed within the pixel region. Pixel units 15 may include, but are not limited to, liquid crystals, organic light-emitting diodes, inorganic light-emitting diodes, or other suitable electronic components. Pixel units 15 may emit light of different colors or the same color, depending on design requirements, but are not limited to this. In some embodiments, the electronic device 1 further includes an optical layer that allows light of a specific wavelength range to pass through or converts light to a specific wavelength, enabling the pixel units 15 to display light of different colors. The disclosure is not limited to this. In some embodiments, the electronic device 1 further includes a light-shielding layer 1513 that blocks light and overlaps the data lines and scan lines (not shown). In some embodiments, the light-shielding layer 1513 may include a dark resin, dark photoresist, dark ink, dark pigment, a low-reflectivity metal or alloy, or any combination thereof, such as, for example, black resin, black photoresist, black ink, black pigment, a black metal or alloy, or any combination thereof, but the disclosure is not limited to this. In some embodiments, the light shielding layer 1513 is disposed on the first substrate 11 and includes a plurality of openings arranged in a matrix, so that the pixel unit 15 can display light of different colors through the openings without color mixing, but the disclosure is not limited thereto. The second insulating island 17 is located within the active area AA. The fourth insulating island 19 is located in the peripheral area PA of the first substrate 11 and is disposed adjacent to the active area AA. The second and fourth insulating islands 17, 19 are disposed between the two substrates to support the two substrates and / or maintain the spacing between them. In some embodiments, the fourth insulating island 19 is located in the peripheral area PA of the first substrate 11 and surrounds the active area AA. The projection of the fourth insulating island 19 on the first substrate 11 does not overlap with the projection of the pixel unit 15 on the first substrate 11. In some embodiments, the height of the second insulating island 17 is greater than or equal to the height of the fourth insulating island 19. In some embodiments, the heights of the second and fourth insulating islands 17, 19 are greater than or equal to 3 micrometers (μm). The second and fourth insulating islands 17, 19 can independently have cylindrical, elliptical, angular, or irregular cylindrical shapes. For example, in some embodiments, both the second and fourth insulating islands 17, 19 have cylindrical shapes, as shown in FIG. In some embodiments, the second insulating island 17 has a cylindrical shape and the fourth insulating island 19 has an angular prism shape. The materials of the second insulating island 17 and the fourth insulating island 19 may include acrylic resin, polyamide, polyimide, novolac epoxy resin, other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. Figure 2 illustrates an enlarged schematic diagram of the peripheral area PA of the electronic device 1 shown in Figure 1, according to one embodiment of the present disclosure. Referring to Figure 2, it can be seen that the conductive structure 12 and the first insulating island 14 covering the conductive structure 12 are located in the peripheral area PA of the first substrate 11. The conductive structure 12 can electrically connect to components in the active area AA via conductive traces or transmit external signals to the active area AA. Figure 3 illustrates a schematic cross-sectional view of the area A shown in Figure 2, taken along line II'. In the embodiment shown in FIG3 , the conductive structure 12 includes a first conductive element 121, a first insulating layer 122, a second conductive element 123, a second insulating layer 124, and a third conductive element 125. The first conductive element 121 is located above the first substrate 11, the second conductive element 123 is located above the first conductive element 121, and the third conductive element 125 is located above the first conductive element 121 and the second conductive element 123. The first insulating layer 122 is located between the first conductive element 121 and the third conductive element 125, and between the second conductive element 123 and the third conductive element 125. The second insulating layer 124 is located between the first conductive element 121 and the second conductive element 123, and between the first insulating layer 122 and the first conductive element 121. The materials of the first insulating layer 122 and the second insulating layer 124 may include silicon oxide (SiO x), silicon nitride (SiN x ), silicon oxynitride, or a combination thereof. The first through hole VH1 penetrates the first insulating layer 122. The second through hole VH2 penetrates the first insulating layer 122 and the second insulating layer 124. In other words, the first insulating layer 122 may have a plurality of first through holes VH1. The direction extending from any line connecting the first through hole VH1 and the second through hole VH2 and passing through the first conductive element 121 and the second conductive element 123 is defined as a first direction DR1. The direction perpendicular to the first direction DR1 is defined as a second direction DR2. In some embodiments, the first direction DR1 may be the direction in which the long sides of the first substrate 11 extend, and the second direction DR2 may be the direction in which the short sides of the first substrate 11 extend, but the present disclosure is not limited thereto. In some embodiments, the first direction DR1 may intersect with the direction in which the long sides of the first substrate 11 extend, and the second direction DR2 may intersect with the direction in which the short sides of the first substrate 11 extend. For ease of understanding, the present disclosure uses the example of the first direction DR1 being the direction in which the long sides of the first substrate 11 extend, and the second direction DR2 being the direction in which the short sides of the first substrate 11 extend. In some embodiments, the first insulating layer 122 has a height in a third direction DR3 perpendicular to the first direction DR1 and the second direction DR2, that is, in the normal direction of the first substrate 11, wherein the height is smaller than the width of the first insulating layer 122 in the first direction DR1 or the second direction DR2, and the ratio of the height to the width of the first insulating layer 122 in the first direction DR1 or the second direction DR2 is less than 10. -5 In some embodiments, the second insulating layer 124 has a height in a third direction DR3 perpendicular to the first direction DR1 and the second direction DR2, that is, in the normal direction of the first substrate 11, the height being smaller than the width of the second insulating layer 124 in the first direction DR1 or the second direction DR2, and the ratio of the height to the width of the second insulating layer 124 in the first direction DR1 or the second direction DR2 is less than 10. -5 . The material of the first conductive element 121 and the second conductive element 123 may include metal. Examples of metals include, but are not limited to, aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), alloys thereof, or any combination thereof. The materials of the first conductive element 121 and the second conductive element 123 may be the same or different. In some embodiments, the material of the first conductive element 121 and the second conductive element 123 may include copper, but the present disclosure is not limited thereto. As shown in FIG2 , the first conductive element 121 has sides 121S1, 121S2, 121S3, and 121S4. The second conductive element 123 has sides 123S1, 123S2, 123S3, and 123S4. The projections of the sides 121S1, 121S2, 121S3, and 121S4 of the first conductive element 121 on the first substrate 11 are adjacent to the projections of the sides 123S1, 123S2, 123S3, and 123S4 of the second conductive element 123 on the substrate 11, respectively. In some embodiments, the sides 121S1 and 121S2 of the first conductive element 121 are substantially parallel to the sides 123S1 and 123S2 of the second conductive element 123. The side edges 121S3 and 121S4 of the first conductive element 121 and the side edges 123S3 and 123S4 of the second conductive element 123 are substantially parallel, but the disclosure is not limited thereto. The second conductive element 123 is disposed on the first conductive element 121, and the projection of the first conductive element 121 on the first substrate 11 may overlap with the projection of the second conductive element 123 on the first substrate 11. In some embodiments, the projection of the first conductive element 121 on the first substrate 11 is larger than the projection of the second conductive element 123 on the first substrate 11. In some embodiments, the first side 123S1 of the second conductive element 123 is located between the first side 121S1 and the second side 121S2 of the first conductive element 121, as shown in FIG3 . In other embodiments, the second side 121S2 of the first conductive element 121 is located between the first side 123S1 and the second side 123S2 of the second conductive element 123. In still other embodiments, the second side 121S2 of the first conductive element 121 is flush with the second side 123S2 of the second conductive element 123. That is, the projection of the second side 121S2 of the first conductive element 121 on the first substrate 11 overlaps with the projection of the second side 123S2 of the second conductive element 123 on the first substrate 11 . The third conductive element 125 is formed on the first insulating layer 122 and the second insulating layer 124 and electrically connected to the first conductive element 121 and the second conductive element 123 through the first through hole VH1 and the second through hole VH2, respectively. In some embodiments, the third conductive element 125 is conformally formed on the first insulating layer 122 and the sidewalls of the first through hole VH1 and the second through hole VH2, and is in direct contact with the first conductive element 121 and the second conductive element 123. In some embodiments, the third conductive element 125 may have a light transmittance of 70% or greater. In this embodiment, the third conductive element 125 may include a transparent conductive material with a light transmittance of 70% or greater. The transparent conductive material may include a metal oxide. Examples of metal oxides include, but are not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, or any combination thereof. In some embodiments, the third conductive element 125 may include ITO, but the present disclosure is not limited thereto. The third conductive element 125 has sides 125S1, 125S2, 125S3, and 125S4. The projections of the sides 125S1, 125S2, 125S3, and 125S4 of the third conductive element 125 on the first substrate 11 are respectively adjacent to the projections of the sides 121S1, 121S2, 121S3, and 121S4 of the first conductive element 121 on the first substrate 11. The projections of the sides 125S1, 125S2, 125S3, and 125S4 of the third conductive element 125 on the first substrate 11 are respectively adjacent to the projections of the sides 123S1, 123S2, 123S3, and 123S4 of the second conductive element 123 on the first substrate 11. In some embodiments, the sides 125S1 and 125S2 of the third conductive element 125 are parallel to the sides 121S1 and 121S2 of the first conductive element 121. In some embodiments, the sides 125S3 and 125S4 of the third conductive element 125 are substantially parallel to the sides 121S3 and 121S4 of the first conductive element 121. In some embodiments, the sides 125S1 and 125S2 of the third conductive element 125 are parallel to the sides 123S1 and 123S2 of the second conductive element 123. In some embodiments, the sides 125S3 and 125S4 of the third conductive element 125 are substantially parallel to the sides 123S3 and 123S4 of the second conductive element 123, but the disclosure is not limited thereto. In some embodiments, the third conductive element 125 covers the first conductive element 121 and the second conductive element 123. In some embodiments, in a cross-sectional view of the electronic device 1, the width of the third conductive element 125 in the first direction DR1 may be greater than the width of the first conductive element 121 and / or the second conductive element 123 in the first direction DR1. In some embodiments, the width of the third conductive element 125 in the second direction DR2 may be greater than the width of the first conductive element 121 and / or the second conductive element 123 in the second direction DR2. In some embodiments, the length of the first side 125S1 of the third conductive element 125 is greater than the length of the first side 121S1 of the first conductive element 121 and greater than the length of the first side 123S1 of the second conductive element 123. The first side 121S1 and the second side 121S2 of the first conductive element 121 and the first side 123S1 and the second side 123S2 of the second conductive element 123 are located between the first side 125S1 and the second side 125S2 of the third conductive element 125. The third side 121S3 and the fourth side 121S4 of the first conductive element 121 and the third side 123S3 and the fourth side 123S4 of the second conductive element 123 are located between the third side 125S3 and the fourth side 125S4 of the third conductive element 125. In other words, the projection of the third conductive element 125 on the first substrate 11 is larger than the projections of the first conductive element 121 and the second conductive element 123 on the first substrate 11, and the projections of the first conductive element 121 and the second conductive element 123 on the first substrate 11 are located within the projection of the third conductive element 125 on the first substrate 11. In some embodiments, the third conductive element 125 may have a minimum height and a maximum height. The "minimum height" herein refers to the height of the third conductive element 125 closest to the first substrate 11 in the cross-sectional view of the electronic device 1 as shown in FIG. 3 . In other words, the "minimum height" refers to the minimum distance between the third conductive element 125 and the first substrate 11 in the third direction DR3 . The "maximum height" herein refers to the height of the third conductive element 125 farthest from the first substrate 11 in the cross-sectional view of the electronic device 1 as shown in FIG. 3 . In other words, the "maximum height" refers to the maximum distance between the third conductive element 125 and the first substrate 11 in the third direction DR3 . The difference between the maximum height and the minimum height of the third conductive element 125 is defined as the first distance V. The first insulating island 14 is disposed on and covers the conductive structure 12. The material of the first insulating island 14 may include acrylic resin, polyamide, polyimide, novolac epoxy resin, other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the material of the first insulating island 14 may be the same as the material of the second insulating island 17 and / or the fourth insulating island 19. The first insulating island 14 has side edges 14S1, 14S2, 14S3, and 14S4. The projections of the sides 14S1, 14S2, 14S3, and 14S4 of the first insulating island 14 on the first substrate 11 are adjacent to the projections of the sides 125S1, 125S2, 125S3, and 125S4 of the third conductive element 125 on the first substrate 11, respectively. In some embodiments, the sides 14S1 and 14S2 of the first insulating island 14 are substantially parallel to the sides 125S1 and 125S2 of the third conductive element 125. In some embodiments, the sides 14S3 and 14S4 of the first insulating island 14 are substantially parallel to the sides 125S3 and 125S4 of the third conductive element 125, but the disclosure is not limited thereto. In some embodiments, the sides 14S1 and 14S2 of the first insulating island 14 extend along the second direction DR2. The sides 14S3 and 14S4 of the first insulating island 14 extend along the first direction DR1, but the disclosure is not limited thereto. In some embodiments, in a cross-sectional view of the electronic device 1, the width W1 of the first insulating island 14 in the first direction DR1 may be greater than the width W2 of the third conductive element 125 in the first direction DR1, and / or the width W1′ of the first insulating island 14 in the second direction DR2 may be greater than the width W2′ of the third conductive element 125 in the second direction DR2. In other words, the length of the first side 14S1 of the first insulating island 14 may be greater than the length of the first side 125S1 of the third conductive element 125, the length of the second side 14S2 of the first insulating island 14 may be greater than the length of the second side 125S2 of the third conductive element 125, the length of the third side 14S3 of the first insulating island 14 may be greater than the length of the third side 125S3 of the third conductive element 125, and the length of the fourth side 14S4 of the first insulating island 14 may be greater than the length of the fourth side 125S4 of the third conductive element 125. The first side 125S1 and the second side 125S2 of the third conductive element 125 are located between the first side 14S1 and the second side 14S2 of the first insulating island 14. The third side 125S3 and the fourth side 125S4 of the third conductive element 125 are located between the third side 14S3 and the fourth side 14S4 of the first insulating island 14. In other words, the projection of the first insulating island 14 on the first substrate 11 is larger than the projection of the third conductive element 125 on the first substrate 11, and the projection of the third conductive element 125 on the first substrate 11 is located within the projection of the first insulating island 14 on the first substrate 11. Thus, the first insulating island 14 covers the third conductive element 125, reducing the possibility of short circuits or damage to the electronic device 1. In some embodiments, the minimum distance between the first side 14S1 to the fourth side 14S4 of the first insulating island 14 and the first side 125S1 to the fourth side 125S4 of the adjacent third conductive element 125 can be the same or different. In some embodiments, the minimum distance between the first side 14S1 to the fourth side 14S4 of the first insulating island 14 and the first side 125S1 to the fourth side 125S4 of the adjacent third conductive element 125 may be greater than 1 micrometer (um), but the disclosure is not limited thereto. In some embodiments, in a cross-sectional view of the electronic device 1, the width of the first insulating island 14 in the first direction DR1 is greater than the width of the first through hole VH1 and / or the second through hole VH2 in the first direction DR1. The width of the first insulating island 14 in the second direction DR2 is greater than the width of the first through hole VH1 and / or the second through hole VH2 in the second direction DR2. The projection of the first insulating island 14 on the first substrate 11 is greater than the projection of the first through hole VH1 and / or the second through hole VH2 on the first substrate 11, and the projection of the first through hole VH1 and / or the second through hole VH2 on the first substrate 11 is located within the projection of the first insulating island 14 on the first substrate 11. Thus, the first insulating island 14 can cover the first through-hole VH1 and / or the second through-hole VH2, thereby preventing the first through-hole VH1 and / or the second through-hole VH2 from being exposed to the outside. This reduces the chance of moisture and / or compounds used during the process penetrating the first through-hole VH1 and / or the second through-hole VH2 and contacting the first conductive element 121, the second conductive element 123, and / or the third conductive element 125, or reduces the possibility of corrosion of the first conductive element 121, the second conductive element 123, and / or the third conductive element 125. In some embodiments, a portion of the first insulating island 14 can be disposed within the first through-hole VH1 and / or the second through-hole VH2 to prevent or reduce the chance of moisture and / or compounds used during the process contacting the first conductive element 121, the second conductive element 123, and / or the third conductive element 125. The first insulating island 14 has a bottom 14B and a top 14T. The bottom 14B refers to the point where the first insulating island 14 is closest to the first substrate 11 in the cross-sectional view of the electronic device 1 as shown in FIG3 . In other words, the bottom 14B refers to the point where the distance between the first insulating island 14 and the first substrate 11 is the smallest in the third direction DR3. In some embodiments, the distance between the bottom 14B of the first insulating island 14 and the first substrate 11 is greater than or equal to 0.5 micrometers (μm). In some embodiments, the distance between the bottom 14B of the first insulating island 14 and the first substrate 11 is between 0.5 and 3 micrometers (μm). In some embodiments, the distance between the bottom 14B of the first insulating island 14 and the first substrate 11 is greater than or equal to 3 micrometers (μm). The top 14T refers to the point where the first insulating island 14 is farthest from the first substrate 11 in the cross-sectional view of the electronic device 1 as shown in FIG3 . In other words, the top 14T refers to the point where the distance between the first insulating island 14 and the first substrate 11 is the largest in the third direction DR3. In some embodiments, the projection of the bottom 14B of the first insulating island 14 on the first substrate 11 is larger than the projection of the top 14T of the first insulating island 14 on the first substrate 11. The distance between the bottom 14B and the top 14T in the third direction DR3 is defined as the thickness H of the first insulating island 14. The thickness H of the first insulating island 14 is greater than the first distance V between the highest and lowest heights of the third conductive element 125. In some embodiments, the ratio of the thickness H of the first insulating island 14 to the first distance V between the highest and lowest heights of the third conductive element 125 is greater than 1.1 (thickness H:first distance V is greater than 1.1:1). In some embodiments, the ratio of the thickness H to the first distance V is less than 3 (thickness H:first distance V is less than 3:1). In some embodiments, the difference between the thickness H and the first distance V is greater than or equal to 0.5 micrometers (μm). Thus, the top 14T of the first insulating island 14 is located above the third conductive element 125, reducing the possibility of the third conductive element 125 being exposed and abraded, or reducing the possibility of damage to the first conductive element 121 and / or the second conductive element. In some embodiments, the height of the first insulating island 14 is less than the height of the second insulating island 17 and / or the fourth insulating island 19. By making the height of the first insulating island 14 less than the height of the second insulating island 17 and / or the fourth insulating island 19, the first insulating island 14 can prevent or reduce the possibility of the first conductive element 121, the second conductive element 123, and / or the third conductive element 125 being scratched, broken, or failing due to foreign matter dropped during the manufacturing process. It should be noted that the "height" referred to here is measured from the same level to the highest point of a component. For example, the height of the first insulating island 14 is the shortest distance from the highest point of the first insulating island 14 to the first substrate 11, but is not limited to this. In some embodiments, the thickness of the first insulating island 14 may be smaller than the width of the first insulating island 14 in the first direction DR1 or the second direction DR2, and the ratio of the thickness of the first insulating island 14 to the width of the first insulating island 14 in the first direction DR1 or the second direction DR2 is greater than 10. -4 In some embodiments, the ratio of the thickness of first insulating island 14 to its width in the first direction DR1 or the second direction DR2 is greater than the ratio of the thickness of first insulating layer 122 to its width in the first direction DR1 or the second direction DR2. In some embodiments, the ratio of the thickness of first insulating island 14 to its width in the first direction DR1 or the second direction DR2 is greater than the ratio of the thickness of second insulating layer 124 to its width in the first direction DR1 or the second direction DR2. By providing first insulating island 14 with a specific thickness-to-width ratio, the possibility of short circuiting in electronic device 1 is prevented or reduced. FIG4 illustrates an enlarged schematic diagram of a peripheral region of the electronic device 1 shown in FIG1 according to another embodiment of the present disclosure. FIG5 illustrates a cross-sectional schematic diagram taken along line II-II' of FIG4 according to another embodiment of the present disclosure. Aside from the difference in conductive structure 12 from the conductive structure 12 of FIG2 , the electronic device shown in FIG4 has substantially the same structure as the electronic device shown in FIG2 . Therefore, the structure of the conductive structure 12 in the embodiment shown in FIG4 will be described in detail below, and other descriptions will be omitted. The conductive structure 12 and the first insulating island 14 covering the conductive structure 12 are located in the peripheral area PA of the first substrate 11. The conductive structure 12 can electrically connect to components in the active area AA through conductive lines or transmit external signals to the active area AA. The conductive structure 12 is disposed on the substrate. The conductive structure 12 includes a first conductive element 121, a first insulating layer 122, a second conductive element 123, a second insulating layer 124, and a third conductive element 125. The first conductive element 121 and the second conductive element 123 are located above the first substrate 11, and the third conductive element 125 is located above the first conductive element 121 and the second conductive element 123. The first insulating layer 122 is located between the first conductive element 121 and the third conductive element 125, and between the second conductive element 123 and the third conductive element 125. The second conductive element 123 is located above the second insulating layer 124, and the second insulating layer 124 is located between the first conductive element 121 and the second conductive element 123, and between the first insulating layer 122 and the first conductive element 121. The first conductive element 121 and the second conductive element 123 do not overlap. In other words, the projection of the first conductive element 121 on the first substrate 11 does not overlap with the projection of the second conductive element 123 on the first substrate 11. The first side 123S1 of the second conductive element 123 is located between the second side 121S2 of the first conductive element 121 and the second side 123S2 of the second conductive element 123. The second side 121S2 of the first conductive element 121 is located between the first side 123S1 of the second conductive element 123 and the first side 123S1 of the first conductive element 121. The second side 121S2 of the first conductive element 121 and the first side 123S1 of the second conductive element 123 are located between the first side 123S1 of the first conductive element 121 and the second side 123S2 of the second conductive element 123. The third conductive element 125 covers the first conductive element 121 and the second conductive element 123. In some embodiments, in a cross-sectional view of the electronic device 1, the width of the third conductive element 125 in the first direction DR1 may be greater than the sum of the widths of the first conductive element 121 and the second conductive element 123 in the first direction DR1. In other embodiments, the width of the third conductive element 125 in the second direction DR2 may be greater than the sum of the widths of the first conductive element 121 and the second conductive element 123 in the second direction DR2. The first side 121S1 and the second side 121S2 of the first conductive element 121 and the first side 123S1 and the second side 123S2 of the second conductive element 123 are located between the first side 125S1 and the second side 125S2 of the third conductive element 125. The third side 121S3 and the fourth side 121S4 of the first conductive element 121 and the third side 123S3 and the fourth side 123S4 of the second conductive element 123 are located between the third side 125S3 and the fourth side 125S4 of the third conductive element 125. In other words, the projection of the third conductive element 125 on the first substrate 11 is larger than the projections of the first conductive element 121 and the second conductive element 123 on the first substrate 11, and the projections of the first conductive element 121 and the second conductive element 123 on the first substrate 11 are located within the projection of the third conductive element 125 on the first substrate 11. In some embodiments, the third conductive element 125 has a maximum height and a minimum height, and the difference between the maximum height and the minimum height is defined as a first distance V, as shown in FIG. 5 . A first insulating island 14 is disposed on and covers the entire conductive structure 12, as shown in Figures 4 and 5. Similar to the first insulating island 14 in the aforementioned embodiments, in the embodiment shown in Figure 5, in a cross-sectional view of the electronic device 1, the width of the first insulating island 14 in the first direction DR1 may be greater than the width of the third conductive element 125 in the first direction DR1, and / or the width of the first insulating island 14 in the second direction DR2 may be greater than the width of the third conductive element 125 in the second direction DR2. The projection of the first insulating island 14 on the first substrate 11 may be larger than the projection of the third conductive element 125 on the first substrate 11, and the projection of the third conductive element 125 on the first substrate 11 may be located within the projection of the first insulating island 14 on the first substrate 11. Thus, the first insulating island 14 covers the third conductive element 125, preventing it from being exposed, thereby reducing the possibility of short circuits in the electronic device 1. Similarly, in some embodiments, in a cross-sectional view of the electronic device 1, the width of the first insulating island 14 in the first direction DR1 may be greater than the width of the first through hole VH1 and / or the second through hole VH2 in the first direction DR1. The width of the first insulating island 14 in the second direction DR2 may be greater than the width of the first through hole VH1 and / or the second through hole VH2 in the second direction DR2. The projection of the first insulating island 14 on the first substrate 11 is greater than the projection of the first through hole VH1 and / or the second through hole VH2 on the first substrate 11, and the projection of the first through hole VH1 and / or the second through hole VH2 on the first substrate 11 is located within the projection of the first insulating island 14 on the first substrate 11. Thus, the first insulating island 14 covers the first through-hole VH1 and / or the second through-hole VH2, preventing the first through-hole VH1 and / or the second through-hole VH2 from being exposed to the outside. This prevents or reduces the chance of moisture and / or compounds used during the manufacturing process from penetrating the first through-hole VH1 and / or the second through-hole VH2 and contacting the first conductive element 121, the second conductive element 123, and / or the third conductive element 125, or reduces the possibility of corrosion of the first conductive element 121, the second conductive element 123, and / or the third conductive element 125. Similarly, in some embodiments, a portion of the first insulating island 14 formed on the third conductive element 125 may be disposed in the first through-hole VH1 and / or the second through-hole VH2. In this way, the first insulating island 14 can reduce the chance of moisture in the environment entering the electronic device 1, reduce the chance of moisture and / or compounds used during the process coming into contact with the first conductive element 121, the second conductive element 123, and / or the third conductive element 125, or reduce the possibility of the first conductive element 121 and / or the second conductive element 123 being oxidized due to high-voltage signals from the peripheral circuits. FIG6 illustrates a schematic cross-sectional view taken along line II-II' of FIG4 according to another embodiment of the present disclosure. In the embodiment shown in FIG6 , the conductive structure 12 includes a first conductive element 121, a first insulating layer 122, a second conductive element 123, and a third conductive element 125. The first conductive element 121 and the second conductive element 123 are located above the first substrate 11, and the third conductive element 125 is located above the first conductive element 121 and the second conductive element 123. The first conductive element 121 and the second conductive element 123 are located in the same layer. In other words, the first conductive element 121 and the second conductive element 123 can be made of the same layer. The first insulating layer 122 is located above the first conductive element 121 and the second conductive element 123 and between the third conductive element 125 and the first conductive element 121 and the second conductive element 123. The materials of the first conductive element 121, the second conductive element 123, the third conductive element 125, and the first insulating layer 122 can be the same as those described in the previous embodiment, and therefore will not be repeated here. In the embodiment shown in FIG6 , the first through-hole VH1 and the second through-hole VH2 penetrate the first insulating layer 122. In other words, the first insulating layer 122 may have a plurality of first through-holes VH1 and second through-holes VH2. The third conductive element 125 is formed on the first insulating layer 122 and electrically connected to the first conductive element 121 and the second conductive element 123 through the first through-hole VH1 and the second through-hole VH2, respectively. In some embodiments, the third conductive element 125 has a maximum height and a minimum height. The difference between the maximum and minimum heights is defined as a first distance V, as shown in FIG6 . A first insulating island 14 is disposed on and covers the entire conductive structure 12, as shown in Figures 4 and 6 . The material, structure, and function of the first insulating island 14 shown in Figure 6 are similar to those of the first insulating island 14 in the previous embodiment, and therefore will not be repeated here. Similar to the first insulating island 14 in the previous embodiment, in the embodiment shown in Figure 6 , in a cross-sectional view of the electronic device 1, the width of the first insulating island 14 in the first direction DR1 may be greater than the width of the third conductive element 125 in the first direction DR1, and / or the width of the first insulating island 14 in the second direction DR2 may be greater than the width of the third conductive element 125 in the second direction DR2. The projection of the first insulating island 14 on the first substrate 11 may be larger than the projection of the third conductive element 125 on the first substrate 11, and the projection of the third conductive element 125 on the first substrate 11 may be located within the projection of the first insulating island 14 on the first substrate 11. Thus, the first insulating island 14 can prevent or reduce the possibility of short circuits in the electronic device 1. Similarly, a portion of the first insulating island 14 formed on the third conductive element 125 may be disposed within the first through hole VH1 and / or the second through hole VH2. In the embodiment shown in FIG6 , the projection of the first insulating island 14 on the first substrate 11 may be larger than the projection of the first through hole VH1 and / or the second through hole VH2 on the first substrate 11, and the projection of the first through hole VH1 and / or the second through hole VH2 on the first substrate 11 may be located within the projection of the first insulating island 14 on the first substrate 11. Thus, the first insulating island 14 can reduce the intrusion of moisture from the environment into the electronic device 1, reduce the chance of moisture and / or compounds used during the manufacturing process coming into contact with the first conductive element 121, the second conductive element 123, and / or the third conductive element 125, and reduce the possibility of oxidation of the first conductive element 121 and / or the second conductive element 123 due to high-voltage signals from peripheral circuits. FIG7 illustrates an enlarged schematic diagram of the peripheral area PA of the electronic device 1 shown in FIG1 , according to one embodiment of the present disclosure. As shown in FIG7 , in addition to the structures described above with reference to FIG1 through FIG6 , the electronic device 1 may further include a transistor 16 and a third insulating island 18 . Transistor 16 and third insulating island 18 are located in the peripheral area PA of the first substrate 11 . FIG8A illustrates an embodiment of the present disclosure, and FIG7 shows a schematic cross-sectional view taken along line III-III'. FIG8B illustrates an enlarged schematic view of region C shown in FIG8A according to another embodiment of the present disclosure. As shown in FIG8A and FIG8B , transistor 16 includes a gate electrode 161, source / drain electrodes 165, a semiconductor device 163 located between the gate electrode 161 and the source / drain electrodes 165, a third insulating layer 162 located between the gate electrode 161 and the semiconductor device 163 and insulating the gate electrode 161 from the semiconductor device 163, and a fourth insulating layer 164 located on the source / drain electrodes 165. The fourth insulating layer 164 covers the gate electrode 161, the source / drain electrodes 165, and the semiconductor device 163. In some embodiments, the projection of the fourth insulating layer 164 on the first substrate 11 is larger than the projection of the gate electrode 161, the source / drain electrode 165, and / or the semiconductor element 163 on the first substrate 11, and the projection of the gate electrode 161, the source / drain electrode 165, and / or the semiconductor element 163 on the first substrate 11 is located in the projection of the fourth insulating layer 164 on the first substrate 11. The third insulating island 18 is disposed on the transistor 16 and covers the gate electrode 161, source / drain electrodes 165, and / or semiconductor device 163 of the transistor 16. The material of the third insulating island 18 may include acrylic resin, polymide, polyimide, novolac epoxy resin, organic photoresist, other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, in a cross-sectional view of the electronic device 1, the width of the third insulating island 18 in the first direction DR1 may be greater than the width of the semiconductor device 163 in the first direction DR1, and / or the width of the third insulating island 18 in the second direction DR2 may be greater than the width of the semiconductor device 163 in the second direction DR2. In some embodiments, the projection of the third insulating island 18 on the first substrate 11 may be larger than the projection of the gate electrode 161, the source / drain electrodes 165, and / or the semiconductor device 163 on the first substrate 11, and the projection of the gate electrode 161, the source / drain electrodes 165, and / or the semiconductor device 163 on the first substrate 11 may be located within the projection of the third insulating island 18 on the first substrate 11. In this way, the third insulating island 18 can cover the gate electrode 161, the source / drain electrodes 165, and / or the semiconductor device 163, so that the gate electrode 161, the source / drain electrodes 165, and / or the semiconductor device 163 are not exposed to the outside. In some embodiments, the bottom of the third insulating island 18 is larger than its top. That is, the projection of the bottom of the third insulating island 18 on the first substrate 11 is larger than the projection of the top of the third insulating island 18 on the first substrate 11, and the projection of the top of the third insulating island 18 on the first substrate 11 is within the projection of the bottom of the third insulating island 18 on the first substrate 11. In some embodiments, the distance between the bottom of the third insulating island 18 and the first substrate 11 is greater than 0.5 micrometers (μm). In some embodiments, the distance between the bottom of the third insulating island 18 and the first substrate 11 is between 0.5 and 3 micrometers (μm). In some embodiments, the distance between the bottom of the third insulating island 18 and the first substrate 11 is greater than 3 micrometers (μm). In some embodiments, the height of third insulating island 18 is less than the height of second insulating island 17 and / or fourth insulating island 19. By making the height of third insulating island 18 less than the height of second insulating island 17 and / or fourth insulating island 19, third insulating island 18 can reduce the possibility of transistor 16 being scratched, broken, or failing due to foreign matter dropped during the manufacturing process. In some embodiments, the thickness of third insulating island 18 is less than the width of third insulating island 18 in first direction DR1 or second direction DR2, and the ratio of the thickness of third insulating island 18 to the width of third insulating island 18 in first direction DR1 or second direction DR2 is greater than 10. -4 In some embodiments, the ratio of the thickness of third insulating island 18 to its width in the first direction DR1 or the second direction DR2 is greater than the ratio of the thickness of first insulating layer 122 to its width in the first direction DR1 or the second direction DR2. In some embodiments, the ratio of the thickness of third insulating island 18 to its width in the first direction DR1 or the second direction DR2 is greater than the ratio of the thickness of second insulating layer 124 to its width in the first direction DR1 or the second direction DR2. By providing third insulating island 18 with a specific aspect ratio, the possibility of short circuiting in electronic device 1 can be prevented or reduced. In the embodiment shown in FIG. 7 , a third insulating island 18 may cover a plurality of transistors 16, but the present disclosure is not limited thereto. In an embodiment in which the third insulating island 18 covers a plurality of transistors 16, in a cross-sectional view of the electronic device 1, the width of the third insulating island 18 is greater than the sum of the widths of the semiconductor elements 163 of the plurality of transistors 16 it covers. The width of the third insulating island 18 in the first direction DR1 may be greater than the sum of the widths of the semiconductor elements 163 of the plurality of transistors 16 it covers in the first direction DR1, and / or the width of the third insulating island 18 in the second direction DR2 may be greater than the sum of the widths of the semiconductor elements 163 of the plurality of transistors 16 it covers in the second direction DR2. In some embodiments, the gate electrodes 161, source / drain electrodes 165, and / or semiconductor elements 163 of the plurality of transistors 16 covered by the third insulating island 18 have a smaller projection on the first substrate 11 than the projection of the third insulating island 18 on the first substrate 11. In this way, the third insulating island 18 can prevent or reduce the entry of moisture from the environment into the electronic device 1, reduce the chance of moisture and / or compounds used during the process coming into contact with the transistor 16, or reduce the possibility of the gate electrode 161 and / or source / drain electrode 165 in the transistor 16 being oxidized due to high-voltage signals from the peripheral circuits. FIG9 is an enlarged schematic diagram of the peripheral area of ​​the electronic device 1 shown in FIG1 according to another embodiment of the present disclosure. In the embodiment shown in FIG9 , the third insulating island 18 includes a plurality of sub-insulating islands 181. The material of the sub-insulating islands 181 may include acrylic resin, polymide, polyimide, novolac epoxy resin, other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. Each sub-insulating island 181 covers the gate electrode 161, source / drain electrodes 165, and / or semiconductor element 163 of at least one transistor 16. In some embodiments, in the cross-sectional view of the electronic device 1, the width of the sub-insulating island 181 is greater than the width of the semiconductor element 163 of one transistor 16. The width of the sub-insulating island 181 in the first direction DR1 may be greater than the width of the semiconductor layer 163 of one transistor 16 in the first direction DR1, and / or the width of the sub-insulating island 181 in the second direction DR2 may be greater than the width of the semiconductor element 163 of the one transistor 16 in the second direction DR2. In some embodiments, the projection of the sub-insulating island 181 on the first substrate 11 is greater than the projection of the gate electrode 161, source / drain electrodes 165, and / or semiconductor element 163 of the at least one transistor 16 on the first substrate 11, and the projection of the gate electrode 161, source / drain electrodes 165, and / or semiconductor element 163 of the at least one transistor 16 on the first substrate 11 is located within the projection of the sub-insulating island 181 on the first substrate 11. In this way, the sub-insulating island 181 can reduce the chance of moisture in the environment entering the electronic device 1, reduce the chance of moisture and / or compounds used during the process coming into contact with the at least one transistor 16, or reduce the possibility of the gate electrode 161 and / or source / drain electrode 165 in the at least one transistor 16 being oxidized due to high-voltage signals from the peripheral circuit. In some embodiments, the height of sub-insulating island 181 is smaller than that of second insulating island 17 and / or fourth insulating island 19. By making sub-insulating island 181 smaller than that of second insulating island 17 and / or fourth insulating island 19, sub-insulating island 181 can reduce the possibility of transistor 16 being damaged, broken, or otherwise failing due to foreign matter dropped during the manufacturing process. In some embodiments, sub-insulating islands 181 are spaced apart from each other. In some embodiments, the third insulating island 18 may further include a connecting portion connecting a plurality of adjacent sub-insulating islands 181. In some embodiments, the connecting portion may connect all sub-insulating islands 181, but the disclosure is not limited thereto. In some embodiments, the connecting portion may optionally connect some sub-insulating islands 181, but the disclosure is not limited thereto. By forming insulating islands on conductive structures and / or transistors, the present disclosure can reduce the possibility of the conductive structures and / or transistors being damaged by foreign matter dropped during the manufacturing process, / or compounds used during the manufacturing process, and / or moisture in the environment, or reduce the possibility of short circuits or failure of electronic devices. Although the embodiments and advantages of the present disclosure have been disclosed above, it should be understood that any person with ordinary knowledge in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the art can understand from the disclosure of some embodiments of the present disclosure that the processes, machines, manufacturing, material compositions, devices, methods and steps currently or in the future developed can be used according to some embodiments of the present disclosure as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present disclosure also includes the combination of each claim and embodiment. 1: electronic device 11: substrate 12: conductive structures 121, 123, 125: Conductive element 122, 124, 162, 164: Insulating layer 121S1, 121S2, 121S3, 121S4, 123S1, 123S2, 123S3, 123S4, 125S1, 125S2, 125S3, 125S4, 14S1, 14S2, 14S3, 14S4: Sides 14, 17, 18, 19: Insulating island 14T: Top 14B: Bottom 15: Pixel unit 1513: Light shielding layer 16: Transistor 161: Gate electrode 163: Semiconductor element 165: Source / drain electrode 181: Sub-insulating island H: Thickness V: First distance VH1, VH2: Through hole DR1, DR2, DR3: Direction PA: Peripheral area AA: Active area W1, W2, W1', W2': Width The following is a detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, wherein: FIG1 is a top schematic diagram of an electronic device according to an embodiment of the present disclosure. FIG2 is an enlarged schematic diagram of the peripheral area of ​​the electronic device shown in FIG1 according to an embodiment of the present disclosure. FIG3 is a cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure. FIG4 is an enlarged schematic diagram of the peripheral area of ​​the electronic device shown in FIG1 according to another embodiment of the present disclosure. FIG5 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. FIG6 is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. FIG7 is an enlarged schematic diagram of the peripheral area of ​​the electronic device shown in FIG1 according to an embodiment of the present disclosure. FIG8A is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. FIG8B is an enlarged schematic diagram of area C shown in FIG8A according to another embodiment of the present disclosure. FIG9 is an enlarged schematic diagram of the peripheral area of ​​the electronic device shown in FIG1 according to another embodiment of the present disclosure. 11:Substrate 12: Conductive structure 121,123,125: Conductive components 122,124: Insulation layer 121S1,121S2,123S1,123S2,125S1,125S2,14S1,14S2: Side 14: Insulation Island 14T: Top 14B: bottom H:Thickness V: First distance VH1, VH2: through hole W1, W2: width DR1, DR3: Direction

Claims

1. An electronic device comprising: A substrate having an active region and a peripheral region adjacent to the active region; A conductive structure is disposed on the substrate and includes a first conductive element, a second conductive element, and a third conductive element, wherein the third conductive element is disposed on and electrically connected to the first and second conductive elements, and the conductive structure is disposed on the peripheral region; a first insulating island is disposed on the conductive structure, wherein in a cross-sectional view of the electronic device, the width of the first insulating island is greater than the width of the third conductive element; a transistor is disposed on the peripheral region; and a third insulating island is disposed on the transistor.

2. The electronic device as claimed in claim 1, wherein in the cross-sectional view of the electronic device, the thickness of the first insulating island is greater than a first distance between the lowest height of the third conductive element and the highest height of the third conductive element.

3. The electronic device as claimed in claim 2, wherein the ratio of the thickness to the first distance is greater than 1.1 and less than 3.

4. The electronic device as claimed in claim 1, wherein in the cross-sectional view of the electronic device, an edge of the third conductive element is adjacent to an edge of the first insulating island, and the minimum distance between the edge of the third conductive element and the edge of the first insulating island is greater than 1 micrometer (µm).

5. The electronic device as claimed in claim 1, further comprising a first insulating layer disposed between the third conductive element and the second conductive element, wherein the first insulating layer has a plurality of through holes through which the third conductive element is electrically connected to the second conductive element.

6. The electronic device as claimed in claim 5, wherein a portion of the first insulating island is disposed in the plurality of through holes.

7. The electronic device as claimed in claim 1, further comprising a second insulating layer disposed between the first conductive element and the second conductive element, wherein the second conductive element overlaps the first conductive element.

8. The electronic device as claimed in claim 1, further comprising a second insulating layer disposed between the first conductive element and the second conductive element, wherein the second conductive element and the first conductive element do not overlap each other.

9. The electronic device as claimed in claim 1, wherein the first conductive element and the second conductive element are made of the same layer.

10. The electronic device as claimed in claim 1, further comprising a second insulating island disposed on the active region, wherein the material of the second insulating island is the same as the material of the first insulating island in the peripheral region.

11. The electronic device as claimed in claim 1, wherein the transistor includes a semiconductor element, and in another cross-sectional view of the electronic device, the width of the third insulating island is greater than the width of the semiconductor element.

12. The electronic device as claimed in claim 1, wherein the material of the first conductive element and the material of the second conductive element are metals, and the material of the third conductive element is a transparent conductive material.

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