System and method for remote access

Abstract

A system having an interface for remote memory. In some embodiments, the system includes interface circuitry having: a first interface configured to be connected to processing circuitry; and a second interface configured to be connected to memory, the first interface including a cache coherence interface, and the second interface being different from the first interface.

Description

Systems and Methods for Remote Access One or more aspects of embodiments in accordance with the present disclosure relate to computing systems, and more particularly to an interface for remote memory. [Cross - reference to related applications] This application claims the benefit and priority of U.S. Provisional Application No. 63 / 408,725, filed on September 21, 2022, and entitled "REMOTE ACCESS SOLUTION FOR CXL MEMORY CLUSTERING ACROSS SERVERS", the entire content of which is incorporated herein by reference. In a computing system, a host central processing unit (CPU) may be connected to a host memory via, for example, an address bus and a data bus or using a high - speed interconnect such as Compute Express Link (CXL). Some systems for forming a connection to the memory may impose limitations on the length of the conductors (e.g., cables) available for forming the connection. Aspects of the present disclosure relate to such an overall technical environment. According to an embodiment of the present disclosure, a system is provided, the system including an interface circuit having: a first interface configured to connect to a processing circuit; and a second interface configured to connect to a memory, the first interface including a cache coherence interface, and the second interface being different from the first interface. In some embodiments, the system further includes a memory server connected to the second interface. In some embodiments, the second interface includes a remote direct memory access interface. In some embodiments, the second interface includes a computer cluster interconnect interface. In some embodiments, the computer cluster interconnect interface includes an Ethernet interface. In some embodiments, the memory server is connected to the second interface by a cable having a length greater than 6 feet. In some embodiments, the cache coherence interface includes a Compute Express Link (CXL) interface. In some embodiments, the first interface is configured to: send data to the processing circuit in response to a load instruction executed by the processing circuit; and receive data from the processing circuit in response to a store instruction executed by the processing circuit. In some embodiments, the system further includes a Compute Express Link (CXL) root complex connected between the processing circuit and the first interface. According to an embodiment of the present disclosure, a system is provided, the system including an interface circuit having: a first interface configured to be connected to a processing circuit; and a second interface configured to be connected to a memory, the first interface including a Compute Express Link (CXL) interface, and the second interface being different from the first interface. In some embodiments, the system further includes a memory server connected to the second interface. In some embodiments, the second interface includes a Remote Direct Memory Access (RDMA) interface. In some embodiments, the second interface includes a Compute Cluster Interconnect (CCI) interface. In some embodiments, the Compute Cluster Interconnect (CCI) interface includes an Ethernet interface. In some embodiments, the memory server is connected to the second interface by a cable having a length greater than 6 feet. In some embodiments, the CXL interface includes a cache coherence interface. In some embodiments, the first interface is configured to: send data to the processing circuit in response to a load instruction executed by the processing circuit; and receive data from the processing circuit in response to a store instruction executed by the processing circuit. In some embodiments, the system further includes a CXL root complex connected between the processing circuit and the first interface. According to an embodiment of the present disclosure, a method is provided, the method including: executing, by a central processing unit, a store instruction for storing a first value in a first memory location at a first address; in response to the execution of the store instruction, sending, by an interface circuit, a store command to a memory including the first memory location, the store command being a command for storing the first value in the first memory location, wherein the interface circuit has: a first interface connected to the central processing unit; and a second interface connected to the memory, the first interface including a Compute Express Link (CXL) interface, and the second interface being different from the first interface. In some embodiments, the method further includes: executing, by the central processing unit, a load instruction for loading a value in a second memory location at a second address into a register of the central processing unit; in response to the execution of the load instruction, sending, by the interface circuit, a read command to the memory, the read command being a command for reading the value in the second memory location. The following detailed description, presented in conjunction with the accompanying drawings, is intended as an illustration of exemplary embodiments of an interface for remote memory provided in accordance with the present disclosure and is not intended to represent the only form in which the present disclosure may be constructed or utilized. This description sets forth the features of the present disclosure in connection with the illustrated embodiments. However, it is to be understood that the same or equivalent functions and structures may be achieved by different embodiments that are also intended to be encompassed within the scope of the present disclosure. As indicated elsewhere herein, like element numbers are intended to indicate like elements or features. In various computing applications, a host may have time-varying requirements for memory, such as when starting a new application on the host, when a currently running application is closed, or when the user's demand for an application changes. However, equipping the host with sufficient main memory to handle the highest foreseeable demand can be costly. Additionally, cable length limitations that may exist for some interfaces between the host central processing unit (CPU) and memory may limit the volume available for memory (e.g., limiting it to the volume available within the same rack as the host CPU). Accordingly, some embodiments create a mechanism for enabling host applications to access a memory pool located outside the local rack level using normal load and store commands. Such embodiments may use a cache coherence interface (e.g., a Compute Express Link (CXL) interface) with the interface circuit, which may operate as the front end of the memory pool, where a low-latency remote memory access protocol (e.g., Remote Direct Memory Access (RDMA)) memory pool operates as the back end of the memory pool. The system may dynamically allocate resources via the interface circuit and the shared memory pool. Such embodiments can achieve memory disaggregation of physically separated memory resources (e.g., resources that do not need to be in the same rack as the processing circuit using the resources), thereby avoiding some limitations of memory interface links (e.g., a link based on Peripheral Component Interconnect Express (PCIe) (such as CXL), the cable length of which may be limited to, for example, a length between 8 inches (for 3rd generation PCIe (PCIe Gen 3)) and 15 inches (for 1st generation PCIe (PCIe Gen 1))). In some embodiments, the host can access the memory pool using load semantics and store semantics, and avoid the need to build physical resources (such as dynamic random access memory (DRAM)) on devices within the same rack as the host. Disaggregated memory (via a low-latency remote memory access protocol such as RDMA) can be used to allocate resources at runtime. In some embodiments, the interface circuit can be reconfigured to any size and mapped to a remote memory pool, and the remote memory pool can provide a set of fluid memory resources that can be dynamically combined to meet the needs of servers in a composable disaggregated memory architecture. Some embodiments achieve a lower total cost of ownership (TCO) by supporting long-distance memory disaggregation via RDMA (which can be compatible with cables longer than, for example, 6 feet) and overcome cable length limitations present in some interfaces. Referring to FIG. 1A, in some embodiments, computing system 100 includes host 102 (including central processing unit (CPU) 105 (central processing unit (CPU) 105 can be or can include processing circuitry) and local memory 110 (local memory 110 can be double data rate (DDR) memory)) and memory system 115. Memory system 115 can include interface circuit 120, which includes a front-end interface 130 having a cache coherent memory access protocol (such as cxl.mem) and a back-end interface 135 having low-latency remote memory access capabilities (such as a network interface card supporting RDMA). Front-end interface 130 can be a CXL interface (such as CXL.mem); in such a case, interface circuit 120 can be referred to as a CXL device. Memory pool server 125 can include back-end interface 135 and memory pool 140. Memory pool 140 can include, for example, dynamic random access memory banks (such as configured as memory modules, each memory module including a plurality of memory chips located on a printed circuit board). The memory can be directly connected to the back-end interface 135 of memory pool server 125, or some or all of the memory can be implemented in one or more memory servers connected to memory pool server 125 via a computer cluster interconnect interface. The front-end interface 130 can be connected to the address bus and data bus of the CPU 105. In this way, from the perspective of the CPU 105, the storage provided by the memory system 115 and the local memory 110 can be substantially the same, and in operation, when the addresses of the load instructions and store instructions executed by the CPU 105 are within the physical address range allocated to the interface circuit 120, the memory system 115 can directly respond to such instructions. The ability of the memory system 115 to directly respond to the load instructions and store instructions executed by the CPU 105 enables the CPU not to call a driver function to store data in the memory system 115 or retrieve data from the memory system 115. The host 102 can view the interface circuit 120 as a CXL device, and the CXL device advertises the memory resources of the CXL device to the host 102 via CXL discovery. For example, a suitable value stored in the Base Address Register (BAR) in the CXL interface of the interface circuit 120 can determine the size of the memory address range allocated to the interface circuit 120. At startup, in order to determine the size of the memory available via the interface circuit 120, the CPU can write a character of all binary ones to the appropriate base address register and then read the same base address register; in response, the interface circuit 120 can send a character indicating the size of the available memory area. The host 102 can use the memory resources by executing a load instruction or a store instruction in the instruction set of the CPU 105. FIG. 1B shows a method that can be adopted at startup. In some embodiments, at startup, the RDMA network interface controller 135 in the interface circuit 120 sends a discovery message to the memory pool server 125 at 155. Then, the memory pool server 125 replies to the discovery message at 160 with a response reporting the capabilities of the memory pool server 125. The reported capabilities can include, for example, the capacity of the memory pool server 125, the bandwidth of the memory pool server 125, and the latency of the memory pool server 125. The RDMA network interface controller 135 can save such capability information and provide the capability information to the memory interface 130 at 165 for CXL bootup. Then, the memory interface 130 can perform CXL bootup at 170 and provide memory-related information to the host 102 using a coherent device attribute table (CDAT) (under the CXL standard, CDAT can be used to send memory information to the host). As shown in the figure, the connection between the interface circuit 120 and the memory pool server 125 can be a Remote Direct Memory Access (RDMA) connection. The RDMA connection can include a cable 145 (e.g., an electrical cable (with multiple conductors) or an optical cable (including multiple optical fibers)). The cable 145 can form a connection between the rear-end interface 135 in the interface circuit 120 and another rear-end interface 135 in the memory pool server 125. The interface between the RDMA network interface controllers 135 can be Ethernet or any other suitable computer cluster interconnect interface (e.g., InfiniBand or Fibre Channel). Configuring the rear-end interface 135 of the interface circuit 120 can include using the Internet Protocol (IP) address of the memory pool server 125 (which can be part of the configuration of the rear-end interface 135) to communicate with the memory pool server 125. The interface circuit 120 can negotiate memory resources with the memory pool server 125 at startup time and establish a Remote Direct Memory Access connection with the RDMA server to perform read or write operations. From the perspective of the host 102, the interface circuit 120 can be a CXL type 3 device. In operation, the Remote Direct Memory Access system can create one or more queue pairs (QP) and cache one or more memory regions (MR). Then, the queue pairs and memory regions can be used to perform Remote Direct Memory Access read and write operations in response to load and store operations executed by the CPU 105 of the host 102. For example, when the CPU 105 of the host 102 executes a store instruction to store a first value in a first memory location at a first address (the first address is mapped to the interface circuit 120), the interface circuit 120 can receive the store instruction (as a result of the first address being mapped to the interface circuit 120), and the interface circuit 120 can send a store command to the memory pool server 125 in response to executing the store instruction. The store command can be sent via Remote Direct Memory Access; for example, to store the first value in the memory pool 140 of the memory pool server 125, the interface circuit 120 can initiate a Remote Direct Memory Access write transfer to store the first value in the memory pool 140. As another example, if the CPU 105 of the host 102 executes a load instruction for loading a value in a second memory location at a second address (the second address is mapped to the interface circuit 120) into a register of the CPU 105, the interface circuit 120 can receive the load instruction (as a result of the second address being mapped to the interface circuit 120), and the interface circuit 120 can send a read command to the memory pool server 125 in response to executing the load instruction. The read command can be sent via Remote Direct Memory Access; for example, in order to read a value stored in the memory pool 140 of the memory pool server 125, the interface circuit 120 can initiate a Remote Direct Memory Access read transfer to read the value from the memory pool 140. CXL 2.0 can support a hot plug feature. In this way, in an embodiment where the front-end interface 130 is a CXL interface, the front-end interface 130 can make a new connection with the interface circuit 120 while the host is operating, or disconnect from the interface circuit 120 while the host is operating without interfering with the operation of the host. In some embodiments, the latency of the memory system 115 is low enough (e.g., as a result of using a low-latency protocol such as Infiniband or RDMA) to enable support for the cache coherence maintenance feature of CXL.cache. Referring to FIG. 1C, in some embodiments, a graphics processing unit (GPU) 148 is connected to the CPU 105 and the interface circuit 120. For example, the connection can be made via a CXL switch 150. In some embodiments, as shown, the graphics processing unit 148 is part of the host 102; in other embodiments, the graphics processing unit 148 can be the main processing circuit of another host, or the graphics processing unit 148 can be a separate CXL device (e.g., a Type 2 CXL device), the separate CXL device is not part of the host 102 and is connected to the host via a CXL link like the interface circuit 120. In some embodiments, the graphics processing unit 148 is located in a Type 2 CXL device. Additionally, as shown in FIG. 1C, in some embodiments, multiple memory pool servers 125 are connected to the RDMA network interface controller 135 of the interface circuit 120. As shown, each of the memory pool servers 125 can be connected to the interface circuit 120 via any suitable type of connection (e.g., Ethernet, InfiniBand, or Fibre Channel). As shown, the interface circuit 120 can include a single RDMA network interface controller 135 capable of supporting multiple corresponding connections with the multiple memory pool servers 125, or the interface circuit 120 can include multiple RDMA network interface controllers 135 or one NIC with multiple physical interfaces, each of the multiple physical interfaces being connected to the memory interface 130 of the interface circuit 120 and each (i) connected to a corresponding one of the memory pool servers 125 and (ii) configured to support the protocol (e.g., Ethernet, InfiniBand, or Fibre Channel) used in the connection between the interface circuit 120 and the corresponding memory pool server 125. For example, a connection using InfiniBand can have lower latency than a connection using Ethernet. Such a connection (e.g., a connection using InfiniBand) can meet the latency requirements of one or more of the three CXL protocols (cxl.io, cxl.mem, and cxl.cache). Referring to FIG. 1D, in some embodiments, the memory pool servers 125 are configured differently. For example, one of the memory pool servers 125 can include a memory pool 140a optimized for high bandwidth, one of the memory pool servers 125 can include a memory pool 140b optimized for low latency, and one of the memory pool servers 125 can include a memory pool 140c optimized for high capacity. In some embodiments, the type of connection used to connect the memory pool servers 125 to the interface circuit 120 can be selected to provide a specific level of performance to the host 102. For example, an InfiniBand connection, which can have relatively low latency, can be used to connect the memory pool server 125 that includes the memory pool 140b optimized for low latency to the interface circuit 120, such that the total latency experienced by the host 102 is reduced for two reasons: (i) due to the type of memory pool 140 used and (ii) due to the type of connection used to connect the memory pool server 125 to the interface circuit 120. In some embodiments, applications running on host 102 may require memory with different characteristics; for example, for performance reasons, an application may require low-latency memory. In some embodiments, such applications may be aware of the different performance characteristics of different memory pool servers 125 connected to host 102 via interface circuit 120. As a result of the startup process (described above), the application may access such information, which may be stored (e.g., by the operating system of host 102) in the host. Then, when the application requests memory from the operating system, the application may request memory with performance characteristics that will achieve an acceptable performance for the application. Referring to FIG. 2, in some embodiments, multiple hosts may each be connected to memory pool server 125 and share the memory resources of memory pool server 125. As in the embodiment shown in FIG. 1A, each interface circuit 120 provides a memory device with a configured dynamic memory size to the corresponding host in the absence of physical memory resources (e.g., DRAM memory) physically present in interface circuit 120. A pool of disaggregated memory resources may be created, for example, in one or more memory servers, and the pool of disaggregated memory resources may be placed in a remote location. A remote collection of memory servers may be referred to as a memory farm. A low-latency network protocol (e.g., Remote Direct Memory Access) may be used to access the memory resources; in such embodiments, the memory resources may be used efficiently and the total cost of ownership (TCO) may be reduced. Referring to FIG. 3, as described above, interface circuit 120 may occupy a portion of the physical address space of CPU 105. Host 102 may further include (in addition to CPU 105 and local memory 110) a CXL root complex 305, which may form an interface to the CXL link shown in FIG. 1A on the host side. In some embodiments, in operation, the host writes a mapped CXL-DRAM into the physical address space, sends a request to CXL root complex 305 (via the address bus and data bus of CPU 105), CXL root complex 305 generates a Transaction Layer Packet (TLP) and sends the TLP to interface circuit 120, and interface circuit 120 converts the transaction layer packet into a Remote Direct Memory Access and sends the Remote Direct Memory Access via the computer cluster interconnect interface. FIG. 4 illustrates an embodiment including a CXL switch 405. Each of the plurality of hosts 102 is connected to the CXL switch 405 (the CXL switch 405 may be or may include, for example, a CXL 2.0 switch), and the CXL switch 405 is connected to one or more interface circuits 120 (each labeled "IC" in FIG. 4) and zero or more other CXL devices 410 (each labeled "D" in FIG. 4). The interface circuit 120 may be connected to a single shared memory pool server 125 via a remote direct memory access connection (as shown), or the interface circuit 120 may be connected to multiple memory pool servers 125 (for example, each interface circuit 120 may be connected to a corresponding memory pool server 125). FIG. 5 is a flowchart of a method in some embodiments. The method includes: at 505, a central processing unit executes a store instruction for storing a first value in a first memory location at a first address; and at 510, in response to executing the store instruction, an interface circuit sends a store command to a memory including the first memory location, the store command being a command for storing the first value in the first memory location. The method may further include: at 515, a central processing unit executes a load instruction for reading a second value, the second value being storable in a second memory location at a second address; and at 520, in response to executing the load instruction, an interface circuit sends a read command to a memory including the second memory location, the read command being a command for reading the second value from the second memory location. The computer cluster interconnect interface described herein is any interface suitable for interconnecting computers, such as InfiniBand, Ethernet, or Fibre Channel. A "portion" of a thing described herein means "at least some" of the thing, and thus may mean less than all of the thing or all of the thing. As such, a "portion" of a thing includes the entire thing as a special case, i.e., the entire thing is an instance of a portion of the thing. When a second quantity is "within Y" of a first quantity X as described herein, it means the second quantity is at least X - Y and the second quantity is at most X + Y. When a second number is "within Y%" of a first number as described herein, it means the second number is at least (1 - Y / 100) times the first number and the second number is at most (1 + Y / 100) times the first number. The term "or" as used herein shall be construed as "and / or", such that, for example, "A or B" means any one of "A" or "B" or "A and B". The background provided in the Background section of this disclosure is included only to set the context and does not admit that the content of this section is prior art. Any one of the components described or any combination of components (e.g., in any system diagram included herein) can be used to perform one or more of the operations of any flowchart included herein. Additionally, (i) the operations are exemplary operations and may involve various additional steps not explicitly covered, and (ii) the chronological order of the operations may vary. As used herein, each of the terms "processing circuitry" and "processing component" is meant to refer to any combination of hardware, firmware, and software for processing data or digital signals. Processing circuitry hardware can include, for example, application specific integrated circuits (ASICs), general-purpose or special-purpose central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), and programmable logic devices such as field programmable gate arrays (FPGAs). In the processing circuitry described herein, each function is performed by hardware configured (i.e., hardwired) to perform the function, or by more general hardware (e.g., a CPU) configured to execute instructions stored in a non-transitory storage medium. The processing circuitry can be fabricated on a single printed circuit board (PCB) or distributed across several interconnected PCBs. The processing circuitry can include other processing circuitry; for example, the processing circuitry can include two processing circuits, an FPGA, and a CPU interconnected on a PCB. As used herein, when a method (e.g., an adjustment) or a first quantity (e.g., a first variable) is said to be "based on" a second quantity (e.g., a second variable), it means that the second quantity is an input to the method or affects the first quantity. For example, the second quantity can be an input (e.g., the only input or one of several inputs) to a function that calculates the first quantity, or the first quantity can be equal to the second quantity, or the first quantity can be the same as the second quantity (e.g., stored in the same one or more locations in memory as the second quantity). It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish between individual elements, components, regions, layers, or sections. Thus, a first element, first component, first region, first layer, or first section discussed herein can be referred to as a second element, second component, second region, second layer, or second section without departing from the spirit and scope of the inventive concept. For ease of explanation, spatially relative terms such as "beneath", "below", "lower", "under", "above", "upper", and similar terms may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. It should be understood that such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped over, an element described as "below" or "beneath" or "under" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "under" can encompass both an upper and a lower orientation. The device may have other orientations (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Additionally, it should also be understood that when a layer is described as being "between" two layers, the layer may be the only layer between the two layers, or there may also be one or more intermediate layers. The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the inventive concept. The terms "substantially", "about", and similar terms used herein are used as approximating terms and not as terms of degree, and are intended to account for the inherent deviations of measured or calculated values that would be known to those of ordinary skill in the art. Unless the context clearly dictates otherwise, the singular forms "a" and "an" used herein are intended to also include the plural forms. It should be further understood that when the term "comprises and / or comprising" is used in this specification, it specifies the presence of the stated feature, integer, step, operation, element, and / or component, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of" when appearing after a series of elements modify the entire series of elements and not each individual element of the series. Additionally, when the term "may" is used in describing embodiments of the inventive concept, it refers to "one or more embodiments of the present disclosure". Further, the term "exemplary" is intended to mean an example or illustration. The terms "use", "using", and "used" used herein may be considered synonymous with the terms "utilize", "utilizing", and "utilized", respectively. It should be understood that when an element or layer is referred to as being "on", "connected to", "coupled to", or "adjacent to" another element or layer, the element or layer can be directly on, directly connected to, directly coupled to, or directly adjacent to the other element or layer, or there can be one or more intermediate elements or layers. In contrast, when an element or layer is referred to as being "directly" on, "directly connected to", "directly coupled to", or "directly adjacent to" another element or layer, there are no intermediate elements or layers. Any numerical range described herein is intended to include all sub-ranges within the range having the same numerical precision. For example, the range "1.0 to 10.0" or "between 1.0 and 10.0" is intended to include all sub-ranges between the minimum value 1.0 and the maximum value 10.0 (and including 1.0 and 10.0), i.e., having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0 (e.g., (for example, 2.4 to 7.6)). Similarly, a range described as "within 35% of 10" is intended to include all sub-ranges between the minimum value 6.5 (i.e., (1 - 35 / 100) multiplied by 10) and the maximum value 13.5 (i.e., (1 + 35 / 100) multiplied by 10) (and including 6.5 and 13.5), i.e., having a minimum value equal to or greater than 6.5 and a maximum value equal to or less than 13.5 (e.g., (for example) 7.4 to 10.6). Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Some embodiments include the features listed in the following numbered statements. 1. A system, comprising: an interface circuit having: a first interface configured to connect to a processing circuit; and a second interface configured to connect to a memory, the first interface including a cache coherence interface, and the second interface being different from the first interface. 2. The system of claim 1, further comprising a memory server connected to the second interface. 3. The system of claim 1 or claim 2, wherein the second interface includes a remote direct memory access interface. 4. The system of any of the preceding claims, wherein the second interface includes a computer cluster interconnect interface. 5. The system of claim 4, wherein the computer cluster interconnect interface includes an Ethernet interface. 6. The system of any of claims 2 to 5, wherein the memory server is connected to the second interface by a cable having a length greater than 6 feet. 7. The system of any of the preceding claims, wherein the cache coherence interface includes a Compute Express Link (CXL) interface. 8. The system of any of the preceding claims, wherein the first interface is configured to: send data to the processing circuit in response to a load instruction executed by the processing circuit; and receive data from the processing circuit in response to a store instruction executed by the processing circuit. 9. The system of any of the preceding claims, further comprising a Compute Express Link (CXL) root complex connected between the processing circuit and the first interface. 10. A system, comprising: an interface circuit having: a first interface configured to connect to a processing circuit; and a second interface configured to connect to a memory, the first interface including a Compute Express Link (CXL) interface, and the second interface being different from the first interface. 11. The system of claim 10, further comprising a memory server connected to the second interface. 12. The system of claim 10 or claim 11, wherein the second interface includes a remote direct memory access interface. 13. The system of any of claims 10 to 12, wherein the second interface includes a computer cluster interconnect interface. 14. The system of any of claims 10 to 13, wherein the computer cluster interconnect interface includes an Ethernet interface. 15. The system of any of claims 10 to 14, wherein the memory server is connected to the second interface by a cable having a length greater than 6 feet. 16. The system of any of claims 10 to 15, wherein the CXL interface includes a cache coherence interface. 17. The system of any of claims 10 to 16, wherein the first interface is configured to: send data to the processing circuit in response to a load instruction executed by the processing circuit; and receive data from the processing circuit in response to a store instruction executed by the processing circuit.18. The system according to any one of claims 10 to 17 further includes a CXL root complex connected between the processing circuit and the first interface. 19. A method includes: executing, by a central processing unit, a store instruction for storing a first value in a first memory location at a first address; in response to the execution of the store instruction, sending, by an interface circuit, a store command to a memory including the first memory location, the store command being a command for storing the first value in the first memory location; wherein the interface circuit has: a first interface connected to the central processing unit; and a second interface connected to the memory; the first interface includes a Compute Express Link (CXL) interface; and the second interface is different from the first interface. 20. The method according to claim 19 further includes: executing, by the central processing unit, a load instruction for loading a value in a second memory location at a second address into a register of the central processing unit; in response to the execution of the load instruction, sending, by the interface circuit, a read command to the memory, the read command being a command for reading the value in the second memory location. Although exemplary embodiments for interfaces for remote memories have been specifically set forth and shown herein, many modifications and variations will be apparent to those skilled in the art. Accordingly, it is to be understood that interfaces for remote memories constructed in accordance with the principles of this disclosure may be implemented differently than specifically set forth herein. The invention is also defined in the following claims and their equivalents. 100: Computing system 102: Host 105, 415: Central processing unit (CPU) 110: Local memory 115: Memory system 120: Interface circuit 125: Memory pool server 130: Front-end interface / memory interface 135: Back-end interface / RDMA network interface controller 140, 140a, 140b, 140c: Memory pool 145: Cable 148: Graphics processing unit 150, 405: CXL switch 155, 160, 165, 170, 505, 510, 515, 520: Operations 305: CXL root complex 410: CXL device Referring to the specification, the claims and the drawings, those and other features and advantages of the present disclosure will be appreciated and understood. In the drawings: FIG. 1A is a block diagram of a single-host computing system according to an embodiment of the present disclosure. FIG. 1B is a flowchart of a startup procedure according to an embodiment of the present disclosure. FIG. 1C is a block diagram of a single-host computing system including a graphics processing unit according to an embodiment of the present disclosure. FIG. 1D is a block diagram of a single-host computing system including multiple different memory pool servers according to an embodiment of the present disclosure. FIG. 2 is a block diagram of a multi-host computing system according to an embodiment of the present disclosure. FIG. 3 is an operational block diagram of a single-host computing system according to an embodiment of the present disclosure. FIG. 4 is a block diagram of a multi-host computing system having a switch according to an embodiment of the present disclosure. FIG. 5 is a flowchart of a method according to an embodiment of the present disclosure. 505, 510, 515, 520: Operations

Claims

1. A system for remote access, comprising: An interface circuit has: a first interface configured to be connected to a processing circuit; and a second interface configured to connect to memory, the memory including: a first memory server including a first performance characteristic, the first performance characteristic including at least one of a first capacity, a first latency, or a first bandwidth; The first memory server includes a second performance characteristic, the second performance characteristic including at least one of a second capacity, a second latency, or a second bandwidth, wherein the first capacity is greater than the second capacity, the first latency is less than the second latency, or the first bandwidth is greater than the second bandwidth, the first interface includes a cache coherence interface, the second interface is different from the first interface, and the interface circuitry is configured to send a message through the first interface to identify the first memory server as having a first capacity greater than the second capacity, a first latency less than the second latency, or a first bandwidth greater than the second bandwidth.

2. The system as described in claim 1 further includes the first memory server and the second memory server connected to the second interface.

3. The system as claimed in claim 2, wherein the second interface includes a remote direct memory access interface.

4. The system as claimed in claim 2, wherein the second interface includes a computer cluster interconnect interface.

5. The system as described in claim 4, wherein the computer cluster interconnect interface includes an Ethernet interface.

6. The system as claimed in claim 2, wherein the first memory server or the second memory server is connected to the second interface via a cable longer than 6 feet.

7. The system as described in claim 1, wherein the cache coherence interface includes a fast compute link (CXL) interface.

8. The system as claimed in claim 1, wherein the first interface is configured to: send data to the processing circuit in response to a load instruction executed by the processing circuit; and receive data from the processing circuit in response to a store instruction executed by the processing circuit.

9. The system as claimed in claim 1 further includes a Fast Computing Link (CXL) root complex connected between the processing circuitry and the first interface.

10. A system for remote access, comprising: An interface circuit has: a first interface configured to be connected to a processing circuit; and a second interface configured to connect to memory, the memory including: a first memory server including a first performance characteristic, the first performance characteristic including at least one of a first capacity, a first latency, or a first bandwidth; The first memory server includes a second performance characteristic, the second performance characteristic including at least one of a second capacity, a second latency, or a second bandwidth, wherein the first capacity is greater than the second capacity, the first latency is less than the second latency, or the first bandwidth is greater than the second bandwidth, the first interface includes a Fast Compute Link (CXL) interface, the second interface is different from the first interface, and the interface circuitry is configured to send messages through the first interface to identify the first memory server as having a first capacity greater than the second capacity, a first latency less than the second latency, or a first bandwidth greater than the second bandwidth.

11. The system as described in claim 10 further includes the first memory server and the second memory server connected to the second interface.

12. The system as claimed in claim 11, wherein the second interface includes a remote direct memory access interface.

13. The system as claimed in claim 11, wherein the second interface includes a computer cluster interconnect interface.

14. The system as claimed in claim 13, wherein the computer cluster interconnect interface includes an Ethernet interface.

15. The system as claimed in claim 13, wherein the first memory server or the second memory server is connected to the second interface via a cable longer than 6 feet.

16. The system as described in claim 13, wherein the fast computation link interface includes a cache coherence interface.

17. The system of claim 10, wherein the first interface is configured to: send data to the processing circuit in response to a load instruction executed by the processing circuit; and receive data from the processing circuit in response to a store instruction executed by the processing circuit.

18. The system as claimed in claim 10 further includes a fast computing link root complex connected between the processing circuitry and the first interface.

19. A method for remote access, comprising: A storage instruction is executed by the central processing unit to store a first value in a first memory location at the first address, and in response to the execution of the storage instruction, a storage command is sent by an interface circuit to a memory including the first memory location, the storage command being a command to store the first value in the first memory location, wherein the interface circuit has: a first interface connected to the central processing unit; and a second interface connected to the memory, the memory further comprising: a first memory server, including a first performance characteristic, the first performance characteristic including at least one of a first capacity, a first latency, or a first bandwidth; The first memory server includes a second performance characteristic, the second performance characteristic including at least one of a second capacity, a second latency, or a second bandwidth, wherein the first capacity is greater than the second capacity, the first latency is less than the second latency, or the first bandwidth is greater than the second bandwidth, the first memory location is associated with the first memory server or the second memory server, the first interface includes a Fast Compute Link (CXL) interface, the interface circuitry is configured to send information about the capacity, latency, or bandwidth of the memory through the first interface, and the second interface is different from the first interface.

20. The method as described in claim 19, further comprising: The central processing unit executes a load instruction to load a value from a second memory location at a second address into a register of the central processing unit. In response to the execution of the load instruction, the interface circuit sends a read command to the memory, the read command being a command to read the value from the second memory location. The second memory location is associated with either the first memory server or the second memory server.

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