High performance verify techniques in a memory device

Abstract

The memory device includes at least one memory block having a plurality of memory cells arranged in a plurality of word lines. The memory device includes a control circuitry configured to program the memory cells of the at least one memory block in a plurality of programming loops. The control circuitry is further configured to receive a command to write user data to the memory device. On at least a portion of a selected word line of the plurality of word lines, the control circuitry is configured to perform a smart authentication operation to obtain a smart authentication programming voltage. After obtaining the smart authentication programming voltage, the control circuitry is configured in the plurality of programming loops to program the memory cells of the selected word line to include the user data and data corresponding to the smart authentication programming voltage.

Description

High-performance verification technology in memory devices The present disclosure relates generally to memory devices and, more particularly, to techniques for verifying the threshold voltage of a memory cell during a programming operation. Semiconductor memory is widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery pack). A NAND memory device includes a chip having a plurality of memory blocks, each comprising an array of memory cells arranged in a plurality of word lines. Programming the memory cells of a word line to retain data typically occurs with a plurality of programming loops, each of which includes applying a programming pulse to a control gate of the word line and, optionally, applying a verify operation to sense the threshold voltage of the memory cell being programmed. In many programming techniques, the programming pulse has an initial programming voltage in a first programming loop, and the voltage of the programming pulse is then incrementally increased between programming loops until programming is complete. The optimal value of the initial programming voltage varies across the plurality of memory blocks in the chip and may also vary within the word lines of a single memory block. If the initial programming voltage is set too high, programming of some memory cells may occur, but if it is set too low, programming performance may be degraded. One method for improving programming performance without requiring the initial programming voltage to be set only at a high level to enable programming is to perform a smart verify operation at the beginning of a programming operation in a memory block. The smart verify operation includes a plurality of smart verify programming loops, each including a programming pulse and a verify operation. During the verify operation in each smart verify programming loop, the number of memory cells having a threshold voltage greater than a predetermined verify voltage is determined and compared to a target. If the verify operation passes, the voltage of the last programming pulse is stored in a NAND register on the chip and used as the initial programming voltage for subsequent programming operations in the memory block. However, NAND registers are generally unable to maintain all optimal initial programming voltages for all memory blocks in the chip. One aspect of the present disclosure relates to a method for programming a memory device. The method includes receiving a command to write user data to the memory device. The method then proceeds with preparing at least one memory block comprising a plurality of memory cells arranged in a plurality of word lines. The method then proceeds with performing a smart verify operation on at least a portion of a selected word line of the plurality of word lines to obtain a smart verify programming voltage. After obtaining the smart verify programming voltage, the method then proceeds with programming the memory cells of the selected word line in a plurality of programming loops to include the user data and data corresponding to the smart verify programming voltage. According to another aspect of the present disclosure, the selected word line includes a plurality of strings, and the step of performing the smart verification operation to obtain the smart verification programming voltage is performed only on a first string of the plurality of strings. The step of programming the memory cells of the selected word line includes programming the data corresponding to the smart verification programming voltage into the memory cells of the first string of the selected word line. According to yet another aspect of the present disclosure, the method further includes the step of using the smart verification programming voltage as an initial programming voltage to program the user data into the memory cells of other strings of the selected word line in a plurality of programming loops. According to yet another aspect of the present disclosure, each of the word lines of the memory block includes the plurality of strings. The method further includes the steps of performing the smart verification operation on the first string of each of the word lines to obtain the smart verification programming voltage for each word line, and programming data corresponding to the smart verification programming voltage for each word line into the memory cells of the first string of the word line. According to a further aspect of the present disclosure, the smart verification programming voltage programmed into the memory cells of the first string of the selected word line is the initial programming voltage when programming at least one additional word line in a plurality of programming loops. According to yet further aspects of the present disclosure, the memory cells of the first string programmed to contain the data corresponding to the smart verify programming voltage are programmed to a one-bit-per-cell (SLC) storage scheme. According to still further aspects of the present disclosure, the first string of memory cells programmed to contain the user data are programmed to a storage scheme of one or more bits per memory cell. According to another aspect of the present disclosure, the data corresponding to the smart verification programming voltage and programmed to the memory cells of the first string is no more than one byte of data. According to yet another aspect of the present disclosure, the memory device has a NAND register that can contain only one byte of data or no more than three bytes of data. Another aspect of the present disclosure relates to a memory device. The memory device includes at least one memory block having a plurality of memory cells arranged in a plurality of word lines. The memory device includes control circuitry configured to program the memory cells of the at least one memory block in a plurality of programming loops. The control circuitry is further configured to receive a command to write user data to the memory device. The control circuitry is configured to perform a smart verification operation on at least a portion of a selected word line of the plurality of word lines to obtain a smart verification programming voltage. After obtaining the smart verification programming voltage, the control circuitry is configured to program the memory cells of the selected word line in the plurality of programming loops to include the user data and data corresponding to the smart verification programming voltage. According to another aspect of the present disclosure, the selected word line includes a plurality of strings, and the control circuitry is configured to program the data corresponding to the smart verification programming voltage into the memory cells of the first string of the selected word line. As yet another aspect of the present disclosure, the control circuit system is further configured to use the smart verification programming voltage as an initial programming voltage to program the user data into the memory cells of other strings of the selected word line in a plurality of programming loops. According to yet another aspect of the present disclosure, each of the word lines of the memory block includes the plurality of strings. The control circuitry is further configured to perform the smart verification operation on the first string of each of the word lines to obtain the smart verification programming voltage for each word line and program data corresponding to the smart verification programming voltage for each word line into the memory cells of the first string of the word line. According to a further aspect of the present disclosure, the smart verification programming voltage programmed by the control circuitry into the memory cells of the first string of the selected word line is the initial programming voltage when programming at least one additional word line of the memory block in a plurality of programming loops. According to yet further aspects of the present disclosure, the first string of memory cells programmed by the control circuitry to contain the data corresponding to the smart verify programming voltage are programmed to a one-bit-per-memory-cell (SLC) storage scheme. According to still further aspects of the present disclosure, the first string of memory cells programmed by the control circuitry to contain the user data are programmed to a storage scheme of two or more bits per memory cell. According to another aspect of the present disclosure, the data corresponding to the smart verification programming voltage and programmed to the memory cells of the first string is no more than one byte of data. According to yet another aspect of the present disclosure, the memory device further includes a NAND register that can contain only one byte of data or no more than three bytes of data. Yet another aspect of the present disclosure relates to a device comprising at least one memory block, the at least one memory block including a plurality of memory cells arranged in a plurality of word lines. The device also includes a programming component for programming user data into the plurality of memory cells. The programming component is configured to program the memory cells of the at least one memory block in a plurality of programming loops. The programming component is further configured to receive a command to write user data to the memory device. The programming component is configured to perform a smart verification operation on a first string of a plurality of strings of a selected word line of the plurality of word lines to obtain a smart verification programming voltage. After obtaining the smart verification programming voltage, the programming component is further configured to program the memory cells of the selected word line in a plurality of programming loops to include the user data and data corresponding to the smart verification programming voltage. The programming component is further configured to use the smart verification programming voltage as an initial programming voltage to program the memory cells of other strings of the selected word line in a plurality of programming loops. According to another aspect of the present disclosure, the programming component is further configured to perform the smart verification operation on the first string of each of the plurality of word lines in the memory block and program data corresponding to a unique smart verification programming voltage into the memory cells of the first string of each word line. One aspect of the present disclosure relates to improved techniques for programming memory cells of a memory block, such that when a smart verify voltage is acquired during a smart verify operation for a memory block, the smart verify voltage is stored directly in the memory cells of the memory block in addition to being stored in a NAND register. In the event that a memory device undergoes a block jump (a change from programming one memory block to programming another) and the smart verify voltage stored in the NAND register does not match the newly selected block, the smart verify voltage for the newly selected block need not be acquired again. Instead, it can be easily accessed from the memory cells of the memory block and input into the NAND register. These programming techniques improve performance by allowing the memory device to skip time-consuming smart verify operations in certain situations (such as after a block jump) without risking programming. These programming techniques are discussed in further detail below. FIG1A is a block diagram of an example memory device 100 configured to operate according to the programming techniques of the present disclosure. Memory die 108 includes a memory structure 126 of memory cells, such as a memory cell array, control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable via word lines via row decoder 124 and via bit lines via column decoder 132. Read / write circuitry 128 includes multiple sense blocks SB1, SB2, ..., SBp (sense circuitry) and allows pages of memory cells to be read or programmed in parallel. Typically, controller 122 is included in the same memory device 100 as one or more memory dies 108 (e.g., a removable memory card). Commands and data are transferred between a host 140 and controller 122 via data bus 120 and between the controller and one or more memory dies 108 via line 118. The memory structure 126 may be two-dimensional or three-dimensional. The memory structure 126 may include one or more arrays of memory cells, including three-dimensional arrays. The memory structure 126 may include a monolithic three-dimensional memory structure in which multiple memory levels are formed above (and not in) a single substrate, such as a wafer, without an intervening substrate. The memory structure 126 may include any type of non-volatile memory monolithically formed in one or more physical levels of an array of memory cells having active regions disposed above a silicon substrate. The memory structure 126 may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate. Control circuitry 110 cooperates with read / write circuits 128 to perform memory operations on memory structure 126 and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. State machine 112 provides chip-level control of memory operations. For example, a storage area 113 for programming parameters may be provided. Programming parameters may include a programming voltage, a programming voltage bias, a position parameter (indicating the location of a memory cell), a contact wire connector thickness parameter, a verify voltage, and / or the like. The position parameters may indicate a location of a memory cell within the entire array of NAND strings, a location of a memory cell within a specific group of NAND strings, a location of a memory cell on a specific plane, and / or the like. The contact wire connector thickness parameters may indicate a thickness of a contact wire connector, a substrate or material comprising the contact wire connector, and / or the like. An on-chip address decoder 114 provides an address interface between the addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. A power control module 116 controls the power and voltage supplied to the word lines and bit lines during memory operations. It may include drivers for the word lines, SGS and SGD transistors, and source lines. In one approach, the sense blocks may include bit line drivers. The SGS transistors are select gate transistors at the source terminal of a NAND string, and the SGD transistors are select gate transistors at the drain terminal of a NAND string. In some embodiments, some components may be combined. In various designs, one or more components other than memory structure 126 (alone or in combination) may be considered as at least one control circuit configured to perform the actions described herein. For example, the control circuit may include any one or a combination of control circuitry 110, state machine 112, decoders 114 / 132, power control module 116, sensing blocks SBb, SB2, ..., SBp, read / write circuitry 128, controller 122, and the like. The control circuits may include a programming circuit configured to perform a programming and verification operation on a set of memory cells, wherein the set of memory cells includes memory cells assigned to represent one data state of a plurality of data states and memory cells assigned to represent another data state of a plurality of data states; the programming and verification operation includes a plurality of programming and verification iterations; and in each programming and verification iteration, the programming circuit programs a selected word line and thereafter applies a verification signal to the selected word line. The control circuits may also include a counting circuit configured to obtain a count of memory cells that pass a verification test for the one data state. The control circuits may also include a determination circuit configured to determine whether the programming operation is complete based on the count exceeding a threshold. For example, FIG. 1B is a block diagram of an example control circuit 150 including a programming circuit 151 , a counting circuit 152 , and a determination circuit 153 . The off-chip controller 122 may include a processor 122c, storage devices (memory, such as ROM 122a and RAM 122b), and an error-correction code (ECC) engine 245. The ECC engine can correct many read errors, such as those caused when the upper tail of the Vth distribution becomes too high. However, in some cases, uncorrectable errors may occur. The techniques provided herein reduce the possibility of uncorrectable errors. Storage device(s) 122a, 122b contain code (such as an instruction set), and processor 122c is operable to execute the instruction set to provide the functionality described herein. Alternatively or additionally, processor 122c may access code from storage device 126a of memory structure 126, such as a reserved area of ​​memory cells in one or more word lines. For example, the code may be used by controller 122 to access memory structure 126, such as for programming, reading, and erasing operations. The code may include boot code and control code (e.g., an instruction set). Boot code is software that initializes controller 122 during a boot or startup process and enables controller 122 to access memory structure 126. The code may be used by controller 122 to control one or more memory structures 126. After power is turned on, processor 122c retrieves the boot code from ROM 122a or storage device 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. When the control code is loaded into RAM 122b, it is executed by processor 122c. The control code includes drivers for performing basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports. Generally, the control code may include instructions to perform the functions described herein, including the steps of the flowcharts discussed further below, and provide voltage waveforms, including those discussed further below. In one embodiment, the host is a computing device (e.g., a laptop, desktop, smartphone, tablet, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices for communicating with the one or more processors. In addition to NAND flash memory, other types of non-volatile memory can also be used. Semiconductor memory devices include volatile memory devices such as dynamic random access memory (DRAM) or static random access memory (SRAM) devices, non-volatile memory devices such as resistive random access memory (ReRAM), electrically erasable programmable read-only memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM), as well as other semiconductor devices capable of storing information. Each type of memory device can have different configurations. For example, a flash memory device can be configured in a NAND or NOR configuration. In any combination, memory devices may be formed from passive and / or active components. By way of non-limiting example, passive semiconductor memory components include ReRAM devices, which, in some embodiments, include a resistivity-switching storage element, such as an antifuse or phase-change material, and optionally a steering element (such as a diode or transistor). Further, by way of non-limiting example, active semiconductor memory components include EEPROM and flash memory devices, which, in some embodiments, include components containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material. Multiple memory elements can be configured so that they are connected in series or so that each element can be accessed individually. By way of non-limiting example, a flash memory device in a NAND configuration (NAND memory) typically contains memory elements connected in series. A NAND string is an example of a group of transistors connected in series, including memory cells and SG transistors. A NAND memory array can be configured such that the array includes multiple memory strings, where a string includes multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements can be configured such that each element can be accessed individually, such as in a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located in and / or above a substrate can be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure. In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device layer. Generally speaking, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in the xy plane) that extends substantially parallel to a major surface of a substrate supporting the memory elements. The substrate can be a wafer, on or in which the layers of the memory elements are formed, or it can be a carrier substrate that is attached to the memory elements after they are formed. As a non-limiting example, the substrate can include a semiconductor, such as silicon. The memory elements can be arranged in a single memory device layer in an ordered array, such as a plurality of rows and / or columns. However, the memory elements can be arranged in an irregular or non-orthogonal configuration. Each memory element can have two or more electrodes or contact lines, such as bit lines and word lines. The three-dimensional memory array is configured such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y, and z directions, where the z direction is substantially vertical and the x and y directions are substantially parallel to the major surface of the substrate). As a non-limiting example, a three-dimensional memory structure can be configured vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be configured as a plurality of vertical rows (e.g., rows extending substantially perpendicular to the major surface of the substrate, i.e., in the y-direction), wherein each row has a plurality of memory elements. These rows can be arranged in a two-dimensional configuration (e.g., in the xy plane), resulting in a three-dimensional configuration of memory elements having multiple vertically stacked elements on the memory plane. Other configurations of memory elements in three dimensions can also constitute a three-dimensional memory array. By way of non-limiting example, in a three-dimensional array of NAND strings, the memory elements can be coupled together to form a NAND string within a single horizontal (e.g., xy) memory device level. Alternatively, the memory elements can be coupled together to form vertical NAND strings that span multiple horizontal memory device levels. Other three-dimensional configurations are envisioned, with some NAND strings containing memory elements in a single memory level, while other strings contain memory elements spanning multiple memory levels. The three-dimensional memory array can also be designed in a NOR configuration and a ReRAM configuration. Generally speaking, in a monolithic three-dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic three-dimensional array, the layers comprising each memory device level of the array are generally formed on layers of underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three-dimensional memory array may share or have intervening layers between the memory device levels. Third, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device with multiple layers of memory. For example, a non-monolithic stacked memory can be constructed by forming memory layers on separate substrates and then stacking the memory layers on top of each other. The substrate can be thinned or removed from the memory device layers before stacking, but because the memory device layers are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device. FIG2 illustrates blocks 200 and 210 of memory cells in an example two-dimensional configuration of the memory array 126 of FIG1 . The memory array 126 may include multiple such blocks 200 and 210. Each example block 200 and 210 includes a number of NAND strings and respective bit lines (e.g., BL0, BL1, ...), which are shared within the block. Each NAND string is connected at one end to a drain-side select gate (SGD), and the control gates of the drain select gates are connected via a common SGD line. The NAND strings are connected at their other ends to a source-side select gate (SGS), which in turn is connected to a common source line 220. For example, one hundred and twelve word lines WL0 through WL111 extend between SGS and SGD. In some embodiments, a memory block may include more or fewer than one hundred and twelve word lines. For example, in some embodiments, a memory block includes one hundred and sixty-four word lines. In some cases, dummy word lines (which do not contain user data) can also be used in the memory array adjacent to the select gate transistors. Such dummy word lines can shield the edge data word lines from certain edge effects. One type of non-volatile memory system that can be provided in a memory array is a floating gate memory, such as the type shown in Figures 3A and 3B. However, other types of non-volatile memory may also be used. As discussed in further detail below, in another example shown in Figures 4A and 4B, a charge trapping memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A triple dielectric layer of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in a confined area. This stored charge then detectably changes the threshold voltage of a portion of the channel of the cell. The cell is erased by injecting hot holes into the nitride. A similar cell can be configured in a split-gate configuration, where the doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor. In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends across the channel between the source and drain diffusions. The charge for one data bit is concentrated in the dielectric layer adjacent to the drain, and the charge for the other data bit is concentrated in the dielectric layer adjacent to the source. Multi-state data storage is achieved by separately reading the binary states of spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known. FIG3A illustrates a cross-sectional view of example floating gate memory cells 300, 310, and 320 in a NAND string. In this figure, a bit line or NAND string direction runs into the page, and the word line direction runs from left to right. As an example, word line 324 extends across the NAND string, including respective channel regions 306, 316, and 326. Memory cell 300 includes control gate 302, floating gate 304, tunnel oxide layer 305, and channel region 306. Memory cell 310 includes control gate 312, floating gate 314, tunnel oxide layer 315, and channel region 316. Memory cell 320 includes control gate 322, floating gate 321, tunnel oxide layer 325, and channel region 326. Each memory cell 300, 310, and 320 is in a different respective NAND string. Also shown is an inter-poly dielectric (IPD) layer 328. Control gates 302, 312, 322 are part of the word line. A cross-sectional view along a contact line connector 329 is provided in FIG3B. The control gates 302, 312, 322 wrap around the floating gates 304, 314, 321, increasing the surface contact area between the control gates 302, 312, 322 and the floating gates 304, 314, 321. This results in higher IPD capacitance, which leads to a higher coupling ratio, making programming and erasing easier. However, as NAND memory devices shrink, the spacing between adjacent cells 300, 310, 320 becomes smaller, leaving little space between two adjacent floating gates 302, 312, 322 for the control gates 302, 312, 322 and the IPD layer 328. As an alternative, as shown in Figures 4A and 4B , flat or planar memory cells 400, 410, and 420 have been developed, in which control gates 402, 412, and 422 are flat or planar; that is, they do not wrap around the floating gate and only contact the charge storage layer 428 above it. In this case, there is no advantage to having a tall floating gate. Instead, the floating gate is made thinner. Alternatively, the floating gate can be used to store charge, or a thin charge-trapping layer can be used to trap charge. This approach avoids the problem of ballistic electron transport (where electrons can travel through the floating gate after tunneling through the tunnel oxide during programming). FIG4A illustrates a cross-sectional view of example charge trapping memory cells 400, 410, and 420 in a NAND string. This view is taken along the wordline of the memory cells 400, 410, and 420, which include planar control gates and charge trapping regions, as a two-dimensional example of the memory cells 400, 410, and 420 in the memory cell array 126 of FIG1 . Charge trapping memory can be used in NOR and NAND flash memory devices. This technology uses an insulator, such as a SiN film, to store electrons, as opposed to floating gate MOSFET technology, which uses a conductor, such as doped polysilicon, to store electrons. As an example, a wordline 424 extends across the NAND string, including respective channel regions 406, 416, and 426. Portions of the wordline provide control gates 402, 412, and 422. Beneath the word lines are IPD layer 428, charge trapping layers 404, 414, 421, polysilicon layers 405, 415, 425, and tunneling layers 409, 407, and 408. Each charge trapping layer 404, 414, 421 extends continuously within a respective NAND string. The planar configuration of the control gate allows for thinner fabrication than a floating gate. Additionally, memory cells can be placed more closely together. FIG4B illustrates a cross-sectional view of the structure of FIG4A along contact line connector 429. NAND string 430 includes SGS transistor 431, example memory cells 400, 433, ..., 435, and SGD transistor 436. Channels in IPD layer 428 between SGS and SGD transistors 431 and 436 allow communication between control gate layer 402 and floating gate layer. Control gate 402 and floating gate layer can be polysilicon, and the tunnel oxide layer can be, for example, silicon oxide. IPD layer 428 can be a stack of nitride (N) and oxide (O), such as in a NONON configuration. A NAND string can be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. A channel voltage Vch can be applied directly to the channel region of the substrate. Figure 5 illustrates an example block diagram of sense block SB1 of Figure 1 . In one approach, a sense block includes multiple sense circuits. Each sense circuit is associated with a data latch. For example, example sense circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different sense blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sense circuits to be separated and handled by a separate processor in each sense block. For example, a sense circuit controller 560 in SB1 can communicate with the set of sense circuits and latches. The sense circuit controller 560 can include a precharge circuit 561 that provides a voltage to each sense circuit for setting a precharge voltage. In one possible approach, the voltage is provided independently to each sense circuit, for example, via a data bus and a local bus. In another possible approach, a common voltage is provided simultaneously to each sense circuit. The sense circuit controller 560 may also include a precharge circuit 561, a memory 562, and a processor 563. The memory 562 may store code executable by the processor to perform the functions described herein. These functions may include reading latches 550b, 551b, 552b, 553b associated with the sense circuits 550a, 551a, 552a, 553a, setting bit values ​​in the latches, and providing a voltage for setting a precharge level in the sense nodes of the sense circuits 550a, 551a, 552a, 553a. Further example details of the sense circuit controller 560 and the sense circuits 550a, 551a, 552a, 553a are provided below. In some embodiments, a memory cell may include a flag register comprising a set of latches storing flag bits. In some embodiments, the number of flag registers may correspond to the number of data states. In some embodiments, one or more flag registers may be used to control the type of verification technique used when verifying a memory cell. In some embodiments, the output of a flag bit may modify the associated logic of the device (e.g., address decoding circuitry) such that a particular block of the cell is selected. Batch operations (e.g., an erase operation, etc.) may be performed using flags set in flag registers, or a combination of flag registers and address registers (e.g., in implicit addressing), or alternatively, by direct addressing using address registers alone. Figure 6A is a perspective view of one set of blocks 600 in an example three-dimensional configuration of the memory array 126 of Figure 1 . On a substrate are example blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (storage elements), along with a surrounding area 604 containing circuitry used by the blocks BLK0, BLK1, BLK2, and BLK3. For example, the circuitry may include a voltage driver 605 that may be connected to the control gate layers of the blocks BLK0, BLK1, BLK2, and BLK3. In one approach, the control gate layers at a common height in the blocks BLK0, BLK1, BLK2, and BLK3 are driven together. The substrate 601 may also carry the circuitry beneath the blocks BLK0, BLK1, BLK2, and BLK3, along with one or more underlying metal layers patterned into conductive paths to carry the circuitry's signals. Blocks BLK0, BLK1, BLK2, and BLK3 are formed in a middle region 602 of the memory device. In an upper region 603 of the memory device, one or more upper metal layers are patterned into conductive paths to carry signals for the circuitry. Each block BLK0, BLK1, BLK2, and BLK3 comprises a stacked region of memory cells, where alternating levels of the stack represent word lines. In one possible approach, each block BLK0, BLK1, BLK2, and BLK3 has opposing layered sides from which vertical contacts extend upward to the upper metal layer to form a connection to the conductive paths. While four blocks BLK0, BLK1, BLK2, and BLK3 are shown as an example, two or more blocks may be used, extending in the x-direction and / or the y-direction. In one possible approach, the length of the plane (in the x-direction) represents the direction in which the signal traces in the one or more upper metal layers extend to the word lines (the word line or SGD line direction), and the width of the plane (in the y-direction) represents the direction in which the signal traces in the one or more upper metal layers extend to the bit lines (the bit line direction). The z-direction represents the height of the memory device. Figure 6B illustrates an example cross-sectional view of a portion of one of the blocks BLK0, BLK1, BLK2, and BLK3 in Figure 6A. This block includes a stack 610 of alternating conductive and dielectric layers. In this example, in addition to data wordline layers (wordlines) WL0 through WL111, the conductive layers include two SGD layers, two SGS layers, and four dummy wordline layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 through DL116. Furthermore, a region of stack 610 is illustrated that includes NAND strings NS1 and NS2. Each NAND string includes a memory hole 618, 619 filled with material forming the memory cells adjacent to those wordlines. Region 622 of stack 610 is shown in greater detail in Figure 6D and discussed in more detail below. Stack 610 includes a substrate 611, an insulating film 612 on substrate 611, and a portion of a source line SL. NS1 has a source terminal 613 at the bottom 614 of the stack and a drain terminal 615 at the top 616 of the stack 610. Contact line connectors (e.g., slits, such as metal-filled gaps) 617 and 620 may be periodically provided across stack 610 as interconnects extending through stack 610, such as connecting a source line to a specific contact line above stack 610. Contact line connectors 617 and 620 may be used during word line formation and subsequently filled with metal. A portion of a bit line BL0 is also shown. A conductive via 621 connects drain terminal 615 to BL0. FIG6C illustrates a graph of the diameter of the memory holes in the stack of FIG6B . The vertical axis is aligned with the stack of FIG6B and depicts the width (wMH), i.e., diameter, of memory holes 618 and 619 . As an example, word line layers WL0 through WL111 of FIG6A are repeated at respective heights z0 through z111 in the stack. In such memory devices, the memory holes etched through the stack have very high aspect ratios. For example, a depth-to-diameter ratio of approximately 25 to 30 is common. The memory holes may have a circular cross-section. Due to the etching process, the memory hole width may vary along the length of the hole. Generally, the diameter gradually decreases from the top to the bottom of the memory hole. That is, the memory hole tapers, narrowing, at the bottom of the stack. In some cases, a slight narrowing occurs at the hole top near the select gate, causing the diameter to become slightly wider before gradually decreasing from the top to the bottom of the memory hole. Due to the uneven width of the memory holes, programming speed (including programming slope and erase speed of the memory cell) can vary based on their location along the memory hole, for example, based on their height in the stack. In the case of a smaller diameter memory hole, the electric field across the tunnel oxide is relatively strong, resulting in relatively higher programming and erase speeds. One approach is to define groups of adjacent word lines with similar memory hole diameters, for example, within a defined diameter range, and apply an optimized verify scheme to each word line in the group. Different groups can have different optimized verify schemes. Figure 6D shows a close-up of region 622 of stack 610 in Figure 6B. Memory cells are formed at different levels of the stack at the intersection of a wordline layer and a memory hole. In this example, SGD transistors 680 and 681 are provided above dummy memory cells 682 and 683 and a data memory cell MC. Several layers may be deposited, for example, along the sidewalls (SW) of memory hole 630 using atomic layer deposition and / or within each wordline layer. For example, each row (e.g., a pillar formed from the material within a memory hole 630) may include a charge trapping layer or film 663 (such as SiN or another nitride), a tunneling layer 664, a polysilicon body or channel 665, and a dielectric core 666. The wordline layer may include a blocking oxide / blocking high-k material 660, a metal barrier 661, and a conductive metal 662, such as tungsten, which serves as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are provided in memory hole 630. In other approaches, some layers may be included in the control gate layer. Additional pillars are similarly formed in different memory holes. A pillar can form the active area (AA) of a row of NAND strings. When a memory cell is programmed, electrons are stored in a portion of the charge-trapping layer associated with the memory cell. These electrons are drawn from the channel into the charge-trapping layer and through the tunneling layer. The Vth of the memory cell increases proportionally to the amount of stored charge. During an erase operation, the electrons return to the channel. Each memory hole 630 may be filled with a plurality of annular layers including a blocking oxide layer, a charge trapping layer 663, a tunneling layer 664, and a channel layer. A core region of each memory hole 630 is filled with a bulk material, and the plurality of annular layers are located between the core region and the word line in each memory hole 630. The NAND string can be considered to have a floating body channel because the length of the channel is not formed on a substrate. In addition, the NAND string is provided by multiple word line layers on top of each other in a stack and separated from each other by dielectric layers. Figure 7A illustrates a top view of an example wordline layer WL0 of stack 610 of Figure 6B. As mentioned, a three-dimensional memory device may include a stack of alternating conductive and dielectric layers. The conductive layers provide the control gates for the SG transistors and memory cells. The layers for the SG transistors are SG layers, and the layers for the memory cells are wordline layers. Furthermore, memory holes are formed in the stack and filled with charge-trapping material and channel material. As a result, a vertical NAND string is formed. The source line connects to the NAND string below the stack, and the bit line connects to the NAND string above the stack. Blocks BLK in a three-dimensional memory device can be divided into sub-blocks, each containing a group of NAND strings with a common SGD control line. For example, see SGD lines / control gates SGD0, SGD1, SGD2, and SGD3 in sub-blocks SBa, SBb, SBc, and SBd, respectively. Furthermore, a word line layer within a block can be divided into regions. Each region is within a respective sub-block and may extend between contact line connectors (e.g., gaps) formed periodically in the stack to process the word line layer during the memory device fabrication process. This processing may include replacing sacrificial material in the word line layer with metal. Generally, the distance between contact line connectors should be relatively small to account for the distance that an etchant can advance laterally to remove the sacrificial material and the distance that the metal can advance to fill the gaps created by the removal of the sacrificial material. For example, the distance between contact line connectors may allow for a series of memory holes between adjacent contact line connectors. The layout of the memory holes and contact line connectors should also consider the limit on the number of bit lines that can be extended across the area when each bit line is connected to a different memory cell. After processing the word line layer, the contact line connector can optionally be filled with metal to provide an interconnect through the stack. In this example, there are four rows of memory holes between adjacent contact line connectors. Here, a row is a group of memory holes aligned in the x-direction. Furthermore, the rows of memory holes are staggered to increase the density of the memory holes. The wordline layer, or wordline, is divided into regions WL0a, WL0b, WL0c, and WL0d, each connected by contact line 713. In one approach, the last region of a wordline layer in one block can be connected to a first region of a wordline layer in the next block. Contact line 713 is then connected to the voltage driver for the wordline layer. Region WL0a has example memory holes 710 and 711 along contact line 712. Region WL0b has example memory holes 714 and 715. Region WL0c has example memory holes 716 and 717. Region WL0d has example memory holes 718 and 719. The memory holes are also shown in FIG. 7B . Each memory hole can be part of a respective NAND string. For example, memory holes 710, 714, 716, and 718 can be part of NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, respectively. Each circle represents a cross-section of a memory hole at a wordline layer or an SG layer. The example circles shown with dashed lines represent memory cells provided by the material in the memory hole and by the adjacent wordline layer. For example, memory cells 720 and 721 are in WL0a, memory cells 724 and 725 are in WL0b, memory cells 726 and 727 are in WL0c, and memory cells 728 and 729 are in WL0d. These memory cells are at a common height in the stack. Contact line connectors (e.g., gaps, such as metal-filled gaps) 701, 702, 703, 704 can be located between regions WL0a through WL0d and adjacent to the edges of these regions. Contact line connectors 701, 702, 703, 704 provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack can be connected to a conductive line above the stack, where the conductive line is connected to a voltage driver in a peripheral region of the memory device. FIG7B illustrates a top view of an example top dielectric layer DL116 of the stack of FIG6B . The dielectric layer is divided into regions DL116a, DL116b, DL116c, and DL116d. Each region can be connected to a respective voltage driver. This allows simultaneous programming of a group of memory cells in one region of a wordline layer, where each memory cell is in a respective NAND string connected to a respective bitline. A voltage can be set on each bitline to enable or disable programming during each programming voltage period. Region DL116a has example memory holes 710 and 711 along contact line 712 that coincides with bit line BL0. Several bit lines extend over and connect to the memory holes, as indicated by the "X" symbols. BL0 connects to a group of memory holes including memory holes 711, 715, 717, and 719. Another example bit line BL1 connects to a group of memory holes including memory holes 710, 714, 716, and 718. Also shown are contact line connectors (e.g., gaps, such as metal-filled gaps) 701, 702, 703, and 704 from FIG. 7A, extending vertically through the stack. The bit lines may be sequentially numbered BL0 through BL23 in the x-direction across the DL116 layers. Different subsets of bit lines connect to memory cells in different columns. For example, BL0, BL4, BL8, BL12, BL16, and BL20 connect to memory cells in the first column of cells at the right-hand edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 connect to memory cells in the adjacent column of cells adjacent to the first column at the right-hand edge. BL3, BL7, BL11, BL15, BL19, and BL23 connect to memory cells in the first column of cells at the left-hand edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 connect to memory cells in the adjacent column of cells adjacent to the first column at the left-hand edge. The memory cells of a memory block can be programmed to store one or more bits of data in multiple data states, each associated with a respective threshold voltage Vt. For example, Figure 8 depicts the threshold voltage Vt distribution for a group of memory cells programmed according to a one-bit-per-cell (SLC) storage scheme. In an SLC storage scheme, there are two total data states, including an erased state (Er) and a single programmed data state (S1). Figure 9 depicts the threshold voltage Vt distribution for a three-bit-per-cell (TLC) storage scheme, which includes eight total data states: an erased state (Er) and seven programmed data states (S1, S2, S3, S4, S5, S6, and S7). Each programmed data state (S1-S7) is associated with a verify voltage (Vv1-Vv7) used during the verify portion of the programming operation. FIG10 depicts the threshold voltage Vt distribution for a four-bit-per-cell (QLC) storage scheme with sixteen total data states, namely, an erased state (Er) and fifteen programmed data states (S1 through S15). Other storage schemes are also available, such as two-bit-per-cell (MLC) with four data states, or five-bit-per-cell (PLC) with thirty-two data states. In some memory dies, memory blocks can be configured to operate in multiple storage scheme modes, such as SLC mode and TLC mode or SLC mode and QLC mode. The memory device can then be configured to initially write data to a memory block operating in SLC mode, which provides high performance. Then, in background operations when performance is not critical, the memory device can program the data into a multiple-bit-per-memory-cell format for long-term storage. Programming to multiple bits per memory cell typically involves multiple programming circuits. FIG11 depicts waveforms 1100 of voltages applied to a selected word line during an example memory cell programming operation for programming memory cells of the selected word line to a greater number of bits per memory cell (e.g., TLC or QLC). As depicted, each programming circuit includes a programming pulse VPGM and one or more verify pulses depending on which data states are being programmed in a particular programming circuit. For simplicity, each pulse is depicted as a square waveform; however, other shapes are possible, such as multi-level shapes or ramp shapes. Incremental Step Pulse Programming (ISPP) is used in this example pulse train, meaning the VPGM pulse amplitude is incrementally increased or stepped up with each successive programming loop. In other words, the pulse train includes VPGM pulses that gradually increase in amplitude with each programming loop using a fixed step size (dVPGM). A new pulse train begins with an initial VPGM pulse level, VPGMU, and ends at a final VPGM pulse level that does not exceed the maximum allowed level. Pulse train 1100 includes a series of VPGM pulses 1101 through 1115 applied to a selected word line comprising a group of nonvolatile memory cells. As an example, one or more verify voltage pulses 1116 through 1129 are provided after each VPGM pulse based on the target data state being verified in the programming loop. The verify voltages correspond to voltages Vv1 through VV7 (shown in FIG. 9 ). In parallel with the application of the verify voltage, a sensing operation can determine whether a particular memory cell in the selected word line has a threshold voltage Vt that is higher than the verify voltage associated with its intended data state by sensing the current through the memory cell. If the current is relatively high, this indicates that the memory cell is in a conductive state, such that its threshold voltage Vth is less than the verify voltage. If the current is relatively low, this indicates that the memory cell is in a non-conductive state, such that its threshold voltage Vth is higher than the verify voltage. If the memory cell passes verification, programming of the memory cell is complete, and further programming of the memory cell is inhibited for all remaining programming loops by applying an inhibit voltage to the bit line coupled to the memory cell. Programming continues until all memory cells pass verification of their intended data states, in which case programming passes, or until a predetermined maximum number of program loops is exceeded, in which case programming fails. The memory cells of a word line can be divided into a series of string groups or simply strings that can be programmed independently of each other, and programming can start from one string and cross the word line to another before continuing to the next word line in the memory block. In some programming operations, a "smart verify operation" is performed during the first few programming loops of a programming operation to determine the optimal starting programming voltage for the word lines in a memory block. Referring to Figures 12 and 13 , during a smart verify operation, only a portion of the selected word lines (e.g., a string) is selected for programming. In the first programming loop, a relatively low VPGMU_SV programming pulse is applied to the selected portion of the word lines, and then a verify operation is performed to determine whether the number of memory cells that have passed the verify level Vver1 is greater than a target number of memory cells. In the example of Figure 13 , after the first programming loop, no memory cells have a threshold voltage greater than the verify level Vver1. If the number of memory cells that passed the verify operation is not greater than the target, the programming voltage is increased (VPGM = VPGM + dVPGM) and another programming loop begins. This continues for as many programming loops as the target number of memory cells that have passed verify exceeding the verify level Vver1 is reached. In the examples of Figures 12 and 13 , three programming loops are used. Once a verify operation passes, VPGM or VPGM plus an increment of dVPGM is set to SV_VPGM and stored in the chip's NAND register. If other strings and word threads in the same memory block are subsequently programmed, the initial programming voltage VPGMU in the first programming loop of these subsequent programming operations is set to SV_VPGM. This improves performance by skipping unnecessary programming loops when no memory cells are being programmed. In the examples of Figures 12 and 13 , the smart verify operation passes the third smart verify programming loop (the shaded area of ​​the curve in Figure 13 identifies memory cells that have passed verification). Therefore, the SV_VPGM for subsequent word lines and strings is set to VPGMU_SV plus three times dVPGM, i.e., SV_VPGM = VPGMU_SV + 3*dVPGM. In other memory blocks within the same chip or in different chips, the number of programming loops that pass smart verify can be less than, equal to, or greater than three. In other words, the optimal SV_VPGM is unique for each memory block and even for each word line within the same memory block. In many chips, the NAND registers storing the SV_VPGM contain only one byte of data per chip, which is sufficient to store data for only one SV_VPGM at a time. In other chips, the NAND registers may contain more than one byte (e.g., no more than three bytes), but the number of bytes in the NAND register is far fewer than the number of memory blocks present in the chip. Within the bytes of data, different bit combinations may be associated with different SV_VPGM voltages, such as those found in Figure 14. Because the optimal initial programming voltage VPGM varies from memory block to memory block across the chip, and the chip's registers contain only one byte of data or far fewer bytes of data than there are memory blocks (e.g., no more than three bytes), it is necessary to re-acquire the SV_VPGM each time programming switches from one block to another (i.e., a block jump). In other words, every time programming jumps from one memory block to another, even if the next block has already been partially programmed and the SV_VPGM has been previously acquired, the memory block's unique SV_VPGM voltage is lost and replaced in the NAND register, and a smart verification operation must be performed to retrieve the SV_VPGM and write it back to the NAND register. This retrieval process consumes time and memory chip resources, thereby reducing performance. One aspect of the present disclosure relates to a programming technique in which, once the SV_VPGM for a memory block is acquired, instead of just writing the SV_VPGM to a register, it is also written directly to a spare byte of the memory block. From there, the SV_VPGM can be retained for a long time and transferred back to the NAND register without the need to perform a smart verify operation again. Thus, in the event of a block jump, the SV_VPGM for the block being programmed can be read from the spare byte and saved to the NAND register for use when programming the word lines in the memory block without the need for a time-consuming re-acquisition operation. This improves the performance of the memory device by reducing programming time. In some embodiments, the SV_VPGM can be saved for the entire memory block in the chip, so that the smart verify operation only needs to occur once for each memory block and only needs to be repeated when the memory block of the memory block is subsequently erased. As discussed in further detail below, in some embodiments, the SV_VPGM can be acquired and stored on a word line by word line basis, further improving programming performance and reliability. In other words, when programming all word lines in a memory block, instead of using a single SV_VPGM, each word line (or some number of word lines) can have its own unique SV_VPGM optimized for long-term storage that is maintained within the word line itself. In a memory block, each wordline contains a large amount of data when programmed. In the example embodiment of FIG. 15 , the depicted wordline contains sixteen kilobytes (16 kB) of total data. The majority of this capacity is reserved for user data, but one or more spare bytes are available for various purposes, such as error correction code (ECC) or row redundancy to repair defective rows. According to the programming techniques disclosed herein, one of these spare bytes for each wordline (hereinafter referred to as a "smart verify byte") is dedicated to storing the SV_VPGM. A table (such as the one depicted in FIG. 14 ) can be stored on-chip, associating different bit combinations in this smart verify byte with different SV_VPGM voltages. In some embodiments, the SV_VPGM can be stored in one wordline of a memory block and then used for all subsequent wordlines in that memory block. In other embodiments, the SV_VPGM is stored in the spare bytes of each wordline. Turning now to FIG. 16 , the steps for programming word lines of an example memory block are depicted. In step 1600 , a data write command is received. In some embodiments, this may be a data write command that requires a block jump. In step 1602 , the control circuitry in the chip checks the memory block to determine whether the SV_VPGM of the target word line is saved to the NAND register, and if not, determines whether the SV_VPGM has been written to the smart verify bytes. In one example embodiment where each word line has a unique SV_VPGM, if the string of the programmed word line WLn is any string other than String_0 (the first string of the word line), the SV_VPGM should have been programmed to the smart verify bytes of WLn, String_0. In other embodiments, the SV_VPGM may be common to a group of word lines or to the entire memory block. In this case, the smart verify bytes may be located elsewhere, such as in the smart verify bytes of another word line. For example, in some embodiments, the SV_VPGM of every other word line can be obtained and used for two, three, or more word lines. If the SV_VPGM voltage is stored in the smart verify bit and not in the NAND register, then at this stage, the SV_VPGM is written to the NAND register. At decision step 1604, a determination is made as to whether SV_VPGM is programmed into the smart verification bytes in the memory block. If the answer to decision step 1604 is "no," then in step 1606, the programming voltage VPGM is set to an initial smart verification programming voltage VPGMU_SV at a relatively low voltage level. In step 1608, the first smart verification programming loop begins by applying a programming pulse VPGM to the target word line and then performing a verify operation. The verify operation includes counting the number of memory cells having a threshold voltage exceeding the smart verification voltage Vver1 (see FIG. 17 ) and comparing that number to a target. In decision step 1610, a determination is made as to whether the verify operation passed, that is, whether the number of memory cells with a threshold voltage above the verify voltage exceeded the target. If the answer to decision step 1610 is "no," then in step 1612, VPGM is incrementally increased, that is, VPGM = VPGM + dVPGM. The method then returns to step 1608 to begin another smart verify programming loop. The method continues the loop from step 1608 to step 1612 for "N" programming loops until the verify operation passes. In the example depicted in FIG17 , the verify operation fails in the first four smart verify programming loops and passes on the fifth smart verify programming loop. However, the number of smart verify programming loops that pass the verify operation will vary from block to block and sometimes from word line to word line. If the answer to decision step 1610 is "yes," then in step 1614, VPGM is set to SV_VPGM and loaded into the NAND register. In step 1616, the user data is programmed into the memory cells of the target word line in one or more programming loops using ISPP programming techniques. The memory cells of the target word line can be programmed to any suitable programming scheme, such as MLC, TLC, or QLC. During step 1616, in programming loop N + m, the smart verify bytes of the target word line are programmed to contain data related to the SV_VPGM voltage. In one example embodiment, even if memory cells containing user data are programmed to a higher number of bits per memory cell with a verify operation in each programming loop, the memory cells of the smart verify bytes can be programmed to SLC in a single programming loop (loop N+m) without verifying. For example, if during erase, the smart verify bytes read "1, 1, 1, 1, 1, 1, 1, 1," and the data associated with the SV_VPGM voltage is "0, 1, 0, 1, 1, 1, 0, 1," then during the programming pulse of programming loop N+m, the bit lines coupled to the second, fourth, fifth, sixth, and eighth memory cells receive an inhibit voltage, causing programming to begin only in the first, third, and seventh memory cells. For the remaining programming loops of the programming operation, programming of all these memory cells is inhibited, making the additional time required to program the smart verify bytes negligible. The specific programming loop on which programming of the smart verify byte occurs can be selected based on the optimal level for a one-programming-pulse, zero-verify (1P0V) programming operation at which the VPGM voltage is at. In one embodiment, the N+m pulse that programs the memory cells of the smart verify byte can be a pulse after programming to the S1 data state is complete. Therefore, programming of the smart verify byte does not increase the time required to program the rest of the wordline, but instead is hidden within the programming operation that has already occurred. In this example, the threshold voltage Vt distribution of the memory cells in the smart verify byte can be similar to that of Figure 8 (SLC), and the threshold voltage Vt distribution of the remaining memory cells in the wordline can be similar to that of Figure 9 (TLC) or Figure 10 (QLC). Because the memory cells of the smart verify byte are non-volatile, the SV_VPGM remains accessible and does not need to be re-acquired even if power is removed and restored to the memory device. If the answer at decision step 1604 is “yes,” then at step 1620 , the smart verify byte is read and the SV_VPGM is loaded into a register without performing a smart verify operation. After step 1616 or step 1620, the remaining strings of the selected WLn are programmed using the ISPP programming technique and an initial programming voltage VPGMU equal to SV_VPGM in step 1618. In step 1622, the programmed word line is incrementally increased, i.e., WLn=WLn+1. This process continues until the write command is completed or the memory block is completely, i.e., closed. FIG18 is a table illustrating the programming order or sequence of the programming techniques discussed above when applied to an example memory block having word lines divided into four strings (labeled String_0 through String_3), according to one embodiment of the present disclosure. The first operation involves performing a smart verify operation on the memory cells of String_0 of the first word line (WLn) to be programmed to obtain a smart verify voltage for that word line WLn, namely, SV_VPGM_WLn. Next, the memory cells of WLn, String_0, are programmed to contain user data and data containing the SV_VPGM_WLn voltage. The second, third, and fourth programming operations respectively program the memory cells of String_1, String_2, and String_3 of word line WLn, using SV_VPGM_WLn as the initial programming voltage VPGMU for these programming operations. Programming then moves to the next sequential word line in the memory block, namely, WLn+1. The fifth programming operation acquires SV_VPGM_WLn+1 and programs String_0 and WLn+1. The sixth, seventh, and eighth programming operations use SV_VPGM_WLn+1 as the initial programming voltage VPGMU for these programming operations to program String_1, String_2, and String_3 of word line WLn+1, respectively. This pattern continues to word line WLn+2 until the write operation is complete. Various terms are used herein to refer to specific system components. Different companies may refer to the same or similar components by different names, and this description is not intended to distinguish between components that differ in name but not function. Where various functional units described in the following disclosure are referred to as "modules," such characterization is not intended to unduly limit the scope of possible implementation mechanisms. For example, a "module" may be implemented as a hardware circuit comprising a customized very-large-scale integration (VLSI) circuit or gate array, or as an off-the-shelf semiconductor comprising a logic chip, transistors, or other discrete components. In another example, a module may also be implemented in a programmable hardware device such as a field programmable gate array (FPGA), programmable array logic, a programmable logic device, or the like. Furthermore, a module may also be implemented at least in part by software executed by various types of processors. For example, a module may include a segment of executable code comprising one or more physical or logical blocks of computer instructions that are converted into an object, procedure, or function. Furthermore, the executable portions of such modules need not be physically located together, but may comprise different instructions stored in different locations that, when executed together, comprise the identified module and achieve the designated purpose of the module. Executable code may comprise only a single instruction or a set of multiple instructions and may be distributed over different code segments, or between different programs, or across several memory devices, etc. In software or partial software, module embodiments, the software portions may be stored on one or more computer-readable and / or executable storage media, including but not limited to electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based systems, apparatuses, or devices, or any suitable combination thereof. Generally, for the purposes of this disclosure, computer-readable and / or executable storage media may include any tangible and / or non-transitory medium capable of containing and / or storing a program for use by or in connection with an instruction execution system, apparatus, processor, or device. Similarly, for the purposes of this disclosure, the term "component" may include any tangible, physical, and non-transitory device. For example, a component may be in the form of a hardwired logic circuit comprising a custom VLSI circuit, a gate array, or other integrated circuit, or may comprise an off-the-shelf semiconductor including a logic chip, a transistor, or other discrete components, or any other suitable mechanical and / or electronic device. Additionally, a component may be implemented as a programmable hardware device, such as a field programmable gate array (FPGA), programmable array logic, a programmable logic device, or the like. Furthermore, a component may comprise one or more silicon-based integrated circuit devices (such as a chip, die, die plane, and package, or other discrete electrical devices) configured to communicate electrically with one or more other components via electrical conductors, such as a printed circuit board (PCB) or the like. Accordingly, the module defined above may be embodied by or implemented as a component in some embodiments, and in some examples, the terms module and component may be used interchangeably. As used herein, the term "circuit" includes one or more electrical and / or electronic components that form one or more conductive paths that allow current to flow. A circuit can be in a closed-loop configuration or an open-loop configuration. In a closed-loop configuration, the circuit components can provide a return path for the current. In contrast, in an open-loop configuration, the circuit components may be considered to form a circuit even though a return path for the current is not included. For example, an integrated circuit is referred to as a circuit regardless of whether the integrated circuit is coupled to ground (as a return path for the current). In certain exemplary embodiments, a circuit may include a collection of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit may include custom VLSI circuits, gate arrays, logic circuits, and / or other forms of integrated circuits, or may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In another example, a circuit may comprise one or more silicon-based integrated circuit devices (such as a chip, die, die plane, and package, or other discrete electrical devices) in electrical communication with one or more other components via electrical conductors, such as a printed circuit board (PCB). A circuit may also be implemented as a composite circuit relative to a programmable hardware device (such as a field programmable gate array (FPGA), programmable array logic, and / or programmable logic device). In other exemplary embodiments, a circuit may comprise a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Accordingly, a module as defined above may, in some embodiments, be embodied by or implemented as a circuit. It should be understood that the example embodiments disclosed herein may include one or more microprocessors and specific stored computer program instructions that control the one or more microprocessors, along with certain non-processor circuits and other components, to implement some, most, or all of the functions disclosed herein. Alternatively, some or all of the functions may be implemented by a state machine without stored program instructions, or by one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), where each or some combination of functions is implemented as custom logic. Combinations of these approaches may also be used. Further, references to a "controller" below shall be defined to include individual circuit elements, an application-specific integrated circuit (ASIC), a microcontroller with control software, a digital signal processor (DSP), a field-programmable gate array (fFPGA), and / or a processor with control software, or any combination thereof. Additionally, the terms “couple,” “coupled,” or “couples” as used herein are intended to refer to both direct and indirect connections. Thus, if a first device couples or is coupled to a second device, that connection may be through a direct connection or through an indirect connection via other devices (or components) and connections. When used herein, terms such as "an embodiment," "one embodiment," "exemplary embodiment," "particular embodiment," or other similar terms are intended to indicate that a particular feature, structure, function, operation, or characteristic described in connection with the embodiment is found in at least one embodiment of the present disclosure. Thus, appearances of phrases such as "in one embodiment," "in an embodiment," and "in an exemplary embodiment" may (but do not necessarily) all refer to the same embodiment, but rather to "one or more but not all embodiments," unless expressly specified otherwise. Furthermore, the terms "comprising," "having," "including," and variations thereof are used in an open-ended manner and, therefore, should be interpreted to mean "including, but not limited to," unless expressly specified otherwise. Furthermore, without further limitations, an element preceded by "comprising, ... and" does not preclude the presence of additional identical elements in the subject process, method, system, article, or apparatus that includes the element. Unless expressly specified otherwise, the terms "a," "an," and "the" also mean "one or more." Additionally, the phrase "at least one of A and B" may be used herein and / or in the following claims, whereby A and B are variables indicating specific objects or properties, indicating a selection of either A or B, or both A and B, similar to the phrase "and / or." Where there are more than two variables in one such phrase, the phrase is hereby defined to include only one of the variables, any one of the variables, any combination (or subcombination) of any of the variables, and all of the variables. Furthermore, as used herein, the terms "about" or "approximately" apply to all numerical values, whether or not expressly indicated. These terms generally refer to a range of values ​​that one of ordinary skill in the art would consider equivalent to the recited value (e.g., having the same function or result). In some instances, these terms may include values ​​rounded to the nearest significant figure. Additionally, unless expressly specified otherwise, any listing of items herein does not imply that any or all of the listed items are mutually exclusive and / or mutually inclusive. Further, according to set theory, unless expressly specified otherwise, the term "set" used herein should be interpreted to mean "one or more," and the term "sets" should be interpreted to mean "one or more / ones or more / ones or mores." The above embodiments have been provided for purposes of illustration and description. They are not intended to be exhaustive or to be limited to the precise forms disclosed. In light of the above description, many modifications and variations are possible. The described embodiments have been chosen to best explain the principles of the present technology and its practical applications, thereby enabling one skilled in the art to best utilize the technology in various embodiments and to envision various modifications suitable for a particular application. The scope of the present technology is defined by the accompanying claims. 100: Memory device 108: Memory die 110: Control circuitry 112: State machine 113: Storage area 114: On-chip address decoder; Decoder 116: Power control module 118: Line 120: Data bus 122: Controller; Off-chip controller 122a: ROM; Storage device 122b: RAM; Storage device 122c: Processor 124: Row decoder; Decoder 126: Memory structure; Memory array; Memory cell array 126a: Storage device 128: Read / write circuit 132: Row decoder; Decoder 140: Host 150: Control circuit 151: Program =Channel 152: Counting Circuit 153: Decision Circuit 200: Block 210: Block 220: Common Source Line 245: Error Correction Code (ECC) Engine 300: Floating Gate Memory Cell; Memory Cell; Cell 302: Control Gate; Floating Gate 304: Floating Gate 305: Tunnel Oxide Layer 306: Channel Region 310: Floating Gate Memory Cell; Memory Cell; Cell 312: Control Gate; Floating Gate 314: Floating Gate 315: Tunnel Oxide Layer 316: Channel Region 320: Floating Gate Memory Cell; Memory Cell; Cell 321: Floating Gate 322: Control Gate; Floating Gate 324: Word Line 325: Tunnel Oxide Layer 326: channel region 328: inter-polysilicon dielectric (IPD) layer 329: contact line connector 400: flat or planar memory cell; charge trapping memory cell; memory cell 402: control gate; control gate layer 404: charge trapping layer 405: polysilicon layer 406: channel region 407: tunneling layer 408: tunneling layer 409: tunneling layer 410: flat or planar memory cell; charge trapping memory cell; memory cell 412: control gate 414: charge trapping layer 415: polysilicon layer 416: channel region 420: flat or planar memory cell; charge trapping memory cell; memory cell 421 : Charge trapping layer 422: Control gate 424: Word line 425: Polysilicon layer 426: Channel region 428: Charge storage layer; IPD layer 429: Contact line connector 430: NAND string 431: SGS transistor 433: Memory cell 435: Memory cell 436: SGD transistor 455: P-type substrate region 456: N-type well 457: P-type well 550a: Sensing circuit 550b: Data latch; Latch 551a: Sensing circuit 551b: Data latch; Latch 552a: Sensing circuit 552b: Data latch; Latch 553a: Sensing circuit 553b: Data latch;Latch 560: Sense circuit controller 561: Precharge circuit 562: Memory 563: Processor 600: Block 601: Substrate 602: Middle region 603: Upper region 604: Peripheral region 605: Voltage driver 610: Stack 611: Substrate 612: Insulation film 613: Source terminal 614: Bottom 615: Drain terminal 616: Top 617: Contact line connector 618: Memory hole 619: Memory hole 620: Contact line connector 621: Conductive Via 622: Region 630: Memory hole 660: Blocking oxide / blocking high-k material 661: Metal barrier 662: Conductive metal 663: Charge trapping layer or film 664: Tunneling layer 665: Polysilicon body or channel 666: Dielectric core 680: SGD transistor 681: SGD transistor 682: Dummy memory cell 683: Dummy memory cell 690: Control gate 691: Control gate 692: Control gate 693: Control gate 694: Control gate 701: Connector Contact wire connector 702: Contact wire connector 703: Contact wire connector 704: Contact wire connector 710: Memory hole 711: Memory hole 712: Contact wire 713: Contact wire 714: Memory hole 715: Memory hole 716: Memory hole 717: Memory hole 718: Memory hole 719: Memory hole 720: Memory unit 721: Memory unit 724: Memory unit 725: Memory unit 726: Memory unit 727: Memory unit 7 28: Memory Cell 729: Memory Cell 1100: Waveform; Pulse Train 1101-1115: VPGM Pulses 1116-1129: Verify Voltage Pulses 1600: Step 1602: Step 1604: Step 1606: Step 1608: Step 1610: Step 1612: Step 1614: Step 1616: Step 1618: Step 1620: Step 1622: Step AA: Active Areas BL0-BL23: Bit Lines BLK, BLK0, BLK1, BLK2, BLK3: Blocks DL0-DL116: Dielectric Layers DL116a, DL116b, DL116c, DL116d: Regions DWLD0, DWLD1, DWLS0, DWLS1: Dummy Word Line Layer dVPGM: Fixed Stride Size;Increment Er: erased state MC: data memory cell NS0_SBa: NAND string NS1: NAND string NS1_SBb: NAND string NS2: NAND string NS2_SBc: NAND string NS3_SBd: NAND string NS4_SBe: NAND string S1-S15: programmed data state SB1, SB2, ... , SBp: sensing block (sensing circuit system) SBa, SBb, SBc, SBd: sub-blocks sd1, sd2, sd3, sd4, sd5, sd6, sd7: N-type source / drain diffusion region SGD: drain-side select gate SGD0, SGD1, SGD2, SGD3: SGD line / control gate SGS: source-side select gate SL: source line String_0, String_1, String_2, String_3: string Vch: channel voltage Vv1-Vv7: verification voltage; voltage V; ver1 :Verify level; Smart verification voltage WL0-WL111: Word line; Data word line layer; Word line layer WL0a, WL0b, WL0c, WL0d: Area WLL0: Word line layer wMH: Width x: Direction y: Direction z: Direction z0-z111: Height The following is a more detailed description of example embodiments with reference to the accompanying drawings, which illustrate exemplary embodiments of the present disclosure and are not to be considered limiting of its scope. The present disclosure is described and explained with added specificity and detail through the use of the accompanying drawings, in which: [FIG. 1A] is a block diagram of an example memory device; [FIG. 1B] is a block diagram of an example control circuit; [FIG. 2] depicts a block of memory cells in an example two-dimensional configuration of the memory array of FIG. 1A; [FIG. 3A] and [FIG. 3B] depict cross-sectional views of an example floating gate memory cell in a NAND string; [FIG. 4A] and [FIG. 4B] depict cross-sectional views of an example charge trapping memory cell in a NAND string; [FIG. 5] depicts an example block diagram of sense block SB1 of FIG. 1; [FIG. 6A] is a perspective view of a set of blocks in an example three-dimensional configuration of the memory array of FIG. 1; [FIG. 6B] depicts an example cross-sectional view of a portion of one of the blocks of FIG. 6A; [FIG. 6C] depicts a graph of memory hole diameters in the stack of FIG. 6B; [FIG. 6D] depicts a close-up view of region 622 of the stack of FIG. 6B; FIG. 7A depicts a top view of an example word line layer WLL0 of the stack of FIG. 6B ; FIG. 7B depicts a top view of an example top dielectric layer DL116 of the stack of FIG. 6B ; FIG. 8 depicts a threshold voltage distribution for a page of memory cells programmed to have one bit per memory cell; FIG. 9 depicts a threshold voltage distribution for a page of memory cells programmed to have three bits per memory cell (TLC); FIG. 10 depicts a threshold voltage distribution for a page of memory cells programmed to have four bits per memory cell (QLC); FIG. 11 depicts a voltage waveform of a voltage applied to a control gate of a selected word line during a programming operation; FIG. 12 depicts a voltage waveform of a voltage applied to a control gate of a selected word line during and immediately after a smart verify operation; FIG. 13 depicts a threshold voltage distribution for a plurality of memory cells before and after a plurality of programming loops of a smart verify operation; [FIG. 14] depicts an example table of SV_VPGM voltages associated with different bit combinations in a smart verify byte; [FIG. 15] is a schematic diagram of an example word line identifying the portion of the word line dedicated to user data and the portion of the word line dedicated to the smart verify byte; [FIG. 16] is a flow chart depicting the steps of programming word lines in a memory block according to an example embodiment of the present disclosure; [FIG. 17] depicts threshold voltage distributions of a plurality of memory cells before and after a plurality of programming loops of a smart verify operation; and [FIG. 18] depicts a table of a series of memory cells programmed in an example embodiment while utilizing an embodiment of the programming technique of the present disclosure. 100:Memory device 108:Memory chip 110: Control circuit system 112: State Machine 113: Storage area 114: chip address decoder; decoder 116: Power control module 118: Line 120: Data bus 122: controller; off-chip controller 122a:ROM; storage device 122b: RAM; storage device 122c: Processor 124: column decoder; decoder 126: memory structure; memory array; memory cell array 126a: Storage device 128: Read / Write Circuit 132: row decoder; decoder 140:Host 245: Error Correction Code (ECC) Engine SB1, SB2, ..., SBp: sensing block (sensing circuit system)

Claims

1. A method of programming a memory device, the method comprising the steps of: receiving a command to write user data to the memory device; preparing at least one memory block comprising a plurality of memory cells configured in a plurality of word lines; performing a smart authentication operation on at least a portion of a selected word line of the plurality of word lines to obtain a smart authentication programming voltage; and after obtaining the smart authentication programming voltage, programming the memory cells of the selected word line in a plurality of programming loops to include the user data and data corresponding to the smart authentication programming voltage, wherein the selected word line comprises a plurality of strings, and wherein the step of performing the smart authentication operation to obtain the smart authentication programming voltage is performed only on a first string of the plurality of strings, and wherein the step of programming the memory cells of the selected word line includes programming the data corresponding to the smart authentication programming voltage into the memory cells of the first string of the selected word line.

2. The method of claim 1, further comprising the step of using the intelligent verification programming voltage as an initial programming voltage to program the user data into the memory cells of other strings of the selected word line in a plurality of programming loops.

3. The method of claim 1, wherein each of the word lines of the memory block includes the plurality of strings, and further includes the steps of performing the smart verification operation on the first string of each of the word lines to obtain the smart verification programmed voltage of each word line and programming the data corresponding to the smart verification programmed voltage of each word line into the memory cells of the first string of the word line.

4. The method of claim 2, wherein the smart verification programming voltage programmed to the memory cells of the first string of the selected word line is the initial programming voltage when at least one additional word line is programmed in a plurality of programming loops.

5. The method of claim 1, wherein the first string is programmed to contain the data corresponding to the smart verification programmed voltage, and the memory cells are programmed into a storage scheme of one bit per memory cell (SLC).

6. The method of claim 5, wherein the first string is programmed to program the memory cells containing the user data into a storage scheme of one or more bits per memory cell.

7. The method of claim 1, wherein the data corresponding to the smart verification programmed voltage and programmed to the memory cells of the first string is no more than one byte of data.

8. The method of claim 1, wherein the memory device has a NAND register that may contain no more than three bytes of data.

9. A memory device comprising: at least one memory block including a plurality of memory cells arranged in a plurality of word lines; a control circuitry configured to program the memory cells of the at least one memory block in a plurality of programming loops, the control circuitry configured to: receive a command to write user data to the memory device; perform a smart authentication operation on at least a portion of a selected word line of the plurality of word lines to obtain a smart authentication programming voltage; and after obtaining the smart authentication programming voltage, program the memory cells of the selected word line in the plurality of programming loops to include the user data and data corresponding to the smart authentication programming voltage, wherein the selected word line includes a plurality of strings, and the control circuitry configured to program the data corresponding to the smart authentication programming voltage into the memory cells of a first string of the selected word line.

10. The memory device of claim 9, wherein the control circuitry is further configured to use the intelligent verification programming voltage as an initial programming voltage to program the user data into the memory cells of the other strings of the selected word line in a plurality of programming loops.

11. The memory device of claim 9, wherein each of the word lines of the memory block comprises the plurality of strings, and wherein the control circuitry is further configured to perform the smart verification operation on the first string of each of the word lines to obtain the smart verification programmed voltage of each word line and to program data corresponding to the smart verification programmed voltage of each word line into the memory cells of the first string of the word lines.

12. The memory device of claim 10, wherein the intelligent verification programming voltage programmed by the control circuit system to the memory cells of the first string via the selected word line is the initial programming voltage when at least one additional word line of the memory block is programmed in a plurality of programming loops.

13. The memory device of claim 9, wherein the memory cells of the first string, programmed by the control circuit system to contain the data corresponding to the smart verification programmed voltage, are programmed into a storage scheme of one bit per memory cell (SLC).

14. The memory device of claim 13, wherein the first string of memory cells containing the user data is programmed by the control circuit system into a storage scheme of two or more bits per memory cell.

15. The memory device of claim 9, wherein the data corresponding to the smart verification programmed voltage and programmed to the memory cells of the first string is no more than one byte of data.

16. The memory device of claim 9 further includes a NAND register that may contain no more than three bytes of data.

17. A memory device comprising: at least one memory block including a plurality of memory cells arranged in a plurality of word lines; a programming component for programming user data into the plurality of memory cells, and configured to program the memory cells of the at least one memory block in a plurality of programming loops, the programming component being configured to: receive a command to write user data to the memory device; and perform a smart verification operation on a first string of a plurality of strings of selected word lines of the plurality of word lines to obtain a smart verification programming voltage. After acquiring the smart verification programming voltage, in a plurality of programming loops, the memory cells of the selected word line are programmed to include the user data and data corresponding to the smart verification programming voltage, and the smart verification programming voltage is used as an initial programming voltage to program the memory cells of other strings of the selected word line in the plurality of programming loops.

18. The memory device of claim 17, wherein the programming component is further configured to perform the smart verification operation on the first string of each word line of the plurality of word lines in the memory block, and to program data corresponding to a unique smart verification programming voltage into the memory cells of the first string of each word line.

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