Memory cells, integrated circuit structures and memory arrays

Abstract

The memory cell includes a device layer and an interconnect structure disposed above the device layer. The device layer includes a plurality of transistors, each transistor including a gate structure extending longitudinally along a first direction. The interconnect structure includes a bottom metal line layer electrically coupled to the transistors in the device layer. The bottom metal line layer includes first, second, third, fourth, fifth, and sixth metal tracks arranged sequentially from first to sixth along the first direction. The distance between any two adjacent first, second, third, fourth, fifth, and sixth metal tracks measured along the first direction is consistent. The first metal track includes a metal line electrically coupled to the electrically grounded memory cell, and the sixth metal track includes a metal line electrically coupled to the power supply of the memory cell.

Description

Memory Cell, Integrated Circuit Structure, and Memory Array Embodiments of the present invention relate to semiconductor technology, and more particularly to memory cells, integrated circuit structures, and memory arrays. The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced generations of integrated circuits, each generation having smaller and more complex circuits than the previous one. In the history of integrated circuit development, the functional density (i.e., the number of interconnected devices per chip area) has increased while the geometric size (i.e., the smallest component or line produced in the manufacturing process) has decreased. This process of reducing the size of components provides the benefits of increased production efficiency and reduced associated costs. This reduction in component size also increases the complexity of processing and manufacturing integrated circuits. Semiconductor memory is an electronic data storage device implemented on a semiconductor-based integrated circuit and has a much faster access time than other types of data storage technologies. For example, static random-access memory (SRAM) devices are commonly used in integrated circuits. Static random-access memory devices are popular in high-speed communication, image processing, and system-on-chip (SOC) applications. A bit can be read from or written to a static random-access memory cell in a few nanoseconds, while the access time of rotational storage such as a hard disk is in the millisecond range. When entering the deep sub-micron era, static random-access memory devices have become increasingly popular due to the lithography-friendly layout shapes of their active regions, polysilicon lines, and metal layers. Among static random-access memory devices, multi-port static random-access memory devices have become popular. For example, two-port (2P) static random-access memory devices allow parallel operations, such as 1R (read) 1W (write) or 2R (read) in one cycle, and thus have a higher bandwidth than single-port static random-access memory devices. However, in the deep sub-micron era, due to insufficient area utilization, static random-access memory cells are generally large, especially multi-port static random-access memory cells (e.g., insufficient area utilization in device layers and metal interconnect structures). As the process node progresses, it is necessary to reduce the cell size of multi-port static random-access memory cells. In some embodiments, a memory cell is provided. The memory cell includes a device layer including a plurality of transistors, each of the plurality of transistors including a gate structure longitudinally extending in a first direction; and an interconnect structure disposed above the device layer, wherein: the interconnect structure includes a bottom-most metal line layer electrically coupled to the plurality of transistors in the device layer, the bottom-most metal line layer including first, second, third, fourth, fifth, and sixth metal tracks sequentially arranged in the first direction from a first one, the distance between any two adjacent ones of the first, second, third, fourth, fifth, and sixth metal tracks measured in the first direction being consistent, the first metal track including a metal line electrically coupled to the electrical ground of the memory cell, and the sixth metal track including a metal line electrically coupled to the power supply of the memory cell. In some embodiments, an integrated circuit structure is provided. The integrated circuit structure includes a device layer including a first gate structure of a first transfer gate transistor, a second gate structure shared by a first pull-down transistor and a first pull-up transistor, a third gate structure shared by a second pull-down transistor and a second pull-up transistor, and a fourth gate structure of a second transfer gate transistor, each of the first, second, third, and fourth gate structures longitudinally extending in a first direction; and a metal layer suspended above the device layer, the metal layer including first, second, third, fourth, fifth, and sixth metal tracks sequentially arranged in the first direction from a first one, each of the first, second, third, fourth, fifth, and sixth metal tracks longitudinally extending in a second direction perpendicular to the first direction, wherein the third metal track includes a metal line spanning the third gate structure, and one of the fourth or fifth metal tracks includes a metal line spanning the second gate structure. In some other embodiments, a memory array is provided. The memory array includes a first memory cell having a first transistor; a second memory cell having a second transistor, the second memory cell adjacent to the first memory cell, wherein the first transistor and the second transistor share a gate structure spanning a boundary line between the first memory cell and the second memory cell; a gate contact disposed on the gate structure; and a metal track suspended above the boundary line, wherein the metal track includes a first pad coupled to the power supply of the first memory cell and the second memory cell and a second pad physically contacting the gate contact. It is to be understood that the following disclosure provides many different embodiments or examples for implementing different components of the subject matter provided. Specific examples of each component and its arrangement are described below to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, the dimensions of the components are not limited to the scope or values of one embodiment of the present disclosure, but may depend on the processing conditions and / or required properties of the components. In addition, in the subsequent description, embodiments in which a first component is formed above or on a second component, including embodiments in which the first and second components are formed in direct contact, and embodiments in which additional components may be formed between the first and second components such that the first and second components do not directly contact. In addition, repeated reference symbols and / or words may be used in different examples in the disclosure. These repeated symbols or words are for the purpose of simplification and clarity and are not intended to limit the relationship between the various embodiments and / or the described external structures. Furthermore, the following disclosure describes embodiments in which a component is formed on, connected to, and / or coupled to another component may include embodiments in which these components are formed in direct contact, and may also include embodiments in which additional components may be formed between these components such that these components do not directly contact. In addition, for the convenience of describing the relationship between a component and another component of an embodiment of the present invention, spatial relative terms may be used, such as "lower", "upper", "horizontal", "vertical", "above", "over", "below", "beneath", "on", "under", "top", "bottom", etc. and the foregoing derivative terms (e.g., "horizontally", "downwardly", "upwardly", etc.). Spatial relative terms are used to cover different orientations of a device including components. Furthermore, when describing a number or a range of numbers with terms such as "about", "approximate" and similar terms, unless otherwise specified, the purpose of this term is to cover numbers within + / - 10% of the described number. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm. Embodiments of the present invention generally relate to static random access memory (SRAM) structures, and particularly to multi-port static random access memory cells. A static random access memory cell has a metal interconnect structure over transistors. The metal interconnect structure includes metal tracks (metal lines) for interconnecting transistor gates and source / drain regions, and power metal tracks for providing power to the cell components. A static random access memory cell may include a metal interconnect structure of multiple layers of metal tracks. For example, a first layer including a plurality of first metal tracks is formed over the cell transistors, and a second layer is disposed over the first layer, and the second layer includes a plurality of second metal tracks formed over the first metal tracks. Metal tracks in the same layer may be parallel to each other or perpendicular to other metal tracks in adjacent parallel planes. As the transistor density increases, there is a need to miniaturize the metal interconnect structure in order to provide sufficient power and signal paths for the increasing number of transistors in a given space. However, due to the process costs and limitations associated with high-volume production, electromigration rules, and other technical issues, the metal pitch of the metal interconnect structure does not scale down with the size of the underlying transistors. As a result, the metal interconnect structure will have a reduced number of metal tracks in a given cell height. Therefore, as the cell height is reduced to accommodate advanced nodes, the metal pitch of the metal pattern structure may not provide sufficient routing resources. Consequently, due to the limitations of the metal pattern structure, the minimum cell area (and die area) cannot be achieved. Embodiments of the present invention provide exemplary circuits in accordance with the layout design of a multi-port static random access memory cell without violating design rules to provide sufficient routing resources while accommodating a smaller cell height. In some embodiments, the layout design indicates that the metal layer zero M0 of the dual-port (2P) static random access memory cell has fewer than 7 metal tracks to fit the cell height. As the area utilization rate in the metal interconnect structure increases, a reduction in the cell size of the multi-port static random access memory cell is achieved. Some exemplary embodiments relate to, but are not limited to, multi-gate devices. Multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin-like field effect transistor (FinFET). The fin-like field effect transistor derives its name from the fin-like structure that extends from the substrate on which it is formed, and the substrate is used to form the field effect transistor channel. Another multi-gate device that has been introduced is the gate-all-around (GAA) transistor to partially address the performance challenges associated with the fin-like field effect transistor. The gate-all-around transistor derives its name from the gate structure that can extend around the channel region (e.g., a stack of nanosheets) to provide a path to the channel on four sides. The gate-all-around transistor is compatible with traditional complementary metal-oxide-semiconductor (CMOS) processes and is capable of aggressively miniaturizing the structure of the gate-all-around transistor while maintaining gate control and mitigating short-channel effects. The following description will continue with one or more gate-all-around examples to illustrate various embodiments of the present invention. However, it should be understood that unless otherwise specified, embodiments of the present invention are not limited to a particular type of device. For example, aspects of embodiments of the present invention can also be applied based on embodiments of fin-like field effect transistors or planar field effect transistors. Details of the device structure of embodiments of the present invention are described in the accompanying drawings. The accompanying drawings outline the features of several embodiments, enabling those of ordinary skill in the art to better understand the following detailed description. Those of ordinary skill in the art should understand that they can easily use the embodiments of the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those of ordinary skill in the art should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention, and these equivalent structures can be subjected to various changes, substitutions, and modifications without departing from the spirit and scope of the embodiments of the present invention. Figures 1A and 1B respectively show a perspective view and a top view of a part of an integrated circuit (IC) device 10 (such as a static random access memory device implemented using fully wrapped gate transistors) according to some embodiments of the present invention. Referring to Figure 1A, the integrated circuit device 10 includes a substrate 12. The substrate 12 may include an elemental (single element) semiconductor (such as silicon, germanium, and / or other suitable materials), a compound semiconductor (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials), an alloy semiconductor (such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials). The substrate 12 may be a single layer of material with a uniform composition. Alternatively, the substrate 12 may include multiple material layers with similar or different compositions suitable for the manufacture of integrated circuit devices. In one example, the substrate 12 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 12 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination of the foregoing. Various doped regions (such as source / drain (S / D) regions) may be formed in or on the substrate 12. Depending on design requirements, the doped regions may be doped with n-type dopants (such as phosphorus or arsenic) and / or p-type dopants (such as boron). The doped regions may be formed directly on the substrate 12, in a p-type well structure, in an n-type well structure, in a dual-well structure, or using a raised structure. The doped regions may be formed by implanting dopant atoms, in-situ doping epitaxial growth, and / or other suitable techniques. The three-dimensional active region 14 is formed on the substrate 12. The active region of a transistor represents the region that forms the source region, drain region, and the channel region under the gate structure of the transistor. In context, the active region is also referred to as the "oxide-definition (OD) region". Each active region 14 includes an elongated nanostructure 26 (as shown in FIG. 2), the nanostructure 26 being vertically stacked in the channel region, the channel region being defined in the active region and above the fin base. The fin base protrudes upward from the substrate 12. Source / drain components 16 are formed in the source / drain regions defined in the active region and above the fin base. The source / drain components 16 adjoin both sides of the nanostructure 26. The source / drain components 16 may include epitaxial layers epitaxially grown on the fin base. The integrated circuit device 10 further includes an isolation structure 18 (or isolation component) formed above the substrate 12. The isolation structure 18 electrically isolates various components of the integrated circuit device 10. The isolation structure 18 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low dielectric constant dielectric materials, and / or other suitable materials. In some embodiments, the isolation structure 18 may include a shallow trench isolation (STI) component. In one embodiment, the isolation structure 18 is formed by etching trenches in the substrate 12 during the formation of the active region 14. Then, the trenches can be filled with the above-mentioned isolation materials, followed by a chemical mechanical planarization (CMP) process. Other types of isolation structures may also be used as the isolation structure 18, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures. Alternatively, the isolation structure 18 may include a multi-layer structure, such as having one or more thermal oxide liner layers. The integrated circuit device 10 also includes a gate structure 20 (or gate stack) formed above and in contact with the active region 14. The gate structure 20 may be a dummy gate structure (e.g., including an oxide gate dielectric and a polysilicon gate electrode), or the gate structure 20 may be a high-k metal gate (HKMG) structure including a high dielectric constant gate dielectric and a metal gate electrode, where the high-k metal gate structure is formed by replacing the dummy gate structure. Although not shown herein, the gate structure 20 may include additional material layers, such as an interface layer, a capping layer, other suitable layers, or a combination of the foregoing. Referring to FIG. 1B, a plurality of active regions 14 are longitudinally oriented in the X direction, and a plurality of gate structures 20 are longitudinally oriented in the Y direction, that is, the gate structures 20 are generally perpendicular to the active regions 14. Transistors are formed at the intersections of the active regions 14 and the gate structures 20. In many embodiments, the integrated circuit device 10 includes additional components, such as gate spacer walls disposed along the sidewalls of the gate structures 20 and many other components. FIG. 2 is a partial schematic cross-sectional view along line A-A of FIG. 1A according to aspects of an embodiment of the present invention, showing the layers (levels) that can be fabricated above the substrate 12. In FIG. 2, the layers include a device layer DL and a metal interconnect structure (also collectively referred to as multilayer interconnect MLI) disposed above the device layer DL. The device layer DL includes devices (such as transistors, resistors, capacitors, and / or inductors) and / or device components (such as doped wells, gate structures, and / or source / drain components). In some embodiments, the device layer DL includes a substrate 12, doped regions 15 (such as n-type wells and / or p-type wells) disposed in the substrate 12, isolation structures 18, and transistors T. In the illustrated embodiment, the transistor T includes a suspended nanostructure 26 (channel layer) and a gate structure 20 disposed between the source / drain components 16, where the gate structure 20 surrounds and / or encircles the suspended nanostructure 26. The nanostructure 26 can include nanosheets, nanotubes, or nanowires that horizontally extend in the X direction or some other type of nanostructure. Each gate structure 20 has a metal gate structure formed by a gate electrode 22 disposed above the gate dielectric 24 and a gate spacer wall 25 disposed along the sidewalls of the metal gate structure. The various devices and / or components of the multi-layer interconnect (MLI) electrically couple the device layers (DLs), enabling the various devices and / or components to operate in the manner specified by the memory design requirements. In the illustrated embodiment, the multi-layer interconnect (MLI) includes a contact layer (CO), a via layer zero (V0), a metal layer zero (M0), a via layer one (V1), a metal layer one (M1), a via layer two (V2), a metal layer two (M2), a via layer three (V3), and a metal layer three (M3). Embodiments of the present invention contemplate multi-layer interconnects (MLIs) with more or fewer layers and / or levels, such as a multi-layer interconnect (MLI) having a total number of N metal layers (levels), where N is an integer in the range of 2 to 10. Each level of the multi-layer interconnect (MLI) includes conductive components (such as metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (such as an interlayer dielectric (ILD) layer and a contact etch stop layer (CESL)). In some embodiments, the conductive components of the same level of the multi-layer interconnect (MLI) are formed simultaneously (such as the metal layer zero (M0)). In some embodiments, the conductive components at the same level of the multi-layer interconnect (MLI) have top surfaces that are substantially coplanar with each other and / or bottom surfaces that are substantially coplanar with each other. The contact layer (CO) includes source / drain contacts (MD) disposed in the dielectric layer 28; the via layer zero (V0) includes gate vias (VG), source / drain contact vias (VD), and butt contacts disposed in the dielectric layer 28; the metal layer zero (M0) includes a metal line (m0) disposed in the dielectric layer 28, where the gate via (VG) connects the gate structure to the metal line (m0), the source / drain contact via (VD) connects the source / drain to the metal line (m0), and the butt contact connects the gate structure and the source / drain together and to the metal line (m0); the via layer one (V1) includes a via (v1) disposed in the dielectric layer 28, where the via (v1) connects the metal line (m0) to the metal line (m1); the metal layer one (M1) includes a metal line (m1) disposed in the dielectric layer 28; the via layer two (V2) includes a via (v2) disposed in the dielectric layer 28, where the via (v2) connects the metal line (m1) to the metal line (m2); the metal layer two (M2) includes a metal line (m2) disposed in the dielectric layer 28; the via layer three (V3) includes a via (v3) disposed in the dielectric layer 28, where the via (v3) connects the metal line (m2) to the metal line (m3). For clarity, FIG. 2 has been simplified to better understand the inventive concept of embodiments of the present invention. Additional components may be added to the various layers of the memory, and for other embodiments of the memory, some of the described components may be replaced, modified, or eliminated. FIG. 2 is only an example and may not reflect the actual cross-sectional schematic of the integrated circuit device 10 and / or the static random access memory cell 100, which will be discussed in more detail below. Please refer to FIG. 3, which shows an exemplary circuit schematic of a dual-port static random access memory cell 100. The dual-port static random access memory cell 100 includes a write port 100W and a read port 100R. The write port 100W includes pull-up transistors PU-1 and PU-2, pull-down transistors PD-1 and PD-2, and transmission gate transistors PG-1 and PG-2. In the illustrated embodiment, the pull-up transistors PU-1 and PU-2 are p-type transistors, and the transmission gate transistors PG-1 and PG-2, and the pull-down transistors PD-1 and PD-2 are n-type transistors. The drains of the pull-up transistor PU-1 and the pull-down transistor PD-1 are coupled together, and the drains of the pull-up transistor PU-2 and the pull-down transistor PD-2 are coupled together. The pull-up transistor PU-1 and the pull-down transistor PD-1 are cross-coupled with the pull-up transistor PU-2 and the pull-down transistor PD-2 to form a data latch. The gates of the pull-up transistor PU-1 and the pull-down transistor PD-1 are coupled together and coupled to the common drain of the pull-up transistor PU-2 and the pull-down transistor PD-2 to form a storage node SN, and the gates of the pull-up transistor PU-2 and the pull-down transistor PD21 are coupled together and coupled to the common drain of the pull-up transistor PU-1 and the pull-down transistor PD-1 to form a complementary storage node SNB. The sources of the pull-up transistors PU-1 and PU-2 are coupled to a power supply voltage node V DD (also referred to as V CC ), and the sources of the pull-down transistors PD-1 and PD-2 are coupled to a ground voltage node V SS , and the ground voltage node V SS may be electrically grounded in some embodiments. The storage node SN of the data latch is coupled to the bit line W_BL of the write port 100W through the transmission gate transistor PG-2, and the complementary storage node SNB is coupled to the complementary bit line W_BLB of the write port 100W through the transmission gate transistor PG-1. The storage node SN and the complementary storage node SNB are complementary nodes, and the complementary nodes are typically at opposite logic levels (logic high or logic low). The gates of the transmission gate transistors PG-1 and PG-2 are coupled to the word line W_WL of the write port 100W. The read port 100R of the static random access memory cell 100 includes a read-port pass-gate transistor (R-PG) coupled between the word line R_BL and the storage node SN (or coupled to the gates of the pull-up transistor PU-1 and the pull-down transistor PD-1). The gate of the read-port pass-gate transistor R-PG is coupled to the word line R_WL of the read port 100R. In the illustrated embodiment, the read-port pass-gate transistor R-PG is a p-type transistor. That is, in the dual-port static random access memory cell 100, the pass-gate transistors in the write port are n-type transistors, while the pass-gate transistors in the read port are p-type transistors. FIG. 4 shows a simplified schematic layout 100A of the device layer DL of the dual-port static random access memory cell 100. The dual-port static random access memory cell 100 includes a write port 100W and a read port 100R. The write port 100W includes pass-gate transistors PG-1 and PG-2, pull-up transistors PU-1 and PU-2, and pull-down transistors PD-1 and PD-2. The read port 100R includes a read-port pass-gate transistor R-PG. For visual clarity and simplicity, the layout 100A includes the active regions and gate structures of these transistors in the static random access memory cell 100 and some gate cut components, but does not include many other components (such as contacts, vias, and metal lines) in or above the device layer DL in the layout 100A. As shown in FIG. 4, the dual-port static random access memory cell 100 includes active regions 102 and 104. The active regions 102 and 104 each extend longitudinally in the X direction in FIG. 4. In the illustrated embodiment, the active regions 102 and 104 may each include (or may be implemented as) the nanostructure 26 of FIG. 2 above. In other embodiments, the active regions 102 and 104 may also include fin structures. The active region 102 is a component of the write port 100W, and the active region 104 has a side portion that is a component of the read port 100R and the remaining portion that is a component of the write port 100W. In other words, the active region 104 is shared by the read port 100R and the write port 100W. In the illustrated embodiment, the active region 104 belongs to the pull-up transistors PU-1 and PU-2, and the read-port transfer gate transistor R-PG. The pull-up transistors PU-1 and PU-2, and the read-port transfer gate transistor R-PG are p-type metal oxide semiconductor devices. Thus, the active region 104 is formed above the n-type well 106. At the same time, the active region 102 belongs to the transfer gate transistor PG-1, the pull-down transistors PD-1 and PD-2, and the transfer gate transistor PG-2. The transfer gate transistor PG-1, the pull-down transistors PD-1 and PD-2, and the transfer gate transistor PG-2 are n-type metal oxide semiconductor devices. Thus, the active region 102 is formed above the p-type well 108 (or p-type substrate). As shown in FIG. 4, the dual-port static random access memory cell 100 further includes gate structures 112, 114, 116, 118, and 120. The gate structures 112, 114, 116, 118, and 120 each extend longitudinally in the Y direction in FIG. 4. The gate structures 112, 114, 116, 118, and 120 may each include (or may be implemented as) the gate structure 20 of FIG. 2 above. The gate structures 112, 114, 116, and 120 are components of the write port 100W. The gate structure 118 is a component of the read port 100R. The gate structures 114 and 116 each extend through the two active regions 102 and 104. Thus, the gate structure 114 is shared by the pull-down transistor PD-1 and the pull-up transistor PU-1, and the gate structure 116 is shared by the pull-down transistor PD-2 and the pull-up transistor PU-2. Referring to FIG. 4, the dual-port static random access memory cell 100 further includes a plurality of gate cut dielectric components longitudinally extending in the X direction. The gate cut dielectric components include a first dielectric component (cut metal gate component 130) longitudinally extending in the X direction and a second dielectric component (continuous polysilicon cross-diffusion layer boundary component 132) longitudinally extending in the Y direction. In the illustrated embodiment, the first dielectric component (cut metal gate component 130) is disposed between the active region 102 and the active region 104 and is adjacent to the gate structures 118 and 120. The first dielectric component (cut metal gate component 130) divides the originally continuous gate structure into two isolated segments corresponding to the gate structure 118 and the gate structure 120. The first dielectric component (cut metal gate component 130) is formed by filling a corresponding cut-metal-gate (CMG) trench in the position of the dielectric component. The first dielectric component is also referred to as a cut metal gate component. In the illustrated embodiment, the cut metal gate component 130 is disposed above the interface between the n-type well 106 and the p-type well 108. The cut metal gate process represents the manufacturing process after a metal gate (such as a high-k metal gate (HKMG)) replaces a dummy gate structure (such as a polysilicon gate), and the metal gate is cut (such as through an etching process) to separate the metal gate into two or more gate segments. Each gate segment serves as the metal gate of an individual transistor. Thereafter, an isolation material fills the trenches between adjacent portions of the metal gate. In an embodiment of the present invention, these trenches are referred to as cut metal gate (CMG) trenches. The dielectric material filling the cut metal gate trenches for isolation is referred to as a cut metal gate component. To ensure complete cutting of the metal gate, the cut metal gate component often further extends into adjacent regions, such as the space between the dielectric layer filling the metal gates. In a top view, the cut metal gate component often has an elongated shape. The second dielectric component (continuous-poly-on-diffusion-edge component 132) is formed in a continuous-poly-on-diffusion-edge (CPODE) process and is thus also referred to as a continuous-poly-on-diffusion-edge component. For the purposes of embodiments of the present invention, a "diffusion edge" may equivalently be referred to as an active edge, where, for example, an active edge adjacent to an adjacent active region is an example. Prior to the continuous-poly-on-diffusion-edge process, the active edge may include a dummy all-around gate structure having a dummy gate structure (such as a polysilicon gate) and a plurality of vertically stacked nanostructures as a channel layer. In addition, internal spacer walls may be disposed between adjacent nanostructures at the lateral ends of the nanostructures. In various examples, source / drain epitaxial components are disposed on either side of the dummy all-around gate structure such that adjacent source / drain epitaxial components contact the internal spacer walls and the nanostructures of the dummy all-around gate structure. A subsequent continuous-poly-on-diffusion-edge etching process removes the dummy gate structure and the channel layer from the dummy all-around gate structure to form a continuous-poly-on-diffusion-edge trench. The dielectric material that fills the continuous-poly-on-diffusion-edge trench for isolation is referred to as a continuous-poly-on-diffusion-edge component. In some embodiments, after forming the continuous-poly-on-diffusion-edge component, the remaining dummy gate structure is replaced by a metal gate structure in a replacement gate (post-gate) process. In other words, in some embodiments, the continuous-poly-on-diffusion-edge component replaces the originally continuous gate structure and is limited between the gate spacer walls on both sides of the replaced portion of the gate structure. In contrast, a cut metal gate component is formed after forming the metal gate structure line, and the cut metal gate component truncates the originally continuous gate structure line and extends into adjacent regions of the gate structure, while the continuous-poly-on-diffusion-edge component is formed after forming the polysilicon gate structure line and before forming the metal gate structure, and the continuous-poly-on-diffusion-edge component extends and aligns with the metal gate structure. In FIG. 4, the continuous-poly-on-diffusion-edge component 132 abuts the gate structure 112 and aligns with the gate structure 112. The continuous-poly-on-diffusion-edge component 132 extends in the Y direction and spans the n-type well 106 to another p-type well 108 of an adjacent static random access memory cell. That is, two adjacent static random access memory cells may share the continuous-poly-on-diffusion-edge component 132. Furthermore, in some embodiments, the continuous-poly-on-diffusion-edge component 132 may extend deeper into the underlying substrate than the cut metal gate component 130. Please refer to FIG. 4. FIG. 4 uses dashed lines to show the boundary 140 of the dual-port static random access memory cell 100. It should be noted that some active regions and gate structures may extend beyond the boundary 140 because these active regions and gate structures may also form components of other adjacent static random access memory cells. The boundary 140 is longer in the X direction than in the Y direction. In other words, the boundary 140 may be rectangular. The first dimension of the boundary 140 in the X direction is labeled as the cell width W, and the second dimension of the boundary 140 in the Y direction is labeled as the cell height H. Repeating the dual-port static random access memory cell 100 in the form of a memory array, the cell width W can represent and can be referred to as the memory cell pitch in the memory array in the X direction, and the cell height H can represent and can be referred to as the memory cell pitch in the memory array in the Y direction. The cell size of the dual-port static random access memory cell 100 is W x H, where the cell width W is about 4 times the polysilicon pitch (e.g., the center-to-center distance between two adjacent gate structures in the X direction), and the cell height H is about 2 times the isolation pitch (e.g., the center-to-center distance between two adjacent shallow trench isolation components in the Y direction). The area obtained by multiplying one polysilicon pitch by one isolation pitch is denoted as the unit area. Each cell area contains the intersection of the gate structure and the active region, and the dual-port static random access memory cell 100 uses a cell size of about 8 times the unit area to accommodate seven transistors, namely the transmission gate transistors PG-1 and PG-2, the pull-up transistors PU-1 and PU-2, the pull-down transistors PD-1 and PD-2, and the read port transmission gate transistor R-PG. The area utilization rate of the device layer of the dual-port static random access memory cell 100 is considered to be efficient because only one unit area is not used to form functional transistors, but hosts the intersection of the continuous polysilicon cross-diffusion layer boundary component and the active region. FIG. 5 shows a simplified schematic layout 200A of a static random access memory array 200 according to an embodiment of the present invention. For visual clarity and simplicity, the layout 200A includes the active regions, gate structures, well regions, and continuous polysilicon cross-diffusion layer boundary components of these transistors in the static random access memory cells, but does not include many other components (such as cut metal gate components, contacts, vias, and metal lines) in the layout 200A. Please refer to FIG. 5. A plurality of dual-port static random access memory units 100 are arranged in the X direction and the Y direction to form a 2 x 2 array of static random access memory units. Each static random access memory unit in the array can use the layout 100A of the static random access memory unit 100 shown in FIG. 4. In some embodiments, two adjacent static random access memory units in the X direction are symmetric with respect to the common boundary line therebetween, and two adjacent static random access memory units in the Y direction are symmetric with respect to the common boundary line therebetween. That is to say, the first static random access memory unit 100 is a replicated unit of the second static random access memory unit 100, but flipped on the Y axis; the third static random access memory unit 100 is a replicated unit of the first static random access memory unit 100, but flipped on the X axis; the fourth static random access memory unit 100 is a replicated unit of the second static random access memory unit 100, but flipped on the X axis. The static random access memory array 200 includes n-type wells 106 and p-type wells 108 that are alternately arranged along the Y axis. In other words, each p-type well 108 is adjacent to an n-type well 106, the n-type well 106 is adjacent to another p-type well 108, and this pattern is repeated. In the embodiment shown in FIG. 5, the gate structures in each dual-port static random access memory unit do not extend beyond the corresponding unit boundary, and each continuous polysilicon cross-diffusion layer boundary component is shared by two adjacent static random access memory units arranged in the Y direction. The distance in the X direction between adjacent continuous polysilicon cross-diffusion layer boundary components (also labeled as the continuous polysilicon cross-diffusion layer boundary to continuous polysilicon cross-diffusion layer boundary pitch) is 7 times the poly pitch. FIG. 6 shows a simplified schematic layout 200B of the static random access memory array 200 according to an embodiment of the present invention. In the alternative layout 200B, some gate structures can be shared by adjacent static random access memory units, such that these gate structures longitudinally extend across the boundary between adjacent static random access memory units. Please refer to FIG. 6. Two read port transfer gate transistors R-PG in two adjacent static random access memory units 100 in the same row (arranged along the Y direction) can share the same gate structure, such that the shared gate structure can longitudinally extend across the boundary between two adjacent static random access memory units 100. FIG. 7A is a partial schematic cross-sectional view along line A-A of FIG. 5 (or FIG. 6) in accordance with aspects of the present invention, where line A-A cuts through the active region 104 in the longitudinal direction. FIG. 7B is a partial schematic cross-sectional view along line B-B of FIG. 5 (or FIG. 6) in accordance with aspects of the present invention, where line B-B cuts through the source / drain regions along the midline of the static random access memory cell 100. Referring jointly to FIGS. 7A and 7B, the active region 104 extends in the X direction through two static random access memory cells 100, but two consecutive polycrystalline cross-diffusion layer boundary components CPODE sandwich the active region 104 therebetween. The consecutive polycrystalline cross-diffusion layer boundary components CPODE replace the original metal gate structure closest to the cell edge. The distance between consecutive polycrystalline cross-diffusion layer boundary components CPODE (distance between consecutive polycrystalline cross-diffusion layer boundaries) is 7 times the poly pitch. Between the consecutive polycrystalline cross-diffusion layer boundary components CPODE, the active region 104 includes a channel region, which is composed of the nanostructure 26 and the source / drain component 16 adjacent to the end of the nanostructure 26. The gate structure surrounds the nanostructure 26 and forms the pull-up transistors PU-1 and PU-2 and the read port transfer gate transistor R-PG in the static random access memory cell 100. The active region 204 is disposed above the n-type well 106, and the active region 102 is disposed above the p-type well 108. The source / drain component 16 formed on the active region 104 is a p-type epitaxial component, and the source / drain component 16 formed on the active region 102 is an n-type epitaxial component. The source / drain contact MD is electrically connected to the source / drain components 16 formed on the active regions 102 and 104. FIGS. 8, 9, 10, and 11 show simplified schematic layouts 100B of the metal interconnect structure of the dual-port static random access memory cell 100 at different layers. In particular, FIG. 8 shows the conductive components in the contact layer CO and via layer zero V0, FIG. 9 shows via layer zero V0 and metal layer zero M0, FIG. 10 shows via layer one V1 and metal layer one M1, and FIG. 11 shows via layer two V2 and metal layer two M2. FIG. 8 shows the conductive components in the contact layer CO and via layer zero V0. Furthermore, for visual clarity, some components used for the device layer DL in the layout 100A are reproduced in FIG. 8, such as the active regions 102, 104, gate structures 112, 114, 116, 118, 120, consecutive polycrystalline cross-diffusion layer boundary components 132, and the boundary 140, while FIG. 8 omits many other components. The gate contact 150A electrically connects the gate (formed by the gate structure 118) of the read port transfer gate transistor R-PG to the read port word line R_WL. The gate contact 150C electrically connects the gate (formed by the gate structure 112) of the transfer gate transistor PG-1 to the write port word line W_WL. The gate contact 150D electrically connects the gate (formed by the gate structure 120) of the transfer gate transistor PG-2 to the write port word line W_WL. The gate contact 150E electrically connects the gate (formed by the gate structure 114) of the write port pull-down transistor PD-1 and the gate (also formed by the gate structure 114) of the write port pull-up transistor PU-1 to the storage node SN. The gate contact 150F electrically connects the gate (formed by the gate structure 116) of the write port pull-down transistor PD-2 and the gate (also formed by the gate structure 116) of the write port pull-up transistor PU-2 to the complementary storage node SNB. The source / drain contact 160A and the source / drain contact via 170A located on the source / drain contact 160A electrically connect the source region of the read port transfer gate transistor R-PG to the read port bit line R_BL. The source / drain contact 160B is located on the source / drain region adjacent to the continuous polysilicon spacer 132 and remains electrically floating, and no corresponding source / drain contact via is located thereon. The source / drain contact 160C and the source / drain contact via 170C located on the source / drain contact 160C electrically connect the source region of the write port transfer gate transistor PG-1 to the write port complementary bit line W_BLB. The source / drain contact 160D and the source / drain contact via 170D located on the source / drain contact 160D electrically connect the source region of the write port transfer gate transistor PG-2 to the write port bit line W_BL. The source / drain contact 160E and the source / drain contact via 170E located on the source / drain contact 160E electrically connect the common drain region of the write port transfer gate transistor PG-1 and the write port pull-down transistor PD-1 and the drain region of the write port pull-up transistor PU-1 to the complementary storage node SNB. The source / drain contact 160F and the source / drain contact via 170F located on the source / drain contact 160F electrically connect the common drain region of the write port transfer gate transistor PG-2 and the write port pull-down transistor PD-2 and the common drain region of the write port pull-up transistor PU-2 and the read port transfer gate transistor R-PG to the storage node SN. The source / drain contact 160G and the source / drain contact via 170G located on the source / drain contact 160G electrically connect the common source region of the write port pull-down transistor PD-1 and the write port pull-down transistor PD-2 to the ground voltage node V SSThe source / drain contact 160H and the source / drain contact vias 170H located on the source / drain contact 160H electrically connect the common source regions of the write port pull-up transistors PU-1 and PU-2 to the power supply voltage node V. DD In the illustrated embodiment, the source / drain contacts 160A, 160B, 160C, 160D, 160E, 160F, 160G, 160H are each elongated and have a longitudinal direction in the Y direction, which is parallel to the extending direction of the gate structure. As shown in FIG. 8, the storage node SN includes a gate contact 150E and source / drain contact vias 170F located on both sides of the gate structure 116. As discussed in more detail below, the metal lines in the metal layer zero M0 extend in the X direction to span the gate structure 116 and connect the gate contact 150E and the source / drain contact vias 170F. In other words, the metal line m0 is suspended above the gate structure 116 and provides a cross-coupling between the gate contact 150E and the source / drain contact vias 170F. Therefore, in the layout 100B, the gate contact 150E and the source / drain contact vias 170F are horizontal in the Y direction, enabling the metal line extending in the X direction to connect the two. Similarly, the complementary storage node SNB (storage node bar) includes a gate contact 150F and source / drain contact vias 170E located on both sides of the gate structure 114. As discussed in more detail below, the metal lines in the metal layer zero M0 extend in the X direction to span the gate structure 114 and connect the gate contact 150F and the source / drain contact vias 170E. In other words, the metal line m0 is suspended above the gate structure 114 and provides a cross-coupling between the gate contact 150F and the source / drain contact vias 170E. Therefore, in the layout 100B, the gate contact 150F and the source / drain contact vias 170E are horizontal in the Y direction, enabling the metal line extending in the X direction to connect the two. FIG. 9 shows the via layer zero V0 and the metal layer zero M0 of the layout 100B of the metal interconnection structure of the dual-port static random access memory cell 100. In the metal layer zero M0, the static random access memory cell 100 includes a plurality of metal tracks arranged in parallel. Specifically, in the illustrated embodiment of the layout 100B, the static random access memory cell 100 includes seven metal tracks arranged in sequence along the Y direction from the first metal track M0 Track 1 to the seventh metal track M0 Track 7. The center lines of the metal tracks are shown as dashed lines in FIG. 9. The distance between the center lines of adjacent metal tracks is labeled as the metal track pitch. A metal track may include a single metal wire extending in the X direction through the entire static random access memory cell 100. This metal wire is labeled as a global metal wire. Alternatively, a metal track may include one or more metal wires that do not extend through the entire static random access memory cell 100. This metal wire is labeled as a local metal wire, or is referred to as an island, pad, or landing pad. In layout 100B, the first metal track M0 Track 1 includes the global metal wire 180A, and the global metal wire 180A is a voltage line (Vss line) electrically coupled to the source / drain contact via hole 170G. The global metal wire 180A is disposed on the upper edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The second metal track M0 Track 2 includes the local metal wire 180B as a pad for the write port word line W_WL. The local metal wire 180B is entirely within the static random access memory cell 100 and is electrically connected to the gate contacts 150C and 150D. The third metal track M0 Track 3 includes three local metal wires 180C, 180D, and 180E. The local metal wire 180C provides a pad for the write port complementary bit line W_BLB. The local metal wire 180C extends beyond the left edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The local metal wire 180D is entirely within the static random access memory cell 100. The local metal wire 180D belongs to the storage node SN and provides a cross-coupling between the gate contact 150E and the source / drain contact via hole 170F. As described above, the local metal wire 180D straddles the gate structure 116. The local metal wire 180E provides a pad for the write port bit line W_BL. The local metal wire 180E extends beyond the right edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The fourth metal track M0 Track 4 includes the local metal wire 180F, and the local metal wire 180F belongs to the complementary storage node SNB. The local metal wire 180F is entirely within the static random access memory cell 100 and provides a cross-coupling between the gate contact 150F and the source / drain contact via hole 170E. As described above, the local metal wire 180F straddles the gate structure 114. The fifth metal track M0 Track 5 includes the global metal wire 180G, and the global metal wire 180G is a read port bit line electrically coupled to the source / drain contact via hole 170A. The sixth metal track M0 Track 6 includes the local metal wire 180H. The local metal wire 180H is entirely within the static random access memory cell 100 and provides a pad for the read port word line R_WL. The seventh metal track M0 Track 7 includes the global metal wire 180I, and the global metal wire 180I is a voltage line (V DD The global metal line 180I is disposed on the lower edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The global metal line 180A has a width w1, half of the width w1 is in one static random access memory cell, and the other half of the width w1 is in an adjacent static random access memory cell. The width of the global metal line 180I can be substantially the same as the width of the global metal line 180A. Half of the width of the global metal line 180I is in one static random access memory cell, and the other half of the width of the global metal line 180I is in an adjacent static random access memory cell. The other metal lines (local metal lines 180B, 180C, 180D, 180E, 180F, 180H and global metal line 180G) can each have the same width w2. The spacing between two adjacent metal lines can be consistent and is labeled as spacing s1. Therefore, the cell height H of the static random access memory is equal to w1 + 5*w2 + 6*s1. FIG. 10 shows the via first layer V1 and the metal first layer M1 of the layout 100B of the metal interconnection structure of the dual-port static random access memory cell 100. Furthermore, for visual clarity, the global metal lines 180A, 180G, 180I and local metal lines 180B, 180C, 180D, 180E, 180F, 180H shown in FIG. 9 are replicated in FIG. 10. In the metal first layer M1, the static random access memory cell 100 includes a plurality of metal tracks arranged in parallel. Specifically, in the illustrated embodiment of the layout 100B, the static random access memory cell 100 includes five metal tracks arranged in sequence from the first metal track M1 Track 1 to the fifth metal track M1 Track 5 in the X direction. The center lines of the metal tracks are shown as dashed lines in FIG. 10. In the layout 100B, the first metal track M1 Track 1 includes a local metal line 192A. The local metal line 192A provides a pad for the write port complementary bit line W_BLB and is electrically coupled to the underlying local metal line 180C through a via 190A. The second metal track M1 Track 2 includes a global metal line 192B. The global metal line 192B is the write port word line W_WL and is electrically coupled to the underlying local metal line 180B (the pad for the write port word line W_WL) through a via 190B. The third metal track M1 Track 3 includes a local metal line 192C. The local metal line 192C provides a pad for the voltage line (V SS line) and is electrically coupled to the underlying global metal line 180A (V SS The fourth metal track M1 Track 4 includes a global metal line 192D, where the global metal line 192D is the read port character line R_WL and is electrically coupled to the underlying local metal line 180H (the pad for the read port character line R_WL) through a via 190D. The fifth metal track M1 Track 5 includes a local metal line 192E, where the local metal line 192E provides a pad for the write port bit line W_BL and is electrically coupled to the underlying local metal line 180E (the pad for the write port bit line W_BL) through a via 190E. FIG. 11 shows the via second layer V2 and the metal second layer M2 of the layout 100B of the metal interconnect structure of the dual-port static random access memory cell 100. Furthermore, for visual clarity, the global metal lines 192B, 192D and the local metal lines 192A, 192C, 192E shown in FIG. 10 are replicated in FIG. 11. In the metal second layer M2, the static random access memory cell 100 includes a plurality of metal tracks arranged in parallel. Specifically, in the illustrated embodiment of the layout 100B, the static random access memory cell 100 includes three metal tracks arranged in sequence from the first metal track M2 Track 1 to the third metal track M2 Track 3 along the Y direction. The center lines of the metal tracks are shown as dashed lines in FIG. 11. In the layout 100B, the first metal track M2 Track 1 includes a local metal line 196A, and the local metal line 196A provides a pad for the voltage line (V SS line) and is electrically coupled to the underlying local metal line 192C (the pad for the voltage line (V SS line)) through a via 194A. The second metal track M2 Track 2 includes a global metal line 196B, where the global metal line 196B is the write port complementary bit line W_BLB and is electrically coupled to the underlying local metal line 192A (the pad for the write port complementary bit line W_BLB) through a via 194B. The third metal track M2 Track 3 includes a global metal line 196C, where the global metal line 196C is the write port bit line W_BL and is electrically coupled to the underlying local metal line 192E through a via 194C. In the illustrated embodiment, the global metal lines 196B and 196C have a greater width than the local metal line 196A. As an alternative embodiment of the metal interconnect structure, FIGS. 12, 13, 14, and 15 show a simplified schematic layout 100C of the metal interconnect structure of the dual-port static random access memory cell 100 at different layers. Specifically, FIG. 12 shows the conductive components in the contact layer CO and via layer V0, FIG. 13 shows via layer V0 and metal layer M0, FIG. 14 shows via layer V1 and metal layer M1, and FIG. 15 shows via layer V2 and metal layer M2. FIG. 12 shows the conductive components in the contact layer CO and via layer V0. Furthermore, for visual clarity, some components used for the device layer DL in the layout 100A are reproduced in FIG. 12, such as the active regions 102, 104, gate structures 112, 114, 116, 118, 120, the continuous polysilicon cross-diffusion layer boundary component 132, and the boundary 140, while many other components are omitted in FIG. 12. The gate contact 150A electrically connects the gate (formed by the gate structure 118) of the read port transfer gate transistor R-PG to the read port word line R_WL. The gate contact 150C electrically connects the gate (formed by the gate structure 112) of the transfer gate transistor PG-1 to the write port word line W_WL. The gate contact 150D electrically connects the gate (formed by the gate structure 120) of the transfer gate transistor PG-2 to the write port word line W_WL. The gate contact 150E electrically connects the gates of the write port pull-down transistor PD-1 (formed by the gate structure 114) and the write port pull-up transistor PU-1 (also formed by the gate structure 114) to the storage node SN. The gate contact 150F electrically connects the gates of the write port pull-down transistor PD-2 (formed by the gate structure 116) and the write port pull-up transistor PU-2 (also formed by the gate structure 116) to the complementary storage node SNB. The source / drain contact 160A and the source / drain contact via 170A located on the source / drain contact 160A electrically connect the source region of the read port transfer gate transistor R-PG to the read port bit line R_BL. The source / drain contact 160B is located on the source / drain region adjacent to the continuous polysilicon crosspiece boundary component 132 and remains electrically floating, and no corresponding source / drain contact via is located thereon. The source / drain contact 160C and the source / drain contact via 170C located on the source / drain contact 160C electrically connect the source region of the write port transfer gate transistor PG-1 to the write port complementary bit line W_BLB. The source / drain contact 160D and the source / drain contact via 170D located on the source / drain contact 160D electrically connect the source region of the write port transfer gate transistor PG-2 to the write port bit line W_BL. The source / drain contact 160E and the source / drain contact via 170E located on the source / drain contact 160E electrically connect the common drain region of the write port transfer gate transistor PG-1 and the write port pull-down transistor PD-1 and the drain region of the write port pull-up transistor PU-1 to the complementary storage node SNB. The source / drain contact 160F and the source / drain contact via 170F located on the source / drain contact 160F electrically connect the common drain region of the write port transfer gate transistor PG-2 and the write port pull-down transistor PD-2 and the common drain region of the write port pull-up transistor PU-2 and the read port transfer gate transistor R-PG to the storage node SN. The source / drain contact 160G and the source / drain contact via 170G located on the source / drain contact 160G electrically connect the common source region of the write port pull-down transistor PD-1 and the write port pull-down transistor PD-2 to the ground voltage node V SS . The source / drain contact 160H and the source / drain contact via 170H located on the source / drain contact 160H electrically connect the common source region of the write port pull-up transistor PU-1 and the write port pull-up transistor PU-2 to the power supply voltage node V DD . In the illustrated embodiment, each of the source / drain contacts 160A, 160B, 160C, 160D, 160E, 160F, 160G, 160H is elongated and has a longitudinal direction in the Y direction, and this longitudinal direction is parallel to the extension direction of the gate structure. As shown in FIG. 12, the storage node SN includes a gate contact 150E and source / drain contact vias 170F located on both sides of the gate structure 116. As discussed in more detail below, the metal lines in the metal layer M0 extend in the X direction to span the gate structure 116 and connect the gate contact 150E and the source / drain contact vias 170F. In other words, the metal line m0 is suspended above the gate structure 116 and provides a cross-coupling between the gate contact 150E and the source / drain contact vias 170F. Therefore, in the layout 100C, the gate contact 150E and the source / drain contact vias 170F are horizontal in the Y direction, allowing the metal line extending in the X direction to connect the two. Similarly, the complementary storage node SNB (storage node bar) includes a gate contact 150F and source / drain contact vias 170E located on both sides of the gate structure 114. As discussed in more detail below, the metal lines in the metal layer M0 extend in the X direction to span the gate structure 114 and connect the gate contact 150F and the source / drain contact vias 170E. In other words, the metal line m0 is suspended above the gate structure 114 and provides a cross-coupling between the gate contact 150F and the source / drain contact vias 170E. Therefore, in the layout 100C, the gate contact 150F and the source / drain contact vias 170E are horizontal in the Y direction, allowing the metal line extending in the X direction to connect the two. The difference between the layout 100B shown in FIG. 8 and the layout 100C shown in FIG. 12 is that: in the layout 100B, the gate contact 150A coupled to the read port word line R_WL is disposed on the active region 104, and the gate contact 150F and the source / drain contact vias 170E belonging to the complementary storage node SNB are disposed between the active region 102 and the active region 104; while in the layout 100C, the gate contact 150A coupled to the read port word line R_WL is disposed between the active region 102 and the active region 104, and the gate contact 150F and the source / drain contact vias 170E belonging to the complementary storage node SNB are disposed on the active region 104. In other words, in the layout 100B, along the Y direction, the conductive components belonging to the complementary storage node SNB are disposed between the conductive components belonging to the storage node SN and the conductive components coupled to the read port word line R_WL; while in the layout 100C, along the Y direction, the conductive components coupled to the read port word line R_WL are disposed between the conductive components belonging to the storage node SN and the conductive components belonging to the complementary storage node SNB. FIG. 13 shows the via layer V0 and the metal layer M0 of the layout 100C of the metal interconnect structure of the dual-port static random access memory cell 100. In the metal layer M0, the static random access memory cell 100 includes a plurality of metal tracks arranged in parallel. Specifically, in the illustrated embodiment of the layout 100C, the static random access memory cell 100 includes six metal tracks arranged in sequence from the first metal track M0 Track 1 to the sixth metal track M0 Track 6 along the Y direction. The center lines of the metal tracks are shown as dashed lines in FIG. 13. In layout 100C, the first metal track M0 Track 1 includes a global metal line 280A, and the global metal line 280A is a voltage line (Vss line) electrically coupled to the source / drain contact via 170G. The global metal line 280A is disposed on the upper edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The second metal track M0 Track 2 includes a local metal line 280B as a pad for the write port word line W_WL. The local metal line 280B is entirely within the static random access memory cell 100 and is electrically connected to the gate contacts 150C and 150D. The third metal track M0 Track 3 includes three local metal lines 280C, 280D, and 280E. The local metal line 280C provides a pad for the write port complementary bit line W_BLB. The local metal line 280C extends beyond the left edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The local metal line 280D is entirely within the static random access memory cell 100, the local metal line 280D belongs to the storage node SN, and provides a cross-coupling between the gate contact 150E and the source / drain contact via 170F. As described above, the local metal line 280D straddles the gate structure 116. The local metal line 280E provides a pad for the write port bit line W_BL. The local metal line 280E extends beyond the right edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The fourth metal track M0 Track 4 includes two local metal lines 280F and 280G. The local metal line 280F is entirely within the static random access memory cell 100 and is electrically floating. Therefore, the local metal line 280F is a non-functional metal line mainly used to improve the metal density uniformity in the layout. The local metal line 280G is entirely within the static random access memory cell 100 and provides a pad for the read port word line R_WL. The fifth metal track M0 Track 5 includes three local metal lines 280H, 280I, and 280J. The local metal line 280H extends beyond the left edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The local metal line 280H is electrically floating. Therefore, the local metal line 280H is a non-functional metal line mainly used to improve the metal density uniformity in the layout. The local metal line 280I is entirely within the static random access memory cell 100, the local metal line 280I belongs to the complementary storage node SNB, and provides a cross-coupling between the gate contact 150F and the source / drain contact via 170E. As described above, the local metal line 280I straddles the gate structure 116.The local metal line 280J extends beyond the right edge of the static random access memory cell 100 and can be shared with an adjacent static random access memory cell. The local metal line 280J provides a pad for the read port bit line R_BL. The sixth metal track M0 Track 6 includes a global metal line 280K, and the global metal line 280K is a voltage line (V ) electrically coupled to the source / drain contact via hole 170H. DD line). The global metal line 280K is disposed on the lower edge of the static random access memory cell 100 and can be shared with an adjacent static random access memory cell. The global metal line 280A has a width w1, half of the width w1 is in one static random access memory cell, and the other half of the width w1 is in an adjacent static random access memory cell. The width of the global metal line 280K can be substantially the same as the width of the global metal line 280A. Half of the width of the global metal line 280K is in one static random access memory cell, and the other half of the width of the global metal line 280K is in an adjacent static random access memory cell. The other metal lines (local metal lines 280B, 280C, 280D, 280E, 280F, 280G, 280H, 280I, 280J) can each have the same width w2. The spacing between two adjacent metal lines can be consistent and is labeled as the spacing s1. Therefore, the cell height H of the static random access memory is equal to w1 + 4*w2 + 5*s1. Compared with the layout 100B, in which the cell height H of the static random access memory is w1 + 5w2 + 6*s1, the layout 100C saves w2 + s1 in the cell height H. The w2 + s1 saved in the cell height H results from using six metal tracks instead of seven metal tracks in the metal layer 0 M0 layout. Specifically, the functions of the fourth metal track M0 Track 4 and the fifth metal track M0 Track 5 in the layout 100B (for the pads of the complementary storage node SNB and for the pads of the read port bit line R_BL) are now combined into the fifth metal track M0 Track 5 in the layout 100C (for the pads of the complementary storage node SNB and for the pads of the read port bit line R_BL). Saving one metal track can translate into a reduction in cell size of approximately 10% to approximately 20%. In some embodiments, the ratio of the length L1 of the local metal line 280B to the poly pitch (labeled as P) ranges from about 2 to about 4 (i.e., 2 < L1 / P < 4); the ratio of the length L2 of the local metal line 280D to the poly pitch ranges from about 1.5 to about 3 (i.e., 1.5 < L2 / P < 3); the ratio of the length L3 of the local metal line 280I to the poly pitch ranges from about 1.5 to about 3 (i.e., 1.5 < L3 / P < 3); the ratio of the length L4 of the local metal line 280E to the poly pitch ranges from about 0.5 to about 2 (i.e., 0.5 < L4 / P < 2); the ratio of the length L5 of the local metal line 280J to the poly pitch ranges from about 0.5 to about 2 (i.e., 0.5 < L5 / P < 2); the ratio of the length L6 of the local metal line 280G to the poly pitch ranges from about 1 to about 2 (i.e., 1 < L6 / P < 2). FIG. 14 shows the via first layer V1 and the metal first layer M1 of the layout 100C of the metal interconnect structure of the dual-port static random access memory cell 100. Furthermore, for visual clarity, the global metal lines 280A, 280K and the local metal lines 280B, 280C, 280D, 280E, 280F, 280G, 280H, 280I, 280J shown in FIG. 13 are replicated in FIG. 14. In the metal first layer M1, the static random access memory cell 100 includes a plurality of metal tracks arranged in parallel. Specifically, in the illustrated embodiment of the layout 100C, the static random access memory cell 100 includes five metal tracks arranged in sequence from the first metal track M1 Track 1 to the fifth metal track M1 Track 5 along the X direction. The center lines of the metal tracks are shown as dashed lines in FIG. 14. In layout 100C, the first metal track M1 Track 1 includes local metal line 292A. Local metal line 292A provides a pad for the write port complementary bit line W_BLB and is electrically coupled to the underlying local metal line 280C through via 290A. The second metal track M1 Track 2 includes global metal line 292B. Global metal line 292B is the write port word line W_WL and is electrically coupled to the underlying local metal line 280B (the pad for the write port word line W_WL) through via 290B. The third metal track M1 Track 3 includes global metal line 292C. Global metal line 292C is also a voltage line (Vss line) and is electrically coupled to the underlying global metal line 280A (voltage line (Vss line)) through via 290C. The fourth metal track M1 Track 4 includes global metal line 292D. Global metal line 292D is the read port word line R_WL and is electrically coupled to the underlying local metal line 280H (the pad for the read port word line R_WL) through via 290D. The fifth metal track M1 Track 5 includes local metal lines 292E and 292F. Local metal line 292E provides a pad for the write port bit line W_BL and is electrically coupled to the underlying local metal line 280E (the pad for the write port bit line W_BL) through via 290E. Local metal line 292F provides a pad for the read port bit line R_BL and is electrically coupled to the underlying local metal line 280J (the pad for the read port bit line R_BL) through via 290F. FIG. 15 shows the via second layer V2 and metal second layer M2 of the layout 100C of the metal interconnect structure of the dual-port static random access memory cell 100. Furthermore, for visual clarity, the global metal lines 292B, 292C, 292D and local metal lines 292A, 292E, 292F shown in FIG. 14 are replicated in FIG. 15. In the metal second layer M2, the static random access memory cell 100 includes a plurality of metal tracks arranged in parallel. Specifically, in the illustrated embodiment of layout 100C, the static random access memory cell 100 includes four metal tracks arranged in sequence from the first metal track M2 Track 1 to the fourth metal track M2 Track 4 along the Y direction. The center lines of the metal tracks are shown as dashed lines in FIG. 15. In layout 100C, the first metal track M2 Track 1 includes a global metal line 296A, the global metal line 296A provides a write port complementary bit line W_BLB, and is electrically coupled to a lower local metal line 292A (a pad for the write port complementary bit line W_BLB) through a via 294A. The second metal track M2 Track 2 includes a global metal line 296B, the global metal line 296B is a write port bit line W_BL, and is electrically coupled to a lower local metal line 292E (a pad for the write port bit line W_BL) through a via 294B. The third metal track M2 Track 3 includes a global metal line 296C, and the global metal line 296C passes through the static random access memory cell 100. The fourth metal track M2 Track 4 includes a global metal line 296D, the global metal line 296D provides a read port bit line R_BL, and is electrically coupled to a lower local metal line 292F (a pad for the read port bit line R_BL) through a via 294D. In the illustrated embodiment, the global metal lines 296A, 296B, 296C, 296D are uniformly distributed with the same metal line width and spacing. As an alternative embodiment of the metal interconnect structure, FIGS. 16, 17, 18, and 19 show a simplified schematic layout 100D of the metal interconnect structure of the dual-port static random access memory cell 100 at different layers. Specifically, FIG. 16 shows the conductive components in the contact layer CO and the via layer V0, FIG. 17 shows the via layer V0 and the metal layer M0, FIG. 18 shows the via layer V1 and the metal layer M1, and FIG. 19 shows the via layer V2 and the metal layer M2. FIG. 16 shows the conductive components in the contact layer CO and the via layer V0. Furthermore, for visual clarity, some components for the device layer DL in layout 100A are reproduced in FIG. 16, such as the active regions 102, 104, the gate structures 112, 114, 116, 118, 120, the continuous polysilicon cross-diffusion layer boundary component 132, and the boundary 140, while many other components are omitted in FIG. 16. The gate contact 150A electrically connects the gate (formed by the gate structure 118) of the read port transfer gate transistor R-PG to the read port word line R_WL. The gate contact 150C electrically connects the gate (formed by the gate structure 112) of the transfer gate transistor PG-1 to the write port word line W_WL. The gate contact 150D electrically connects the gate (formed by the gate structure 120) of the transfer gate transistor PG-2 to the write port word line W_WL. The gate contact 150E electrically connects the gate (formed by the gate structure 114) of the write port pull-down transistor PD-1 and the gate (also formed by the gate structure 114) of the write port pull-up transistor PU-1 to the storage node SN. The gate contact 150F electrically connects the gate (formed by the gate structure 116) of the write port pull-down transistor PD-2 and the gate (also formed by the gate structure 116) of the write port pull-up transistor PU-2 to the complementary storage node SNB. The source / drain contact 160A and the source / drain contact via 170A located on the source / drain contact 160A electrically connect the source region of the read port transfer gate transistor R-PG to the read port bit line R_BL. The source / drain contact 160B is located on the source / drain region adjacent to the continuous polysilicon spacer 132 and remains electrically floating, and there is no corresponding source / drain contact via located on it. The source / drain contact 160C and the source / drain contact via 170C located on the source / drain contact 160C electrically connect the source region of the write port transfer gate transistor PG-1 to the write port complementary bit line W_BLB. The source / drain contact 160D and the source / drain contact via 170D located on the source / drain contact 160D electrically connect the source region of the write port transfer gate transistor PG-2 to the write port bit line W_BL. The source / drain contact 160E and the source / drain contact via 170E located on the source / drain contact 160E electrically connect the common drain region of the write port transfer gate transistor PG-1 and the write port pull-down transistor PD-1 and the drain region of the write port pull-up transistor PU-1 to the complementary storage node SNB. The source / drain contact 160F and the source / drain contact via 170F located on the source / drain contact 160F electrically connect the common drain region of the write port transfer gate transistor PG-2 and the write port pull-down transistor PD-2 and the common drain region of the write port pull-up transistor PU-2 and the read port transfer gate transistor R-PG to the storage node SN. The source / drain contact 160G and the source / drain contact via 170G located on the source / drain contact 160G electrically connect the common source region of the write port pull-down transistor PD-1 and the write port pull-down transistor PD-2 to the ground voltage node V SSThe source / drain contact 160H and the source / drain contact via 170H located on the source / drain contact 160H electrically connect the common source regions of the write port pull-up transistor PU-1 and the write port pull-up transistor PU-2 to the power supply voltage node V. DD In the illustrated embodiment, each of the source / drain contacts 160A, 160B, 160C, 160D, 160E, 160F, 160G, 160H is elongated and has a longitudinal direction in the Y direction, which longitudinal direction is parallel to the extending direction of the gate structure. As shown in FIG. 16, the storage node SN includes the gate contact 150E and the source / drain contact vias 170F located on both sides of the gate structure 116. As discussed in more detail below, the metal line in the metal layer zero M0 extends in the X direction to span the gate structure 116 and connect the gate contact 150E and the source / drain contact via 170F. In other words, the metal line m0 is suspended above the gate structure 116 and provides a cross-coupling between the gate contact 150E and the source / drain contact via 170F. Therefore, in the layout 100D, the gate contact 150E and the source / drain contact via 170F are horizontal in the Y direction, enabling the metal line extending in the X direction to connect the two. Similarly, the complementary storage node SNB (storage node bar) includes the gate contact 150F and the source / drain contact vias 170E located on both sides of the gate structure 114. As discussed in more detail below, the metal line in the metal layer zero M0 extends in the X direction to span the gate structure 114 and connect the gate contact 150F and the source / drain contact via 170E. In other words, the metal line m0 is suspended above the gate structure 114 and provides a cross-coupling between the gate contact 150F and the source / drain contact via 170E. Therefore, in the layout 100D, the gate contact 150F and the source / drain contact via 170E are horizontal in the Y direction, enabling the metal line extending in the X direction to connect the two. The difference between layout 100C shown in FIG. 12 and layout 100D shown in FIG. 16 is that, in layout 100C, the gate contact 150F and the source / drain contact via 170E, which belong to the complementary storage node SNB, are disposed on the active region 104 and aligned with the source / drain contact via 170A in the X direction; while in layout 100D, the gate contact 150F and the source / drain contact via 170E, which belong to the complementary storage node SNB, are disposed between the active region 102 and the active region 104 and aligned with the gate contact 150A. In other words, in layout 100C, in the Y direction, the conductive component coupled to the read port word line R_WL is disposed between the conductive component belonging to the storage node SN and the conductive component belonging to the complementary storage node SNB; while in layout 100D, in the Y direction, the conductive component belonging to the complementary storage node SNB and the conductive component coupled to the read port word line R_WL are disposed between the conductive component belonging to the storage node SN and the conductive component coupled to the read port word line R_WL. FIG. 17 shows the via layer zero V0 and the metal layer zero M0 of the layout 100D of the metal interconnection structure of the dual-port static random access memory cell 100. In the metal layer zero M0, the static random access memory cell 100 includes a plurality of metal tracks arranged in parallel. Specifically, in the illustrated embodiment of layout 100D, the static random access memory cell 100 includes six metal tracks arranged in sequence from the first metal track M0 Track 1 to the sixth metal track M0 Track 6 in the Y direction. The center lines of the metal tracks are shown as dashed lines in FIG. 17. In layout 100D, the first metal track M0 Track 1 includes a global metal line 380A, which is a voltage line (Vss line) electrically coupled to the source / drain contact via 170G. The global metal line 380A is disposed on the upper edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The second metal track M0 Track 2 includes a local metal line 380B as a pad for the write port word line W_WL. The local metal line 380B is entirely within the static random access memory cell 100 and is electrically connected to the gate contacts 150C and 150D. The third metal track M0 Track 3 includes three local metal lines 380C, 380D, and 380E. The local metal line 380C provides a pad for the write port complementary bit line W_BLB. The local metal line 380C extends beyond the left edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The local metal line 380D is entirely within the static random access memory cell 100. The local metal line 380D belongs to the storage node SN and provides a cross-coupling between the gate contact 150E and the source / drain contact via 170F. As described above, the local metal line 380D crosses the gate structure 116. The local metal line 380E provides a pad for the write port bit line W_BL. The local metal line 380E extends beyond the right edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The fourth metal track M0 Track 4 includes two local metal lines 380F and 380G. The local metal line 380F is entirely within the static random access memory cell 100. The local metal line 380F belongs to the complementary storage node SNB and provides a cross-coupling between the gate contact 150F and the source / drain contact via 170E. As described above, the local metal line 380F crosses the gate structure 116. The local metal line 380G is entirely within the static random access memory cell 100 and provides a pad for the read port word line R_WL. The fifth metal track M0 Track 5 includes a global metal line 380H, which is the read port bit line R_BL and is electrically coupled to the source / drain contact via 170A. The sixth metal track M0 Track 6 includes a global metal line 380I, which is a voltage line (V DD line) electrically coupled to the source / drain contact via 170H. The global metal line 380I is disposed on the lower edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The global metal line 380A has a width w1, with half of the width w1 in one static random access memory cell and the other half of the width w1 in an adjacent static random access memory cell. The width of the global metal line 380I can be substantially the same as the width of the global metal line 380A, with half of the width of the global metal line 380I in one static random access memory cell and the other half of the width of the global metal line 280I in an adjacent static random access memory cell. The other metal lines (local metal lines 380B, 380C, 380D, 380E, 380F, 380G, global metal line 380H) can each have the same width w2. The spacing between two adjacent metal lines can be consistent and is labeled as spacing s1. Thus, the cell height H of the static random access memory is equal to w1 + 4*w2 + 5*s1. Compared with layout 100B, where the cell height H of the static random access memory is w1 + 5w2 + 6*s1, layout 100D saves w2 + s1 in the cell height H. The w2 + s1 saved in the cell height H results from using six metal tracks instead of seven metal tracks in the metal layer zero M0 layout. Specifically, the functions of the fourth metal track M0 Track 4 and the sixth metal track M0 Track 6 in layout 100B (for the pads of the complementary storage node SNB and for the pads of the read port word line R_WL) are now combined into the fourth metal track M0 Track 4 in layout 100D (for the pads of the complementary storage node SNB and for the pads of the read port bit line R_BL). Saving one metal track can translate into a reduction in cell size of approximately 10% to approximately 20%. In some embodiments, the ratio of the length L10 of the local metal line 380G to the poly pitch (labeled as P) is in the range of about 0.7 to about 1.5 (i.e., 0.7 < L10 / P < 1.5); the ratio of the length L11 of the local metal line 380F to the poly pitch is in the range of about 2 to about 3 (i.e., 2 < L11 / P < 3). FIG. 18 shows the via first layer V1 and the metal first layer M1 of the layout 100D of the metal interconnect structure of the dual-port static random access memory cell 100. Furthermore, for visual clarity, the global metal lines 380A, 380H, 380I and the local metal lines 380B, 380C, 380D, 380E, 380F, 380G shown in FIG. 17 are replicated in FIG. 18. In the metal first layer M1, the static random access memory cell 100 includes a plurality of metal tracks arranged in parallel. Specifically, in the illustrated embodiment of layout 100D, the static random access memory cell 100 includes five metal tracks arranged in sequence from the first metal track M1 Track 1 to the fifth metal track M1 Track 5 along the X direction. The center lines of the metal tracks are shown as dashed lines in FIG. 18. In layout 100D, the first metal track M1 Track 1 includes local metal line 392A. Local metal line 392A provides a pad for the write port complementary bit line W_BLB and is electrically coupled to the underlying local metal line 380C through via 390A. The second metal track M1 Track 2 includes global metal line 392B. Global metal line 392B is the write port word line W_WL and is electrically coupled to the underlying local metal line 380B (the pad for the write port word line W_WL) through via 390B. The third metal track M1 Track 3 includes global metal line 392C. Global metal line 392C is also a voltage line (Vss line) and is electrically coupled to the underlying global metal line 380A (voltage line (Vss line)) through via 390C. The fourth metal track M1 Track 4 includes global metal line 392D. Global metal line 392D is the read port word line R_WL and is electrically coupled to the underlying local metal line 380G (the pad for the read port word line R_WL) through via 390D. The fifth metal track M1 Track 5 includes local metal line 392E. Local metal line 392E provides a pad for the write port bit line W_BL and is electrically coupled to the underlying local metal line 380E (the pad for the write port bit line W_BL) through via 390E. FIG. 19 shows via second layer V2 and metal second layer M2 of layout 100D of the metal interconnect structure of the dual-port static random access memory cell 100. Furthermore, for visual clarity, the global metal lines 392B, 392C, 392D and local metal lines 392A, 392E shown in FIG. 18 are replicated in FIG. 19. In metal second layer M2, the static random access memory cell 100 includes a plurality of metal tracks arranged in parallel. Specifically, in the illustrated embodiment of layout 100D, the static random access memory cell 100 includes two metal tracks arranged in sequence from the first metal track M2 Track 1 to the second metal track M2 Track 2 along the Y direction. The center lines of the metal tracks are shown as dashed lines in FIG. 19. In layout 100D, the first metal track M2 Track 1 includes a global metal line 396A that provides a write port complementary bit line W_BLB and is electrically coupled through a via 394A to a lower local metal line 392A (a pad for the write port complementary bit line W_BLB). The second metal track M2 Track 2 includes a global metal line 396B that is a write port bit line W_BL and is electrically coupled through a via 394B to a lower local metal line 392E (a pad for the write port bit line W_BL). In the illustrated embodiment, the global metal lines 396A and 396B are uniformly distributed with the same metal line width and spacing. As an alternative embodiment of the metal interconnect structure, FIGS. 20, 21, 22, and 23 show simplified schematic layouts 100E of the metal interconnect structure of the dual-port static random access memory cell 100 at different layers. Specifically, FIG. 20 shows conductive components in the contact layer CO and via layer V0. FIG. 21 shows via layer V0 and metal layer M0. FIG. 22 shows via layer V1 and metal layer M1. And FIG. 23 shows via layer V2 and metal layer M2. FIG. 20 shows conductive components in the contact layer CO and via layer V0. Further, for visual clarity, some components for the device layer DL in layout 100A are reproduced in FIG. 20, such as active regions 102, 104, gate structures 112, 114, 116, 118, 120, continuous polysilicon cross-diffusion layer boundary components 132, and boundary 140, while FIG. 20 omits many other components. The gate contact 150A electrically connects the gate of the read port transfer gate transistor R-PG (formed by the gate structure 118) to the read port word line R_WL. The gate contact 150C electrically connects the gate of the transfer gate transistor PG-1 (formed by the gate structure 112) to the write port word line W_WL. The gate contact 150D electrically connects the gate of the transfer gate transistor PG-2 (formed by the gate structure 120) to the write port word line W_WL. The gate contact 150E electrically connects the gate of the write port pull-down transistor PD-1 (formed by the gate structure 114) and the gate of the write port pull-up transistor PU-1 (also formed by the gate structure 114) to the storage node SN. The gate contact 150F electrically connects the gate of the write port pull-down transistor PD-2 (formed by the gate structure 116) and the gate of the write port pull-up transistor PU-2 (also formed by the gate structure 116) to the complementary storage node SNB. The source / drain contact 160A and the source / drain contact via 170A located on the source / drain contact 160A electrically connect the source region of the read port transfer gate transistor R-PG to the read port bit line R_BL. The source / drain contact 160B is located on the source / drain region adjacent to the continuous polysilicon cross-diffusion layer boundary component 132 and remains electrically floating, and no corresponding source / drain contact via is located thereon. The source / drain contact 160C and the source / drain contact via 170C located on the source / drain contact 160C electrically connect the source region of the write port transfer gate transistor PG-1 to the write port complementary bit line W_BLB. The source / drain contact 160D and the source / drain contact via 170D located on the source / drain contact 160D electrically connect the source region of the write port transfer gate transistor PG-2 to the write port bit line W_BL. The source / drain contact 160E and the source / drain contact via 170E located on the source / drain contact 160E electrically connect the common drain region of the write port transfer gate transistor PG-1 and the write port pull-down transistor PD-1 and the drain region of the write port pull-up transistor PU-1 to the complementary storage node SNB. The source / drain contact 160F and the source / drain contact via 170F located on the source / drain contact 160F electrically connect the common drain region of the write port transfer gate transistor PG-2 and the write port pull-down transistor PD-2 and the common drain region of the write port pull-up transistor PU-2 and the read port transfer gate transistor R-PG to the storage node SN. The source / drain contact 160G and the source / drain contact via 170G located on the source / drain contact 160G electrically connect the common source region of the write port pull-down transistor PD-1 and the write port pull-down transistor PD-2 to the ground voltage node V SS . The source / drain contact 160H and the source / drain contact via 170H located on the source / drain contact 160H electrically connect the common source region of the write port pull-up transistor PU-1 and the write port pull-up transistor PU-2 to the power supply voltage node V DD . In the illustrated embodiment, each of the source / drain contacts 160A, 160B, 160C, 160D, 160E, 160F, 160G, 160H is elongated and has a longitudinal direction in the Y direction, and this longitudinal direction is parallel to the extension direction of the gate structure. As shown in FIG. 20, the storage node SN includes a gate contact 150E and source / drain contact vias 170F located on both sides of the gate structure 116. As discussed in more detail below, the metal lines in the metal layer zero M0 extend in the X direction to span the gate structure 116 and connect the gate contact 150E and the source / drain contact vias 170F. In other words, the metal line m0 is suspended above the gate structure 116 and provides a cross-coupling between the gate contact 150E and the source / drain contact vias 170F. Therefore, in the layout 100E, the gate contact 150E and the source / drain contact vias 170F are horizontal in the Y direction, allowing the metal line extending in the X direction to connect the two. Similarly, the complementary storage node SNB (storage node bar) includes a gate contact 150F and source / drain contact vias 170E located on both sides of the gate structure 114. As discussed in more detail below, the metal lines in the metal layer zero M0 extend in the X direction to span the gate structure 114 and connect the gate contact 150F and the source / drain contact vias 170E. In other words, the metal line m0 is suspended above the gate structure 114 and provides a cross-coupling between the gate contact 150F and the source / drain contact vias 170E. Therefore, in the layout 100E, the gate contact 150F and the source / drain contact vias 170E are horizontal in the Y direction, allowing the metal line extending in the X direction to connect the two. The difference between the layout 100E shown in FIG. 20 and the other layouts 100B, 100C, 100D described above is that in the layout 100E, the gate structure 118 for the read port transfer gate transistor R-PG extends in the Y direction across the boundary between the static random access memory cell 100 and the adjacent static random access memory cell (also shown in FIG. 6), which allows the gate contact 150A to be disposed on the lower edge of the static random access memory cell 100. FIG. 21 shows the via layer zero V0 and the metal layer zero M0 of the layout 100E of the metal interconnection structure of the dual-port static random access memory cell 100. In the metal layer zero M0, the static random access memory cell 100 includes a plurality of metal tracks arranged in parallel. In particular, in the illustrated embodiment of the layout 100E, the static random access memory cell 100 includes six metal tracks arranged in sequence from the first metal track M0 Track 1 to the sixth metal track M0 Track 6 in the Y direction. The center lines of the metal tracks are shown as dashed lines in FIG. 21. In layout 100E, the first metal track M0 Track 1 includes a global metal line 480A, and the global metal line 480A is a voltage line (Vss line) electrically coupled to the source / drain contact via hole 170G. The global metal line 480A is disposed on the upper edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The second metal track M0 Track 2 includes a local metal line 480B as a pad for the write port word line W_WL. The local metal line 480B is entirely within the static random access memory cell 100 and is electrically connected to the gate contact 150C and the gate contact 150D. The third metal track M0 Track 3 includes three local metal lines 480C, 480D, and 480E. The local metal line 480C provides a pad for the write port complementary bit line W_BLB. The local metal line 480C extends beyond the left edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The local metal line 380D is entirely within the static random access memory cell 100. The local metal line 480D belongs to the storage node SN and provides a cross-coupling between the gate contact 150E and the source / drain contact via hole 170F. As described above, the local metal line 480D straddles the gate structure 116. The local metal line 480E provides a pad for the write port bit line W_BL. The local metal line 480E extends beyond the right edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The fourth metal track M0 Track 4 includes two local metal lines 480F. The local metal line 480F is entirely within the static random access memory cell 100. The local metal line 480F belongs to the complementary storage node SNB and provides a cross-coupling between the gate contact 150F and the source / drain contact via hole 170E. As described above, the local metal line 480F straddles the gate structure 116. The fifth metal track M0 Track 5 includes a global metal line 480G, and the global metal line 480G is the read port bit line R_BL and is electrically coupled to the source / drain contact via hole 170A. The sixth metal track M0 Track 6 includes local metal lines 480H and 480I. The local metal line 480H provides a pad for the voltage line (V DD line) electrically coupled to the source / drain contact via hole 170H. The local metal line 480I provides a pad for the read port word line R_WL electrically coupled to the gate contact 150A. The local metal line 480I is disposed on the lower edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. The global metal line 480A has a width w1, with half of the width w1 in one static random access memory cell and the other half of the width w1 in an adjacent static random access memory cell. The widths of the pads for the local metal line 480H and the widths of the pads for the local metal line 480I can be approximately the same as the width of the global metal line 480A. Half of the widths of the pads for the local metal line 480H and the widths of the pads for the local metal line 480I are in one static random access memory cell, and the other half of the width is in an adjacent static random access memory cell. The other metal lines (local metal lines 480B, 480C, 480D, 480E, 480F, global metal line 480G) can each have the same width w2. The spacing between two adjacent metal lines can be consistent and is labeled as the spacing s1. Thus, the cell height H of the static random access memory is equal to w1 + 4*w2 + 5*s1. Compared with layout 100B, where the cell height H of the static random access memory is w1 + 5w2 + 6*s1, layout 100E saves w2 + s1 in the cell height H. The w2 + s1 saved in the cell height H results from using six metal tracks instead of seven metal tracks in the metal layer 0 (M0) layout. Specifically, the functions of the sixth metal track M0 Track 6 and the seventh metal track M0 Track 7 in layout 100B (for the pads of the read port word line R_WL and for the voltage line (V DD line)) are now combined into the sixth metal track M0 Track 6 in layout 100E (for the pads of the read port word line R_WL and for the voltage line (V DD line)). Saving one metal track can translate into a reduction in cell size of approximately 10% to approximately 20%. In some embodiments, the ratio of the length L15 of the local metal line 480H to the poly pitch (labeled as P) is in the range of about 0.1 to about 3 (i.e., 0.1 < L15 / P < 3); the ratio of the length L16 of the local metal line 480I to the poly pitch is in the range of about 0.1 to about 2 (i.e., 0.1 < L16 / P < 2). Figure 22 shows via first layer V1 and metal first layer M1 of layout 100E of the metal interconnect structure of dual-port static random access memory cell 100. Furthermore, for visual clarity, global metal lines 480A, 480G and local metal lines 480B, 480C, 480D, 480E, 480F, 480H, 480I shown in Figure 21 are replicated in Figure 22. In metal first layer M1, the static random access memory cell 100 includes a plurality of metal tracks arranged in parallel. Specifically, in the illustrated embodiment of layout 100E, the static random access memory cell 100 includes five metal tracks arranged in sequence from the first metal track M1 Track 1 to the fifth metal track M1 Track 5 in the X direction. The center lines of the metal tracks are indicated by dashed lines in Figure 22. In layout 100E, the first metal track M1 Track 1 includes local metal line 492A. Local metal line 492A provides a pad for the write port complementary bit line W_BLB and is electrically coupled to the underlying local metal line 480C through via 490A. The second metal track M1 Track 2 includes global metal line 492B. Global metal line 492B is the write port word line W_WL and is electrically coupled to the underlying local metal line 480B (the pad for the write port word line W_WL) through via 490B. The third metal track M1 Track 3 includes local metal line 492C. Local metal line 492C provides a pad for the voltage line (V DD line) and is electrically coupled to the underlying local metal line 480H (the pad for the voltage line (V DD line)) through via 490C. The fourth metal track M1 Track 4 includes global metal line 492D. Global metal line 492D is the read port word line R_WL and is electrically coupled to the underlying local metal line 480I (the pad for the read port word line R_WL) through via 490D. The fifth metal track M1 Track 5 includes local metal line 492E. Local metal line 492E provides a pad for the write port bit line W_BL and is electrically coupled to the underlying local metal line 480E (the pad for the write port bit line W_BL) through via 490E. FIG. 23 shows via second layer V2 and metal second layer M2 of layout 100E of the metal interconnect structure of dual-port static random access memory cell 100. Furthermore, for visual clarity, global metal lines 492B, 492D and local metal lines 492A, 492C, 492E shown in FIG. 22 are replicated in FIG. 23. In metal second layer M2, the static random access memory cell 100 includes a plurality of metal tracks arranged in parallel. Specifically, in the illustrated embodiment of layout 100E, the static random access memory cell 100 includes three metal tracks arranged in sequence from the first metal track M2 Track 1 to the third metal track M2 Track 3 along the Y direction. The center lines of the metal tracks are indicated by dashed lines in FIG. 23. In layout 100E, the first metal track M2 Track 1 includes global metal line 496A, and global metal line 496A provides a write port complementary bit line W_BLB and is electrically coupled to the underlying local metal line 492A (pad for write port complementary bit line W_BLB) through via 494A. The second metal track M2 Track 2 includes global metal line 496B, and global metal line 496B is a write port bit line W_BL and is electrically coupled to the underlying local metal line 492E (pad for write port bit line W_BL) through via 494B. The third metal track M2 Track 3 includes global metal line 496C, and global metal line 496C is a voltage line (V DD line), and is electrically coupled to the underlying local metal line 492C (pad for voltage line (V DD line)) through via 494C. Global metal line 496C is disposed on the lower edge of the static random access memory cell 100 and can be shared with adjacent static random access memory cells. In the illustrated embodiment, global metal lines 496A, 496B are uniformly distributed with the same line width, and this line width is greater than the line width of global metal line 496C. The multi-port static random access memory cells and corresponding layouts shown in various exemplary embodiments of the present invention provide better unit area utilization, which reduces the unit size required to implement multi-port static random access memory cells. In some embodiments, the layout design of the metal interconnect structure indicates that a dual-port (2P) static random access memory cell has only six metal tracks of metal zero layer M0 to fit the cell height. Furthermore, the embodiments of the present invention can be easily integrated into existing semiconductor manufacturing processes. In an exemplary aspect, embodiments of the present invention relate to a memory cell. The memory cell includes a device layer including a plurality of transistors, each of the plurality of transistors including a gate structure longitudinally extending in a first direction; and an interconnect structure disposed above the device layer. The interconnect structure includes a bottommost metal line layer electrically coupled to the plurality of transistors in the device layer. The bottommost metal line layer includes a first metal track, a second metal track, a third metal track, a fourth metal track, a fifth metal track, and a sixth metal track sequentially arranged from the first to the sixth in the first direction. The distance between any two adjacent ones of the first metal track, the second metal track, the third metal track, the fourth metal track, the fifth metal track, and the sixth metal track measured in the first direction is consistent. The first metal track includes a metal line electrically coupled to the electrical ground of the memory cell. The sixth metal track includes a metal line electrically coupled to the power supply of the memory cell. In some embodiments, the memory cell includes a write port and a read port, and the fifth metal track includes a metal line coupled to the read port bit line of the memory cell. In some embodiments, the metal line of the fifth metal track extends completely through the boundary of the memory cell in a second direction perpendicular to the first direction. In some embodiments, the metal line of the fifth metal track is configured to be coupled to the landing pad of the read port bit line. In some embodiments, the metal line of the sixth metal track is configured to be coupled to the landing pad of the power supply. In some embodiments, the sixth metal track includes another metal line configured to be coupled to the landing pad of the read port word line of the memory cell. In some embodiments, the memory cell includes a storage node and a complementary storage node, and the third metal track includes a metal line coupled to the storage node. In some embodiments, the fourth metal track includes a metal line coupled to the complementary storage node. In some embodiments, the fifth metal track includes a metal line coupled to the complementary storage node. In some embodiments, the metal line of the third metal track spans the gate structure of one of the plurality of transistors having a gate contact coupled to the complementary storage node. In another exemplary aspect, embodiments of the present invention relate to an integrated circuit structure. The integrated circuit structure includes a device layer, the device layer including a first gate structure of a first transfer gate transistor, a second gate structure shared by a first pull-down transistor and a first pull-up transistor, a third gate structure shared by a second pull-down transistor and a second pull-up transistor, and a fourth gate structure of a second transfer gate transistor. Each of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure extends longitudinally in a first direction; and a metal layer suspended above the device layer. The metal layer includes first to sixth metal tracks arranged in sequence from the first in the first direction, namely, a first metal track, a second metal track, a third metal track, a fourth metal track, a fifth metal track, and a sixth metal track. Each of the first metal track, the second metal track, the third metal track, the fourth metal track, the fifth metal track, and the sixth metal track extends longitudinally in a second direction perpendicular to the first direction. The third metal track includes a metal line spanning across the third gate structure, and one of the fourth metal track or the fifth metal track includes a metal line spanning across the second gate structure. In some embodiments, the fifth metal track includes a metal line spanning across the second gate structure, and the fourth metal track includes an electrically floating metal island. In some embodiments, the fourth metal track includes a metal line spanning across the second gate structure. The metal line of the fourth metal track is electrically coupled to the third gate structure, and the metal line of the third metal track is electrically coupled to the second gate structure. In some embodiments, the first metal track and the sixth metal track include metal lines coupled to a power supply and electrical ground of the device layer. In some embodiments, the device layer further includes a fifth gate structure of a third transfer gate transistor. The first transfer gate transistor and the second transfer gate transistor are of a first conductivity type, and the third transfer gate transistor is of a second conductivity type relative to the first conductivity type. In some embodiments, the sixth metal track includes a metal line coupled to the fifth gate structure. In some embodiments, the fourth metal track includes a metal line coupled to the fifth gate structure. In another illustrative aspect, embodiments of the present invention relate to a memory array that includes a first memory cell having at least one first transistor; a second memory cell having at least one second transistor, the second memory cell being adjacent to the first memory cell, and the first transistor and the second transistor sharing a gate structure that straddles a boundary line between the first memory cell and the second memory cell; a gate contact disposed on the gate structure; and a metal track suspended above the boundary line, the metal track including a first pad coupled to a power supply for the first memory cell and the second memory cell and a second pad physically contacting the gate contact. In some embodiments, the first memory cell includes a write port and a read port, the second memory cell includes a write port and a read port, the first transistor is a transfer gate transistor of the first memory cell, and the second transistor is a transfer gate transistor of the second memory cell. In some embodiments, the metal track is a first metal track, and the memory array also includes a second metal track suspended above the first metal track, the second metal track including a third pad coupled to the first pad through a first via; and a third metal track suspended above the second metal track, the third metal track including a power supply line coupled to the third pad through a second via. The foregoing text outlines the features of many embodiments, enabling those of ordinary skill in the art to better understand the embodiments of the present invention from various aspects. Those of ordinary skill in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention and achieve the same purpose and / or the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the present invention. 10: Integrated circuit device 12: Substrate 14, 102, 104: Active region 15: Doped region 16: Source / drain component 18: Isolation structure 20, 112, 114, 116, 118, 120: Gate structure 22: Gate electrode 24: Gate dielectric 25: Gate spacer 26: Nanostructure 28: Dielectric layer 100: Static random access memory cell 100A, 100B, 100C, 100D, 100E, 200A, 200B: Layout 100R: Read port 100W: Write port 106: n-type well 108: p-type well 130: Cut metal gate component 132, CPODE: Continuous polysilicon over-diffusion layer boundary component 140: Boundary 150A, 150C, 150D, 150E, 150F: Gate contact 160A, 160B, 160C, 160D, 160E, 160F, 160G, 160H, MD: Source / drain contact 170A, 170C, 170D, 170E, 170F, 170G, 170H, VD: Source / drain contact via 200: Static random access memory array 180A, 180G, 180I, 192B, 192D, 196B, 196C, 280A, 280K, 292B, 292C, 292D, 296A, 296B, 296C, 296D, 380A, 380H, 380I, 392B, 392C, 392D, 396A, 396B, 480A, 480G, 492B, 492D, 496A, 496B, 496C: Global metal line 180B, 180C, 180D, 180E, 180F, 180H, 192A, 192C, 192E, 196A, 280B, 280C, 280D, 280E, 280F, 280G, 280H, 280I, 280J, 292A, 292E, 292F, 380B, 380C, 380D, 380E, 380F, 380G, 392A, 392E, 480B, 480C, 480D, 480E, 480F, 480H, 480I, 492A, 492C, 492E: Local metal line 190A, 190B, 190C, 190D, 190E, 194A, 194B, 194C, 290A, 290B, 290C, 290D, 290E, 290F, 294A, 294B, 294D, 390A, 390B, 390C, 390D, 390E, 394A, 394B, 490A, 490B, 490C, 490D, 490E, 494A, 494B494C: Via hole T: Transistor DL: Device layer MLI: Multilayer interconnection CO: Contact layer M0: Metal layer 0 M1: Metal layer 1 M2: Metal layer 2 M3: Metal layer 3 V0: Via hole layer 0 V1: Via hole layer 1 V2: Via hole layer 2 V3: Via hole layer 3 VG: Gate via Butted contact: Butt contact v1, v2, v3: Via holes M0 Track 1, M1 Track 1, M2 Track 1: First metal track M0 Track 2, M1 Track 2, M2 Track 2: Second metal track M0 Track 3, M1 Track 3, M2 Track 3: Third metal track M0 Track 4, M1 Track 4, M2 Track 4: Fourth metal track M0 Track 5, M1 Track 5: Fifth metal track M0 Track 6: Sixth metal track M0 Track 7: Seventh metal track PG-1, PG-2: Transmission gate transistors PU-1, PU-2: Pull-up transistors PD-1, PD-2: Pull-down transistors R-PG: Read port transmission gate transistor R_BL, W_BL: Bit lines W_BLB: Complementary bit line R_WL, W_WL: Word lines R_WLB: Complementary word line SN: Storage node SNB: Complementary storage node V, DD : Power supply voltage node V SS : Ground voltage node H: Cell height W: Cell width L1, L2, L3, L4, L5, L6, L10, L11, L15, L16: Lengths s1: Spacing w1, w2: Widths Embodiments of the present invention can be better understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, the various components (features) in the drawings are not necessarily drawn to scale. In fact, the dimensions of the various components may be arbitrarily enlarged or reduced for clear illustration. FIGS. 1A and 1B respectively show a perspective view and a top view of a part of a memory device according to some embodiments of the present invention. FIG. 2 shows a schematic cross-sectional view of the layers of a memory device according to some embodiments of the present invention. FIG. 3 shows a circuit schematic diagram of a dual-port static random access memory (SRAM) cell according to some embodiments of the present invention. FIG. 4 shows the layout of the device layer of the dual-port static random access memory cell in FIG. 3 according to some embodiments of the present invention. FIGS. 5 and 6 show the layout of a static random access memory array based on the dual-port static random access memory cell in FIG. 4 according to some other embodiments of the present invention. FIGS. 7A and 7B show schematic cross-sectional views of a part of the static random access memory array in FIGS. 5 and 6. FIGS. 8, 9, 10, 11 show a first layout of the metal interconnect structure in the respective contact layers and metal layers of the dual-port static random access memory cell as in FIG. 3 according to some embodiments of the present invention. FIGS. 12, 13, 14, 15 show a second layout of the metal interconnect structure in the respective contact layers and metal layers of the dual-port static random access memory cell as in FIG. 3 according to some embodiments of the present invention. FIGS. 16, 17, 18, 19 show a third layout of the metal interconnect structure in the respective contact layers and metal layers of the dual-port static random access memory cell as in FIG. 3 according to some embodiments of the present invention. FIGS. 20, 21, 22, 23 show a fourth layout of the metal interconnect structure in the respective contact layers and metal layers of the dual-port static random access memory cell as in FIG. 3 according to some embodiments of the present invention. 100: Static random access memory cell 100C: Layout 140: Boundary 150A, 150C, 150D, 150E, 150F: Gate contact 170A, 170C, 170D, 170E, 170F, 170G, 170H: Source / drain contact via 280A, 280K: Global metal line 280B, 280C, 280D, 280E, 280F, 280G, 280H, 280I, 280J: Local metal line M0: Metal layer 0 V0: Via layer 0 M0 Track 1: First metal track M0 Track 2: Second metal track M0 Track 3: Third Metal Track M0 Track 4: Fourth Metal Track M0 Track 5: Fifth Metal Track M0 Track 6: Sixth Metal Track H: Unit Height W: Unit Width L1, L2, L3, L4, L5, L6: Lengths s1: Spacing w1, w2: Widths

Claims

1. A memory cell, comprising: a device layer including a plurality of transistors, wherein each of the plurality of transistors includes a gate structure extending longitudinally along a first direction; and an interconnect structure disposed above the device layer, wherein: the interconnect structure includes a bottom metal line layer electrically coupled to the plurality of transistors in the device layer, the bottom metal line layer including a first metal track, a second metal track, a third metal track, a fourth metal track, a fifth metal track, and a sixth metal track arranged sequentially from first to sixth along the first direction, wherein the distance between any two adjacent first metal tracks, second metal tracks, third metal tracks, fourth metal tracks, fifth metal tracks, and sixth metal tracks measured along the first direction is consistent, the first metal track includes a metal line electrically coupled to an electrically grounded metal line of the memory cell, and the sixth metal track includes a metal line electrically coupled to a power supply of the memory cell, wherein the third metal track is electrically coupled to the gate structure.

2. The memory cell of claim 1, wherein the memory cell includes a write port and a read port, and the fifth metal track includes a metal line coupled to a read port bit line of the memory cell.

3. The memory cell of claim 2, wherein the metal line of the fifth metal track extends completely through a boundary of the memory cell in a second direction perpendicular to the first direction.

4. The memory cell of any one of claims 1 to 3, wherein the metal line of the sixth metal track is configured to be coupled to a landing pad of the power supply.

5. The memory cell of claim 4, wherein the sixth metal rail includes another metal line configured to be coupled to a landing pad of a read port word line of the memory cell.

6. A memory cell as claimed in any one of claims 1 to 3, wherein the memory cell includes a storage node and a complementary storage node, and the third metal track includes a metal wire coupled to the storage node.

7. The memory cell of claim 6, wherein the fourth or fifth metal track includes a metal line coupled to the complementary storage node.

8. The memory cell of claim 6, wherein the metal line of the third metal track spans the gate structure of one of the plurality of transistors having a gate contact coupled to the complementary storage node.

9. An integrated circuit structure, comprising: a device layer including a first gate structure of a first transmission gate transistor, a second gate structure shared by a first pull-down transistor and a first pull-up transistor, a third gate structure shared by a second pull-down transistor and a second pull-up transistor, and a fourth gate structure of a second transmission gate transistor, each of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure extending longitudinally along a first direction; and a bottom metal layer suspended above the device layer, the bottom metal layer including a first metal track, a second metal track, a third metal track, a fourth metal track, a fifth metal track, and a sixth metal track arranged sequentially from first to sixth along the first direction, each of the first metal track, the second metal track, the third metal track, the fourth metal track, the fifth metal track, and the sixth metal track extending longitudinally along a second direction perpendicular to the first direction. The third metal track includes a metal line that crosses the third gate structure, and one of the fourth or fifth metal tracks includes a metal line that crosses the second gate structure. The distance between any two adjacent tracks along the first direction of the first, second, third, fourth, fifth, and sixth metal tracks is consistent, and the metal line of the third metal track is electrically coupled to the second gate structure.

10. The integrated circuit structure of claim 9, wherein the fifth metal track includes the metal line spanning the second gate structure, and the fourth metal track includes an electrically floating metal island.

11. The integrated circuit structure of claim 9, wherein the fourth metal track includes a metal line spanning the second gate structure, the metal line of the fourth metal track being electrically coupled to the third gate structure.

12. An integrated circuit structure as claimed in any of claims 9 to 11, wherein the device layer further includes a fifth gate structure of a third transmission gate transistor, the first transmission gate transistor and the second transmission gate transistor being of a first conductivity type, and the third transmission gate transistor being of a second conductivity type relative to the first conductivity type.

13. The integrated circuit structure of claim 12, wherein the fourth metal track or the sixth metal track includes a metal line coupled to the fifth gate structure.

14. A memory array, comprising: a first memory cell having a first transistor; a second memory cell having a second transistor, the second memory cell being adjacent to the first memory cell, wherein the first transistor and the second transistor share a gate structure spanning a boundary line between the first memory cell and the second memory cell; a gate contact disposed on the gate structure; and a bottom metal layer suspended above the gate contact, the bottom metal layer comprising a plurality of metal rails arranged along a first direction, the distance between any two adjacent metal rails measured along the first direction being consistent, the metal rails comprising: a first metal rail suspended above the boundary line, wherein the first metal rail includes a first pad coupled to a power supply to the first memory cell and the second memory cell and a second pad physically contacting the gate contact; A second metal rail adjacent to the first metal rail, wherein the second metal rail is electrically coupled to the gate structure; and a third metal rail suspended above the first metal rail, the third metal rail including a third pad coupled to the first pad through a first via; and a fourth metal rail suspended above the third metal rail, the fourth metal rail including a power supply line coupled to the third pad through a second via.

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