Image signal and phase detection autofocus signal extraction and storage in an arithmetic logic unit

Abstract

An arithmetic logic unit (ALU) includes a front-end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. A first input of an adder stage is coupled to receive the output of the GC to binary stage. An adder input latch stage includes first and second adder input latches, each containing a first and a second input coupled to receive the output of the GC to binary stage. An adder input multiplexer stage includes an output coupled to a second input of the adder stage and first and second inputs respectively coupled to the outputs of the first and second adder input latches.

Description

Extraction and storage of image signals and phase detection autofocus signals in the arithmetic logic unit The present invention relates generally to image sensors and, particularly, but not exclusively, to an arithmetic logic unit for use in an image sensor. Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, as well as in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, there is a desire to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design and image capture processing. A typical image sensor operates in response to image light from an external scene incident on the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge upon absorption. The image charge generated by the pixels can be measured as analog output image signals on row bit lines that vary with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light. This is read out as an analog image signal from the row bit lines and converted into a digital value to provide information representing the external scene. Various examples are described herein for extracting and storing image signals and phase-detection autofocus signals in an arithmetic logic unit (ALU) within an analog-to-digital converter (ADC) of an imaging system. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, one skilled in the art will recognize that the techniques described herein can be practiced without one or more of the specific details, or using other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects. Reference throughout this specification to "one example" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrase "in one example" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples. For ease of description, spatially relative terms (such as "below," "beneath," "down," "beneath," "above," "up," "top," "bottom," "left," "right," "center," "middle," and the like) may be used herein to describe the relationship of one element or feature relative to another element or feature, as depicted in the figures. It should be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is rotated or flipped, an element described as "below," "beneath," or "beneath" another element or feature would then be oriented "above" the other element or feature. Thus, the exemplary terms "below" or "beneath" would encompass both above and below orientations. The device can be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Furthermore, it should be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Throughout this specification, several technical terms are used. These terms have their ordinary meanings in the art unless specifically defined herein or the context of their use clearly implies otherwise. It should be noted that element names and symbols are used interchangeably in this document (e.g., Si versus silicon); however, they have the same meaning. As will be discussed, various examples of an image sensor readout circuit are disclosed in which analog image signals and phase-detection autofocus signals from a pixel array are extracted via row bit lines of an image sensor and stored in a row arithmetic logic unit (ALU). In various examples, it will be appreciated that digital power consumption is reduced by the row ALU in accordance with the teachings of the present invention by extracting the phase-detection autofocus signals and then storing them locally in latches contained within the row ALU rather than in an image signal processor (ISP) external to the row ALU. In addition, in various embodiments, image sensing and phase detection autofocus signals can be read out from the image sensor via correlated double sampling (CDS) outputs and via dual conversion gains (e.g., high conversion gain and low conversion gain). In various embodiments, each row bit line of the pixel array is coupled to one of the inputs of a respective comparator. The other input of each comparator is coupled to receive a global ramp signal. The output of each comparator is coupled to a respective row ALU, which is configured to extract, store, and output digital or binary representations of the image signal and phase detection autofocus signal from the pixel array. In various embodiments, the normalized output (e.g., CDS output) generated by the row ALU can be based on a difference between one or more image signals or phase detection autofocus samples (e.g., a signal and a black signal or a reset signal) from the pixel array. According to the teachings of the present invention, in various examples, a common Gray code (GC) generator is used to generate GC outputs that are coupled to be received by each of the row ALUs to perform parallel analog-to-digital conversion (ADC) of the signals read out from the bit lines. For illustration, FIG1 shows an example of an imaging system 100 including a pixel array 102 having image sensing and phase detection autofocus (PDAF) pixels and a readout circuit 106 including a row arithmetic logic unit (ALU) for extracting and storing various signals in accordance with the teachings of the present invention. In one example, in accordance with an embodiment of the present invention, analog image signals and phase detection autofocus (PDAF) signals are read out in parallel to readout circuit 106 via row bit lines 112. As will be discussed in greater detail below, in accordance with the teachings of the present invention, in various examples, readout circuit 106 includes circuitry for performing analog-to-digital conversion (ADC) of image and PDAF data from pixel array 102, including parallel row ALUs and a shared Gray code (GC) generator for correlated double sampling (CDS) and / or dual conversion gain (DCG) processing. Specifically, the example depicted in FIG1 shows an imaging system 100 including a pixel array 102, control circuitry 110, readout circuitry 106, and function logic 108. In one example, pixel array 102 comprises a two-dimensional (2D) array of a plurality of pixel circuits 104, each of which includes photodiodes (e.g., P1, P2, ..., Pn). In various examples, photodiodes P1, P2, ..., Pn include photodiodes configured to provide image data and photodiodes configured to provide PDAF data. In various examples, the photodiodes configured to provide PDAF data may be interspersed among the photodiodes configured to provide image data. As shown in the depicted example, pixel circuits 104 are arranged into rows (e.g., R1 through Ry) and columns (e.g., C1 through Cx) to capture image data and / or PDAF data of a person, location, object, etc., which can then be used to reconstruct an image of the person, location, object, etc. In one embodiment, each pixel circuit 104 is configured to photogenerate an image and / or PDAF charge in response to incident light. After each pixel circuit 104 captures its image and / or PDAF charge, the corresponding analog image and / or PDAF charge data is read out by readout circuitry 106 via row bit lines 112. In various embodiments, the image and / or PDAF charge data from each column of pixel circuits 104 is read out in parallel by readout circuitry 106 via row bit lines 112. In accordance with the teachings of the present invention, in various embodiments, the analog image charge signal and / or PDAF charge signal is converted into a digital value, which is then transmitted to function logic 108. In various embodiments, analog-to-digital conversion is performed using parallel ALUs and a shared Gray code generator included in readout circuitry 106. In various embodiments, the parallel ALUs included in readout circuitry 106 can be configured to extract image signals and PDAF signals and perform correlated double sampling (CDS) processing by taking the difference between one or more signal level samples and one or more black level samples from each of a plurality of pixel circuits 104 in pixel array 102. In various embodiments, the extracted image signals and the extracted PDAF signals can be stored locally in the row ALUs in readout circuitry 106 and then output to image signal processing. In various embodiments, function logic 108 can store image data and phase detection autofocus data or even manipulate the image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or other). FIG2 illustrates an example of a portion of a readout circuit including a row analog-to-digital converter having a Gray code generator and parallel row ALUs for extracting and storing various signals in accordance with the teachings of the present invention. It should be understood that readout circuit 206 of FIG2 may be an example of readout circuit 106 of image sensor 100 shown in FIG1 , and that similarly named and numbered elements are similarly coupled and operate hereinafter. As shown in the example depicted in FIG. 2 , a portion of the readout circuitry 206 includes a plurality of comparators 216. Each of the plurality of comparators 216 is coupled to receive a ramp signal 214, which in one example is a global ramp signal. Each of the plurality of comparators 216 is further coupled to a respective one of a plurality of row bit lines 212 from an image sensor to receive a respective analog image or PDAF data signal from a row of the image sensor. As shown in the example, the outputs of the plurality of comparators 216 are coupled in parallel to respective row ALUs 218. Each of the plurality of ALUs 218 is also coupled to receive a Gray code (GC) output 222 generated by a common Gray code (GC) generator 220, as shown. In one example, the GC output 222 generated by the GC generator 220 is a phase-aligned 13-bit Gray code signal. In operation, each of the plurality of comparators 216 is coupled to generate a respective comparator output in response to comparing a respective analog image or PDAF data signal received from a respective bit line 212 with one of the ramp signals 214. In one example, a falling edge occurs at the output of the respective comparator 216 when the voltage of the ramp signal 214 ramps down to a value equal to or less than the voltage of the analog image or PDAF data signal carried by the respective row bit line 212. In one example, each respective row ALU 218 is coupled to sample and hold or latch a 13-bit Gray code signal 222 received from the GC generator 220 when a falling edge occurs at the output of the respective comparator 216 coupled to the respective row ALU 218. In various examples, each row ALU 218 is then configured to perform Gray code to binary code conversion on the latched GC code signal 222. In various embodiments, row ALU 218 is configured to extract an image signal and a PDAF signal and store the signals locally within the row ALU. By extracting and storing the PDAF signal locally within row ALU 218 rather than storing it in an image signal processor external to row ALU 218, it will be appreciated that digital power consumption is reduced in accordance with the teachings of the present invention. In various embodiments, row ALU 218 can also be coupled to concurrently perform a correlated double sampling (CDS) operation in accordance with the teachings of the present invention by determining a difference between one or more sample and hold reset (SHR) values ​​(also referred to herein as black level samples) and one or more sample and hold signal (SHS) samples (also referred to herein as signal level samples) from respective row bit lines 212 to generate a normalized digital image signal or PDAF data from the image sensor. In one example, the digital image or PDAF signal data extracted and stored within the row ALU 218 may then be output to respective global read bit lines of the readout circuitry 206 . In one example, the portion of readout circuitry 206 shown in FIG2 may be one of multiple portions of readout circuitry 206 that are repeated or "stitched together" across rows of an image sensor array. In the example shown in FIG2 , the image signal output from row ALU 218 may thus be relayed from "right" to "left" through row ALUs 218 of each portion of readout circuitry 206, with shift register readouts 224 coupled to the first and last rows and interspersed between every N rows of the image sensor array to read out image or PDAF data from the image sensor array. For example, in an example of a 48-megapixel sensor array, there are 8,000 rows. In this example, a single GC generator 220 can be shared between every N=500 rows of the sensor array, so that a total of 16x portions of one of the readout circuits 206 shown in FIG2 are included with shift register readouts 224 coupled to the first and last rows and interspersed between every 500 rows to read out image signal outputs from the sensor array. In other words, the shift register readouts 224 are coupled to respective ALUs 218 coupled to the first and last rows of the image sensor. Additionally, the shift registers 224 are coupled to and interspersed between the plurality of ALUs 218 of each of the plurality of readout circuits 206 to read out respective digital image data signals from the plurality of ALUs 218. FIG3A is a schematic diagram illustrating an example of a portion of an ALU 318 in accordance with the teachings of the present invention. It should be understood that the portion of ALU 318 depicted in FIG3A may be an example of one of the plurality of row ALUs 218 shown in FIG2 , and that similarly named and numbered elements described above are similarly coupled and operate hereinafter. It should also be understood that the portion of ALU 318 depicted in FIG3A illustrates circuitry for processing one of the bits of an ALU 318. For example, in various examples, it should be noted that each of the plurality of ALUs 318 is coupled to sample and hold or latch a corresponding bit of a received 12-bit Gray code q_gc<11:0> 322 in response to a falling edge at comparator output cmpout 350 to perform analog-to-digital conversion by converting the latched 12-bit Gray code q_gc<11:0> 322 into a binary value. 3A includes a front-end latch stage 326 coupled to receive and latch a respective bit of the Gray code q_gc<11:0> 322 signal in response to the comparator output cmpout 350. In the illustrated example, each latch of the front-end latch stage 326 has a data input "D" coupled to receive a respective bit of the Gray code q_gc<11:0>. In one example, ALU 318 also includes a pulse generator 344 coupled to receive comparator output cmpout 350 from its respective comparator (e.g., comparator 216). In one example, pulse generator 344 is coupled to generate a front-end latch enable signal 352 in response to a falling edge at comparator output cmpout 350. In one example, a pulse of front-end latch enable signal 352 is coupled to an enable input of each latch of front-end latch stage 326. In the depicted example, ALU 318 also includes a signaling latch stage 328 coupled to the output of front-end latch stage 326. In operation, signaling latch stage 328 is coupled to latch the output of front-end latch stage 326 in response to a signaling latch enable signal wen_sig 354. As shown in the depicted example, each latch of signaling latch stage 328 includes a data input "D" coupled to the "Q" output of a respective one of the latches of front-end latch stage 326. 3A shows that ALU 318 also includes a GC-to-binary stage (e.g., G2B) 330 coupled to generate a binary representation of the Gray code q_gc<0> 322 signal value latched in front latch stage 326. In one example, GC-to-binary stage 330 includes a plurality of XOR gates (not shown), each of which has an output coupled to generate a corresponding binary bit and a first input coupled to receive a respective “Q” output of a respective latch of signal latch stage 328. 3A , the ALU 318 also includes an adder stage 336 comprising a plurality of full adders, each of the plurality of full adders having a first input coupled to an output of the GC-to-binary stage 330 and a second input coupled to an output of an adder input multiplexer stage 334, as described in greater detail below. In operation, the output of the adder stage 336 is generated in response to the first input from the GC-to-binary stage 330 and the second input from the adder input multiplexer stage 334. In one example, the output of the adder stage 336 is configured to determine the difference between the value received at the first input and the value received at the second input of the adder stage 336. 3A , the ALU 318 further includes an adder input latch stage 332 coupled to latch GC to the output of the binary stage 330. In one example, the adder input latch stage 332 includes a first adder input latch 332A configured to latch GC to the output of the binary stage 330 in response to a first adder input latch enable signal wen_1st 356A. In one example, the adder input stage 332 includes a second adder input latch 332B configured to latch GC to the output of the binary stage 330 in response to a second adder input latch enable signal wen_2nd 356B. In the depicted example, a first input of adder input multiplexer stage 334 is coupled to receive the output of first adder input latch 332A, and a second input of adder input multiplexer stage 334 is coupled to receive the output of second adder input latch 332B. In operation, a second input of adder stage 336 is coupled to receive the output of either first adder input latch 332A or second adder input latch 332B via the output of adder input multiplexer stage 334. 3A shows that ALU 318 also includes one data latch stage 340 coupled to latch the output of adder stage 336. As shown in the depicted example, data latch stage 340 includes a first data latch 340A, a second data latch 340B, and a third data latch 340C. As will be discussed in the depicted example, the first data latch 340A is configured to latch a first phase detection signal (e.g., cdssigL) from the output of the adder stage 336 in response to a first data latch enable signal wwl_PDL 364A, the second data latch 340B is configured to latch a second phase detection signal (e.g., cdssigR) from the output of the adder stage 336 in response to a second data latch enable signal wwl_PDR 364B, and the third data latch 340C is configured to latch a first summed data signal (e.g., cdssigLR) from the output of the adder stage 336 in response to a third data latch enable signal wwl_sum 364C. In various examples, it should be understood that the data latch stage 340 includes a PDAF data storage latch 345 coupled to latch PDAF data and an image storage latch 346 coupled to latch image signal data. In the example, the PDAF data storage latch 345 includes a first data latch 340A and a second data latch 340B, and the image storage latch 346 includes a third data latch 340C. As previously discussed, in various examples, it should be understood that a pixel array (e.g., pixel array 102) includes pixels (e.g., pixel 104) that include PDAF pixels interspersed among image sensing pixels. Thus, there are more image sensing pixels than PDAF pixels. Consequently, there are more third data latches 340C in image storage latch 346 than there are first data latches 340A and second data latches 340B in PDAF data storage latch 345. In one example, data latch stage 340 includes three first data latches 340A and three second data latches 340B for every twelve third data latches 340C. For illustration purposes, the example depicted in FIG3A shows a data latch stage 340 with a first data latch 340A of 3 bits, a second data latch 340B of 3 bits, and a third data latch 340C of 3 bits x 4. In this example, the data itself is 12 bits and grouped into 4x3 bits, which illustrates the storage distribution. In the example of a 4-row array with a 4x8 pixel region of a pixel array (e.g., pixel array 102), the storage provided by data latches 340 for the top four analog-to-digital converters includes 4x3 bits of image signal data provided by third data latch 340C, plus 3 bits of PDAF "left" data provided by first data latch 340A, plus 3 bits of PDAF "right" data provided by second data latch 340B. In other words, it should be understood that the PDAF data storage latch 345 can be shared among multiple rows of a pixel array (eg, pixel array 102 ). FIG3B illustrates an example of the timing of various analog-to-digital conversion (ADC) operations and storage of extracted signals in the example arithmetic logic unit 318 of FIG3A according to the teachings of the present invention. Specifically, FIG3B shows a sequence of three ADC operations, including a first ADC operation 349A, a second ADC operation 349B, and a third ADC operation 349C. In this example, the second ADC operation 349B occurs after the first ADC operation 349A, and the third ADC operation 349C occurs after the second ADC operation 349B. In this example, an ADC operation of a black signal (e.g., blk) occurs during the first ADC operation 349A. Thus, after the first ADC operation 349A is completed and before the second ADC operation 349B begins, the Gray code representation q_gc<11:0> 322 of the black signal (e.g., blk) is latched in the signal latch stage 328 and the binary representation of the black signal (e.g., blk) is latched in the first adder input latch 332A of the adder input latch stage 332 in response to the first adder input latch enable signal wen_1st 356A. During the second ADC operation 349B, an ADC operation of a left signal (e.g., sigL) occurs. Thus, after the second ADC operation 349B is completed and before the third ADC operation 349C begins, the Gray code representation q_gc<11:0> 322 of the left signal (e.g., sigL) is latched in the signal latch stage 328, and the binary representation of the left signal (e.g., sigL) is latched in the second adder input latch 332B of the adder input latch stage 332 in response to the second adder input latch enable signal wen_2nd 356B. Additionally, the binary representation of the left signal (e.g., sigL) is also received by the first input of the adder stage 336. In an example, the adder input multiplexer stage 334 is configured such that the black signal (e.g., blk) latched in the first adder input latch 332A is coupled to be received by the second input of the adder stage 336 through the first input of the adder input multiplexer stage 334. Thus, when the left signal (e.g., sigL) is at the first input of the adder stage 336 and when the black signal (e.g., blk) is at the second input of the adder stage 336, a correlated double sampling (CDS) left signal (e.g., cdssigL) is coupled to be latched in the first data latch 340A of the data latch stage 340 through the output of the adder stage 336 in response to the first data latch enable signal wwl_PDL 364A. In an example, the CDS left signal (e.g., cdssigL) is equal to the difference between the first and second inputs of the adder stage 336 (e.g., sigL-blk). During the third ADC operation 349C, an ADC operation of a left-right signal (e.g., sigLR) occurs. Thus, during ADC operation 349C, a left-right signal is coupled to be latched in signal latch stage 328 and received by a first input of adder stage 336. Specifically, a Gray code representation q_gc<11:0> 322 of the left-right signal (e.g., sigLR) is latched in signal latch stage 328, and a binary representation of the left-right signal (e.g., sigLR) is coupled to be received by a first input of adder stage 336. In this example, adder input multiplexer stage 334 is configured such that the left signal (e.g., sigL) latched in second adder input latch 332B is coupled to be received by a second input of adder stage 336 via a second input of adder input multiplexer stage 334. Thus, when the left-right signal (e.g., sigLR) is at the first input of adder stage 336 and when the left signal (e.g., sigL) is at the second input of adder stage 336, a CDS right signal (e.g., cdssigR) is coupled in response to the second data latch enable signal wwl_PDR 364B and latched in the second data latch 340B of data latch stage 340 via the output of adder stage 336. In this example, the CDS right signal (e.g., cdssigR) is equal to the difference between the first and second inputs of adder stage 336 (e.g., sigLR−sigL). Continuing with the third ADC operation 349C, after the CDS right signal (e.g., cdssigR) is latched in the second data latch 340B, the adder input multiplexer stage 334 is configured such that the black signal (e.g., blk) latched in the first adder input latch 332A is coupled to be received by the second input of the adder stage 336 through the first input of the adder input multiplexer stage 334. Thus, when the left-right signal (e.g., sigLR) is at the first input of the adder stage 336 and when the black signal (e.g., blk) is at the second input of the adder stage 336, a CDS left-right signal (e.g., cdssigLR) is coupled to be latched in the third data latch 340C of the data latch stage 340 through the output of the adder stage 336 in response to the third data latch enable signal wwl_sum 364C. In an example, the CDS left-right signal (eg, cdssigLR) is equal to the difference between the first and second inputs of adder stage 336 (eg, sigLR-blk). In various examples, it should be understood that the CDS left signal (e.g., cdssigL) latched in the first data latch 340A, the CDS right signal (e.g., cdssigR) latched in the second data latch 340B, and the CDS left-right signal (e.g., cdssigLR) latched in the third data latch 340C can be output from the ALU 318 as output bits rbl<11:0> 347 through output switches rwl_pdl 343A, rwl_pdr 343B, and rwl_cdssig 343C, respectively, as shown. FIG4A is a schematic diagram illustrating another example of a portion of one of a plurality of ALUs 418 in accordance with the teachings of the present invention. It should be understood that the portion of ALU 418 depicted in FIG4A may be another example of one of the plurality of row ALUs 218 shown in FIG2 , and that similarly named and numbered elements are similarly coupled and operate hereinafter. It should also be understood that the portion of ALU 418 depicted in FIG4A shares many similarities with ALU 318 depicted in FIG3A . For example, in various examples, it should be noted that each of the plurality of ALUs 418 is coupled to sample and hold or latch a corresponding bit of a received 12-bit Gray code q_gc<11:0> 422 in response to a falling edge at comparator output cmpout 450 to perform analog-to-digital conversion by converting the latched 12-bit Gray code q_gc<11:0> 422 into a binary value. As shown in the depicted example, ALU 418 includes a front-end latch stage 426 coupled to receive and latch a respective bit of the Gray code q_gc<11:0> 422 signal in response to comparator output cmpout 450. In the depicted example, each latch of front-end latch stage 426 has a data input "D" coupled to receive a respective bit of the Gray code q_gc<11:0>. In one example, the ALU 418 also includes a pulse generator 444 coupled to receive the comparator output cmpout 450 from its respective comparator (e.g., comparator 216). In one example, the pulse generator 444 is coupled to generate a front-end latch enable signal 452 in response to a falling edge at the comparator output cmpout 450. In one example, the pulse of the front-end latch enable signal 452 is coupled to an enable input of each latch of the front-end latch stage 426. In the depicted example, ALU 418 also includes a signaling latch stage 428 coupled to the output of front-end latch stage 426. In operation, signaling latch stage 428 is coupled to latch the output of front-end latch stage 426 in response to a signaling latch enable signal wen_sig 454. As shown in the depicted example, each latch of signaling latch stage 428 includes a data input "D" coupled to the "Q" output of a respective one of the latches of front-end latch stage 426. 4A shows that ALU 418 also includes a GC-to-binary stage (e.g., G2B) 430 coupled to generate a binary representation of the Gray code q_gc<0> 422 signal value latched in front latch stage 426. In one example, GC-to-binary stage 430 includes a plurality of exclusive-OR gates (not shown), each of which has an output coupled to generate a corresponding binary bit and a first input coupled to receive a respective “Q” output of a respective latch of signal latch stage 428. 4A , the ALU 418 also includes an adder stage 436 comprising a plurality of full adders, each of the plurality of full adders having a first input coupled to an output of the GC-to-binary stage 430 and a second input coupled to an output of an adder input multiplexer stage 434, as described in greater detail below. In operation, the output of the adder stage 436 is generated in response to the first input from the GC-to-binary stage 430 and the second input from the adder input multiplexer stage 434. In one example, the output of the adder stage 436 is configured to determine the difference between the value received at the first input and the value received at the second input of the adder stage 436. One difference between the ALU 418 of FIG4A and the ALU 318 of FIG3A is that the ALU 418 of FIG4A also includes a feedback multiplexer stage 451. As shown in the example depicted in FIG4A, the feedback multiplexer stage 451 includes a first feedback multiplexer 451A having a first input coupled to the output of the GC to binary stage 430 and a second input coupled to the output of the adder stage 436. As shown, the feedback multiplexer stage 451 also includes a second feedback multiplexer 451B having a first input coupled to the output of the GC to binary stage 430 and a second input coupled to the output of the adder stage 436. 4A , the ALU 418 further includes an adder input latch stage 432 coupled to latch GC to the output of the binary stage 430 or the output of the adder stage 436 via the feedback multiplexer stage 451. In one example, the adder input latch stage 432 includes a first adder input latch 422A configured to latch GC to the output of the binary stage 430 or the adder stage 436 in response to a first adder input latch enable signal wen_1st 456A. ​​In one example, the adder input stage 432 also includes a second adder input latch 432B configured to latch GC to the output of the binary stage 430 or the adder stage 436 in response to a second adder input latch enable signal wen_2nd 456B. In the depicted example, a first input of adder input multiplexer stage 434 is coupled to receive the output of first adder input latch 432A, and a second input of adder input multiplexer stage 434 is coupled to receive the output of second adder input latch 432B. In operation, a second input of adder stage 436 is coupled to receive the output of either first adder input latch 432A or second adder input latch 432B via the output of adder input multiplexer stage 434. The example in Figure 4A shows that ALU 418 also includes a data latch stage 440 coupled to latch the output of adder stage 436. It should be appreciated that data latch stage 440 of Figure 4A shares many similarities with data latch stage 340 of Figure 3A. For example, as shown in the example depicted in Figure 4A, data latch stage 440 includes a first data latch 440A, a second data latch 440B, and a third data latch 440C. In the example, the first data latch 440A is configured to latch a first phase detection signal (e.g., cdssigL) from the output of the adder stage 436 in response to a first data latch enable signal wwl_PDL 464A, the second data latch 440B is configured to latch a second phase detection signal (e.g., cdssigR) from the output of the adder stage 436 in response to a second data latch enable signal wwl_PDR 464B, and the third data latch 440C is configured to latch a first summed data signal (e.g., cdssigL+cdssigR) from the output of the adder stage 436 in response to a third data latch enable signal wwl_sum 464C. In various examples, it should be understood that the data latch stage 440 includes a PDAF data storage latch 445 coupled to latch PDAF data and an image storage latch 446 coupled to latch image signal data. In this example, the PDAF data storage latch 445 includes a first data latch 440A and a second data latch 440B, and the image storage latch 446 includes a third data latch 440C. In the depicted example, it should be appreciated that there are more third data latches 440C in image storage latch 446 than first data latches 440A and second data latches 440B in PDAF data storage latch 445. In one example, data latch stage 440 includes three first data latches 440A and three second data latches 440B for every twelve third data latches 440C. Similar to the example depicted in FIG3A , the example depicted in FIG4A shows that data latch stage 440 includes a first data latch 440A of 3 bits, a second data latch 440B of 3 bits, and a third data latch 440C of 3 bits x 4. In this example, the data itself is 12 bits and grouped into 4x3 bits, which depicts the storage distribution. In the example of a 4-row array with a 4x8 pixel region of a pixel array (e.g., pixel array 102), for the top four analog-to-digital converters, the storage provided by data latches 440 includes 4x3 bits of image signal data provided by third data latch 440C, plus 3 bits of PDAF "left" data provided by first data latch 440A, plus 3 bits of PDAF "right" data provided by second data latch 440B. In other words, it should be understood that the PDAF data storage latch 445 can be shared among multiple rows of a pixel array (eg, pixel array 102 ). FIG4B illustrates another example of the timing of analog-to-digital conversion (ADC) operations and storage of various extracted signals in the example arithmetic logic unit 418 of FIG4A according to the teachings of the present invention. Specifically, FIG4B shows a sequence of four ADC operations, including a first ADC operation 449A, a second ADC operation 449B, a third ADC operation 449C, and a fourth ADC operation 449D. In this example, the second ADC operation 449B occurs after the first ADC operation 449A, the third ADC operation 449C occurs after the second ADC operation 449B, and the fourth ADC operation 449D occurs after the third ADC operation 449C. In this example, an ADC operation of a left black signal (e.g., blkL) occurs during the first ADC operation 449A. Thus, after the first ADC operation 449A is completed and before the second ADC operation 449B begins, the Gray code representation q_gc<11:0> 422 of the left black signal (e.g., blkL) is latched in the signal latch stage 428 and the binary representation of the black signal (e.g., blkL) is latched in the first adder input latch 432A of the adder input latch stage 432 via the first input of the first feedback multiplexer 451A and in response to the first adder input latch enable signal wen_1st 456A. During the second ADC operation 449B, an ADC operation of a left signal (e.g., sigL) occurs. Thus, after the second ADC operation 449B is completed and before the third ADC operation 449C begins, the Gray code representation q_gc<11:0> 422 of the left signal (e.g., sigL) is latched in the signal latch stage 428 and the binary representation of the left signal (e.g., sigL) is coupled to be received at the first input of the adder stage 436. In this example, the adder input multiplexer stage 434 is configured such that the left black signal (e.g., blkL) latched in the first adder input latch 432A is coupled to be received by the second input of the adder stage 436 through the first input of the adder input multiplexer stage 434. Thus, when the left signal (e.g., sigL) is at the first input of adder stage 436 and when the left black signal (e.g., blkL) is at the second input of adder stage 436, a correlated double sampling (CDS) left signal (e.g., cdssigL) is coupled in response to the first data latch enable signal wwl_PDL 464A and latched in the first data latch 440A of the data latch stage 440 via the output of adder stage 436. In this example, the CDS left signal (e.g., cdssigL) is equal to the difference between the first and second inputs of adder stage 436 (e.g., sigL-blkL). In addition, the CDS left signal (eg, cdssigL) is also latched in the second adder input latch 432B of the adder input latch stage 432 in response to the second adder input latch enable signal wen_2nd 456B via the second input of the second feedback multiplexer 451B. During the third ADC operation 449C, an ADC operation of a right black signal (e.g., blkR) occurs. Thus, during ADC operation 449C, a right black signal is coupled to be latched in signal latch stage 428 and received by a first input of adder stage 436. Specifically, a Gray code representation q_gc<11:0> 422 of the right black signal (e.g., blkR) is latched in signal latch stage 428, and a binary representation of the right black signal (e.g., blkR) is coupled to be received by a first input of adder stage 436. In this example, adder input multiplexer stage 434 is configured such that the CDS left signal (e.g., cdssigL) latched in second adder input latch 432B is coupled to be received by a second input of adder stage 436 via a second input of adder input multiplexer stage 434. Thus, when the right black signal (e.g., blkR) is at the first input of the adder stage 436 and when the CDS left signal (e.g., cdssigL) is at the second input of the adder stage 436, a difference between the right black signal and the CDS left signal (e.g., blkR-cdssigL) is coupled in response to the second data latch enable signal wwl_PDR 464B and is latched in the first data latch 440A of the data latch stage 440 through the output of the adder stage 436 and through the second input of the first feedback multiplexer 451A. Continuing with the third ADC operation 449C, after the difference between the right black signal and the CDS left signal (e.g., blkR−cdssigL) is latched in the first adder input latch 432A, the right black signal (e.g., blkR) is latched in the second adder input latch 432B via the first input of the second feedback multiplexer 451B. During the fourth ADC operation 449D, an ADC operation of a right signal occurs. Thus, during ADC operation 449D, a right signal (e.g., sigR) is coupled to be latched in signal latch stage 428 and received by a first input of adder stage 436. Specifically, a Gray code representation q_gc<11:0> 422 of the right signal (e.g., sigR) is latched in signal latch stage 428, and a binary representation of the right signal (e.g., sigR) is coupled to be received by a first input of adder stage 436. In this example, adder input multiplexer stage 434 is configured such that the difference between the right black signal and the CDS left signal (e.g., blkR−cdssigL), latched in first adder input latch 432A, is coupled to be received by a second input of adder stage 436 via a first input of adder input multiplexer stage 434. Thus, when the right signal (e.g., sigR) is at the first input of the adder stage 436 and when the difference between the right black signal and the CDS left signal (e.g., blkR-cdssigL) is at the second input of the adder stage 436, a difference between the right signal (e.g., sigR) and the difference between the right black signal and the CDS left signal (e.g., blkR-cdssigL) (which is equal to sigR-(blkR-cdssigL), which is equal to a CDS left-right signal (e.g., cdssigL+cdssigR)) is coupled to be latched in the third data latch 440C of the data latch stage 440 through the output of the adder stage 436. Continuing with the fourth ADC operation 449D, after the CDS left-right signal (e.g., cdssigL+cdssigR) is latched in the third data latch 440C, the right black signal (e.g., blkR) latched in the second adder input latch 432B is coupled to be received at the second input of the adder stage 436 via the second input of the adder input multiplexer stage 434. Thus, when the right signal (e.g., sigR) is at the first input of the adder stage 436 and when the right black signal (e.g., blkR) is at the second input of the adder stage 436, a difference between the right signal and the right black signal (e.g., sigR-blkR), which is equal to a CDS right signal (e.g., cdssigR), is coupled to be latched in the second data latch 440B of the data latch stage 440 via the output of the adder stage 436. In various examples, it should be understood that the CDS left signal (e.g., cdssigL) latched in the first data latch 440A, the CDS right signal (e.g., cdssigR) latched in the second data latch 440B, and the CDS left-right signal (e.g., cdssigL+cdssigR) latched in the third data latch 440C can be output from the ALU 418 as output bits rbl<11:0> 447 through output switches rwl_pdl 443A, rwl_pdr 443B, and rwl_cdssig 443C, respectively, as shown. FIG5A is a schematic diagram illustrating another example of a portion of one of a plurality of ALUs 518 in accordance with the teachings of the present invention. It should be understood that the portion of ALU 518 depicted in FIG5A may be another example of one of the plurality of row ALUs 218 shown in FIG2 , and that similarly named and numbered elements are similarly coupled and operate hereinafter. It should also be understood that the portion of ALU 518 depicted in FIG5A shares many similarities with portions of ALU 418 depicted in FIG4A and / or with ALU 318 depicted in FIG3A . For example, in various examples, it should be noted that each of the plurality of ALUs 518 is coupled to sample and hold or latch a corresponding bit of a received 12-bit Gray code q_gc<11:0> 522 in response to a falling edge arriving at the comparator output cmpout 550 to perform analog-to-digital conversion by converting the latched 12-bit Gray code q_gc<11:0> 522 into a binary value. As shown in the depicted example, ALU 518 includes a front-end latch stage 526 coupled to receive and latch a respective bit of the Gray code q_gc<11:0> 522 signal in response to comparator output cmpout 550. In the depicted example, each latch of front-end latch stage 526 has a data input "D" coupled to receive a respective bit of the Gray code q_gc<11:0>. In one example, the ALU 518 also includes a pulse generator 544 coupled to receive the comparator output cmpout 550 from its respective comparator (e.g., comparator 216). In one example, the pulse generator 544 is coupled to generate a front-end latch enable signal 552 in response to a falling edge at the comparator output cmpout 550. In one example, the pulse of the front-end latch enable signal 552 is coupled to an enable input of each latch of the front-end latch stage 526. In the depicted example, ALU 518 also includes a signaling latch stage 528 coupled to the output of the front-end latch stage 526. In operation, signaling latch stage 528 is coupled to latch the output of the front-end latch stage 526 in response to a signaling latch enable signal wen_sig 554. As shown in the depicted example, each latch of signaling latch stage 528 includes a data input "D" coupled to the "Q" output of a respective one of the latches of the front-end latch stage 526. 5A shows that ALU 518 also includes a GC-to-binary stage (e.g., G2B) 530 coupled to generate a binary representation of the Gray code q_gc<0> 522 signal value latched in front-end latch stage 526. In one example, GC-to-binary stage 530 includes a plurality of XOR gates (not shown), each of which has an output coupled to generate a corresponding binary bit and an input coupled to receive a respective “Q” output of a respective latch of signal latch stage 528. 5A , the ALU 518 also includes an adder stage 536 comprising a plurality of full adders, each of the plurality of full adders having a first input coupled to an output of the GC-to-binary stage 530 and a second input coupled to an output of an adder input multiplexer stage 534, as described in greater detail below. In operation, the output of the adder stage 536 is generated in response to the first input from the GC-to-binary stage 530 and the second input from the adder input multiplexer stage 534. In one example, the output of the adder stage 536 is configured to determine the difference between the value received at the first input and the value received at the second input of the adder stage 536. 5A , ALU 518 further includes an adder input latch stage 532 coupled to latch GC to the output of binary stage 530. One difference between ALU 518 of FIG5A and ALU 318 of FIG3A is that adder input latch stage 532 of FIG5A includes three adder input latches. For example, as shown in the example depicted in FIG5A , the adder input latch stage 532 includes a first adder input latch 532A configured to latch GC to the output of the binary stage 530 in response to a first adder input latch enable signal wen_1st 556A; a second adder input latch 532B configured to latch GC to the output of the binary stage 530 in response to a second adder input latch enable signal wen_2nd 556B; and a third adder input latch 532C configured to latch GC to the output of the binary stage 530 in response to a third adder input latch enable signal wen_3rd 556C. In the depicted example, a first input of adder input multiplexer stage 534 is coupled to receive the output of first adder input latch 532A, a second input of adder input multiplexer stage 534 is coupled to receive the output of second adder input latch 532B, and a third input of adder input multiplexer stage 534 is coupled to receive the output of third adder input latch 532C. In operation, a second input of adder stage 536 is coupled to receive the output of one of first adder input latch 532A, second adder input latch 532B, or third adder input latch 532C via the output of adder input multiplexer stage 534. The example in FIG5A shows that ALU 518 also includes a data latch stage 540 coupled to latch the output of adder stage 536. It should be appreciated that data latch stage 540 of FIG5A also shares many similarities with data latch stage 440 of FIG4A and / or data latch stage 340 of FIG3A. For example, as shown in the example depicted in FIG5A, data latch stage 540 includes a first data latch 540A, a second data latch 540B, and a third data latch 540C. One difference between data latch stage 540 of FIG5A and data latch stage 440 of FIG4A or data latch stage 340 of FIG3A is that data latch stage 540 of FIG5A further includes a fourth data latch 540D. In this example, the first data latch 540A is configured to latch a high conversion gain (HCG) CDS left signal (e.g., HCGcdssigL) from the output of the adder stage 536 in response to a first data latch enable signal wwl_PDL 564A, the second data latch 540B is configured to latch a HCG CDS right signal (e.g., HCGcdssigR) from the output of the adder stage 536 in response to a second data latch enable signal wwl_PDR 564B, the third data latch 540C is configured to latch a HCG CDS left-right signal (e.g., HCGcdsLR) from the output of the adder stage 536 in response to a third data latch enable signal wwl_hcg 564C, and the fourth data latch 540D is configured to latch a fourth data latch enable signal wwl_lcg 564D latches the LCG CDS left-right signal (eg, LCGcdsLR) from the output of adder stage 536. In various examples, it should be understood that the data latch stage 540 includes a PDAF data storage latch 545 coupled to latch PDAF data and an image storage latch 546 coupled to latch image signal data. In the example, the PDAF data storage latch 545 includes a first data latch 540A and a second data latch 540B, and the image storage latch 546 includes a third data latch 540C and a fourth data latch 540D. In the depicted example, it should be understood that there are more third data latches 540C and fourth data latches 540D in image storage latch 546 than first data latches 540A and second data latches 540B in PDAF data storage latch 545. For example, in one example, data latch stage 540 includes three first data latches 540A or three second data latches 540B for every twelve third data latches 540C or every twelve fourth data latches 540D. In another example, data latch stage 540 includes three first data latches 540A and three second data latches 540B for every twelve third data latches 540C and every twelve fourth data latches 540D. Similar to the examples depicted in FIG3A and FIG4A , the example depicted in FIG5A shows that in data latch stage 540, there is a first data latch 540A of "3 bits", a second data latch 540B of "3 bits", a third data latch 540C of "3 bits x 4", and a fourth data latch 540D of "3 bits x 4". In this example, the data itself is 12 bits and is grouped into 4 x 3 bits, which illustrates the storage distribution. In an example of 8 rows with a 4x8 pixel region of a pixel array (e.g., pixel array 102), for 4 upper A / D converters plus 4 lower A / D converters, the storage provided by data latch 540 includes 4x3 bits provided by third data latch 540C or fourth data latch 540D plus 1x3 bits provided by first data latch 540A for HCG CDS left PDAF data or by second data latch 540B for HCG CDS right PDAF data. Therefore, it should be understood that PDAF data storage latch 545 can be shared among multiple rows of a pixel array (e.g., pixel array 102). FIG5B illustrates another example of the timing of analog-to-digital conversion and storage of various extracted signals in the example arithmetic logic unit 518 of FIG5A according to the teachings of the present invention. Specifically, FIG5B shows a sequence of five ADC operations, including a first ADC operation 549A, a second ADC operation 549B, a third ADC operation 549C, a fourth ADC operation 549D, and a fifth ADC operation 549E. In this example, the second ADC operation 549B occurs after the first ADC operation 549A, the third ADC operation 549C occurs after the second ADC operation 549B, the fourth ADC operation 549D occurs after the third ADC operation 549C, and the fifth ADC operation 549E occurs after the fourth ADC operation 549D. In this example, an ADC operation of a low conversion gain (LCG) black signal (e.g., LCGblk) occurs during a first ADC operation 549A. Thus, after the first ADC operation 549A is completed and before the second ADC operation 549B begins, a Gray code representation q_gc<11:0> 522 of the LCG black signal (e.g., LCGblk) is latched in the signal latch stage 528 and a binary representation of the LCG black signal (e.g., LCGblk) is latched in the first adder input latch 532A of the adder input latch stage 532 in response to the first adder input latch enable signal wen_1st 556A. During the second ADC operation 549B, an ADC operation of a high conversion gain (HCG) black signal (e.g., HCGblk) occurs. Thus, after the second ADC operation 549B is completed and before the third ADC operation 549C begins, the Gray code representation q_gc<11:0> 522 of the HCG black signal (e.g., HCGblk) is latched in the signal latch stage 528 and the binary representation of the HCG black signal (e.g., HCGblk) is latched in the second adder input latch 532B of the adder input latch stage 532 in response to the second adder input latch enable signal wen_2nd 556B. During the third ADC operation 549C, an ADC operation of a HCG left signal (e.g., HCGsigL) occurs. Thus, after the third ADC operation 549C is completed and before the fourth ADC operation 549D begins, the Gray code representation q_gc<11:0> 522 of the HCG left signal (e.g., HCGsigL) is latched in the signal latch stage 528 and the binary representation of the HCG left signal (e.g., HCGsigL) is latched in the third adder input latch 532C of the adder input latch stage 532 in response to the third adder input latch enable signal wen_3rd 556C and coupled to be received at the first input of the adder stage 536. In the example, the adder input multiplexer stage 534 is configured such that the HCG black signal (e.g., HCGblk) latched in the second adder input latch 532B is coupled to be received by the second input of the adder stage 536 through the second input of the adder input multiplexer stage 534. Thus, when the HCG left signal (e.g., HCGsigL) is at the first input of the adder stage 536 and when the HCG black signal (e.g., HCGblk) is at the second input of the adder stage 536, a HCG correlated double sampling (CDS) left signal (e.g., HCGcdsL) is coupled to be latched in the first data latch 540A of the data latch stage 540 through the output of the adder stage 536 in response to the first data latch enable signal wwl_PDL 564A. In an example, the HCG CDS left signal (eg, HCGcdsL) is equal to the difference between the first and second inputs of adder stage 536 (eg, HCGsigL−HCGblk). During the fourth ADC operation 549D, an ADC operation of a HCG left-right signal (e.g., HCGsigLR) occurs. Thus, during the fourth ADC operation 549D, a HCG left-right signal (e.g., HCGsigLR) is coupled to be latched in the signal latch stage 528 and received by the first input of the adder stage 536. Specifically, the Gray code representation q_gc<11:0> 522 of the HCG left-right signal (e.g., HCGsigLR) is latched in the signal latch stage 528 and the binary representation of the HCG left-right signal (e.g., HCGsigLR) is coupled to be received at the first input of the adder stage 536. In the example, the adder input multiplexer stage 534 is configured such that the HCG left signal (e.g., HCGsigL) latched in the third adder input latch 532C of the adder input latch stage 532 is coupled to be received by the second input of the adder stage 536 through the third input of the adder input multiplexer stage 534. Thus, when the HCG left-right signal (e.g., HCGsigLR) is at the first input of the adder stage 536 and when the HCG left signal (e.g., HCGsigL) is at the second input of the adder stage 536, a HCG correlated double sampling (CDS) right signal (e.g., HCGcdsR) is coupled to be latched in the second data latch 540B of the data latch stage 540 through the output of the adder stage 536 in response to the second data latch enable signal wwl_PDR 564B. In an example, the HCG CDS right signal (eg, HCGcdsR) is equal to the difference between the first and second inputs of the adder stage 536 (eg, HCGsigLR−HCGsigL). Continuing with the fourth ADC operation 549D, after the HCG CDS right signal (e.g., HCGcdsR) is latched in the second data latch 540B, the adder input multiplexer stage 534 is configured such that the HCG black signal (e.g., HCGblk) latched in the second adder input latch 532B is coupled to be received by the second input of the adder stage 536 through the second input of the adder input multiplexer stage 534. Thus, when the HCG left-right signal (e.g., HCGsigLR) is at the first input of the adder stage 536 and when the HCG black signal (e.g., HCGblk) is at the second input of the adder stage 536, a HCG correlated double sampling (CDS) left-right signal (e.g., HCGcdsLR) is coupled in response to the third data latch enable signal wwl_hcg 564C and latched in the third data latch 540C of the data latch stage 540 via the output of the adder stage 536. In this example, the HCG CDS left-right signal (e.g., HCGcdsLR) is equal to the difference between the first and second inputs of the adder stage 536 (HCGsigLR−HCGblk). During the fifth ADC operation 549E, an ADC operation of a low conversion gain (LCG) left-right signal (e.g., LCGsigLR) occurs. Thus, after the fifth ADC operation 549E is completed, the Gray code representation q_gc<11:0> 522 of the LCG left-right signal (e.g., LCGsigLR) is latched in the signal latch stage 528 and the binary representation of the LCG left-right signal (e.g., LCGsigLR) is coupled to be received at the first input of the adder stage 536. In this example, the adder input multiplexer stage 534 is configured such that the LCG black signal (e.g., LCGblk) latched in the first adder input latch 532A is coupled to be received by the second input of the adder stage 536 via the first input of the adder input multiplexer stage 534. Thus, when the LCG left-right signal (e.g., LCGsigLR) is at the first input of the adder stage 536 and when the LCG black signal (e.g., LCGblk) is at the second input of the adder stage 536, an LCG correlated double sampling (CDS) left-right signal (e.g., LCGcdsLR) is coupled in response to the fourth data latch enable signal wwl_lcg 564D and latched in the fourth data latch 540D of the data latch stage 540 via the output of the adder stage 536. In this example, the LCG CDS left-right signal (e.g., LCGcdsLR) is equal to the difference between the first and second inputs of the adder stage 536 (e.g., LCGsigLR−LCGblk). In various examples, it should be understood that the HCG CDS left signal (e.g., HCGcdsL) latched in the first data latch 540A, the HCG CDS right signal (e.g., HCGcdsR) latched in the second data latch 540B, the HCG CDS left-right signal (e.g., HCGcdsLR) latched in the third data latch 540C, and the LCG CDS left-right signal (e.g., LCGcdsLR) latched in the fourth data latch 540D can be output from the ALU 518 as output bits rbl<11:0> 547 through output switches rwl_pdl 543A, rwl_pdr 543B, rwl_cdssig_hcg 543C, and rwl_cdssig_lcg 543D, respectively, as shown. The above description of the examples shown in the embodiments (including the content described in the Abstract) is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Although specific examples of the embodiments are described herein for illustrative purposes, those skilled in the art will recognize that various modifications are possible within the scope of the embodiments. Such modifications may be made to the embodiments in light of the above detailed description. The terms used in the appended claims should not be construed to limit the embodiments to the specific examples disclosed in the specification. Rather, the scope of the embodiments is to be determined entirely by the appended claims, which are to be construed in accordance with established principles of claim interpretation. 100: Imaging System 102: Pixel Array 104: Pixel Circuit 106: Readout Circuit 108: Functional Logic 110: Control Circuit 112: Row Bit Line 206: Readout Circuit 212: Row Bit Line 214: Ramp Signal 216: Comparator 218: Row Arithmetic Logic Unit (ALU) 220: Gray Code (GC) Generator 222: GC Output 224: Shift Register Readout 318: ALU 322: 12-bit Gray Code q_gc<11:0> 326: Front-end latch stage 328: Signal latch stage 330: GC to binary stage 332: Adder input latch stage 332A: First adder input latch 332B: Second adder input latch 334: Adder input multiplexer stage 336: Adder stage 340: Data latch stage 340A: First data latch 340B: Second data latch 340C: Third data latch 343A: Output switch rwl_pdl 343B: Output switch rwl_pdr 343C: Output switch rwl_cdssig 344: Pulse generator 345: Phase detection autofocus (PDAF) data storage latch 346: Image storage latch 347: Output bits rbl<11:0> 349A: First analog-to-digital conversion (ADC) operation 349B: Second ADC operation 349C: Third ADC operation 350: Comparator output cmpout 352: Front-end latch enable signal 354: Signal latch enable signal wen_sig 356A: First adder input latch enable signal wen_1st 356B: Second adder input latch enable signal wen_2nd 364A: First data latch enable signal wwl_PDL 364B: Second data latch enable signal wwl_PDR 364C: Third data latch enable signal wwl_sum 418: ALU 422: 12-bit Gray code q_gc<11:0> 426: Front-end latch stage 428: Signal latch stage 430: GC to binary stage 432: Adder input latch stage 432A: First adder input latch 432B: Second adder input latch 434: Adder input multiplexer stage 436: Adder stage 440: Data latch stage 440A: First data latch 440B: Second data latch 440C: Third data latch 443A: Output switch rwl_pdl 443B: Output switch rwl_pdr 443C: Output switch rwl_cdssig 444: Pulse generator 445: PDAF data storage latch 446: Image storage latch 447: Output bits rbl<11:0> 449A: First ADC operation 449B: Second ADC operation449C: Third ADC operation 449D: Fourth ADC operation 450: Comparator output cmpout 451: Feedback multiplexer stage 451A: First feedback multiplexer 451B: Second feedback multiplexer 452: Front-end latch enable signal 454: Signal latch enable signal wen_sig 456A: First adder input latch enable signal wen_1st 456B: Second adder input latch enable signal wen_2nd 464A: First data latch enable signal wwl_PDL 464B: Second data latch enable signal wwl_PDR 464C: Third data latch enable signal wwl_sum 518: ALU 522: 12-bit Gray code q_gc<11:0> 526: Front-end latch stage 528: Signal latch stage 530: GC to binary stage 532: Adder input latch stage 532A: First adder input latch 532B: Second adder input latch 532C: Third adder input latch 534: Adder input multiplexer stage 536: Adder stage 540: Data latch stage 540A: First data latch 540B: ​​Second data latch 540C: Third data latch 540D: Fourth data latch 543A: Output switch rwl_pdl 543B: Output switch rwl_pdr 543C: Output switch rwl_cdssig_hcg 543D: Output switch rwl_cdssig_lcg 544: Pulse generator 545: PDAF data storage latch 546: Image storage latch 547: Output bit rbl<11:0> 549A: First ADC operation 549B: Second ADC operation 549C: Third ADC operation 549D: Fourth ADC operation 549E: Fifth ADC operation 550: Comparator output cmpout 552: Front-end latch enable signal 554: Signal latch enable signal wen_sig 556A: First adder input latch enable signal wen_1st 556B: Second adder input latch enable signal wen_2nd 556C: Third adder input latch enable signal wen_3rd 564A: First data latch enable signal wwl_PDL 564B: Second data latch enable signal wwl_PDR 564C: Third data latch enable signal wwl_hcg 564D: fourth data latch enable signal wwl_lcg blk: black signal blkL: left black signal blkR: right black signal cdssigL: first phase detection signal cdssigR: second phase detection signal C1 to Cx: column HCGblk: high conversion gain (HCG) black signal HCGcdsL: HCG CDS left-right signalHCGcdsLR: HCG CDS left-right signal HCGcdsR: HCG correlated double sampling (CDS) right signal HCGsigL: HCG left signal HCGsigLR: HCG left-right signal LCGblk: Low conversion gain (LCG) black signal LCGcdsLR: LCG CDS left-right signal LCGsigLR: Low conversion gain (LCG) left-right signal P1 to Pn: Photodiodes R1 to Ry: Columns sigL: Left signal sigLR: Left-right signal sigR: Right signal Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. 1 illustrates an example of an imaging system including a pixel array having image sensing and phase detection autofocus pixels and a readout circuit including row arithmetic logic units for extracting and storing various signals in accordance with the teachings of the present invention. 2 illustrates an example of a portion of a readout circuit including a row analog-to-digital converter having a Gray code generator and parallel row arithmetic logic units for extracting and storing various signals in accordance with the teachings of the present invention. 3A is a schematic diagram illustrating an example of a portion of one of a plurality of arithmetic logic units according to the teachings of the present invention. 3B illustrates an example of the timing of analog-to-digital conversion and storage of various extracted signals in an example arithmetic logic unit according to the teachings of the present invention. FIG. 4A is a schematic diagram illustrating another example of a portion of one of a plurality of arithmetic logic units according to the teachings of the present invention. 4B illustrates another example of the timing of analog-to-digital conversion and storage of various extracted signals in another example ALU according to the teachings of the present invention. FIG. 5A is a schematic diagram illustrating yet another example of a portion of one of a plurality of arithmetic logic units according to the teachings of the present invention. 5B illustrates yet another example of the timing of analog-to-digital conversion and storage of various extracted signals in yet another example arithmetic logic unit according to the teachings of the present invention. Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Those skilled in the art will appreciate that the elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to facilitate understanding of the various embodiments of the present invention. Additionally, common but well-known elements that are useful or necessary in a commercially feasible embodiment are often not depicted to facilitate an unobstructed view of one of the various embodiments of the present invention. 318: Arithmetic Logic Unit (ALU) 322:12-bit Gray code q_gc<11:0> 326:Front-end latch stage 328: Signal latch stage 330: Gray code (GC) to binary level 332: Adder input latch stage 332A: First adder input latch 332B: Second adder input latch 334: Adder input multiplexer stage 336: Adder stage 340: Data latch level 340A: First data latch 340B: Second data latch 340C: Third data latch 343A: output switch rwl_pdl 343B: output switch rwl_pdr 343C: output switch rwl_cdssig 344: Pulse Generator 345: Phase detection autofocus (PDAF) data storage latch 346: Image storage latch 347: Output bit rbl<11:0> 350: Comparator output cmpout 352: Front-end latch enable signal 354: Signal latch enable signal wen_sig 356A: First adder input latch enable signal wen_1st 356B: Second adder input latch enable signal wen_2nd 364A: First data latch enable signal wwl_PDL 364B: Second data latch enable signal wwl_PDR 364C: Third data latch enable signal wwl_sum

Claims

1. An arithmetic logic unit (ALU), comprising: A front-end latch stage coupled to a Gray code (GC) generator to latch the GC output of the GC generator in response to a comparator output; A latch stage coupled to latch the output of the front-end latch stage in response to a latch enable signal; a GC-to-binary stage coupled to generate a binary representation of the GC outputs latched in the latch stage; an adder stage including a first input and a second input, wherein the first input of the adder stage is coupled to receive the output of the GC-to-binary stage, wherein the output of the adder stage is generated in response to the first input and the second input of the adder stage; An adder input latch stage coupled to latch the outputs of the GC to the binary stage, wherein the adder input latch stage includes: a first adder input latch configured to latch the outputs of the GC to the binary stage in response to a first adder input latch enable signal; and a second adder input latch configured to latch the outputs of the GC to the binary stage in response to a second adder input latch enable signal; and an adder input multiplexer stage, wherein a first input of the adder input multiplexer stage is coupled to receive the outputs of the first adder input latches, wherein a second input of the adder input multiplexer stage is coupled to receive the outputs of the second adder input latches, and wherein the second inputs of the adder stage are coupled to receive the outputs of the adder input multiplexer stage.

2. The ALU of claim 1, further comprising a pulse generator coupled to the comparator output to generate a front-end latch enable signal in response to an analog-to-digital (ADC) operation on a signal from a pixel array, wherein the front-end latch stage is coupled to latch the GC outputs of the GC generator in response to the front-end latch enable signal.

3. The ALU of claim 2, further comprising a data latch stage coupled to latch the output of the adder stage, wherein the data latch stage includes: A first data latch, configured to latch a first phase detection signal from the outputs of the adder stage in response to a first data latch enable signal; a second data latch, configured to latch a second phase detection signal from the outputs of the adder stage in response to a second data latch enable signal; and a third data latch, configured to latch a first summing data signal from the outputs of the adder stage in response to a third data latch enable signal.

4. The ALU as requested in item 3, wherein the data latch level includes 3 first data latches and 3 second data latches configured for every 12 third data latches.

5. The ALU of claim 3, wherein the data latch stage further includes a fourth data latch configured to latch a second summing data signal from the outputs of the adder stage in response to a fourth data latch enable signal.

6. The ALU as requested in item 5, wherein the data latch level includes 3 first data latches or 3 second data latches configured for every 12 third data latches or every 12 fourth data latches.

7. The ALU of request item 5, wherein the data latch level includes 3 first data latches and 3 second data latches configured for every 12 third data latches and every 12 fourth data latches.

8. The ALU of claim 3, wherein the ADC operation comprises one of a sequence of ADC operations including a first ADC operation, wherein after the first ADC operation, a black signal is coupled to be latched in the signal latch stage and latched in the first adder input latches of the adder input latch stage.

9. The ALU of claim 8, wherein the ADC operation sequence further includes a second ADC operation occurring after the first ADC operation, wherein after the second ADC operation: a left signal is coupled to be latched in the signal latch stage, latched in the second adder input latches of the adder input latch stage, and received by the first inputs of the adder stage; the black signal is coupled to be received by the second inputs of the adder stage through the first inputs of the adder input multiplexer stage; and a correlated double sample (CDS) left signal is coupled to be latched in the first data latches of the data latch stage through the outputs of the adder stage.

10. The ALU of claim 9, wherein the ADC operation sequence further includes a third ADC operation occurring after the second ADC operation, wherein after the third ADC operation: a left-right signal is coupled to be latched in the signal latch stage and received by the first inputs of the adder stage; the left signal is coupled to be received by the second inputs of the adder stage through the second inputs of the adder input multiplexer stage; and a CDS right signal is coupled to be latched in the second data latches of the data latch stage through the outputs of the adder stage.

11. The ALU of claim 10, wherein after the CDS right signal is latched in the second data latches of the data latch stage: the left-right signal is coupled to be received by the first inputs of the adder stage, the black signal is coupled to be received by the second inputs of the adder stage through the first inputs of the adder input multiplexer stage, and a CDS left-right signal is coupled to be latched in the third data latches of the data latch stage through the outputs of the adder stage.

12. The ALU as described in request item 3, wherein the ALU further includes a feedback multiplexer stage, wherein the feedback multiplexer stage includes: A first feedback multiplexer has a first input coupled to the outputs of the GC-to-binary stage and a second input coupled to the outputs of the adder stage, wherein the first adder input latches are further configured to latch the outputs of the GC-to-binary stage or the outputs of the adder stage; and a second feedback multiplexer has a first input coupled to the outputs of the GC-to-binary stage and a second input coupled to the outputs of the adder stage, wherein the second adder input latches are further configured to latch the outputs of the GC-to-binary stage or the outputs of the adder stage.

13. The ALU of claim 12, wherein the ADC operation comprises one of a sequence of ADC operations including a first ADC operation, wherein after the first ADC operation, a left black signal is coupled to be latched in the signal latch stage and latched in the first adder input latches of the adder input latch stage through the first inputs of the first feedback multiplexers of the feedback multiplexer stage.

14. The ALU of claim 13, wherein the ADC operation sequence further includes a second ADC operation occurring after the first ADC operation, wherein after the second ADC operation: a left signal is coupled to be latched in the signal latch stage and received by the first inputs of the adder stage; the left black signal is coupled to be received by the second inputs of the adder stage through the first inputs of the adder input multiplexer stage; and a correlated double sample (CDS) left signal is coupled to be latched through the outputs of the adder stage into the first data latches of the data latch stage and through the second inputs of the second feedback multiplexers of the feedback multiplexer stage into the second adder input latches of the adder input latch stage.

15. The ALU of claim 14, wherein the ADC operation sequence further includes a third ADC operation occurring after the second ADC operation, wherein after the third ADC operation: a right black signal is coupled to be latched in the signal latch stage and received by the first inputs of the adder stage; the CDS left signal is coupled to be received by the second inputs of the adder stage through the second inputs of the adder input multiplexer stage; and a right black-CDS left difference signal is coupled to be latched in the first adder input latches of the adder input latch stage through the second inputs of the first feedback multiplexer of the feedback multiplexer stage and through the outputs of the adder stage.

16. The ALU of claim 15, wherein after the right black-CDS left difference signal is coupled to be latched in the first adder input latches of the adder input latch stage, the right black signal is coupled to be latched in the second adder input latches of the adder input latch stage through the first inputs of the second feedback multiplexer of the feedback multiplexer stage.

17. The ALU of claim 16, wherein the ADC operation sequence further includes a fourth ADC operation that occurs after the right black signal is coupled to be latched in the second adder input latches of the adder input latch stage, wherein after the fourth ADC operation: a right signal is coupled to be latched in the signal latch stage and received by the first inputs of the adder stage; the right black-CDS left difference signal is coupled to be received by the second inputs of the adder stage through the first inputs of the adder input multiplexer stage; and a CDS left-right signal is coupled to be latched in the third data latches of the data latch stage through the outputs of the adder stage.

18. The ALU of claim 17, wherein after the CDS left-right signal is latched in the third data latches of the data latch stage: the right black signal is coupled to be received from the second inputs of the adder stage through the second inputs of the adder input multiplexer stage, and a CDS right signal is coupled to be latched in the second data latches of the data latch stage through the outputs of the adder stage.

19. The ALU of claim 5, wherein the adder input latch stage further includes a third adder input latch configured to latch the outputs of the GC to the binary stage in response to a third adder input latch enable signal, wherein a third input of the adder input multiplexer stage is coupled to receive the outputs of the third adder input latch.

20. The ALU of claim 19, wherein the ADC operation comprises one of a sequence of ADC operations including a first ADC operation, wherein after the first ADC operation, a low conversion gain (LCG) black signal is coupled to be latched in the signal latch stage and latched in the first adder input latches of the adder input latch stage.

21. The ALU of claim 20, wherein the ADC operation sequence further includes a second ADC operation occurring after the first ADC operation, wherein after the second ADC operation, a high conversion gain (HCG) black signal is coupled to be latched in the signal latch stage and latched in the second adder input latches of the adder input latch stage.

22. The ALU of claim 21, wherein the ADC operation sequence further includes a third ADC operation occurring after the second ADC operation, wherein after the third ADC operation: an HCG left signal is coupled to be latched in the signal latch stage, latched in the third adder input latches of the adder input latch stage, and received by the first inputs of the adder stage; the HCG black signal is coupled to be received by the second inputs of the adder stage through the second inputs of the adder input multiplexer stage; and an HCG CDS left signal is coupled to be latched in the first data latches of the data latch stage through the outputs of the adder stage.

23. The ALU of claim 22, wherein the ADC operation sequence further includes a fourth ADC operation occurring after the third ADC operation, wherein after the fourth ADC operation: an HCG left-right signal is coupled to be latched in the signal latch stage and received by the first inputs of the adder stage; the HCG left signal is coupled to be received by the second inputs of the adder stage through the third inputs of the adder input multiplexer stage; and an HCG CDS right signal is coupled to be latched in the second data latches of the data latch stage through the outputs of the adder stage.

24. The ALU of claim 23, wherein after the HCG CDS right signal is latched in the second data latches of the data latch stage: the HCG black signal is coupled to be received from the second inputs of the adder stage through the second inputs of the adder input multiplexer stage, and an HCG CDS left-right signal is coupled to be latched in the third data latches of the data latch stage through the outputs of the adder stage.

25. The ALU of claim 24, wherein after the HCG CDS left-right signal is latched in the third data latch of the data latch stage: an LCG left-right signal is coupled to be latched in the signal latch stage and received by the first input of the adder stage; the LCG black signal is coupled to be received by the second input of the adder stage through the first input of the adder input multiplexer stage; and an LCG CDS left-right signal is coupled to be latched in the fourth data latch of the data latch stage through the output of the adder stage.

26. An imaging system comprising: A pixel array comprising a plurality of pixel circuits configured in columns and rows, wherein each of the plurality of pixel circuits is coupled to generate an analog image data signal in response to incident light; and a control circuit system coupled to the pixel array to control the operation of the pixel array. The system includes a readout circuit coupled to the pixel array via a plurality of row bit lines, the readout circuit comprising: a plurality of comparators, each of the plurality of comparators being coupled to receive a ramp signal, each of the plurality of comparators being further coupled to one of the plurality of row bit lines to receive a respective analog image data signal, each of the plurality of comparators being coupled to generate a respective comparator output in response to a comparison of the respective analog image data signal with one of the ramp signals; a Gray code (GC) generator coupled to generate a GC output; and a plurality of arithmetic logic units (ALUs), each of the plurality of ALUs being coupled to receive the GC outputs, each of the plurality of ALUs being further coupled to one of the plurality of comparators to receive the respective comparator output, wherein each of the plurality of ALUs includes: A front-end latch stage coupled to the GC generator to latch the GC output of the GC generator in response to the respective comparator outputs; a signal latch stage coupled to latch the output of the front-end latch stage in response to a signal latch enable signal; a GC-to-binary stage coupled to generate a binary representation of the GC outputs latched in the signal latch stage; an adder stage including a first input and a second input, wherein the first input of the adder stage is coupled to receive the output of the GC-to-binary stage, wherein the output of the adder stage is generated in response to the first input and the second input of the adder stage; an adder input latch stage coupled to latch the output of the GC-to-binary stage, wherein the adder input latch stage includes: A first adder input latch, configured to latch the outputs of the GC to the binary stage in response to a first adder input latch enable signal; and a second adder input latch, configured to latch the outputs of the GC to the binary stage in response to a second adder input latch enable signal; and an adder input multiplexer stage, wherein a first input of the adder input multiplexer stage is coupled to receive the outputs of the first adder input latches, wherein a second input of the adder input multiplexer stage is coupled to receive the outputs of the second adder input latches, and wherein a second input of the adder stage is coupled to receive the output of the adder input multiplexer stage.

27. The imaging system of claim 26, further comprising functional logic coupled to the readout circuit to store the image data read from the pixel array.

28. The imaging system of claim 26, wherein each of the plurality of ALUs includes a pulse generator coupled to the respective comparator output to generate a front-end latch enable signal in response to an analog-to-digital (ADC) operation on a signal from the pixel array, wherein the front-end latch stage is coupled to latch the GC outputs of the GC generator in response to the front-end latch enable signal.

29. The imaging system of claim 28, wherein each of the plurality of ALUs includes a data latch stage coupled to latch the output of the adder stage, wherein the data latch stage includes: A first data latch, configured to latch a first phase detection signal from the outputs of the adder stage in response to a first data latch enable signal; a second data latch, configured to latch a second phase detection signal from the outputs of the adder stage in response to a second data latch enable signal; and a third data latch, configured to latch a first summing data signal from the outputs of the adder stage in response to a third data latch enable signal.

30. The imaging system of claim 29, wherein the data latch stage includes three first data latches and three second data latches configured for every 12 third data latches.

31. The imaging system of claim 29, wherein the data latch stage further includes a fourth data latch configured to latch a second summed data signal from the outputs of the adder stage in response to a fourth data latch enable signal.

32. The imaging system of claim 31, wherein the data latch stage includes three first data latches or three second data latches configured for every 12 third data latches or every 12 fourth data latches.

33. The imaging system of claim 31, wherein the data latch stage includes three first data latches and three second data latches configured for every 12 third data latches and every 12 fourth data latches.

34. The imaging system of claim 29, wherein the ADC operation comprises one of a sequence of ADC operations including a first ADC operation, wherein after the first ADC operation, a black signal is coupled to be latched in the signal latch stage and latched in the first adder input latches of the adder input latch stage.

35. The imaging system of claim 34, wherein the ADC operation sequence further includes a second ADC operation occurring after the first ADC operation, wherein after the second ADC operation: a left signal is coupled to be latched in the signal latch stage, latched in the second adder input latches of the adder input latch stage, and received by the first inputs of the adder stage; the black signal is coupled to be received by the second inputs of the adder stage through the first inputs of the adder input multiplexer stage; and a correlated double sample (CDS) left signal is coupled to be latched in the first data latches of the data latch stage through the outputs of the adder stage.

36. The imaging system of claim 35, wherein the ADC operation sequence further includes a third ADC operation occurring after the second ADC operation, wherein after the third ADC operation: a left-right signal is coupled to be latched in the signal latch stage and received by the first inputs of the adder stage; the left signal is coupled to be received by the second inputs of the adder stage through the second inputs of the adder input multiplexer stage; and a CDS right signal is coupled to be latched in the second data latches of the data latch stage through the outputs of the adder stage.

37. The imaging system of claim 36, wherein after the CDS right signal is latched in the second data latches of the data latch stage: the left-right signal is coupled to be received by the first inputs of the adder stage, the black signal is coupled to be received by the second inputs of the adder stage through the first inputs of the adder input multiplexer stage, and a CDS left-right signal is coupled to be latched in the third data latches of the data latch stage through the outputs of the adder stage.

38. The imaging system of claim 29, wherein each of the plurality of ALUs further includes a feedback multiplexer stage, wherein the feedback multiplexer stage includes: A first feedback multiplexer has a first input coupled to the outputs of the GC-to-binary stage and a second input coupled to the outputs of the adder stage, wherein the first adder input latches are further configured to latch the outputs of the GC-to-binary stage or the outputs of the adder stage; and a second feedback multiplexer has a first input coupled to the outputs of the GC-to-binary stage and a second input coupled to the outputs of the adder stage, wherein the second adder input latches are further configured to latch the outputs of the GC-to-binary stage or the outputs of the adder stage.

39. The imaging system of claim 38, wherein the ADC operation comprises one of a sequence of ADC operations including a first ADC operation, wherein after the first ADC operation, a left black signal is coupled to be latched in the signal latch stage and latched in the first adder input latches of the adder input latch stage through the first inputs of the first feedback multiplexers of the feedback multiplexer stage.

40. The imaging system of claim 39, wherein the ADC operation sequence further includes a second ADC operation occurring after the first ADC operation, wherein after the second ADC operation: a left signal is coupled to be latched in the signal latch stage and received by the first inputs of the adder stage; a left black signal is coupled to be received by the second inputs of the adder stage through the first inputs of the adder input multiplexer stage; and a correlated double sample (CDS) left signal is coupled to be latched through the outputs of the adder stage into the first data latches of the data latch stage and through the second inputs of the second feedback multiplexers of the feedback multiplexer stage into the second adder input latches of the adder input latch stage.

41. The imaging system of claim 40, wherein the ADC operation sequence further includes a third ADC operation occurring after the second ADC operation, wherein after the third ADC operation: a right black signal is coupled to be latched in the signal latch stage and received by the first inputs of the adder stage; the CDS left signal is coupled to be received by the second inputs of the adder stage through the second inputs of the adder input multiplexer stage; and a right black-CDS left difference signal is coupled to be latched in the first adder input latches of the adder input latch stage through the second inputs of the first feedback multiplexer of the feedback multiplexer stage and through the outputs of the adder stage.

42. The imaging system of claim 41, wherein after the right black-CDS left difference signal is coupled to be latched in the first adder input latch of the adder input latch stage, the right black signal is coupled to be latched in the second adder input latch of the adder input latch stage through the first inputs of the second feedback multiplexer of the feedback multiplexer stage.

43. The imaging system of claim 42, wherein the ADC operation sequence further includes a fourth ADC operation occurring after the right black signal is coupled to be latched in the second adder input latches of the adder input latch stage, wherein after the fourth ADC operation: a right signal is coupled to be latched in the signal latch stage and received by the first inputs of the adder stage; the right black-CDS left difference signal is coupled to be received by the second inputs of the adder stage through the first inputs of the adder input multiplexer stage; and a CDS left-right signal is coupled to be latched in the third data latches of the data latch stage through the outputs of the adder stage.

44. The imaging system of claim 43, wherein after the CDS left-right signal is latched in the third data latches of the data latch stage: the right black signal is coupled to be received from the second inputs of the adder stage through the second inputs of the adder input multiplexer stage, and a CDS right signal is coupled to be latched in the second data latches of the data latch stage through the outputs of the adder stage.

45. The imaging system of claim 31, wherein the adder input latch stage further includes a third adder input latch configured to latch the outputs of the GC to binary stage in response to a third adder input latch enable signal, wherein a third input of the adder input multiplexer stage is coupled to receive the outputs of the third adder input latch.

46. ​​The imaging system of claim 45, wherein the ADC operation comprises one of a sequence of ADC operations including a first ADC operation, wherein after the first ADC operation, a low conversion gain (LCG) black signal is coupled to be latched in the signal latch stage and latched in the first adder input latches of the adder input latch stage.

47. The imaging system of claim 46, wherein the ADC operation sequence further includes a second ADC operation occurring after the first ADC operation, wherein after the second ADC operation, a high conversion gain (HCG) black signal is coupled to be latched in the signal latch stage and latched in the second adder input latches of the adder input latch stage.

48. The imaging system of claim 47, wherein the ADC operation sequence further includes a third ADC operation occurring after the second ADC operation, wherein after the third ADC operation: an HCG left signal is coupled to be latched in the signal latch stage, latched in the third adder input latches of the adder input latch stage, and received by the first inputs of the adder stage; the HCG black signal is coupled to be received by the second inputs of the adder stage through the second inputs of the adder input multiplexer stage; and an HCG CDS left signal is coupled to be latched in the first data latches of the data latch stage through the outputs of the adder stage.

49. The imaging system of claim 48, wherein the ADC operation sequence further includes a fourth ADC operation occurring after the third ADC operation, wherein after the fourth ADC operation: an HCG left-right signal is coupled to be latched in the signal latch stage and received by the first inputs of the adder stage; the HCG left signal is coupled to be received by the second inputs of the adder stage through the third inputs of the adder input multiplexer stage; and an HCG CDS right signal is coupled to be latched in the second data latches of the data latch stage through the outputs of the adder stage.

50. The imaging system of claim 49, wherein after the HCG CDS right signal is latched in the second data latches of the data latch stage: the HCG black signal is coupled to be received from the second inputs of the adder stage through the second inputs of the adder input multiplexer stage, and an HCG CDS left-right signal is coupled to be latched in the third data latches of the data latch stage through the outputs of the adder stage.

51. The imaging system of claim 50, wherein after the HCG CDS left-right signal is latched in the third data latch of the data latch stage: an LCG left-right signal is coupled to be latched in the signal latch stage and received by the first input of the adder stage; the LCG black signal is coupled to be received by the second input of the adder stage through the first input of the adder input multiplexer stage; and an LCG CDS left-right signal is coupled to be latched in the fourth data latch of the data latch stage through the output of the adder stage.

Images