Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes a pixel electrode and a transistor. The transistor includes a first gate electrode, a first insulating layer above the first gate electrode, a semiconductor layer above the first insulating layer, a second insulating layer above the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are disposed on the second insulating layer. The first gate electrode has a region overlapping the semiconductor layer, with the first insulating layer disposed therebetween. The second gate electrode has a region overlapping the semiconductor layer, with the second insulating layer disposed therebetween. A first region is at least a portion of the region where the second gate electrode overlaps with the semiconductor layer. A second region is at least a portion of the region where the pixel electrode is disposed. The second insulating layer is thinner in the first region than in the second region.

Description

Semiconductor device and method for manufacturing the same The present invention relates to semiconductor devices, display devices, light-emitting devices, and methods for manufacturing these devices. In particular, the present invention relates to semiconductor devices, display devices, and light-emitting devices each including a transistor, and methods for manufacturing these devices. The present invention also relates to electronic devices including semiconductor devices, display devices, or light-emitting devices. It is known that by controlling the threshold voltage, the on-state current of a transistor comprising upper and lower gate electrodes with a semiconductor layer disposed therebetween can be increased, and the off-state current of the transistor can be reduced. A transistor having this structure is called a dual-gate transistor or a dual-gate transistor. In the following description, a transistor having this structure is also referred to as a bottom-gate transistor with a back-gate electrode. A bottom-gate transistor having a back gate electrode can be used in, for example, a display device (see FIG. 7 of Patent Document 1). [Reference Document] Patent document 1: Japanese published patent application number 2010-109342. In the display device disclosed in Patent Document 1, a planarized insulating layer is formed above the transistor to increase the aperture ratio or reduce noise from the pixel electrode, and the pixel electrode is formed above the planarized insulating layer. Here, the back gate electrode of the transistor is formed below the planarized insulating layer and in a position close to the semiconductor layer of the transistor (the semiconductor layer forming the channel). In the display device disclosed in Patent Document 1, the back gate electrode is formed using a layer different from the pixel electrode. Therefore, the display device disclosed in Patent Document 1 has a problem of increasing the number of manufacturing steps compared to a display device including transistors without a back gate electrode. When the back gate electrode and the pixel electrode are formed using the same layer to reduce the number of manufacturing steps, a planarization insulating layer is present between the back gate electrode and the semiconductor layer of the transistor. Because the planarization insulating layer is usually thick, there is a problem that the back gate electrode does not function properly. One embodiment of the present invention aims to manufacture a semiconductor device including a bottom-gate transistor with a back gate electrode using fewer steps. Alternatively, one embodiment of the present invention aims to provide a semiconductor device including a bottom-gate transistor with a back gate electrode that can be manufactured using fewer steps. Alternatively, one embodiment of the present invention aims to provide a semiconductor device in which a strong electric field can be applied to a semiconductor layer via a back gate electrode. Alternatively, one embodiment of the present invention aims to provide a semiconductor device with a controlled threshold voltage. Alternatively, one embodiment of the present invention aims to provide a semiconductor device that is easily normally shut down. Alternatively, one embodiment of the present invention aims to provide a semiconductor device including a transistor with a high on-state current. Alternatively, one embodiment of the present invention aims to provide a semiconductor device including a transistor capable of suppressing light from entering a channel. Alternatively, one embodiment of the present invention aims to provide a semiconductor device including a transistor that is not easily degraded. Alternatively, one embodiment of the present invention is directed to providing a semiconductor device in which the thickness of an insulating layer disposed above a transistor channel is varied using a halftone mask or a gray tone mask. Alternatively, one embodiment of the present invention is directed to providing a better semiconductor device while suppressing an increase in the number of steps. Alternatively, one embodiment of the present invention is directed to providing a semiconductor device that suppresses an increase in cost by suppressing an increase in the number of steps. Alternatively, one embodiment of the present invention is directed to providing a display device capable of accurately displaying images by using transistors with low off-state current. Alternatively, one embodiment of the present invention is directed to providing a display device with a high aperture ratio. Alternatively, one embodiment of the present invention is directed to providing a semiconductor device in which pixel electrodes have low noise. Alternatively, one embodiment of the present invention is directed to providing a semiconductor device in which the insulating layer is thicker below the pixel electrode than below the back gate electrode. It should be noted that the description of these objectives does not preclude the existence of other objectives. It should be noted that in one embodiment of the present invention, not all objectives need to be achieved. Other objectives may be more clearly understood or derived from the description, drawings, patent claims, etc. in the specification. One embodiment of the present invention is a semiconductor device comprising a transistor and a pixel electrode. The transistor comprises a first gate electrode, a first insulating layer above the first gate electrode, a semiconductor layer above the first insulating layer, a second insulating layer above the semiconductor layer, and a second gate electrode above the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer, with the first insulating layer disposed therebetween. The second gate electrode has a region overlapping with the semiconductor layer, with the second insulating layer disposed therebetween. The pixel electrode is disposed above the second insulating layer. The first region is at least a portion of a region where the second gate electrode at least partially overlaps with at least a portion of the semiconductor layer. The second region is at least a portion of a region where the pixel electrode is disposed. The second insulating layer is thinner in the first region than in the second region. The transistor may further include a first electrode and a second electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode. The pixel electrode may be electrically connected to the transistor via an opening in the second insulating layer. The second insulating layer may include one or both of a color filter and a black matrix. One embodiment of the present invention is a method for manufacturing a semiconductor device. The method includes forming a first gate electrode on an insulating surface; forming a first insulating layer on the first gate electrode; forming a semiconductor layer on the first insulating layer so that the semiconductor layer at least partially overlaps at least a portion of the first gate electrode and has the first insulating layer disposed therebetween; forming a second insulating layer comprising a first region and a second region on the semiconductor layer; and forming a second gate electrode and a pixel electrode on the second insulating layer so that the second gate electrode at least partially overlaps at least a portion of the semiconductor layer and has the first region of the second insulating layer disposed therebetween, and at least a portion of the pixel electrode is disposed above at least a portion of the second region of the second insulating layer. The first region of the second insulating layer is thinner than the second region of the second insulating layer. One embodiment of the present invention is a method for manufacturing a semiconductor device. The method includes the steps of forming a first gate electrode on an insulating surface; forming a first insulating layer on the first gate electrode; forming a semiconductor layer on the first insulating layer so that the semiconductor layer at least partially overlaps at least a portion of the first gate electrode and has the first insulating layer disposed therebetween; forming a second insulating layer comprising a first region, a second region, and a through hole on the semiconductor layer; and forming a second gate electrode and a pixel electrode on the second insulating layer so that the second gate electrode at least partially overlaps at least a portion of the semiconductor layer and has the first region of the second insulating layer disposed therebetween, and the pixel electrode at least partially overlaps at least a portion of the second region of the second insulating layer and contacts a lower wiring or lower electrode via the through hole. The first region of the second insulating layer is thinner than the second region of the second insulating layer. The second insulating layer may be formed using a halftone mask, a gray tone mask, a phase shift mask, or a multi-tone mask. According to one embodiment of the present invention, a semiconductor device including a bottom-gate transistor with a back gate electrode can be manufactured with fewer steps. Alternatively, a semiconductor device including a bottom-gate transistor with a back gate electrode can be provided that can be manufactured with fewer steps. Alternatively, a semiconductor device can be provided in which a strong electric field can be applied to the semiconductor layer via the back gate electrode. Alternatively, a semiconductor device can be provided in which a threshold voltage can be controlled. Alternatively, a semiconductor device can be provided that is easily normally shut down. Alternatively, a semiconductor device can be provided in which a transistor with high on-state current can be provided. Alternatively, a semiconductor device can be provided in which the thickness of an insulating layer provided over the transistor channel is varied using a halftone mask, a gray tone mask, a phase shift mask, or a multi-tone mask. Alternatively, a better semiconductor device can be provided while suppressing an increase in the number of steps. Alternatively, a semiconductor device can be provided in which a cost increase can be suppressed by suppressing an increase in the number of steps. Alternatively, a display device can be provided that accurately displays images by using transistors with low off-state current. Alternatively, a display device with a high aperture ratio can be provided. Alternatively, a display device with low pixel electrode noise can be provided. Alternatively, a display device can be provided in which the insulating layer is thicker below the pixel electrode than below the back gate electrode. 100: Transistor 101: Electrode 101a: Electrode 101b: Electrode 102: Insulation layer 103: semiconductor layer 103a: semiconductor layer 104a: Electrode 104b: Electrode 104c: Electrode 105: Insulation layer 105a: Insulation layer 105b: Insulation layer 105c: Insulation layer 106: Electrode 106a: Electrode 107: Insulation layer 108a: conductive layer 108b: conductive layer 109: Part 110: Electrode 121: Area 121c: Area 122: Area 123:Through hole 124: Opening 125: Opening 126: Opening 127: Opening 128: Opening 128a: Opening 131a: End 131b: end 132a: End 132b: end 191: Open 192: Open 193: Opening 194: Open 195: Opening 196: Opening 197: Opening 198: Opening 200: Insulation surface 281: Part 282: Part 283: Part 441: Open 442: Open 443: Open 444: Open 445: Open 446: Open 447: Open 448: Opening 451: Open 452: Open 453: Open 454: Open 455: Open 456: Open 457: Open 458: Open 501a: Opening 501b: Opening 502a: Opening 502b: Opening 510: protrusion 510a: Layer 510b: Layer 530: pixels 531:Capacitor 532:Capacitor 550: Electrode 551: Gate signal line 552: Source signal line 553:Capacitor wire 560:EL components 561: Power supply line 562: Transistor 563: Transistor 564:Capacitor 591:Insulating film 592: Halftone Mask 592a: Area 592b: Area 592c: Area 601a: Insulating film 601b: Insulating film 602: resist 603: Halftone Mask 603a: Area 603b: Area 603b: Area 604: Anti-corrosion mask 652: Black Matrix 701: Transistor 702: Transistor 703: Transistor 704: Transistor 705: Transistor 706: Transistor 707: Transistor 708: Transistor 709: Transistor 710: Transistor 711: Transistor 712: Transistor 713: Transistor 714:Capacitor 715: Transistor 801: Transistor 802: Transistor 803: Transistor 804: Transistor 805: Transistor 806: Transistor 807: Transistor 808: Transistor 809: Transistor 810: Transistor 811: Transistor 812: Transistor 813: Transistor 814: Transistor 815: Transistor 816: Transistor 817: Transistor 901: Shell 902: Display device 903: Backlight unit 904: Shell 905: Driver IC 906:Terminal 5000: Shell 5001: Display unit 5002: Second display unit 5003: Speaker 5004: LED lamp 5005: Operation keys 5006:Connection terminal 5007:Sensor 5008: Microphone 5009:Switch 5010: Infrared port 5011: Memory media reading unit 5012: Bracket 5013:Headphones 5014: Antenna 5015:Shutter button 5016: Image receiving unit 5017: Charger 5018:Support base 5019: External port 5020: Positioning device 5021:Reader / Writer 5022: Shell 5023: Display unit 5024: Remote Control 5025: Speaker 5026: Display panel 5027:Bathroom unit 5028: Display panel 5029: Car body 5030: Ceiling 5031: Display panel 5032: Hinge In the attached figure: 1A to 1E are cross-sectional views of the structures of semiconductor devices; 2A to 2E are cross-sectional views of the structures of semiconductor devices; 3A to 3E are cross-sectional views of the structures of semiconductor devices; 4A and 4B are cross-sectional views each showing a structure of a semiconductor device; 5A and 5B are cross-sectional views each showing a structure of a semiconductor device; 6A to 6E are cross-sectional views of the structures of semiconductor devices; 7A to 7E are cross-sectional views of the structures of semiconductor devices; 8A to 8E are cross-sectional views of the structures of semiconductor devices; 9A to 9E are cross-sectional views of the structures of semiconductor devices; 10A to 10E are cross-sectional views of the structures of semiconductor devices; 11A to 11E are cross-sectional views of the structures of semiconductor devices; 12A to 12E are cross-sectional views of the structures of semiconductor devices; 13A to 13E are cross-sectional views of the structures of semiconductor devices; 14A to 14E are cross-sectional views of the structures of semiconductor devices; 15A to 15E are cross-sectional views each showing a structure of a semiconductor device; 16A to 16E are cross-sectional views each showing a structure of a semiconductor device; 17A to 17E are cross-sectional views of the structures of semiconductor devices; 18A to 18E are cross-sectional views each showing a structure of a semiconductor device; 19A to 19D are cross-sectional views each showing a structure of a semiconductor device; 20A to 20D are cross-sectional views each showing a structure of a semiconductor device; 21A to 21D are cross-sectional views each showing a structure of a semiconductor device; 22A to 22E are cross-sectional views each showing a structure of a semiconductor device; 23A to 23E are cross-sectional views each showing a structure of a semiconductor device; 24A to 24E are cross-sectional views each showing a structure of a semiconductor device; 25A to 25E are cross-sectional views each showing a structure of a semiconductor device; 26A to 26E are cross-sectional views each showing a structure of a semiconductor device; 27A to 27E are cross-sectional views each showing a structure of a semiconductor device; 28A to 28E are cross-sectional views each showing a structure of a semiconductor device; 29A and 29B are cross-sectional views each showing a structure of a semiconductor device; 30A and 30B are cross-sectional views each showing a structure of a semiconductor device; 31A to 31E are cross-sectional views each showing a structure of a semiconductor device; 32A to 32E are cross-sectional views of the structures of semiconductor devices; 33A to 33E are cross-sectional views of the structures of semiconductor devices; 34A to 34E are cross-sectional views each showing a structure of a semiconductor device; 35A to 35E are cross-sectional views each showing a structure of a semiconductor device; 36A to 36E are cross-sectional views each showing a structure of a semiconductor device; 37A to 37E are cross-sectional views each showing a structure of a semiconductor device; 38A to 38E are cross-sectional views each showing a structure of a semiconductor device; 39A to 39E are cross-sectional views each showing a structure of a semiconductor device; 40A to 40E are cross-sectional views each showing a structure of a semiconductor device; 41A to 41E are cross-sectional views each showing a structure of a semiconductor device; 42A to 42E are cross-sectional views each showing a structure of a semiconductor device; 43A to 43E are cross-sectional views each showing a structure of a semiconductor device; 44A to 44D are cross-sectional views each showing a structure of a semiconductor device; 45A to 45D are cross-sectional views each showing a structure of a semiconductor device; 46A to 46D are cross-sectional views each showing a structure of a semiconductor device; 47A to 47D are cross-sectional views each showing a structure of a semiconductor device; 48A to 48E are cross-sectional views each showing a structure of a semiconductor device; 49A to 49E are cross-sectional views each showing a structure of a semiconductor device; 50A to 50E are cross-sectional views each showing a structure of a semiconductor device; 51A to 51E are cross-sectional views each showing a structure of a semiconductor device; 52A and 52B are each a cross-sectional view of the structure of a semiconductor device; FIG53 is a top view of the structure of a semiconductor device; FIG54 is a top view of the structure of a semiconductor device; 55A to 55H are circuit diagrams each showing a structure of a semiconductor device; 56A to 56C are circuit diagrams each showing a structure of a semiconductor device; 57A and 57B are circuit diagrams each showing a structure of a semiconductor device; 58A to 58D are cross-sectional views each showing a structure of a semiconductor device; 59A to 59E are diagrams illustrating a method for manufacturing a semiconductor device; 60A to 60E are diagrams showing a method for manufacturing a semiconductor device; 61A to 61D are diagrams illustrating a method for manufacturing a semiconductor device; 62A to 62E are diagrams illustrating a method for manufacturing a semiconductor device; 63A to 63E are diagrams illustrating a method for manufacturing a semiconductor device; 64A to 64E are diagrams showing a method for manufacturing a semiconductor device; 65A to 65D are cross-sectional views each showing a structure of a semiconductor device; 66A to 66C are cross-sectional views each showing a structure of a semiconductor device; 67A to 67H are diagrams of electronic devices; 68A to 68H are diagrams of electronic devices; 69A to 69E are diagrams each showing a structure of an oxide semiconductor layer; 70A to 70C are diagrams showing the structure of an oxide semiconductor layer; 71A to 71C are structural diagrams of an oxide semiconductor layer; and Figure 72 is a diagram of the display module. The following describes an embodiment of the present invention in detail with reference to the accompanying drawings. It should be noted that the present invention is not limited to the following description. Those skilled in the art will readily appreciate that the modes and details of the present invention may be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the following description of the embodiments. It should be noted that in the structures described below, the same reference numerals are used in different drawings to represent the same parts or parts having similar functions, and their descriptions are omitted. It should be noted that the content described in one embodiment (or may be part of the content) may be applied to, combined with, or replace the different content described in the embodiment (or may be part of the different content) and / or the content described in one or more different embodiments (or may be part of the content). It should be noted that the structure of a figure illustrated in one embodiment (or which may be a part of a figure) may be combined with the structure of another part of the figure, the structure of a different figure illustrated in an embodiment (or which may be a part of a different figure), and / or the structure of a figure illustrated in one or more different embodiments (or which may be a part of a figure). It should be noted that in some cases, dimensions, thicknesses, or areas in the drawings are exaggerated for clarity. Thus, one aspect of the present invention is not limited to such dimensions. Alternatively, the drawings are perspective views of idealized examples. Thus, one aspect of the present invention is not limited to the shapes, etc., illustrated in the drawings. For example, variations in shape due to manufacturing techniques or dimensional variations may be included. It is important to note that the explicit wording “ X and Y is connected" means X and Y is electrically connected, X and Y is functionally linked, and X and Y is directly connected. Here, X and Each of Y is an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer). Therefore, connections other than those shown in the drawings and herein are also included, and are not limited to predetermined connections, such as those shown in the drawings and herein. For example, in X and In the case where Y is electrically connected, X and One or more components (e.g., switches, transistors, capacitors, conductors, resistors, and / or diodes) electrically connected between Y can be connected to X and Between Y. For example, in X and In the case where Y is functionally linked, enabling X and One or more circuits of the functional connection between Y can be connected to X and Y. Note that, for example, even when another circuit is set X and When the output is between Y X's signal is still sent to In the case of Y, X and Y is functionally linked. It is important to note that the explicit wording “ X and Y is electrically connected" means X and Y is electrically connected, X and Y is functionally connected, and X and Y is directly connected. That is, the explicit wording " X and Y is electrically connected" with clear simple wording " X and Y is connected". It should be noted that even when independent components are electrically connected to each other in a circuit diagram, there are cases where a conductive layer functions as multiple components (e.g., wiring and electrodes), such as when a portion of a wiring functions as an electrode. The term "electrically connected" in this specification also means that a conductive layer functions as multiple components. (Example 1) In this embodiment, an aspect of a semiconductor device or the like (eg, a display device or a light-emitting device) according to the present invention is described with reference to the drawings. Figure 1A is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. The semiconductor device includes a transistor 100 and an electrode 110 on an insulating surface (or insulating substrate) 200. Transistor 100 includes an electrode 101, an insulating layer 102 on electrode 101, a semiconductor layer 103 on insulating layer 102, an insulating layer 105 on semiconductor layer 103, and an electrode 106 on insulating layer 105. Electrode 101 has a region overlapping with semiconductor layer 103, with insulating layer 102 disposed therebetween. Electrode 106 has a region overlapping with semiconductor layer 103, with insulating layer 105 disposed therebetween. Electrode 110 is disposed on insulating layer 105. Region 121 is at least a portion of the region where electrode 106 at least partially overlaps at least a portion of semiconductor layer 103. Region 122 is at least a portion of the region where electrode 110 is disposed. Insulating layer 105 is thinner in region 121 than in region 122. In other words, the insulating layer 105 includes a region 121 and a region 122 thicker than the thin region 121 . The region 121 is at least a portion of the region where the electrode 106 partially overlaps with the semiconductor layer 103 , and the region 122 at least partially overlaps with the electrode 110 . Here, electrode 101 and electrode 106 can serve as the first gate electrode and second gate electrode (back gate electrode) of transistor 100, respectively. Electrode 110 can serve as a pixel electrode. Electrode 106 overlaps with semiconductor layer 103, with a thin region (region 121) having insulating layer 105 disposed therebetween; thus, electrode 106 can effectively serve as a back gate electrode. Electrodes 110 and 106 can be formed by etching a conductive film. In that case, electrodes 110 and 106 have the same material and substantially the same thickness. Alternatively, electrodes 110 and 106 can be formed by etching different conductive films. Etching a conductive film can reduce the number of processing steps. It should be noted that the transistor preferably includes both a first gate electrode and a second gate electrode (back gate electrode). However, one aspect of the present invention is not limited to this. The transistor may include one of the first gate electrode and the second gate electrode (back gate electrode) but not the other. For example, as shown in FIG66C , a transistor structure may be used in which the electrode 106 is not included. Even in such a case, the transistor can still operate correctly. In FIG1A , transistor 100 further includes electrodes 104 a and 104 b. One of electrodes 104 a and 104 b may be a source electrode, while the other may be a drain electrode. In FIG1A , electrodes 104 a and 104 b are disposed on semiconductor layer 103 (e.g., electrodes 104 a and 104 b are disposed in contact with the top and side surfaces of semiconductor layer 103). The bottom surface of semiconductor layer 103 is not in contact with electrodes 104 a and 104 b. It should be noted that the transistor preferably includes both a source electrode and a drain electrode. However, one aspect of the present invention is not limited thereto. The transistor may have one of the source electrode and the drain electrode but not the other, or may have neither electrode. Even in such a case, when the transistor is connected to a different device (e.g., a different transistor) via the semiconductor layer 103, the transistor having a channel formed in the semiconductor layer 103 can still operate properly. It should be noted that a transistor is a device with at least three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. Here, because the source and drain of a transistor vary depending on the transistor's structure, operating conditions, and so on, it is difficult to define which is the source or drain. Thus, in some cases, the region that serves as the source or the region that serves as the drain is not referred to as the source or drain. In such cases, for example, one of the source or drain may be referred to as a first terminal, a first electrode, or a first region, and the other of the source and drain may be referred to as a second terminal, a second electrode, or a second region. The electrode 110 may be electrically connected to the transistor 100 through an opening formed in the insulating layer 105 . It is important to note that the explicit wording “ X on Y" or " Above X "Y" does not necessarily mean Y in X and X direct contact. The wording also means X and Y are not in direct contact with each other, i.e., another object is placed X and Y. Here, X and Each of Y is an object (eg, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer). Thus, for example, the explicit wording "layer Layer on (or above) X "Y" means layer Y in layer X and layer X is in direct contact, while another layer (e.g., layer Z) in the layer X and layer X direct contact and layer Y is on another layer and in direct contact with the other layer. Z) can be a single layer or a plurality of layers (stack of layers). Likewise, the clear wording " Above X "Y" does not necessarily mean Y in X and X is in direct contact, and another object may be disposed therebetween. Thus, for example, the wording "layer Layers above X "Y" means layer Y in layer X and layer X is in direct contact, while another layer (e.g., layer Z) in the layer X and layer X is in direct contact with and layer Y is on another layer and in direct contact with another layer. Z) can be a single layer or a plurality of layers (stack of layers). Note that the same can be applied to the wording " Under X Y" or " Below the X Y". Note that, as shown in FIG9A , the region of the semiconductor layer 103 that does not overlap with the electrodes 104 a and 104 b can be thinned. For example, when etching is performed to form the electrodes 104 a and 104 b, a portion of the surface of the semiconductor layer 103 below the layer to become the electrodes 104 a and 104 b can be etched. A transistor in which at least a portion of the region of the semiconductor layer 103 that serves as the channel is thinned in this manner (or a transistor in which a channel protection film is not provided between the upper portion of the channel and the electrodes 104 a and 104 b) is also referred to as a channel-etched transistor. One aspect of the semiconductor device of the present invention is not limited to the structure of FIG1A. The following describes different structural examples of the semiconductor device of the present invention. Note that the same reference numerals are used to indicate the same parts as those in FIG1A, and their descriptions are omitted. For example, as shown in FIG1B , an insulating layer 107 may be provided between the semiconductor layer 103 and the electrodes 104a and 104b. The insulating layer 107 serves as a protective film (channel protection film) to prevent the semiconductor layer 103 (particularly, the region of the semiconductor layer 103 that serves as the channel) from being etched during the etching process to form the electrodes 104a and 104b. A transistor having a channel protection film may be referred to as a channel-protected transistor. In this case, the semiconductor layer 103 can be thinned, thereby improving (reducing) the subthreshold swing (S value) of the transistor 100. Note that, in the case where the transistor is a channel protection transistor, as shown in FIG65D , the insulating layer 105 can be removed from the region 121. In that case, the electrode 106 and the insulating layer 107 are in local direct contact with each other. As a result, the electrode 106, acting as the back gate electrode, can apply a stronger electric field to the semiconductor layer 103. Alternatively, for example, as shown in FIG2A , electrodes 104 a and 104 b may be formed below semiconductor layer 103 (e.g., some of the upper surfaces and end surfaces of electrodes 104 a and 104 b may be in contact with the lower surface of semiconductor layer 103). As a result, semiconductor layer 103 can be prevented from being damaged during etching for electrodes 104 a and 104 b. Alternatively, semiconductor layer 103 may be thinned to improve (reduce) subthreshold swing (S value). Alternatively, for example, as shown in FIG3A , the ends 131 a and 131 b of the semiconductor layer 103 can be substantially aligned with the ends 132 a and 132 b of the electrodes 104 a and 104 b. The semiconductor layer 103 and the electrodes 104 a and 104 b can be formed by etching the stack of semiconductor films and conductive films thereon using a mask. A photomask having three or more regions with different light transmittances for exposure (hereinafter referred to as a halftone mask, gray tone mask, phase shift mask, or multi-tone mask) can be used as a mask. By using a halftone mask, regions where the semiconductor layer 103 is exposed and regions where the semiconductor layer 103 is removed can be formed by etching using a mask. In this way, the number of processes required to form the transistor 100 can be further reduced, and the cost of the semiconductor device can be further reduced. It should be noted that, in the case where the semiconductor layer 103 and the electrodes 104a and 104b are formed using a halftone mask, the semiconductor layer 103 always exists below the electrodes 104a and 104b. The end 132a and / or the end 132b may be a stepped end. Alternatively, as shown in Figure 3B, an insulating layer 107 serving as a channel protection film may be provided in the structure shown in Figure 3A. In this way, in diagrams other than Figure 3B, a channel protection film may be additionally provided in various transistors that do not have a channel protection film. Alternatively, for example, as shown in FIG9A , the conductive layers 108 a and 108 b may be provided between the semiconductor layer 103 and the electrodes 104 a and 104 b. The conductive layers 108 a and 108 b may be formed using, for example, a semiconductor layer to which an impurity element imparting conductivity is added. Alternatively, for example, the conductive layers 108 a and 108 b may be formed using a conductive metal oxide. Alternatively, for example, the conductive layers 108 a and 108 b may be formed using a conductive metal oxide to which an impurity element imparting conductivity is added. Note that in FIG1A and the like, the impurity element imparting conductivity may be added to a portion of the semiconductor layer 103. Examples of impurity elements imparting conductivity include phosphorus, arsenic, boron, hydrogen, and tin. Here, in FIG9A , the region of the semiconductor layer 103 that does not overlap with the electrodes 104a and 104b and the conductive layers 108a and 108b is thinned. This is because when etching is performed to form the electrodes 104a and 104b and the conductive layers 108a and 108b, a portion of the surface of the semiconductor layer 103 below the layer to become the electrodes 104a and 104b and the layer to become the conductive layers 108a and 108b is etched (the transistor in FIG9A is a channel-etched transistor). Note that a channel protection film may be provided between the semiconductor layer 103 and the conductive layers 108a and 108b (the transistor in FIG9A may be a channel protection transistor) to prevent the semiconductor layer 103 from being etched. It should be noted that although the electrodes 110 and 106 are formed using the same layer in the above structure, this embodiment is not limited thereto and the electrodes 110 and 106 may be formed using different layers. Alternatively, an insulating layer may be provided between the electrodes 104a and 104b and the semiconductor layer 103 or between the electrodes 104a and 104b and the conductive layers 108a and 108b. Furthermore, openings may be provided in the insulating layer so that the electrodes 104a and 104b can be connected to the semiconductor layer 103 or the electrodes 104a and 104b can be connected to the conductive layers 108a and 108b. It should be noted that various substrates can be used as the substrate having the insulating surface 200, and the substrate is not limited to a certain type. Examples of the substrate include a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI (silicon on insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate including a stainless steel sheet, a tungsten substrate, a substrate including a tungsten sheet, a flexible substrate, an adhesive film, paper including a fiber material, and a base film. It should be noted that the transistor 100 can be formed on a substrate and then transferred to a different substrate, so that the transistor 100 can be configured on a different substrate. As described above, the back gate electrode of transistor 100 in Figures 1A, 1B, 2A, 3A, 3B, 9A, and the like can effectively control the threshold voltage. This allows transistor 100 to be easily shut down normally. Alternatively, the back gate electrode can effectively increase the on-state current. Alternatively, the back gate electrode can effectively reduce the off-state current. Alternatively, the back gate electrode can increase the on / off ratio. Thus, when a display device has the above structure, the display device can accurately display images. Alternatively, when a display device or light-emitting device has the above structure and the insulating layer 105 serves as a planarization film, the aperture ratio can be increased. This embodiment is one of the basic structural examples of an embodiment according to the present invention. As such, this embodiment can be freely combined with another embodiment obtained by performing changes, additions, modifications, removals, applications, super-conceptualizations, or sub-conceptualizations on part or all of this embodiment. (Example 2) In this embodiment, one aspect of a semiconductor device or the like (eg, a display device or a light-emitting device) according to the present invention is described with reference to the drawings. In the structure described in Example 1 with reference to FIG. 1A , FIG. 1B , FIG. 2A , FIG. 3A , FIG. 3B , FIG. 9A , etc., the insulating layer 105 in the region 122 or a portion of the region 122 may include a stack of multiple layers. m layers of stacking ( m is a natural number of 2 or greater). The insulating layer 105 in the region 121 or a portion of the region 121 may include The insulating layer 105 may include a stack of m or less layers or a single layer. The insulating layer 105 may include an organic insulating layer or a stack of an organic insulating layer and an inorganic insulating layer. For example, in the structures shown in Figures 1A, 1B, 2A, 3A, 3B, 9A, and the like, the insulating layer 105 in region 122 may include a stack of layers 105a and 105b, while the insulating layer 105 in region 121 may include a single layer of layer 105a. Layer 105b is formed on layer 105a. Figures 1C, 1D, 2B, 3C, 3D, and 9B each illustrate such a structure. With this structure, a stack of layers 105a and 105b can be obtained by utilizing differences in etching sensitivity to only necessary portions (etch selectivity). Therefore, the thickness of the insulating layer 105 in each region can be easily controlled. Alternatively, regions may have different functions (e.g., planarization, impurity blocking, and light blocking) depending on film quality. Alternatively, using a photosensitive material to form a portion of the layer can reduce the number of processing steps. Here, layer 105a can be an inorganic insulating layer, and layer 105b can be an organic insulating layer. In this case, because an organic material is used, layer 105b can be thicker than layer 105a. When layer 105a is an inorganic insulating layer (preferably a silicon nitride film), for example, impurities in layer 105b can be prevented from entering transistor 100. Alternatively, when layer 105b is an organic insulating layer, it can function as a planarization layer, thereby reducing unevenness caused by transistor 100 and other components. This allows the surface of electrode 110 to be planarized. This, for example, can reduce display defects when electrode 110 is used as a pixel electrode. Alternatively, because the thickness of layer 105b can be increased, pixel electrode noise can be reduced. Furthermore, because etching selectivity can be varied depending on film quality, only necessary areas can be selectively etched, resulting in a stack of layers 105a and 105b having a predetermined shape. Alternatively, layer 105a and / or layer 105b (or a portion thereof, preferably layer 105b) may be a color filter and / or a black matrix. When layer 105a and / or layer 105b is a color filter and / or a black matrix, a mounting margin for the substrate (a substrate having an insulating surface 200) on which transistor 100 is disposed and another substrate (e.g., an opposing substrate in a display device, etc.) may be increased. Alternatively, when the black matrix is ​​disposed in layer 105a and / or layer 105b (or a portion thereof) near transistor 100, light is not easily incident on transistor 100. When light is not easily incident on transistor 100, the off-state current of transistor 100 or degradation of transistor 100 can be reduced. For example, as shown in FIG65A , a black matrix 652 may be disposed in a portion of layer 105b. Note that a plurality of overlapping color filters having different colors may be used as the black matrix. It should be noted that the color filter and / or black matrix are preferably formed using organic materials; thus, the color filter and / or black matrix are preferably formed in layer 105b. It should be noted that this embodiment is not limited thereto, and a light-blocking conductive film can be used as the black matrix. Alternatively, the thickness of layer 105a may be smaller than that of layer 105b. When the thickness of layer 105a is reduced, the electric field generated by electrode 106 can be appropriately applied to the channel. Alternatively, when the thickness of layer 105b is increased, unevenness caused by transistor 100 and the like can be appropriately reduced. Alternatively, for example, in the structures shown in Figures 1A, 1B, 2A, 3A, 3B, 9A, etc., the insulating layer 105 in region 122 may include a stack of layers 105b and 105c, and the insulating layer 105 in region 121 may include a single layer of layer 105c. Layer 105c is formed on layer 105b. Figures 26A, 26B, 27A, 28A, 28B, and 34A each illustrate such a structure. With this structure, a stack of layers 105b and 105c can be obtained by utilizing differences in etching sensitivity to only necessary portions (etching selectivity). Therefore, the thickness of the insulating layer 105 in each region can be easily controlled. Alternatively, regions may have different functions (e.g., planarization, impurity blocking, and light blocking) depending on film quality. Alternatively, since a portion of the layer is formed using a photosensitive material, the number of processes can be reduced. Here, layer 105b can be an organic insulating layer, and layer 105c can be an inorganic insulating layer. In that case, because an organic material is used, layer 105b can be thicker than layer 105c. When layer 105c is an inorganic insulating layer (preferably a silicon nitride film), impurities in layer 105b can be prevented from entering electrode 106 or the layer above electrode 106 (such as a liquid crystal layer, an alignment film, or an organic EL layer). Alternatively, when layer 105b is an organic insulating layer, the organic insulating layer can serve as a planarization layer and can reduce unevenness caused by transistor 100, etc. In this way, the surface of electrode 110 can be planarized. In this way, for example, in the case of using electrode 110 as a pixel electrode, display defects can be reduced. Alternatively, because the thickness of layer 105b can be increased, the noise of the pixel electrode can be reduced. Alternatively, since etching selectivity can be changed depending on film quality, only necessary portions are selectively etched so that a stack of layers 105b and 105c having a predetermined shape can be obtained. Alternatively, layer 105b and / or layer 105c (or a portion thereof, preferably layer 105b) may be a color filter and / or a black matrix. When layer 105b and / or layer 105c are color filters and / or black matrices, an attachment margin between a substrate (a substrate having an insulating surface 200) on which transistor 100 is disposed and another substrate (e.g., an opposing substrate in a display device, etc.) may be increased. Alternatively, when a black matrix is ​​disposed in layer 105b and / or layer 105c (or a portion thereof) near transistor 100, light cannot easily be incident on transistor 100. When light cannot easily be incident on transistor 100, the off-state current of transistor 100 and / or degradation of transistor 100 may be reduced. For example, as shown in FIG65B , a black matrix 652 may be disposed in a portion of layer 105b. Note that a plurality of color filters having different colors overlapping each other may be used as a black matrix. It should be noted that the color filter and / or black matrix are preferably formed using organic materials; thus, the color filter and / or black matrix are preferably formed in layer 105b. It should be noted that this embodiment is not limited thereto, and a light-blocking conductive film can be used as the black matrix. Alternatively, the thickness of layer 105c may be smaller than that of layer 105b. When the thickness of layer 105c is reduced, the electric field generated by electrode 106 can be appropriately applied to the channel. Alternatively, when the thickness of layer 105b is increased, unevenness caused by transistor 100 and the like can be appropriately reduced. Alternatively, for example, in the structures shown in Figures 1A, 1B, 2A, 3A, 3B, 9A, etc., the insulating layer 105 in region 122 may include a stack of layers 105a, 105b, and 105c, and the insulating layer 105 in region 121 may include a stack of layers 105a and 105c. Figures 26C, 26D, 27B, 28C, 28D, and 34B each illustrate such a structure. With this structure, by utilizing differences in etching sensitivity to only necessary portions (etching selectivity), a stack of layers 105a, 105b, and 105c can be obtained. Therefore, the thickness of the insulating layer 105 in each region can be easily controlled. Alternatively, regions may have different functions (e.g., planarization, impurity blocking, and light blocking) depending on film quality. Alternatively, since a portion of the layer is formed using a photosensitive material, the number of processes can be reduced. Here, layer 105a can be an inorganic insulating layer, layer 105b can be an organic insulating layer, and layer 105c can be an inorganic insulating layer. In this case, because organic materials are used, layer 105b can be thicker than both layers 105a and 105c. When layer 105a is an inorganic insulating layer (preferably a silicon nitride film), impurities in layer 105b can be prevented from entering transistor 100. Alternatively, when layer 105c is an inorganic insulating layer (preferably a silicon nitride film), impurities in layer 105b can be prevented from entering electrode 106 or layers above electrode 106. When layer 105b is an organic insulating layer, the organic insulating layer can function as a planarization layer and reduce unevenness caused by transistor 100 and the like. In this way, the surface of electrode 110 can be planarized. This can reduce display defects, for example, when electrode 110 is used as a pixel electrode. Alternatively, the thickness of layer 105b can be increased, thereby reducing pixel electrode noise. Alternatively, layers 105a and 105b can have different film qualities, or layers 105b and 105c can have different film qualities. Since etching selectivity can be varied based on film quality, only necessary areas are selectively etched, resulting in a stack of layers 105a, 105b, and 105c having a predetermined shape. Alternatively, layer 105a, layer 105b, and / or layer 105c (or a portion thereof, preferably layer 105b) may be a color filter and / or a black matrix. When layer 105a, layer 105b, and / or layer 105c is a color filter and / or a black matrix, a mounting edge for the substrate (a substrate having an insulating surface 200) on which transistor 100 is disposed and another substrate (e.g., an opposing substrate in a display device, etc.) may be increased. Alternatively, when the black matrix is ​​disposed in layer 105a, layer 105b, and / or layer 105c (or a portion thereof) near transistor 100, light is not easily incident on transistor 100. When light is not easily incident on transistor 100, the off-state current of transistor 100 and / or degradation of transistor 100 can be reduced. For example, as shown in FIG65C , a black matrix 652 may be disposed in a portion of layer 105b. It should be noted that a plurality of overlapping color filters having different colors may be used as a black matrix. It should be noted that the color filter and / or black matrix are preferably formed using organic materials; thus, the color filter and / or black matrix are preferably formed in layer 105b. It should be noted that this embodiment is not limited thereto, and a light-blocking conductive film can be used as the black matrix. It should be noted that each of the layers 105a, 105b, and 105c may be a single layer or a stack of multiple layers. This embodiment is obtained by performing changes, additions, modifications, removals, applications, higher-level conceptualizations, or lower-level conceptualizations on part or all of Embodiment 1. Thus, this embodiment can be freely combined with or replaced by another embodiment (e.g., Embodiment 1). (Example 3) In this embodiment, one aspect of a semiconductor device or the like (eg, a display device or a light-emitting device) according to the present invention is described with reference to the drawings. In the structure described in Example 1 with reference to Figures 1A, 1B, 2A, 3A, 3B, 9A, etc., the insulating layer 105 is thinned near the channel of the transistor 100. However, the scope of the region (region 121) where the insulating layer 105 is thinned is not limited thereto. The scope of region 121 may be a portion near the channel. For example, the structure shown in Figure 1A may be modified to the structure shown in Figure 66A. In Figure 66A, the scope of region 121 is a portion near the channel (the scope of region 121 in Figure 66A is smaller than the scope of region 121 in Figure 1A). The structures shown in other embodiments except Figure 1A may be modified similarly. Alternatively, the scope of region 121 may be near the entire transistor 100 or larger than the entire transistor 100. For example, the insulating layer 105 may be thinned near the transistor 100 (e.g., the region where electrode 106 overlaps with electrode 104a and / or electrode 104b). In the structures described in Example 2 with reference to Figures 1C, 1D, 2B, 3C, 3D, 9B, 26A, 26B, 27A, 28A, 28B, 34A, 26C, 26D, 27B, 28C, 28D, 34B, 65A, 65B, and 65C, layer 105b near the channel of transistor 100 is removed and insulating layer 105 is thinned. However, the area where layer 105b is removed is not limited to this. The area where layer 105b is removed can be a portion near the channel. For example, the structure shown in Figure 1C can be modified to the structure shown in Figure 66B. In Figure 66B, the scope of region 121 is a portion near the channel (the scope of region 121 in Figure 66B is smaller than the scope of region 121 in Figure 1C). The structures shown in other parts of Figure 1C can be modified in the same manner. Alternatively, region 121 may extend approximately across or beyond the entire transistor 100. For example, in the structures shown in FIG1C , FIG1D , FIG2B , FIG3C , FIG3D , FIG9B , FIG26C , FIG26D , FIG27B , FIG28C , FIG28D , or FIG34B , layer 105b near the channel of transistor 100 may be removed and insulating layer 105 may be thinned. For example, layer 105b may be removed from the region where electrode 106 overlaps with electrode 104a and / or electrode 104b. FIG1E , FIG2D , FIG2C , FIG3E , FIG2E , FIG9C , FIG26E , FIG27D , FIG27C , FIG28E , FIG27E , and FIG34C , respectively, illustrate such a structure. It should be noted that in the structures shown in Figures 26E, 27D, 27C, 28E, 27E, and 34C, one of layers 105a and 105c may be further removed from part or all of the area where layer 105b is removed. In a structure in which the insulating layer 105 is thinned near the transistor 100 (e.g., in the region where the electrode 106 overlaps with the electrode 104a and / or the electrode 104b), the capacitance value of the parasitic capacitance generated by the overlapping electrode 106 and the electrode 104a and / or the electrode 104b can be increased. In this way, the parasitic capacitance can be actively used as a storage capacitor. For example, the storage capacitor can be used as a storage capacitor in a pixel. Even when the insulating layer 105 is thinned near the transistor 100 as described above, in the case where the pixel potential is applied to the electrode 106, the potential still does not affect the potential of the electrode 104a and / or the potential of the electrode 104b. It should be noted that one aspect of the embodiment of the present invention is not limited to this. On the contrary, when a changing potential (e.g., a pulse potential) is applied to electrode 106 (e.g., a signal similar to the signal input to electrode 101 is input to electrode 106), in order to reduce the influence of the potential change applied to electrode 106 on the potential of electrode 104a and / or the potential of electrode 104b, it is preferable to thicken the insulating layer 105 between electrode 106 and electrode 104a and / or electrode 104b. For example, it is preferable that layer 105b is arranged between electrode 106 and electrode 104a and / or electrode 104b. In this way, the influence of the potential change applied to electrode 106 on the potential of electrode 104a and / or electrode 104b can be reduced. For example, noise of the signal input to electrode 110 connected to electrode 104b can be prevented. In this way, in the case of using electrode 110 as a pixel electrode, the display quality of the display device can be improved. It should be noted that one aspect of the embodiment of the present invention is not limited to this. It should be noted that the electrode 106 can be formed on the entire region 121 or at least a portion of the region 121. In the case where the electrode 106 is small, the overlap between the electrode 104a and / or the electrode 104b and the electrode 106 is small. In this way, the effect of a change in the potential applied to the electrode 106 on the potential of the electrode 104a and / or the potential of the electrode 104b can be reduced. Alternatively, in the case where a driver circuit (e.g., a scan line driver circuit or a signal line driver circuit for inputting signals to pixels) is formed using transistors 100, the entire area above the driver circuit can be area 121. For example, the entire layer 105b above the driver circuit can be removed. This is because it is not necessary to set a display element for displaying an image above the driver circuit, and it is not necessary to perform planarization using layer 105b. Alternatively, when the entire layer 105b above the driver circuit is removed, the capacitance (parasitic capacitance) formed by the electrodes or wiring can be increased. In this way, the capacitance (parasitic capacitance) used for boosting operation or the capacitance (parasitic capacitance) used for dynamic circuits can be increased. Alternatively, when the entire layer 105b above the driver circuit is removed, a portion of the edge of layer 105b is not required; thus, the layout area of ​​the entire driver circuit can be reduced. In that case, the electrodes 106 of the plurality of transistors 100 included in the driver circuit can be electrically connected to each other. Alternatively, the electrodes 106 of the plurality of transistors 100 included in the driver circuit may or may not be isolated from each other. This embodiment is obtained by performing changes, additions, modifications, removals, applications, higher-level conceptualizations, or lower-level conceptualizations on part or all of Embodiment 1 or part or all of Embodiment 2. Thus, this embodiment can be freely combined with or replaced by another embodiment (e.g., Embodiment 1 or 2). (Example 4) In this embodiment, one aspect of a semiconductor device or the like (eg, a display device or a light-emitting device) according to the present invention is described with reference to the drawings. An example of the structure of a portion where the electrode 110 and the electrode 104b are connected to each other in the semiconductor devices of Embodiments 1 to 3 will be described. An example of a structure of a portion where the electrodes 110 and 104b are connected to each other in the case of the insulating layer 105 including a stack of layers 105a and 105b will be described with reference to FIG. 4A and FIG. 4B and FIG. 5A and FIG. 5B. FIG4A illustrates the structure of FIG1C and an enlarged view of the portion of the structure where electrodes 110 and 104b are connected. In the enlarged view of FIG4A , the ends of the openings in layer 105a and the ends of the openings in layer 105b are substantially aligned with each other. For example, such openings can be formed by forming a stack of film A, which will become layer 105a, and film B, which will become layer 105b, and then etching films A and B using a photomask. The shape of the portion where electrodes 110 and 104b are connected to each other is not limited to the shape shown in the enlarged view of FIG. 4A . For example, the shape shown in FIG. 4B may be used. In FIG. 4B , the ends of the opening in layer 105a and the ends of the opening in layer 105b are not aligned with each other, and the diameter of the opening in layer 105b is larger than the diameter of the opening in layer 105a (the diameter difference between the openings is represented by Δx1 in FIG. 4B ). For example, an opening having such a shape can be formed by forming the structure shown in the enlarged view of FIG. 4A and then performing ashing on layer 105b. In the case where ashing is performed on layer 105b, an organic insulating layer is used to form layer 105b. It should be noted that ashing refers to removing a portion of a layer by chemically reacting with reactive oxygen molecules, ozone molecules, oxygen atoms, etc. generated by discharge, etc., on an organic substance layer, thereby ashing the layer. Alternatively, a stack of film A to become layer 105a and film B to become layer 105b may be formed, and films A and B may be etched using a single photomask, followed by further etching of the etched film B using a different photomask to form an opening having such a shape. Alternatively, a stack of film A to become layer 105a and film B to become layer 105b may be formed, and film B may be etched using a single photomask, followed by further etching of film A using a different photomask to form an opening having such a shape. In the case where films A and B are etched using different photomasks, for example, as shown in FIG5B , the diameter of the opening in layer 105b is significantly larger than the diameter of the opening in layer 105a compared to the structure of FIG4B (the diameter difference between the openings is represented by Δx3 in FIG5B ). Alternatively, in the case where films A and B are etched using different photomasks, for example, as shown in FIG5A , the diameter of the opening in layer 105a may be larger than the diameter of the opening in layer 105b (the diameter difference between the openings is represented by Δx2 in FIG5A ). FIG4A and FIG5A and FIG5B each illustrate an example structure of the portion where electrodes 110 and 104b are connected to each other in the case of an insulating layer 105 including a stack of layers 105a and 105b. However, the layer structure of the insulating layer 105 is not limited to this. The shape of the portion where electrodes 110 and 104b are connected to each other can vary depending on the layer structure. For example, Figures 29A and 29B each illustrate an example structure of a portion where electrodes 110 and 104b are connected to each other in the case of an insulating layer 105 including a stack of layers 105b and 105c. Figure 29A illustrates the structure of Figure 26A and an enlarged view of the portion where electrodes 110 and 104b are connected to each other in the structure. In Figure 29A, the ends of the openings in layer 105b and 105c are misaligned, and the diameter of the openings in layer 105b is larger than the diameter of the openings in layer 105c. In Figure 29B, the ends of the openings in layer 105b and 105c are misaligned, and the diameter of the openings in layer 105c is larger than the diameter of the openings in layer 105b. For example, an opening having the shape of FIG29A or FIG29B can be formed by forming a film B to be the layer 105b, etching the film B using a photomask, forming a film C to be the layer 105c, and then etching the film C using a different photomask. For example, an opening having the shape of FIG29B can be formed by forming a stack of the film B to be the layer 105b and the film C to be the layer 105c, etching the films B and C using a photomask, and then further etching the etched film C using a different photomask. It should be noted that, although not shown in Figures 29A and 29B, the ends of the openings in layer 105b and the ends of the openings in layer 105c may be substantially aligned with each other. For example, Figures 30A and 30B each illustrate an example structure of a portion where electrodes 110 and 104b are connected to each other in the case of an insulating layer 105 stacked including layers 105a, 105b, and 105c. Figure 30A illustrates the structure of Figure 26C and an enlarged view of the portion where electrodes 110 and 104b are connected to each other in the structure. In Figure 30A, the ends of the openings in layer 105a and 105b are substantially aligned with each other. The ends of the openings in layer 105a and 105b are not aligned with each other, and the diameter of each of the openings in layers 105a and 105b is larger than the diameter of the opening in layer 105c. In Figure 30B, the ends of the openings in layer 105a and 105c are substantially aligned with each other. The ends of the openings in layer 105a and the ends of the openings in layer 105c are not aligned with each other, and the diameter of the openings in layer 105b is larger than the diameter of each of the openings in layers 105a and 105c. For example, by forming a stack of film A to be layer 105a and film B to be layer 105b, etching film B and film A using a photomask to form film C to be layer 105c, and then etching film C using a different photomask, an opening having the shape of Figure 30A can be formed. For example, by forming a stack of film A to be layer 105a and film B to be layer 105b, etching film B using a photomask to form film C to be layer 105c, and then etching film C and film A using different photomasks, an opening having the shape of Figure 30B can be formed. It should be noted that, although not shown in Figures 30A and 30B, the ends of the openings in layer 105a, the ends of the openings in layer 105b, and the ends of the openings in layer 105c may be aligned with each other. Alternatively, a structure can be used in which the ends of the opening in layer 105a, the ends of the opening in layer 105b, and the ends of the opening in layer 105c are not aligned with each other. In that case, the ends of layer 105a can be covered by layer 105b. The ends of layer 105b may or may not be covered by layer 105c. It should be noted that in each of the structures shown in Figures 4A and 4B and Figures 5A and 5B, the taper angle of the end of the opening in layer 105a (denoted by θ2 in Figures 4A and 4B and Figures 5A and 5B) can be substantially the same as or different from the taper angle of the end of the opening in layer 105b (denoted by θ1 in Figures 4A and 4B and Figures 5A and 5B). In the structure shown in Figures 29A and 29B, the taper angle of the end of the opening in layer 105b (denoted by θ1 in Figures 29A and 29B) can be substantially the same as or different from the taper angle of the end of the opening in layer 105c (denoted by θ3 in Figures 29A and 29B). In the structure shown in Figures 30A and 30B, the taper angle of the end of the opening in layer 105a (represented by θ2 in Figures 30A and 30B), the taper angle of the end of the opening in layer 105b (represented by θ1 in Figures 30A and 30B), and the taper angle of the end of the opening in layer 105c (represented by θ3 in Figures 30A and 30B) can all be substantially the same, two of the taper angles can be substantially the same, or all of the taper angles can be different from each other. For example, when layer 105b is thick, θ1 is preferably small so that the end of layer 105b can be as smooth as possible. For example, θ2 is preferably greater than θ1. Furthermore, θ3 is preferably greater than θ1. It should be noted that one aspect of the present invention is not limited to this. Here, the taper angle of a layer tip is the angle formed by the side surface of the layer tip (the tangent at the lower end) and the bottom surface of the layer when the layer is viewed in a cross-sectional direction. The taper angle of each layer can be controlled by controlling the thickness and material of each layer, the etching conditions used to form the opening in each layer, and so on. Note that Figures 4A and 4B, 5A and 5B, 29A and 29B, and 30A and 30B illustrate examples of the structure of the portion where the electrodes 110 and 104b are connected to each other in the structures shown in Figures 1C, 26A, and 26C. However, similar structures can be used in the portion where the electrodes 110 and 104b are connected to each other in the semiconductor device in Examples 1 to 3 having other structures. Each of the structural examples of the portion where the electrodes 110 and 104b are connected to each other in Figures 4A and 4B, Figures 5A and 5B, Figures 29A and 29B, and Figures 30A and 30B can be used as a structure where a given electrode provided below the insulating layer 105 is electrically connected to a given electrode provided above the insulating layer 105 via an opening formed in the insulating layer 105. For example, each of the structural examples of the portion where the electrodes 110 and 104b are connected to each other in Figures 4A and 4B, Figures 5A and 5B, Figures 29A and 29B, and Figures 30A and 30B can also be used as a structure where an electrode formed using the same layer as the electrode 110 is connected to an electrode formed using the same layer as the electrode 104b. For example, any of the structural examples of the portion where the electrodes 110 and 104b are connected to each other in Figures 4A and 4B, Figures 5A and 5B, Figures 29A and 29B, and Figures 30A and 30B can be used as the structure of the portion where the electrode 110 or an electrode formed on the same layer as the electrode 110 is connected to the electrode 101, or an electrode formed on the same layer as the electrode 101 is used. For example, any of the structural examples of the portion where the electrodes 110 and 104b are connected to each other in Figures 4A and 4B, Figures 5A and 5B, Figures 29A and 29B, and Figures 30A and 30B can be used as the structure of the portion where the electrode 106 or an electrode formed on the same layer as the electrode 106 is connected to the electrode 101, or an electrode formed on the same layer as the electrode 101 is used. For example, each of the structural examples of the portions where electrodes 110 and 104b are connected to each other in Figures 4A and 4B, Figures 5A and 5B, Figures 29A and 29B, and Figures 30A and 30B can be used as the structure of the portion where electrode 106 or an electrode system formed using the same layer as electrode 106 is connected to electrode 104b or an electrode formed using the same layer as electrode 104b. This embodiment is obtained by performing changes, additions, modifications, removals, applications, higher-level conceptualizations, or lower-level conceptualizations on part or all of Embodiment 1, part or all of Embodiment 2, or part or all of Embodiment 3. Thus, this embodiment can be freely combined with or replaced by another embodiment (e.g., any one of Embodiments 1 to 3). (Example 5) In this embodiment, an example of electrical connection between the electrode 106 of the transistor 100 and different electrodes or wiring is described. Note that in the drawings, the same reference numerals are used to indicate the same parts as those in any of the drawings of the above embodiments, and their description is omitted. For example, electrode 106 can be electrically connected to electrode 101. With this connection, the same potential as electrode 101 can be supplied to electrode 106. This can increase the on-state current of transistor 100. Figures 6A to 6E, 7A to 7E, 8A to 8E, 9D and 9E, 31A to 31E, 32A to 32E, 33A to 33E, and 34D and 34E each illustrate an example of electrically connecting electrode 106 to electrode 101. Note that the electrical connections between electrodes 106 and 101 in these figures can be similar to those in the various figures of Examples 1 to 4. It should be noted that in the case where the transistor 100 is arranged in a pixel and forms a pixel matrix composed of a plurality of pixels, an opening can be formed for each pixel so that the electrode 106 can be electrically connected to the electrode 101. Therefore, the contact resistance or wiring resistance can be reduced. Another option is to form an opening for each of the plurality of pixels so that the electrode 106 can be electrically connected to the electrode 101. Therefore, the layout area can be reduced. Another option is that the electrode 106 can be electrically connected to the electrode 101 in the pixel matrix area or outside the pixel matrix area. When the electrode 106 is electrically connected to the electrode 101 outside the pixel matrix area, the layout area in the pixel matrix area can be reduced. Therefore, the aperture ratio can be increased. It should be noted that in the case where the driver circuit is arranged outside the pixel matrix area, it is better for the electrode 106 to be electrically connected to the electrode 101 in the area between the driver circuit and the pixel matrix area. Alternatively, for example, electrode 106 may be electrically connected to electrode 104a or electrode 104b. With this connection, the same potential as electrode 104a or electrode 104b can be supplied to electrode 106. Figures 13A to 13E, Figures 14A to 14E, Figures 15A to 15E, Figures 38A to 38E, Figures 39A to 39E, and Figures 40A to 40E each illustrate an example in which electrode 106 is connected to electrode 104b. It should be noted that the electrical connections between electrode 106 and electrode 104a or electrode 104b in these figures can be similar to those in the various figures of Examples 1 to 4. It should be noted that in the case where the transistor 100 is disposed in a pixel and forms a pixel matrix composed of a plurality of pixels, an opening can be formed for each pixel so that the electrode 106 can be electrically connected to the electrode 104b. Alternatively, an opening can be formed for each of the plurality of pixels so that the electrode 106 can be electrically connected to the electrode 104b. Alternatively, the electrode 106 can be electrically connected to the electrode 104b within or outside the pixel matrix region. In this manner, as in the above-described example, contact resistance or wiring resistance can be reduced and / or the layout area can be reduced. Alternatively, for example, electrode 106 can be electrically connected to electrodes 104b and 110. With this connection, the same potential as electrodes 104b and 110 can be supplied to electrode 106. Figures 16A to 16E, Figures 17A to 17E, Figures 18A to 18E, Figures 41A to 41E, Figures 42A to 42E, and Figures 43A to 43E each illustrate an example in which electrode 106 is connected to electrodes 104b and 110. It should be noted that in the structures of these figures, electrodes 110 and 106 are formed using a conductive film, and electrodes 110 and 106 are collectively referred to as electrodes 110. While examples in which electrodes 110 and 106 are formed using a conductive film are described, this embodiment is not limited thereto. Electrodes 110 and 106 can be formed by etching different conductive films. Alternatively, electrodes 110 and 106 can be brought into contact with each other to be electrically connected. It should be noted that the electrical connections between the electrode 106 and the electrodes 104b and 110 in these figures may be similar to those in the various figures of Examples 1-4. Alternatively, for example, the electrode 106 may be electrically connected to the electrode 101a formed using the same layer as the electrode 101. Here, the electrodes 101 and 101a can be formed by etching a conductive film using a mask (photomask). That is, the electrodes 101 and 101a are patterned simultaneously. Thus, for example, the electrodes 101 and 101a have substantially the same material and thickness. Figures 10A to 10E, Figures 11A to 11E, Figures 12A to 12E, Figures 35A to 35E, Figures 36A to 36E, and Figures 37A to 37E each illustrate an example of the electrode 106 being connected to the electrode 101a. It should be noted that the electrical connections between the electrode 106 and the electrode formed using the same layer as the electrode 101 in these figures may be similar to those in the various figures of Examples 1 to 4. It should be noted that in the case where the transistor 100 is arranged in a pixel and forms a pixel matrix composed of a plurality of pixels, an opening can be formed for each pixel so that the electrode 106 can be electrically connected to the electrode 101a. Alternatively, an opening can be formed for a plurality of pixels so that the electrode 106 can be electrically connected to the electrode 101a. Alternatively, the electrode 106 can be electrically connected to the electrode 101a in the pixel matrix area or outside the pixel matrix area. For example, the electrode 101a can be a capacitor line arranged in the pixel matrix. By overlapping with different wirings, electrodes, conductive layers, etc. and having an insulating layer arranged therebetween, the capacitor line forms a capacitor such as a storage capacitor. Alternatively, the electrode 101a can be a gate signal line of different gate signal lines arranged in different pixels or the same pixel. Alternatively, for example, electrode 106 may be electrically connected to electrode 104c formed using the same layer as electrode 104a or electrode 104b. Here, electrodes 104a, 104b, and 104c may be formed by etching a conductive film using a mask (photomask). That is, electrodes 104a, 104b, and 104c are patterned simultaneously. Thus, for example, electrodes 104a, 104b, and 104c have substantially the same material and thickness. Figures 23A to 23E, Figures 24A to 24E, Figures 25A to 25E, Figures 49A to 49E, Figures 50A to 50E, and Figures 51A to 51E each illustrate an example of electrode 106 being connected to electrode 104c. Note that in Figures 25A to 25E and Figures 51A to 51E , the semiconductor layer 103a formed using the same layer as the semiconductor layer 103 is provided below the electrode 104c. Note that the electrical connections between the electrode 106 and the electrode formed using the same layer as the electrode 104a or the electrode 104b in these figures can be similar to those in the various figures of Examples 1 to 4. It should be noted that in the case where the transistor 100 is arranged in a pixel and forms a pixel matrix composed of a plurality of pixels, an opening can be formed for each pixel so that the electrode 106 can be electrically connected to the electrode 104c. Alternatively, an opening can be formed for each of the plurality of pixels so that the electrode 106 can be electrically connected to the electrode 104c. Alternatively, the electrode 106 can be electrically connected to the electrode 104c in the pixel matrix area or outside the pixel matrix area. For example, the electrode 104c can be a capacitor line arranged in the pixel matrix. By overlapping with different wirings, electrodes, conductive layers, etc. and having an insulating layer arranged therebetween, the capacitor line forms a capacitor such as a storage capacitor. Alternatively, the electrode 104c can be a signal line or a power supply line arranged in different pixels or different signal lines or different power supply lines in the same pixel. Here, in the case where the electrode 101a or the electrode 104c is a capacitor line, the following structure can be used. A capacitor line may be used to electrically connect the electrodes 106 of the transistors 100 in each pixel column (or pixel row) of the pixel matrix and each pixel column (or pixel row) to the capacitor line provided in the pixel column (or pixel row). Alternatively, a capacitor line may be used to electrically connect the electrodes 106 of the transistors 100 in each pixel column (or pixel row) of the pixel matrix and each pixel column (or pixel row) to the capacitor line provided in the pixel column (or pixel row) adjacent to the pixel column (or pixel row). Note that, in the case where a pixel of the pixel matrix includes a plurality of sub-pixels, a capacitor line may be used to electrically connect the electrode 106 of the transistor 100 disposed in each sub-pixel column (or each sub-pixel row) and each sub-pixel column (or each sub-pixel row) to the capacitor line disposed in the sub-pixel column (or sub-pixel row). Alternatively, in the case where a pixel of the pixel matrix includes a plurality of sub-pixels, a capacitor line may be used to electrically connect the electrode 106 of the transistor 100 disposed in each sub-pixel column (or each sub-pixel row) and each sub-pixel column (or each sub-pixel row) to the capacitor line disposed in the pixel column (or pixel row). Alternatively, in the case where a pixel of the pixel matrix includes a plurality of sub-pixels, a capacitor line may be used to electrically connect the electrode 106 of the transistor 100 disposed in each sub-pixel column (or each sub-pixel row) and each sub-pixel column (or each sub-pixel row) to the capacitor line disposed in the sub-pixel column (or sub-pixel row) adjacent to the sub-pixel column (or sub-pixel row). Multiple capacitor lines can be combined into a single capacitor line. For example, a capacitor line can be shared between adjacent pixels (or sub-pixels). This can reduce the number of capacitor lines. It should be noted that, in the case where electrode 106 of transistor 100 is electrically connected to a capacitor line, a fixed potential (preferably a potential equal to or lower than the lowest potential applied to electrode 101) can be applied to the capacitor line. In this way, the threshold voltage of transistor 100 can be controlled so that transistor 100 can be properly turned off. Furthermore, noise input to electrode 110 due to capacitive coupling with electrode 101, electrode 104a, and so on can be prevented. Note that, when electrode 106 of transistor 100 is electrically connected to a capacitor line, a pulse signal can be supplied to the capacitor line. For example, when performing common inversion driving, in some cases, the potential of the opposing electrode and the potential of the capacitor line are changed with the same amplitude. Even in such a case, when a low potential is supplied to electrode 106 to turn off transistor 100, the threshold voltage of transistor 100 can still be controlled so that transistor 100 can be normally turned off. It should be noted that, in the case where the electrode 106 of the transistor 100 is electrically connected to the capacitor line, it is preferred that the semiconductor layer 103 is not disposed between a pair of electrodes of the capacitor (one of which is the capacitor line). It should be noted that the electrode 101a or the electrode 104c is not limited to a capacitor line, but can be a different wiring. For example, the electrode 101a or the electrode 104 can be a power supply line, an initialization wiring, etc. For example, the electrode 101a or the electrode 104 can be a wiring provided in a pixel circuit of a display device including an EL element (e.g., an organic light-emitting element). Alternatively, the electrode 101a or the electrode 104 can be a wiring provided in a driver circuit (e.g., a scan line driver circuit or a signal line driver circuit in a display device). This embodiment is obtained by performing changes, additions, modifications, removals, applications, higher-level conceptualizations, or lower-level conceptualizations on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, or part or all of Embodiment 4. Thus, this embodiment can be freely combined with or replaced by another embodiment (e.g., any one of Embodiments 1 to 4). (Example 6) In this embodiment, an example of electrical connection between electrode 101 of transistor 100 (or an electrode formed using the same layer as electrode 101) and electrode 104a or electrode 104b of transistor 100 (or an electrode formed using the same layer as electrode 104a or electrode 104b) is described with reference to Figures 19A to 19D, Figures 44A to 44D, and Figures 45A to 45D. Note that in the drawings, the same reference numerals are used to indicate the same parts as those in any of the drawings of the above-mentioned embodiments, and their description is omitted. 19A to 19D each illustrate an example of electrical connection between an electrode 101a formed using the same layer as the electrode 101 of the transistor 100 and an electrode 104c formed using the same layer as the electrode 104a or the electrode 104b in the case of an insulating layer 105 including layers 105a and 105b. In the structure shown in FIG. 19A , electrode 110 b , electrode 104 c and electrode 101 a are electrically connected to each other via opening 191 formed in layers 105 a and 105 b and opening 192 formed in insulating layer 102 and layers 105 a and 105 b . 19B , electrode 104c and electrode 101a are electrically connected to each other via electrode 110b formed in opening 193 in layer 105a and opening 194 in insulating layer 102 and layer 105a. That is, layer 105b is not provided in portion 109 where electrodes 104c and 101a are connected to each other. Note that layer 105b is not necessarily omitted from the entire portion where electrodes 104c and 101a are connected. For example, in the structure shown in FIG19C or FIG19D, layer 105b may be provided in a portion of portion 109 where electrodes 104c and 101a are connected. In the structure shown in FIG. 19C , electrodes 104c and 101a are electrically connected to each other via electrode 110b formed through opening 195 in layer 105a and opening 196 formed in insulating layer 102 and layers 105a and 105b. In the structure shown in FIG. 19D , electrodes 104c and 101a are electrically connected to each other via electrode 110b formed through openings 197 in layers 105a and 105b and openings 198 formed in insulating layer 102 and layer 105a. 44A to 44D each illustrate an example of electrical connection between an electrode 101a formed using the same layer as the electrode 101 of the transistor 100 and an electrode 104c formed using the same layer as the electrode 104a or the electrode 104b in the case of an insulating layer 105 including layers 105b and 105c. In the structure shown in FIG. 44A , the electrode 110 b , the electrode 104 c , and the electrode 101 a are electrically connected to each other via the opening 441 formed in the layers 105 b and 105 c and the opening 442 formed in the insulating layer 102 and the layers 105 b and 105 c . In the structure shown in FIG44B, electrode 104c and electrode 101a are electrically connected to each other via electrode 110b formed in opening 443 in layer 105c and opening 444 in insulating layer 102 and layer 105c. In other words, layer 105b is not provided in portion 109 where electrodes 104c and 101a are connected to each other. Note that layer 105b need not necessarily be omitted from the entire portion where electrodes 104c and 101a are connected. For example, in the structure shown in FIG44C or FIG44D, layer 105b may be provided in a portion of portion 109 where electrodes 104c and 101a are connected. In the structure shown in FIG. 44C , electrodes 104c and 101a are electrically connected to each other via electrode 110b through opening 445 formed in layer 105c and opening 446 formed in insulating layer 102 and layers 105b and 105c. In the structure shown in FIG. 44D , electrodes 104c and 101a are electrically connected to each other via electrode 110b through openings 447 formed in layers 105b and 105c and openings 448 formed in insulating layer 102 and layer 105c. Next, Figures 45A to 45D each illustrate an example of electrical connection between an electrode 101a formed using the same layer as the electrode 101 of the transistor 100 and an electrode 104c formed using the same layer as the electrode 104a or the electrode 104b in the case of an insulating layer 105 including layers 105a, 105b and 105c. In the structure shown in FIG. 45A , the electrode 110b, the electrode 104c and the electrode 101a are electrically connected to each other via the opening 451 formed in the layers 105a , 105b , and 105c and the opening 452 formed in the insulating layer 102 and the layers 105a , 105b , and 105c. In the structure shown in FIG45B, electrode 104c and electrode 101a are electrically connected to each other via electrode 110b formed through openings 453 formed in layers 105a and 105c and openings 454 formed in insulating layer 102 and layers 105a and 105c. In other words, layer 105b is not provided in portion 109 where electrodes 104c and 101a are connected to each other. Note that layer 105b need not necessarily be omitted from the entire portion where electrodes 104c and 101a are connected. For example, in the structure shown in FIG45C or FIG45D, layer 105b may be provided in a portion of portion 109 where electrodes 104c and 101a are connected. In the structure shown in FIG. 45C , electrodes 104c and 101a are electrically connected to each other via electrode 110b through openings 455 formed in layers 105a and 105c and openings 456 formed in insulating layer 102 and layers 105a , 105b , and 105c . In the structure shown in FIG. 45D , electrodes 104c and 101a are electrically connected to each other via electrode 110b through openings 457 formed in layers 105a , 105b , and 105c and openings 458 formed in insulating layer 102 and layers 105a and 105c . Each of the connections between electrodes 104c and 101a in this embodiment can be used, for example, as the connection between electrode 104b and electrode 101 in the case of diode-connected transistor 100. Diode-connected transistors can be used in protection circuits, driver circuits, and the like. Alternatively, the connection between electrodes 104c and 101a can also be used when the gate electrode is connected to the source electrode or the drain electrode. For example, in a pixel circuit or driver circuit in which one pixel includes a plurality of transistors, the connection between electrodes 104c and 101a is used when the gate electrode is connected to the source electrode or the drain electrode. For example, in a pixel circuit in which a pixel includes an EL element (e.g., an organic light-emitting element), in some cases, a plurality of transistors are provided and the gate electrode is connected to the source electrode or the drain electrode. Alternatively, a plurality of transistors are also provided in the circuit for driving the gate line. In addition, the openings 191 to 198 of Figures 19A to 19D, the openings 441 to 448 of Figures 44A to 44D, and the openings 451 to 458 of Figures 45A to 45D may have shapes similar to the shapes of the openings described in Example 4 with reference to Figures 4A and 4B, Figures 5A and 5B, Figures 29A and 29B, and Figures 30A and 30B. It should be noted that the electrodes 104c and 101a may be connected to each other without using the electrode 110b. For example, the electrodes 104c and 101a may be directly connected to each other through a contact hole formed in the insulating layer 102. This embodiment is obtained by performing changes, additions, modifications, removals, applications, higher-level conceptualizations, or lower-level conceptualizations on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, part or all of Embodiment 4, or part or all of Embodiment 5. Thus, this embodiment can be freely combined with or replaced by another embodiment (e.g., any one of Embodiments 1 to 5). (Example 7) In this embodiment, examples of a structure for increasing the parasitic capacitance of transistor 100 and a structure for increasing the capacitance of a capacitor electrically connected to transistor 100 are described with reference to Figures 20A to 20D, Figures 21A to 21D, Figures 46A to 46D, and Figures 47A to 47D. Note that in the drawings, the same reference numerals are used to indicate the same parts as those in any of the drawings of the above-described embodiments, and their descriptions are omitted. Note that each of Figures 20A to 20D and Figures 21A to 21D uses a stack of layers 105a and 105b as an example of the insulating layer 105. Each of Figures 46A to 46C and Figures 47B and 47C uses a stack of layers 105b and 105c as an example of the insulating layer 105. Each of Figures 46B to 46D and Figures 47A to 47D uses a stack of layers 105a, 105b, and 105c as an example of the insulating layer 105. In Figures 20A to 20D, 21A to 21D, 46A to 46D, and 47A to 47D, the entire layer 105b above the electrode 104b or a large portion of the layer 105b above the electrode 104b is removed, and the capacitance value of the parasitic capacitance (or the capacitance value of the capacitor including the electrode 104b and the electrode 106) is large. In Figures 20A to 20D, 21A to 21D, 46A to 46D, and 47A to 47D, for example, parasitic capacitance and / or a capacitor is formed in the portion 281 surrounded by the dotted line. The capacitance value can be adjusted by appropriately determining the shapes of the electrodes 104b and 106, the extent to which the layer 105b above the electrode 104b is removed, and the like. 20A to 20D , 21A to 21D , 46A to 46D , and 47A to 47D , parasitic capacitance is also generated between electrodes 104b and 101 and / or a capacitor including electrodes 104b and 101 may be formed. The capacitance value can be adjusted by appropriately determining the shapes of electrodes 104b and 101. In this way, the capacitance between the gate and source of transistor 100 can be increased. Alternatively, a capacitor with a large capacitance value can be formed. For example, in the case where transistor 100 is used in a circuit that performs a boost operation, it is preferable to increase the capacitance between the gate and source. Alternatively, when a signal is held in a capacitor in a dynamic circuit, a large capacitor is preferable. In this way, it is preferable to use transistor 100 having the structures shown in Figures 20A to 20D, Figures 21A to 21D, Figures 46A to 46D, and Figures 47A to 47D. This embodiment is obtained by performing changes, additions, modifications, removals, applications, higher-level conceptualizations, or lower-level conceptualizations on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, part or all of Embodiment 4, part or all of Embodiment 5, or part or all of Embodiment 6. Thus, this embodiment can be freely combined with or replaced by another embodiment (e.g., any one of Embodiments 1 to 6). (Example 8) In this embodiment, a structural example of a capacitor included in a semiconductor device (e.g., a display device or a light-emitting device) is described with reference to FIG22A to FIG22E and FIG48A to FIG48E. Note that in the drawings, the same reference numerals are used to indicate the same parts as those in the drawings of any of the above embodiments, and their description is omitted. Note that each of Figures 22A to 22E uses a stack of layers 105a and 105b as an example of the insulating layer 105. Figures 48A to 48C each use a stack of layers 105b and 105c as an example of the insulating layer 105. Figures 48B, 48D, and 48E each use a stack of layers 105a, 105b, and 105c as an example of the insulating layer 105. It is possible to form a capacitor having electrode 101a formed using the same layer as electrode 101 as one electrode and electrode 104c formed using the same layer as electrode 104a as the other electrode. Figures 22A and 22B each illustrate such an example. In Figures 22A and 22B, for example, the capacitor is formed in the portion 282 surrounded by the dotted line. It should be noted that electrode 106a is formed using the same layer as electrode 106. Although Figures 22A and 22B each illustrate an example in which electrode 106a is electrically connected to electrode 104c, one aspect of an embodiment of the present invention is not limited to this. Electrode 106a is not necessarily electrically connected to electrode 104c. Electrode 106a may be electrically connected to electrode 101a or to both electrodes 101a and 104c. Alternatively, electrode 106a is not necessarily provided above portion 282. A capacitor can be formed with electrode 101a formed using the same layer as electrode 101 as one electrode and electrode 106a as the other electrode. Figures 22C to 22E and 48A to 48E each illustrate such an example. In Figures 22C to 22E and 48A to 48E, for example, a capacitor is formed in portion 283 surrounded by a dotted line. It should be noted that Figure 22D corresponds to a structure in which a portion of layer 105b is removed from Figure 22C. In the structure shown in Figure 22D, layer 105b in region 121c is not provided. In addition, Figure 22E corresponds to a structure in which layer 105b is removed by a width wider than the width of electrode 101a in Figure 22D (in the horizontal direction in the figure). Moreover, Figures 48C and 48D each illustrate a structure in which a portion of layer 105b is removed from Figure 48A or Figure 48B. In each of the structures shown in Figures 48C and 48D, layer 105b in region 121c is not provided. Figure 48E corresponds to a structure in which layer 105b is removed by a width wider than the width of electrode 101a in Figure 48D (in the horizontal direction in the figure). Note that in Figures 22A to 22E and Figures 48A to 48E, electrode 106a may be electrode 106, electrode 110, or an electrode formed using the same layer as electrode 110. Electrode 101a may be electrode 101. Electrode 104c may be electrode 104. Note that each of the capacitors illustrated in Figures 22A to 22E and Figures 48A to 48E can be used as a capacitor provided between the gate and source of transistor 100. Alternatively, for example, each of the capacitors illustrated in Figures 22A to 22E and Figures 48A to 48E can be used as a storage capacitor provided in a pixel. Alternatively, each of the capacitors illustrated in Figures 22A to 22E and Figures 48A to 48E can be used as a capacitor for holding a signal in a driver circuit. This embodiment is obtained by performing changes, additions, modifications, removals, applications, higher-level conceptualizations, or lower-level conceptualizations on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, part or all of Embodiment 4, part or all of Embodiment 5, part or all of Embodiment 6, or part or all of Embodiment 7. Thus, this embodiment can be freely combined with or replaced by another embodiment (e.g., any one of Embodiments 1 to 7). (Example 9) In this embodiment, examples of materials for the insulating layer, electrode, semiconductor layer, etc. of Embodiments 1 to 8 are described. The following describes the material of the semiconductor layer 103 in the transistor 100. Note that similar materials can be used for semiconductor layers formed using the same layer as the semiconductor layer 103. The semiconductor layer 103 in the transistor 100 may include a layer containing an oxide semiconductor (oxide semiconductor layer). For example, a tetrametallic oxide, such as an In-Sn-Ga-Zn-O-based oxide semiconductor, a trimetallic oxide, such as an In-Ga-Zn-O-based oxide semiconductor, an In-Sn-Zn-O-based oxide semiconductor, an In-Al-Zn-O-based oxide semiconductor, a Sn-Ga-Zn-O-based oxide semiconductor, an Al-Ga-Zn-O-based oxide semiconductor, a Sn-Al-Zn-O-based oxide semiconductor, or an Hf-In-Zn-O-based oxide semiconductor, or a dimetallic oxide. As the oxide semiconductor, a metal semiconductor such as an In-Zn-O-based oxide semiconductor, a Sn-Zn-O-based oxide semiconductor, an Al-Zn-O-based oxide semiconductor, a Zn-Mg-O-based oxide semiconductor, a Sn-Mg-O-based oxide semiconductor, an In-Mg-O-based oxide semiconductor, or an In-Ga-O-based oxide semiconductor, or a single metal oxide such as an In-O-based oxide semiconductor, a Sn-O-based oxide semiconductor, or a Zn-O-based oxide semiconductor can be used. In addition, the oxide semiconductor may contain elements other than In (indium), Ga (gallium), Sn (tin), and Zn (zinc), such as SiO 2. For example, an In-Sn-Zn-O-based oxide semiconductor refers to an oxide semiconductor containing indium (In), tin (Sn), and zinc (Zn), and the composition ratio is not limited. For example, an In-Ga-Zn-O-based oxide semiconductor refers to an oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn), and the composition ratio is not limited. An In-Ga-Zn-O-based oxide semiconductor may be referred to as IGZO. The oxide semiconductor layer can be formed using an oxide semiconductor film. In the case of forming an In-Sn-Zn-O-based oxide semiconductor by sputtering, a target having a composition ratio (atomic ratio) of In:Sn:Zn = 1:2:2, 2:1:3, 1:1:1, 20:45:35, etc. is used. In the case of forming an In-Zn-O based oxide semiconductor by sputtering, the target material has a composition ratio of In:Zn = 50:1 to 1:2 (atomic ratio) (In 2O 3: ZnO = 25:1 to 1:4 (molar ratio)), In: Zn = 20:1 to 1:1 (atomic ratio) (In 2O 3: ZnO = 10:1 to 1:2 (molar ratio)) preferably, In: Zn = 1.5:1 to 15:1 (atomic ratio) (In 2O 3:ZnO=3:4 to 15:2 (molar ratio)) is better. For example, when the target has an atomic ratio of In:Zn:O= X: Y: At Z, Z>1.5 X+ Y. In the case of forming an In—Ga—Zn—O-based oxide semiconductor by sputtering, the target may have a composition ratio of In:Ga:Zn=1:1:0.5, 1:1:1, or 1:1:2 (atomic ratio). When the purity of the target material is set to 99.99% or higher, the amount of alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxide, hydrides, etc. mixed into the oxide semiconductor film can be reduced. In addition, by using the target material, the concentration of alkali metals such as lithium, sodium, or potassium in the oxide semiconductor film can be reduced. It should be noted that oxide semiconductors are not sensitive to impurities and have no problem even when a considerable amount of metal impurities is contained in the film. Moreover, it is possible to use amorphous oxide semiconductors containing a large amount of alkaline metals such as sodium (Na) and inexpensive soda lime (Kamiya, Nomura, and Hosono, "Carrier Transport Characteristics and Electronic Structure of Amorphous Oxide Semiconductors: Current Status"). (KOTAI BUTSURI (Solid State Physics), 2009, Vol. 44, pp. 621-633). However, this consideration is not appropriate. Alkali metals are not elements included in oxide semiconductors and are therefore impurities. In the case where alkaline earth metals are not included in oxide semiconductors, alkaline earth metals are also impurities. When the insulating film in contact with the oxide semiconductor layer is an oxide and Na diffuses into the insulating film, the alkaline metal, especially Na, becomes Na. + . In addition, in the oxide semiconductor layer, Na cuts or enters the bond between the metal and oxygen included in the oxide semiconductor. As a result, for example, degradation of the characteristics of the transistor such as the normal on state of the transistor due to the displacement of the critical voltage in the negative direction or a reduction in mobility occurs. Characteristic changes also occur. When the hydrogen concentration in the oxide semiconductor layer is sufficiently low, the characteristic changes and degradation of the characteristics of the transistor due to impurities are significant. Thus, when the hydrogen concentration in the oxide semiconductor layer is 1×10 18 / cm 3 or lower, 1×10 17 / cm 3 or lower, it is better to reduce the impurity concentration. In particular, the Na concentration measured by secondary ion mass spectrometry is 5×10 16 / cm 3 or less is better, 1×10 16 / cm 3 or less is better, 1×10 15 / cm 3 Likewise, the measured value of Li(lithium) concentration is 5×10 15 / cm 3 or less is better, 1×10 15 / cm 3 Likewise, the measured value of K (potassium) concentration is 5×10 15 / cm 3 or less is better, 1×10 15 / cm 3 Or less is better. It should be noted that the oxide semiconductor layer may be amorphous or crystalline. The oxide semiconductor layer may be single crystal or non-single crystal. In the case of non-single crystal, the oxide semiconductor layer may be amorphous or polycrystalline. In addition, the oxide semiconductor may have an amorphous structure including a crystalline portion or may be amorphous. Regarding the oxide semiconductor layer, an oxide including a crystal with c-axis alignment (also referred to as a c-axis aligned crystal (CAAC)) can be used, wherein the CAAC has a phase having a triangular, hexagonal, regular triangular, or regular hexagonal atomic order when viewed from a direction perpendicular to the ab plane, and wherein metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when viewed from a direction perpendicular to the c-axis direction. CAAC is described in detail with reference to Figures 69A to 69E, Figures 70A to 70C, and Figures 71A to 71C. It should be noted that in Figures 69A to 69E, Figures 70A to 70C, and Figures 71A to 71C, the vertical direction corresponds to the c-axis direction and the plane perpendicular to the c-axis direction corresponds to the ab plane, unless otherwise specified. When the terms "upper half" and "lower half" are simply used, they refer to the upper half above the ab plane and the lower half below the ab plane (the upper and lower halves with respect to the ab plane). In addition, in Figures 69A to 69E, O (oxygen) atoms surrounded by circles represent four-coordinate O atoms, while O atoms surrounded by double circles represent three-coordinate O atoms. Figure 69A illustrates a structure consisting of one six-coordinate In (indium) atom and six four-coordinate oxygen atoms (hereinafter referred to as four-coordinate O atoms) proximal to the In atom. Here, the structure illustrating only one In atom and the oxygen atoms proximal to the In atom is referred to as a subunit. The structure of Figure 69A is actually an octahedral structure, but for simplicity of illustration, it is depicted as a planar structure. Note that three four-coordinate O atoms are present in each of the upper and lower halves of Figure 69A. The charge in the subunit shown in Figure 69A is zero. Figure 69B illustrates a structure consisting of a five-coordinate Ga (gallium) atom, three three-coordinate oxygen atoms (hereinafter referred to as three-coordinate O atoms) proximal to the Ga atom, and two four-coordinate O atoms proximal to the Ga atom. All three-coordinate O atoms are located on the ab plane. One four-coordinate O atom is present in each of the upper and lower halves of Figure 69B. In atoms can have the structure shown in Figure 69B because they can have five ligands. In the subunit shown in Figure 69B, the charge is zero. Figure 69C illustrates a structure including one tetrahedral Zn (zinc) atom and four tetrahedral O atoms adjacent to the Zn atom. In Figure 69C , one tetrahedral O atom is located in the upper half, while three tetrahedral O atoms are located in the lower half. Alternatively, in Figure 69C , three tetrahedral O atoms may be located in the upper half, while one tetrahedral O atom may be located in the lower half. The charge in the subunit shown in Figure 69C is zero. Figure 69D illustrates a structure including one hexa-coordinate Sn (tin) atom and six tetra-coordinate O atoms adjacent to the Sn atom. In Figure 69D, three tetra-coordinate O atoms are present in each of the upper and lower halves. In the subunit shown in Figure 69D, the charge is +1. Figure 69E illustrates a subunit including two Zn atoms. In Figure 69E, one four-coordinate O atom is present in each of the upper and lower halves. In the subunit shown in Figure 69E, the charge is -1. Here, a group of certain subunits is referred to as a group, and some of the group is referred to as a unit. Here, the rules for combining subunits are explained. In Figure 69A , the three O atoms in the upper half of the six-coordinate In atom each have three neighboring In atoms facing downward, and the three O atoms in the lower half each have three neighboring In atoms facing upward. In Figure 69B , the one O atom in the upper half of the five-coordinate Ga atom each has one neighboring Ga atom facing downward, and the one O atom in the lower half each has one neighboring Ga atom facing upward. In Figure 69C , the one O atom in the upper half of the four-coordinate Zn atom each has one neighboring Zn atom facing downward, and the three O atoms in the lower half each have three neighboring Zn atoms facing upward. In this way, the number of four-coordinate O atoms above a metal atom equals the number of neighboring metal atoms below it. Similarly, the number of four-coordinate O atoms below a metal atom equals the number of neighboring metal atoms above it. Because the coordinate number of an O atom is 4, the sum of the number of adjacent metal atoms below the O atom and the number of adjacent metal atoms above the O atom is 4. Therefore, when the sum of the number of four-coordinate O atoms above a metal atom and the number of four-coordinate O atoms below another metal atom is 4, two subunits including metal atoms can be bonded to each other. For example, in the case of a six-coordinate metal (In or Sn) atom bonded via three four-coordinate O atoms in the upper half, the six-coordinate metal atom is bonded to a five-coordinate metal (Ga or In) atom or a four-coordinate metal (Zn) atom. Metal atoms with the aforementioned number of coordinates are bonded to other metal atoms via four O atoms in the c-axis direction. Furthermore, the subunits are bonded to each other so that the total charge in the layer structure is zero. This forms a group. FIG70A illustrates a model of one group included in a layer structure based on In-Sn-Zn-O. FIG70B illustrates a unit cell including three groups. Note that FIG70C illustrates the atomic order in the example of the layer structure of FIG70B viewed from the c-axis direction. In Figure 70A , for simplicity, three-coordinate O atoms are not illustrated, and four-coordinate O atoms are illustrated by circles; the numbers within the circles represent the number of four-coordinate O atoms. For example, three four-coordinate O atoms present in each of the upper and lower halves of a Sn atom are represented by circled 3s. Similarly, in Figure 70A , one four-coordinate O atom present in each of the upper and lower halves of an In atom is represented by a circled 1. Figure 70A also illustrates a Zn atom near one four-coordinate O atom in the lower halves and three four-coordinate O atoms in the upper halves, as well as a Zn atom near one four-coordinate O atom in the upper halves and three four-coordinate O atoms in the lower halves. In the group of layers comprising the In-Sn-Zn-O-based material structure shown in FIG70A , in order from the top, Sn atoms close to three O atoms in each of the upper and lower halves bond to In atoms close to one O atom in each of the upper and lower halves, the In atoms bond to Zn atoms close to three O atoms in the upper halves, the Zn atoms bond to In atoms close to three O atoms in each of the upper and lower halves via one O atom in the lower halves of the Zn atoms, the In atoms bond to a subunit comprising two Zn atoms and close to one O atom in the upper halves, and the subunit bonds to Sn atoms close to three O atoms in each of the upper and lower halves via one O atom in the lower halves of the subunit. Some groups bond to each other to form a unit. Here, the charge for a combination of three-coordinate O atoms and the charge for a combination of four-coordinate O atoms can be assumed to be -0.667 and -0.5, respectively. For example, the charge of six-coordinate or five-coordinate In atoms, the charge of four-coordinate Zn atoms, and the charge of five-coordinate or six-coordinate Sn atoms are +3, +2, and +4, respectively. In this way, the charge of the subunit comprising the Sn atom is +1. As a result, it is necessary to offset the charge -1 of the charge +1 to form a layer structure comprising the Sn atom. As a structure with a charge -1, a subunit comprising two Zn atoms as shown in Figure 69E can be specified. For example, when a subunit comprising two Zn atoms is provided to a subunit comprising Sn atoms, the charges are offset so that the total charge in the layer structure can be 0. In atoms may have five ligands or six ligands. In particular, when forming the unit shown in FIG. 70B , a crystal with In-Sn-Zn-O as the base (In 2SnZn 3O 8) It should be noted that the obtained In-Sn-Zn-O based crystal layer structure can be expressed as the chemical formula In 2SnZn 2O 7(ZnO) m ( m is 0 or a natural number). The above rules also apply to the following oxides: tetrametallic oxides, such as In-Sn-Ga-Zn-O based oxides; trimetallic oxides, such as In-Ga-Zn-O based oxides (also known as IGZO), In-Al-Zn-O based oxides, Sn-Ga-Zn-O based oxides, Al-Ga-Zn-O based oxides, or Sn-Al-Zn-O based oxides; dimetallic oxide semiconductors, such as In-Zn-O based oxides, Sn-Zn-O based oxides, Al-Zn-O based oxides, Zn-Mg-O based oxides, Sn-Mg-O based oxides, In-Mg-O based oxides, or In-Ga-O based oxides; or monometallic oxides, such as In-O based oxides, Sn-O based oxides, or Zn-O based oxides. For example, FIG. 71A illustrates a model of one of the groups included in a layer structure in which In-Ga-Zn-O is a base material. In the groups included in the In-Ga-Zn-O-based layer structure of FIG71A , in order from the top, an In atom close to three O atoms in each of the upper and lower halves is bonded to a Zn atom close to one O atom in the upper halves, a Zn atom is bonded to a Ga atom close to one O atom in each of the upper and lower halves via three O atoms in the lower halves of the Zn atom, and a Ga atom is bonded to an In atom close to three O atoms in each of the upper and lower halves via one O atom in the lower halves of the Ga atom. Some of these groups are bonded to form a unit. Fig. 71B illustrates a unit cell including three groups. Note that Fig. 71C illustrates the atomic order in the example of the layer structure of Fig. 71B viewed from the c-axis direction. Here, since the charges of the six-coordinate or five-coordinate In atoms, the four-coordinate Zn atoms, and the five-coordinate Ga atoms are +3, +2, and +3, respectively, the charge of the subunit including the In atoms, Zn atoms, and Ga atoms is 0. Thus, the total charge of the layer structure composed of this combination of seed units is always 0. Here, since the charges of the six-coordinate or five-coordinate In atoms, the four-coordinate Zn atoms, and the five-coordinate Ga atoms are +3, +2, and +3, respectively, the charge of a subunit containing any one of the In, Zn, and Ga atoms is 0. Thus, the total charge of a group containing this combination of seed units is always 0. An oxide semiconductor film including CAAC (hereinafter also referred to as a CAAC film) can be formed by sputtering. The above-mentioned materials can be used as target materials. In the case of forming a CAAC film by sputtering, it is better to have a high proportion of oxygen in the atmosphere. In the case of performing sputtering in a mixed gas of argon and oxygen, for example, the proportion of oxygen is preferably 30% or more, and more preferably 40% or more, because the supply of oxygen from the atmosphere promotes the crystallization of CAAC. In the case of forming a CAAC film by sputtering, the substrate on which the CAAC film is formed is preferably heated to 150° C. or higher, more preferably 170° C. or higher. This is because the higher the substrate temperature becomes, the more the crystallization of CAAC is promoted. After performing heat treatment on the CAAC film in a nitrogen atmosphere or in a vacuum, it is preferable to perform heat treatment in an oxygen atmosphere or a mixed gas of oxygen and another gas. This is because oxygen deficiency caused by the previous heat treatment can be corrected by supplying oxygen from the atmosphere in the subsequent heat treatment. The film surface (deposition surface) on which the CAAC film is formed is preferably flat. This is because the c-axis, which is approximately perpendicular to the deposition surface, exists in the CAAC film, so irregularities in the deposition surface lead to the formation of grain boundaries in the CAAC film. Therefore, it is preferable to perform a planarization process such as chemical mechanical polishing (CMP) on the deposition surface before forming the CAAC film. The average roughness of the deposition surface is preferably 0.5 mm or less, and more preferably 0.3 mm or less. Note that in some cases, an oxide semiconductor film formed by sputtering or the like contains moisture or hydrogen (including hydroxide) as impurities. In one embodiment of the present invention, to reduce impurities such as moisture or hydrogen in the oxide semiconductor film (or an oxide semiconductor layer formed using the oxide semiconductor film) (for dehydration or dehydrogenation), a heat treatment is performed on the oxide semiconductor film (or oxide semiconductor layer) in a reduced-pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen atmosphere, or ultra-dry air (when measured using a dew point meter using cavity ring-down spectroscopy (CRDS)), the moisture content is 20 ppm (at -55°C, converted to a dew point) or less, preferably 1 ppm or less, and more preferably 10 ppb or less). By performing a heat treatment on the oxide semiconductor film (oxide semiconductor layer), moisture or hydrogen in the oxide semiconductor film (oxide semiconductor layer) can be eliminated. In particular, the heat treatment is preferably performed at a temperature higher than or equal to 250°C and lower than or equal to 750°C, or higher than or equal to 400°C and lower than or equal to the strain point of the substrate. For example, the heat treatment can be performed at 500°C for 3 to 6 minutes. When RTA is used for the heat treatment, dehydration or dehydrogenation can be performed in a short time; thus, the treatment can be performed even at a temperature higher than the strain point of the glass substrate. After moisture or hydrogen is removed from the oxide semiconductor film (oxide semiconductor layer) in this manner, oxygen is added. This can reduce oxygen vacancies in the oxide semiconductor film (oxide semiconductor layer), thereby making the oxide semiconductor film (oxide semiconductor layer) intrinsic (i-type) or substantially intrinsic. Oxygen can be added by, for example, forming an insulating film including a region having an oxygen ratio higher than the stoichiometric ratio in contact with the oxide semiconductor film (oxide semiconductor layer) and then performing heat treatment. In this way, excess oxygen in the insulating film can be supplied to the oxide semiconductor film (oxide semiconductor layer). In this way, the oxide semiconductor film (oxide semiconductor layer) can contain excess oxygen. Excess oxygen exists, for example, between the crystal lattices of the crystals included in the oxide semiconductor film (oxide semiconductor layer). Note that the insulating film including a region having an oxygen ratio higher than the stoichiometric ratio can be applied to either the insulating film located above the oxide semiconductor film (oxide semiconductor layer) or the insulating film located below the oxide semiconductor film (oxide semiconductor layer) in contact with the oxide semiconductor film (oxide semiconductor layer); however, it is preferable to apply such an insulating film to both the insulating film in contact with the oxide semiconductor film (oxide semiconductor layer). The above effect can be enhanced by a structure in which the oxide semiconductor film (oxide semiconductor layer) is provided between insulating films including regions having an oxygen ratio higher than the stoichiometric ratio. Such an insulating film is used as the insulating film located above and below the oxide semiconductor film (oxide semiconductor layer) in contact with the oxide semiconductor film (oxide semiconductor layer). Here, the insulating film including a region where the oxygen ratio is higher than the stoichiometric ratio may be a single-layer insulating film or a plurality of stacked insulating films. It should be noted that it is preferable that the insulating film includes as little impurities as possible, such as moisture or hydrogen. When hydrogen is contained in the insulating film, hydrogen enters the oxide semiconductor film (oxide semiconductor layer) or oxygen in the oxide semiconductor film (oxide semiconductor layer) is extracted by hydrogen, whereby the oxide semiconductor film has a lower resistance (n-type conductivity); thus, a parasitic channel can be formed. Thus, it is important to utilize a deposition method that does not use hydrogen in order to form an insulating film containing as little hydrogen as possible. A material having high barrier properties is preferably used for the insulating film. As an insulating film having high barrier properties, for example, a silicon nitride film, an oxynitride silicon film, an aluminum nitride film, an aluminum oxide film, an oxynitride aluminum film, etc. can be used. When a plurality of stacked insulating films are used, an insulating film having a low nitrogen content, such as a silicon oxide film or a silicon oxynitride film, is formed on a side closer to the oxide semiconductor film (oxide semiconductor layer) than the insulating film having high barrier properties. Then, the insulating film having high barrier properties is formed to overlap with the oxide semiconductor film (oxide semiconductor layer), with the insulating film having a low nitrogen content sandwiched therebetween. When an insulating film having high barrier properties is used, impurities such as moisture or hydrogen can be prevented from entering the oxide semiconductor film (oxide semiconductor layer) or the interface between the oxide semiconductor film (oxide semiconductor layer) and another insulating film and its vicinity. In addition, an insulating film having a low nitrogen content, such as a silicon oxide film or a silicon oxynitride film, is formed in contact with the oxide semiconductor film (oxide semiconductor layer) so as to prevent the insulating film having high barrier properties from directly contacting the oxide semiconductor film (oxide semiconductor layer). Alternatively, oxygen can be added after eliminating moisture or hydrogen in the oxide semiconductor film (oxide semiconductor layer) by performing heat treatment on the oxide semiconductor film (oxide semiconductor layer) in an oxygen atmosphere. The heat treatment is preferably performed at, for example, a temperature of 100° C. or higher and lower than 350° C., or 150° C. or higher and lower than 250° C. The oxygen used for the heat treatment in the oxygen atmosphere preferably does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen introduced into the heat treatment apparatus is preferably 6N (99.9999%) or higher, more preferably 7N (99.99999%) or higher (i.e., the impurity concentration in the oxygen is 1 ppm or lower, preferably 0.1 ppm or lower). Alternatively, oxygen may be added after eliminating moisture or hydrogen in the oxide semiconductor film (oxide semiconductor layer) by ion implantation, ion doping, etc. For example, oxygen that becomes plasma at 2.45 GHz may be added to the oxide semiconductor film (oxide semiconductor layer). The oxide semiconductor layer thus formed can be used as the semiconductor layer 103 of the transistor 100. In this way, the transistor 100 having an extremely low off-state current can be obtained. The semiconductor layer 103 of transistor 100 may include microcrystalline silicon. Microcrystalline silicon is a semiconductor with an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystalline structures). In microcrystalline silicon, columnar or needle-shaped crystals with a grain size of 2 to 200 nm, preferably 10 to 80 nm, more preferably 20 to 50 nm, and even more preferably 25 to 33 nm are grown perpendicular to the substrate surface. Thus, in some cases, grain boundaries are formed at the interfaces between the columnar or needle-shaped crystals. A typical example is the Raman spectrum of microcrystalline silicon, which shifts to 520 cm -1 In other words, the peak of the Raman spectrum of microcrystalline silicon is at 520 cm, which represents single crystal silicon. -1 and 480cm representing amorphous silicon -1 In addition, the microcrystalline silicon contains hydrogen or halogen at a concentration of at least 1 atomic percent to terminate dangling bonds. Furthermore, the microcrystalline silicon contains a rare gas element such as helium, argon, krypton, or neon to further promote lattice deformation, thereby increasing stability and achieving satisfactory microcrystalline silicon. Such microcrystalline silicon is disclosed, for example, in U.S. Patent No. 4,409,134. The semiconductor layer 103 of the transistor 100 may include amorphous silicon. The semiconductor layer 103 of the transistor 100 may include polycrystalline silicon. Alternatively, the semiconductor layer 103 of the transistor 100 may include an organic semiconductor, carbon nanotubes, or the like. Next, the material of the electrode 110 will be described. Note that similar materials can be used for electrodes formed using the same layer as the electrode 110. The electrode 110 can be formed using a light-transmitting conductive material. As the light-transmitting conductive material, indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide, indium zinc oxide, etc. can be used. It should be noted that the electrode 110 can have both a light-transmitting area and a reflective area. In this way, a semi-transmissive display device can be obtained. Alternatively, the electrode 110 can be formed using a reflective conductive material. In this way, a reflective display device can be obtained. Another option is to obtain a top-emitting light-emitting device in which light is emitted to the side opposite to the side forming the pixel. In particular, in the case where a reflective conductive material is used for the electrode 110 , the aperture ratio can be increased when the electrode 110 is disposed above the transistor 100 to overlap with the transistor 100 . Next, the material of the electrode 106 will be described. Note that similar materials can be used for electrodes formed using the same layer as the electrode 106. The electrode 106 can be formed using a light-transmitting conductive material, such as indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide, indium zinc oxide, and the like. Next, the material of the insulating layer 105 will be described. The insulating layer 105 may include an organic insulating layer. The insulating layer 105 may include an inorganic insulating layer. The insulating layer 105 may include a stack of inorganic insulating layers and organic insulating layers. For example, layers 105a and 105c may be inorganic insulating layers. Layer 105b may be an organic insulating layer. When the insulating layer 105 or layer 105b is a color filter, a green organic insulating layer, a blue organic insulating layer, a red organic insulating layer, etc. can be used as the insulating layer 105 or layer 105b. When the insulating layer 105 or layer 105b is a black matrix, a black organic insulating layer can be used as the insulating layer 105 or layer 105b. Acrylic acid, polyimide, polyamide, or the like can be used for the organic insulating layer. Using polyimide can reduce degradation of the light-emitting element formed on the insulating layer 105 or layer 105b. Alternatively, a photosensitive material can be used for the organic insulating layer. The film including the photosensitive material can be etched without forming a resist mask. The organic insulating layer can be formed using a droplet discharge method such as an inkjet method. Alternatively, a layer formed and etched using a droplet discharge method such as an inkjet method can be used. For example, a layer formed using a droplet discharge method such as an inkjet method and etched using a resist mask can be used. A silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like can be used for the inorganic insulating layer. This embodiment is obtained by performing changes, additions, modifications, removals, applications, higher-level conceptualizations, or lower-level conceptualizations on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, part or all of Embodiment 4, part or all of Embodiment 5, part or all of Embodiment 6, part or all of Embodiment 7, or part or all of Embodiment 8. Thus, this embodiment can be freely combined with or replaced by another embodiment (e.g., any one of Embodiments 1 to 8). (Example 10) In this embodiment, one aspect of a method for manufacturing a semiconductor device is described. 59A to 59E illustrate an example of a method for manufacturing a semiconductor device having the structure shown in FIG 1A. An electrode 101 is formed on an insulating surface 200, an insulating layer 102 is formed on the electrode 101, and a semiconductor layer 103 is formed that at least partially overlaps at least a portion of the electrode 101 and has the insulating layer 102 disposed therebetween (FIG. 59A). The electrodes 104a and 104b are formed on the semiconductor layer 103. The insulating film 591 is formed on the electrodes 104a and 104b. The insulating film 591 is formed using a positive photosensitive material (FIG. 59B). Next, the insulating film 591 is exposed using a halftone mask 592. The halftone mask 592 has regions 592a, 592b, and 592c, and these regions have different light transmittances for exposure. Here, (transmittance of region 592c) > (transmittance of region 592b) > (transmittance of region 592a) ( FIG. 59C ). When the insulating film 591 is subjected to exposure using the halftone mask 592, the insulating layer 105 can be formed, which has the regions 121 and 122 and the through hole 123. The region 121 is thinner than the region 122 (FIG. 59D). Thereafter, an electrode 106 at least partially overlapping at least a portion of the semiconductor layer 103 and having the region 121 disposed therebetween is formed on the insulating layer 105, and at least a portion of the electrode 110 is formed on at least a portion of the region 122 (FIG. 59E). In this way, a semiconductor device can be manufactured. Note that although the insulating film 591 is formed using a positive photosensitive material, this embodiment is not limited thereto. The insulating film 591 may be formed using a negative photosensitive material. Alternatively, the insulating layer 105 may be formed by forming the insulating film 591 without using a photosensitive material, forming a resist over the insulating film 591, exposing the resist using a halftone mask to form a resist mask, and then etching the insulating film 591 using the resist mask. 60A to 60E illustrate an example of a method for manufacturing a semiconductor device having the structure shown in FIG 1C. Electrode 101 is formed on insulating surface 200, and insulating layer 102, semiconductor layer 103, and electrodes 104a and 104b are formed. The manufacturing steps up to this stage are similar to those in Figures 59 and 59B. Insulating film 601a is formed on electrodes 104a and 104b, and insulating film 601b is formed on insulating film 601a (Figure 60A). Next, a resist 602 is formed on the insulating film 601b. The resist 602 is a positive resist. The resist 602 is exposed using a halftone mask 603. The halftone mask 603 has regions 603a, 603b, and 603c, and these regions have different light transmittances for exposure. Here, (transmittance of region 603c) > (transmittance of region 603b) > (transmittance of region 603a) ( FIG. 60B ). When the resist 602 is subjected to exposure by using the halftone mask 603, a resist mask 604 having three regions with different thicknesses is formed (FIG. 60C). When the insulating films 601a and 601b are etched using the resist mask 604, an insulating layer (a stack of layers 105a and 105b) can be formed having regions 121 and 122 and a through hole 123. The region 121 is thinner than the region 122 (FIG. 60D). Thereafter, an electrode 106 at least partially overlapping at least a portion of the semiconductor layer 103 and having the region 121 disposed therebetween is formed on the insulating layer 105b, and at least a portion of the electrode 110 is formed on at least a portion of the region 122 (FIG. 60E). In this way, a semiconductor device can be manufactured. Note that while the resist 602 in the manufacturing steps of Figures 60A to 60E is a positive resist, this embodiment is not limited thereto. The resist 602 can be formed using a negative photosensitive material. Alternatively, the insulating layer (the stack of layers 105a and 105b) can be formed by not using the resist 602, forming the insulating film 601b using a photosensitive material, and then exposing the insulating film 601b using a halftone mask. Although a halftone mask is used in the manufacturing steps of Figures 60A to 60E, this embodiment is not limited thereto. For example, the manufacturing steps shown in Figures 61A to 61D may be used. The manufacturing steps up to the step of FIG. 61A are similar to those of FIG. 60A . 61A to 61D , the insulating film 601b is etched to form the region 121 and the opening 124. In this way, the layer 105b is formed ( FIG 61B ). Next, the insulating film 601a exposed through the opening 124 is etched to form the through-hole 123. In this case, a portion of the layer 105b may be further etched. This forms an insulating layer (a stack of layers 105a and 105b) having regions 121 and 122 and the through-hole 123. Region 121 is thinner than region 122 ( FIG. 61C ). Thereafter, an electrode 106 at least partially overlapping with at least a portion of the semiconductor layer 103 and having the region 121 arranged therebetween is formed on the insulating layer 105b, and at least a portion of the electrode 110 is formed on at least a portion of the region 122 (FIG. 61D). In this way, a semiconductor device can be manufactured. Note that although the insulating films 601a and 601b are stacked and then etched in the manufacturing steps of Figures 61A to 61D, this embodiment is not limited thereto. For example, the manufacturing steps shown in Figures 62A to 62E may be used. The steps up to the step of forming the insulating film 601a (FIG. 62A) are similar to the manufacturing steps of FIG. 61A. After the insulating film 601a is formed, the insulating film 601a is etched to form a layer 105a having an opening 125 (FIG. 62B). Then, an insulating film 601b is formed to cover the layer 105a (FIG. 62C). Then, the insulating film 601b is etched. In this case, a portion of the layer 105a may be further etched. This allows the insulating layer (a stack of layers 105a and 105b) to be formed, which has regions 121 and 122 and a through hole 123. Region 121 is thinner than region 122 ( FIG. 62D ). Thereafter, an electrode 106 at least partially overlapping at least a portion of the semiconductor layer 103 and having the region 121 disposed therebetween is formed on the insulating layer 105b, and at least a portion of the electrode 110 is formed on at least a portion of the region 122 (FIG. 62E). In this way, a semiconductor device can be manufactured. It should be noted that in the steps of FIG. 60A to 60E, FIG. 61A to 61D, and FIG. 62A to 62E, the insulating layer 105 is composed of two films (insulating films 601a and 601b), and only one of the films is selectively removed to form the regions 121 and 122. However, this embodiment is not limited thereto. The insulating layer 105 may be composed of It is formed by m (m is a natural number) films and can only be selectively removed Of the m membranes n membranes ( n is less than m is a natural number) to form regions 121 and 122. For example, Figures 63A to 63E illustrate steps of forming the insulating layer 105 using three films. The steps in Figures 63A to 63E correspond to steps of manufacturing the semiconductor device having the structure shown in Figure 26C. The steps up to the step of FIG. 63A are similar to the manufacturing steps of FIG. 60A . After the insulating film 601b is formed, the insulating film 601b is etched to form a layer 105b having openings 126 and 127 (FIG. 63B). Then, an insulating film 601c is formed to cover the layer 105b (FIG. 63C). Then, the insulating films 601a and 601c are etched to form the through hole 123. In this way, an insulating layer (a stack of layers 105a, 105b, and 105c) can be formed, which has the regions 121 and 122 and the through hole 123. The region 121 is thinner than the region 122 (FIG. 63D). Thereafter, an electrode 106 at least partially overlapping at least a portion of the semiconductor layer 103 and having the region 121 disposed therebetween is formed on the insulating layer 105c, and at least a portion of the electrode 110 is formed on at least a portion of the region 122 (FIG. 63E). In this way, a semiconductor device can be manufactured. Note that Figures 64A to 64E illustrate the steps of forming the insulating layer 105 using three films. These steps are different from the steps of Figures 63A to 63E. The steps of Figures 64A to 64E correspond to the steps of manufacturing a semiconductor device in the case where layer 105b covers the end of layer 105a in the structure shown in Figure 26C. First, the insulating film is etched to form the layer 105a having the opening 128a, and then the insulating film 601b is formed (FIG. 64A). The insulating film 601b is etched to form a layer 105b having an opening 127 and an opening 128 (FIG. 64B). Here, the opening 128 is formed in the opening 128a and has a smaller diameter than the opening 128a. Then, an insulating film 601c is formed to cover the layer 105b (FIG. 64C). Then, the insulating film 601c is etched to form the through hole 123. In this way, an insulating layer (a stack of layers 105a, 105b, and 105c) can be formed having the regions 121 and 122 and the through hole 123. The region 121 is thinner than the region 122 (FIG. 64D). Thereafter, an electrode 106 at least partially overlapping at least a portion of the semiconductor layer 103 and having the region 121 disposed therebetween is formed on the insulating layer 105c, and at least a portion of the electrode 110 is formed on at least a portion of the region 122 (FIG. 64E). In this way, a semiconductor device can be manufactured. It should be noted that Figures 59A to 59E, Figures 60A to 60E, Figures 61A to 61D, Figures 62A to 62E, Figures 63A to 63E, and Figures 64A to 64E illustrate the steps of manufacturing a semiconductor device obtained by some modifications of the semiconductor device in Figure 1A, Figure 1C, or Figure 26C; however, semiconductor devices having other structures of the above-mentioned embodiments can also be manufactured. This embodiment is obtained by performing changes, additions, modifications, removals, applications, higher-level conceptualizations, or lower-level conceptualizations on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, part or all of Embodiment 4, part or all of Embodiment 5, part or all of Embodiment 6, part or all of Embodiment 7, part or all of Embodiment 8, or part or all of Embodiment 9. Thus, this embodiment can be freely combined with or replaced by another embodiment (e.g., any one of Embodiments 1 to 9). (Example 11) In this embodiment, an example of applying any one of the semiconductor devices in Embodiments 1 to 10 to a display device will be described. Any of the semiconductor devices in Examples 1 to 10 can be used for pixels in liquid crystal display devices and the like. Figures 52A and 52B show examples of cross-sectional views of pixels in a liquid crystal display device. Figures 52A and 52B show cross-sectional views of an example in which the semiconductor device having the structure shown in Figure 1C is applied to a liquid crystal display device. Note that in Figures 52A and 52B , portions identical to those in Figures 1A to 1E are denoted by the same reference numerals, and their descriptions are omitted. 52A and 52B , transistor 100 may be disposed in a pixel. Electrode 110 may be a pixel electrode. Layer 105b may be a color filter and / or a black matrix. In FIG52A , protrusions 510 are provided in region 122. Protrusions 510 can function as spacers. Thus, the gap between the substrate forming transistor 100 (hereinafter referred to as the pixel substrate) and the substrate used to seal the liquid crystal layer (hereinafter referred to as the counter substrate) can be controlled using protrusions 510. It should be noted that the black matrix can be formed using protrusions 510. Alternatively, protrusions 510 can function as ribs for controlling the alignment of liquid crystal molecules. Using protrusions 510, the direction of alignment of the liquid crystal molecules can be controlled. Note that Figures 52A and 52B do not illustrate the liquid crystal layer, the electrode forming a pair with the pixel electrode (hereinafter referred to as the counter electrode), and the counter electrode. The counter electrode can be provided using either the pixel substrate or the counter substrate. Although an alignment film is not illustrated, it may or may not be provided. In the structure shown in FIG52A, as shown in FIG52B, layers 510a and 510b can be provided to fill areas where the insulating layer 105 is thin or not provided (for example, areas where layer 105b is removed). In this way, the unevenness of the area on the pixel substrate facing the liquid crystal layer can be reduced. Layers 510a and 510b can be formed using a material different from or the same as the material of the protrusion 510. The black matrix can be formed using any one or all of the layers 510a, 510b, and the protrusion 510. It should be noted that in FIG52B, it is not necessary to provide one of the layers 510a and 510b. For example, only layer 510a is provided. Note that in Figures 52A and 52B , protrusion 510 and layers 510a and 510b can be formed by photolithographically processing an insulating layer. Alternatively, a photosensitive material can be used to form protrusion 510 and layers 510a and 510b. Note that protrusion 510 and layers 510a and 510b can also be formed using a droplet discharge method such as an inkjet method. While Figures 52A and 52B each illustrate an example in which protrusion 510 is disposed on a pixel substrate, this embodiment is not limited thereto. Protrusion 510 may also be disposed on an opposing substrate. Although Figures 52A and 52B each illustrate an example in which the protrusion 510 is arranged to overlap with the electrode 110, this embodiment is not limited thereto. The protrusion 510 may be arranged so as not to overlap with the electrode 110. Alternatively, the protrusion 510 may be arranged so as to overlap with the electrode 110 but not overlap with another portion of the electrode 110. In addition, the protrusion 510 may be provided for each pixel or for each of a plurality of pixels. The protrusion 510 may be arranged so as to partially overlap with the wiring of the pixel, or may be arranged so as to partially overlap with the black matrix. Although Figures 52A and 52B each illustrate an example in which the semiconductor device of Figure 1C is applied to a liquid crystal display device, this embodiment is not limited thereto. Any of the semiconductor devices of Examples 1 to 10 can be applied to a liquid crystal display device. For example, any of the semiconductor devices of Examples 1 to 10 can be applied to a liquid crystal display device, and any of the protrusion 510, layer 510a, and layer 510b can be provided as shown in Figures 52A and 52B. This embodiment is obtained by performing changes, additions, modifications, removals, applications, higher-level conceptualizations, or lower-level conceptualizations on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, part or all of Embodiment 4, part or all of Embodiment 5, part or all of Embodiment 6, part or all of Embodiment 7, part or all of Embodiment 8, part or all of Embodiment 9, or part or all of Embodiment 10. Thus, this embodiment can be freely combined with or replaced with another embodiment (e.g., any one of Embodiments 1 to 10). (Example 12) In this embodiment, an example in which any one of the semiconductor devices in Embodiments 1 to 10 is applied to a display device will be described. For example, any of the semiconductor devices in Embodiments 1 to 10 can be used for pixels of a liquid crystal display device or the like. Figures 55A to 55F are examples of circuit diagrams of a pixel in the pixel portion of a liquid crystal display device. The pixel includes a transistor, a capacitor, and a liquid crystal element. The pixel also includes a gate signal line 551, a source signal line 552, a capacitor line 553, and the like. The source signal line 552 can also be called a video signal line. It should be noted that each of the pixels illustrated in Figures 55A to 55F includes a sub-pixel. The transistor 100 in any one of Examples 1 to 10 can be used as the transistor. Figure 55G illustrates the symbol of the transistor used in Figures 55A to 55F. Figure 55G illustrates the symbol of the transistor and the correspondence between the symbol of the transistor and the transistor 100 in any one of Examples 1 to 10. FIG55H illustrates the liquid crystal element from FIG55A to FIG55F. As shown in FIG55H, the liquid crystal element includes an electrode 110 (corresponding to a pixel electrode) and an electrode 550 (corresponding to a counter electrode). A liquid crystal layer is disposed between the electrode 110 and the electrode 550. Alternatively, the parasitic capacitance or capacitor in Example 7 or Example 8 may be used as the capacitor in Figures 55A to 55F. Any of the semiconductor devices in Examples 1 to 10 can be used for a pixel in a display device including an EL element (eg, an organic light-emitting element) (hereinafter referred to as an EL display device) or a light-emitting device. Figures 56A to 56C are examples of circuit diagrams of pixels in an EL display device. The pixels in Figures 56A to 56C include an EL element 560, a transistor 562, a transistor 563, and a capacitor 564. The pixel also includes a gate signal line 551, a source signal line 552, a capacitor line 553, a power supply line 561, and the like. The source signal line 552 is also called a video signal line. The transistor 562 has a function of controlling whether a video signal is supplied to the gate of the transistor 563. The transistor 563 has a function of controlling the current to be supplied to the EL element 560. The transistor 100 in any one of Examples 1 to 10 can be used as the transistor. Figure 55G illustrates the symbol of the transistor and the correspondence between the symbol of the transistor and the transistor 100 in any one of Examples 1 to 10. In addition, any of the semiconductor devices in Examples 1 to 10 can be used in a driver circuit in a liquid crystal display device, an EL display device, or the like. For example, any of the semiconductor devices in Examples 1 to 10 can be used in a driver circuit such as a scan line driver circuit or a signal line driver circuit for outputting signals to pixels. Figures 57A and 57B illustrate an example of a portion of a driver circuit. The transistor 100 in any of Examples 1 to 10 can be used as some or all of the transistors (transistors 701, 702, 703, 704, 705, 706, 707, 708, 709, 710, 711, 712, 713, 715, 801, 802, 803, 804, 805, 806, 807, 808, 809, 810, 811, 812, 813, 814, 815, 816, and 817) included in the driver circuit. Alternatively, the parasitic capacitance or capacitor in Example 7 or Example 8 may be used as the capacitor 714 in FIG. 57A . This embodiment is obtained by performing changes, additions, modifications, removals, applications, higher-level conceptualizations, or lower-level conceptualizations on part or all of Example 1, part or all of Example 2, part or all of Example 3, part or all of Example 4, part or all of Example 5, part or all of Example 6, part or all of Example 7, part or all of Example 8, part or all of Example 9, part or all of Example 10, or part or all of Example 11. In this way, this embodiment can be freely combined with or replaced with another embodiment (e.g., any one of Examples 1 to 11). (Example 13) In this embodiment, an example in which any of the semiconductor devices in Embodiments 1 to 10 is applied to a display device such as a liquid crystal display device will be described. Figure 53 and Figures 58A and 58B illustrate one aspect of the structure of a pixel in a liquid crystal display device. The cross-sectional view taken along line A1-A2 in the top view of Figure 53 corresponds to Figure 58A or 58B. In Figures 53 and 58A and 58B, pixel 530 includes transistor 100, capacitor 531, and a liquid crystal element (or display element). Note that pixel 530 may be a sub-pixel. Figures 53 and 58A to 58D illustrate only electrode 110 corresponding to the pixel electrode of the liquid crystal element (or display element), and do not illustrate the counter electrode (common electrode). Any of the various structures in Examples 1 to 10 can be used as the structure of transistor 100. Thus, the structure of transistor 100 is similar to any of the structures in Examples 1 to 10. Therefore, the same reference numerals are used for the same parts as those in any of the structures in Examples 1 to 10, and their descriptions are omitted. Note that FIG58A illustrates an example using transistor 100 having the structure of FIG1A. FIG58B illustrates an example using transistor 100 having the structure of FIG1C. Alternatively, the parasitic capacitance or capacitor described in Example 7 or Example 8 can be used as capacitor 531. Note that FIG58A illustrates an example in which capacitor 531 is formed in region 121c where insulating layer 105 is thinned. FIG58B illustrates an example in which capacitor 531 is formed in region 121c where layer 105b is removed. The structure of capacitor 531 in FIG58B corresponds to the structure of the capacitor in FIG22D. Electrode 106 of transistor 100 is electrically connected to electrode 101a via opening 501a. Electrode 101 of transistor 100 serves as both the gate electrode and the gate line of the transistor. Electrode 101a is arranged parallel to electrode 101. Electrode 101a serves as both a wiring for applying a potential to electrode 106 of transistor 100 and a capacitor line in a pixel (or sub-pixel) in an adjacent column. Electrode 104a of transistor 100 serves as both a source electrode and a drain electrode, and a source line. The source line is arranged to intersect the gate line. Electrode 104b of transistor 100 serves as the other of the source electrode and the drain electrode, and is electrically connected to electrode 110 via opening 501b. One of a pair of electrodes of capacitor 531 is electrode 110, and the other electrode of capacitor 531 is electrode 101a. It should be noted that the electrode 101a can be formed using, for example, the same layer and the same material as the electrode 101. It should be noted that the electrodes 101a and 101 can be formed using different materials. Figure 54 and Figures 58C and 58D illustrate another aspect of the structure of a pixel in a liquid crystal display device. The cross-sectional view taken along line A1-A2 in the top view of Figure 54 corresponds to Figure 58C or 58D. 54 and 58C and 58D, the pixel 530 includes the transistor 100, the capacitor 532, and the liquid crystal element (or the display element). Note that the pixel 530 may be a sub-pixel. The structure of transistor 100 is similar to any of the structures in Examples 1 to 10. Therefore, the same reference numerals are used for the same parts as those in any of the structures in Examples 1 to 10, and their descriptions are omitted. Note that FIG58C illustrates an example using transistor 100 having the structure of FIG1A. FIG58D illustrates an example using transistor 100 having the structure of FIG1C. In this way, any of the various structures in Examples 1 to 10 can be used as the structure of transistor 100. Alternatively, the parasitic capacitance or capacitor described in Example 7 or Example 8 can be used as capacitor 532. Note that FIG58C illustrates an example in which capacitor 532 is formed in region 121c where insulating layer 105 is thinned. FIG58D illustrates an example in which capacitor 532 is formed in region 121c where layer 105b is removed. The structure of capacitor 532 in FIG58D corresponds to the structure of the capacitor in FIG22E. Electrode 106 of transistor 100 is electrically connected to electrode 101a via opening 502a. Electrode 101 of transistor 100 serves as both the gate electrode and the gate line of the transistor. Electrode 101b is arranged parallel to electrode 101. Electrode 101b serves as a capacitor line. Electrode 104a of transistor 100 serves as both the source electrode, the drain electrode, and the source line. The source line is arranged to intersect the gate line. Electrode 104b of transistor 100 serves as the other of the source electrode and the drain electrode and is electrically connected to electrode 110 via opening 502b. One of a pair of electrodes of capacitor 532 is electrode 110, and the other electrode of capacitor 532 is electrode 101b. It should be noted that the electrode 101b can be formed using, for example, the same layer and the same material as the electrode 101. It should be noted that the electrodes 101b and 101 can be formed using different materials. Note that FIG54 illustrates an example in which the electrode 110 has a plurality of openings; however, this embodiment is not limited thereto. Furthermore, the structure shown in FIG53 may also be a structure in which the electrode 110 has a plurality of openings. The electrode 110 may have a given shape. In Figures 53, 54, and 58A to 58D, the electrode 110 may be a light-transmitting electrode. Alternatively, the electrode 110 may be an electrode having both a reflective region and a light-transmitting region. When the electrode 110 is an electrode having both a reflective region and a light-transmitting region, the liquid crystal display device may be a semi-transmissive type. In the case where electrode 110 has both a reflective region and a light-transmitting region, electrode 106 can be formed using the same layer and material as the layer providing the reflective electrode included in the reflective region. This allows semiconductor layer 103 of transistor 100 to shield light. Electrodes having both a reflective region and a light-transmitting region can be formed by etching a stack of light-transmitting and reflective films using a halftone mask. It should be noted that display elements, display devices including display elements, light-emitting elements, and light-emitting devices including light-emitting elements can utilize various modes and include various elements. For example, display media whose contrast, brightness, reflectance, transmittance, etc. are changed by electromagnetic action, such as EL (electroluminescent) elements (e.g., EL elements including organic and inorganic materials, organic EL elements, or inorganic EL elements), LEDs (e.g., white LEDs, red LEDs, green LEDs, or blue LEDs), transistors (transistors that emit light in response to an electric current), electron emitters, liquid crystal elements, electronic ink, electrophoretic elements, electrowetting elements, grating light valves (GLVs), plasma display panels (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, or carbon nanotubes, can be used as display elements, display devices, light-emitting elements, or light-emitting devices. Display devices including EL elements include EL displays, etc. Display devices including electron emitters include field emission displays (FEDs), SED-type flat panel displays (SEDs: surface conduction electron emitter displays), etc. Display devices with liquid crystal elements include liquid crystal displays (e.g., transmissive liquid crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, or projection liquid crystal displays), etc. Display devices with electronic ink or electrophoretic elements include electronic paper, etc. This embodiment is obtained by performing changes, additions, modifications, removals, applications, higher-level conceptualizations, or lower-level conceptualizations on part or all of Example 1, part or all of Example 2, part or all of Example 3, part or all of Example 4, part or all of Example 5, or part or all of Example 6, part or all of Example 7, part or all of Example 8, or part or all of Example 9, part or all of Example 10, part or all of Example 11, or part or all of Example 12. In this way, this embodiment can be freely combined with or replaced with another embodiment (e.g., any one of Embodiments 1 to 12). (Example 14) In this embodiment, an example of applying the display device to a display module is described. Figure 72 illustrates a display module. The display module in Figure 72 includes a housing 901, a display device 902, a backlight unit 903, and a housing 904. Display device 902 is electrically connected to a driver IC 905. A power supply voltage or signal is supplied to backlight unit 903 via terminal 906. It should be noted that this embodiment is not limited to the display module shown in FIG72 , and a display module with a touch panel can be used. The display module can include a flexible printed circuit (FPC). In FIG72 , the driver IC 905 can be electrically connected to the display device 902 via the flexible printed circuit (FPC). In addition, the display module can include an optical film such as a polarizing plate or a deceleration film. This embodiment is obtained by performing changes, additions, modifications, removals, applications, higher-level conceptualizations, or lower-level conceptualizations on part or all of Example 1, part or all of Example 2, part or all of Example 3, part or all of Example 4, part or all of Example 5, or part or all of Example 6, part or all of Example 7, part or all of Example 8, or part or all of Example 9, part or all of Example 10, part or all of Example 11, part or all of Example 12, or part or all of Example 13. In this way, this embodiment can be freely combined with or replaced with another embodiment (e.g., any one of Embodiments 1 to 13). (Example 15) In this embodiment, an example of an electronic device is described. Figures 67A to 67H and 68A to 68D illustrate electronic devices. These electronic devices may include a housing 5000, a display portion 5001, a speaker 5003, an LED light 5004, operation keys 5005 (including a power switch or an operation switch), connection terminals 5006, sensors 5007 (sensors capable of measuring force, displacement, position, velocity, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, slope, oscillation, odor, or infrared rays), a microphone 5008, and the like. Figure 67A illustrates a portable computer, which, in addition to the aforementioned components, may also include a switch 5009, an infrared port 5010, and the like. Figure 67B illustrates a portable video playback device (e.g., a DVD player) equipped with a memory medium, which, in addition to the aforementioned components, may also include a second display unit 5002, a memory medium reader 5011, and the like. Figure 67C illustrates a goggle-type display, which, in addition to the aforementioned components, may also include a second display unit 5002, a stand 5012, headphones 5013, and the like. Figure 67D illustrates a portable game console, which, in addition to the aforementioned components, may also include a memory medium reader 5011. Figure 67E illustrates a digital camera with a television reception function, which, in addition to the aforementioned components, may also include an antenna 5014, a shutter button 5015, an image receiving unit 5016, and the like. Figure 67F illustrates a portable game console, which, in addition to the aforementioned components, may also include a second display unit 5002, a memory medium reader 5011, and the like. Figure 67G illustrates a television receiver, which, in addition to the aforementioned components, may also include a tuner, an image processing unit, and so on. Figure 67H illustrates a portable television receiver, which, in addition to the aforementioned components, may also include a charger 5017 capable of transmitting and receiving signals, and so on. Figure 68A illustrates a display, which, in addition to the aforementioned components, may also include a support base 5018, and so on. Figure 68B illustrates a camera, which, in addition to the aforementioned components, may also include an external connection port 5019, a shutter button 5015, an image receiving unit 5016, and so on. Figure 68C illustrates a computer, which, in addition to the aforementioned components, may also include a positioning device 5020, an external connection port 5019, a reader / writer 5021, and so on. Figure 68D illustrates a mobile phone, which, in addition to the aforementioned components, may also include a transmitter, a receiver, a tuner for 1seg (digital television service) local reception services for mobile phones and mobile terminals, and so on. The electronic devices shown in Figures 67A to 67H and Figures 68A to 68D can have various functions, such as the function of displaying a variety of information (e.g., still images, moving images, and text images) on a display unit; a touch panel function; a function of displaying a calendar, date, time, etc.; a function of controlling processing using various software (programs); a wireless communication function; a function of connecting to various computer networks using the wireless communication function; a function of transmitting and receiving a variety of data using the wireless communication function; a function of reading programs and data stored in a memory medium and displaying the programs and data on a display unit. Furthermore, electronic devices including multiple display units can have the function of primarily displaying image information on one display unit while simultaneously displaying text information on another display unit, a function of displaying three-dimensional images by displaying images that take parallax into account on multiple display units, and the like. Furthermore, the electronic device including the image receiving unit may have a function of capturing still images, a function of capturing moving images, a function of automatically or manually correcting captured images, a function of storing captured images in a memory medium (external memory medium or a memory medium integrated in the camera), a function of displaying captured images on a display unit, etc. It should be noted that the functions that can be provided to the electronic devices shown in Figures 67A to 67H and Figures 68A to 68D are not limited thereto, and the electronic devices may have various functions. Each of the electronic devices in this embodiment includes a display portion for displaying certain types of information. Next, application examples of semiconductor devices will be described. Figure 68E illustrates an example of a semiconductor device incorporated into a building structure. Figure 68E illustrates a housing 5022, a display unit 5023, a remote control 5024 for operating the device, a speaker 5025, and the like. The semiconductor device is incorporated into the building structure as a wall-mounted device and can be installed without requiring a large space. 68F illustrates another example of semiconductor devices incorporated into a building structure. A display panel 5026 is incorporated into a prefabricated bathroom unit 5027 so that a bather can view the display panel 5026. It should be noted that although this embodiment describes walls and prefabricated bathroom units as examples of building structures, this embodiment is not limited thereto. Semiconductor devices can be installed in various building structures. Next, an example of incorporating a semiconductor device into a mobile object will be described. FIG68G illustrates an example of a semiconductor device incorporated into a car. A display panel 5028 is incorporated into a vehicle body 5029 and can display information related to vehicle operation or information input from inside or outside the vehicle as needed. Note that display panel 5028 can also have a navigation function. Figure 68H illustrates an example of a semiconductor device incorporated into a passenger aircraft. Figure 68H illustrates a use case where a display panel 5031 is installed on a ceiling 5030 above a passenger aircraft seat. Display panel 5031 is integrated into ceiling 5030 via a hinge 5032, and passengers can view display panel 5031 by extending and retracting hinge 5032. Display panel 5031 displays information in response to passenger operation. It should be noted that although this embodiment illustrates the bodies of cars and airplanes as examples of mobile objects, this embodiment is not limited to these. Semiconductor devices can be installed on various objects, such as two-wheeled vehicles, four-wheeled vehicles (including cars, buses, etc.), trains (including monorails, railways, etc.), and ships. It should be noted that in this specification, etc., in the diagrams or texts describing an embodiment, a portion of the diagrams or texts may be taken out and may constitute an embodiment of the present invention. Thus, in the case of describing a portion of a diagram or text related to a certain part, the context taken out from a portion of the diagram or text is also disclosed as an embodiment of the present invention and may constitute an embodiment of the present invention. Thus, for example, in the diagrams or texts describing one or more active components (such as transistors or diodes), wiring, passive components (such as capacitors or resistors), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operating methods, manufacturing methods, etc., a portion of the diagram or text may be taken out and may constitute an embodiment of the present invention. For example, from the setting N circuit elements (e.g., transistors or capacitors) N is an integer) in the circuit diagram M circuit elements (e.g., transistors or capacitors) ( M is an integer, where M< N), and can constitute an embodiment of the present invention. As another example, from setting N-layer N is an integer) M layer ( M is an integer, where M< N), and can constitute an embodiment of the present invention. As another example, from setting N element ( N is an integer) flowchart M element ( M is an integer, where M< N), and may constitute an embodiment of the present invention. It should be noted that in this specification, etc., in the drawings or text describing an embodiment, when at least one specific example is described, it should be readily apparent to those skilled in the art that a broader concept of the specific example can be derived. Thus, in the drawings or text describing an embodiment, when at least one specific example is described, the broader concept of the specific example is disclosed as an embodiment of the present invention and can constitute an embodiment of the present invention. It should be noted that in this specification and other disclosures, at least the content illustrated in the drawings (or possibly a portion of the drawings) is disclosed as an embodiment of the present invention and may constitute an embodiment of the present invention. Thus, when certain content is illustrated in a drawing, even when the content is not described herein, such content is disclosed as an embodiment of the present invention and may constitute an embodiment of the present invention. Similarly, a portion of a drawing extracted from a drawing is disclosed as an embodiment of the present invention and may constitute an embodiment of the present invention. This application is based on Japanese Patent Application No. 2011-103344 published by the Japan Patent Office on May 5, 2011, the entire contents of which are hereby incorporated by reference. 100: Transistor 101: Electrode 102: Insulation layer 103: semiconductor layer 104a: Electrode 104b: Electrode 105: Insulation layer 106: Electrode 110: Electrode 121: Area 122: Area 200: Insulation surface

Claims

1. A display device comprising: an EL element in a pixel and a transistor having the function of controlling the current supplied to the EL element; a first conductive layer; and a first insulating layer having a region above the first conductive layer; An oxide semiconductor layer having a region above the first insulating layer; a second conductive layer having a region above the oxide semiconductor layer; A second insulating layer having a region above the second conductive layer; A third insulating layer having a region above the second insulating layer; A fourth insulating layer having a region above the third insulating layer; A third conductive layer having a region above the fourth insulating layer; wherein: the first conductive layer has a region overlapping the oxide semiconductor layer across the first insulating layer; the oxide semiconductor layer has a region serving as a channel forming region of the transistor; the first conductive layer has a region serving as a gate electrode of the transistor; the second conductive layer has a region serving as a source electrode or drain electrode of the transistor; the third conductive layer has a first region, a second region, and a third region; the first region overlaps with the second insulating layer, the third insulating layer, and the fourth insulating layer; the first... The region serves as the pixel electrode of the EL element; the second region does not overlap with the third insulating layer, and overlaps with the channel forming region through the second insulating layer and the fourth insulating layer; the third region does not overlap with the fourth insulating layer, does not overlap with the third insulating layer, and does not overlap with the second insulating layer; in the third region, the third conductive layer has a region that contacts the second conductive layer; the third insulating layer serves as a color filter; and in the region below the second region and overlapping with the channel forming region, the upper surface of the second insulating layer contacts the lower surface of the fourth insulating layer.

2. A display device comprising: an EL element in a pixel and a transistor having the function of controlling the current supplied to the EL element; a first conductive layer; and a first insulating layer having a region above the first conductive layer; An oxide semiconductor layer having a region above the first insulating layer; a second conductive layer having a region above the oxide semiconductor layer; A second insulating layer having a region above the second conductive layer; A third insulating layer having a region above the second insulating layer; A fourth insulating layer having a region above the third insulating layer; A third conductive layer having a region above the fourth insulating layer; wherein: the first conductive layer has a region overlapping the oxide semiconductor layer across the first insulating layer; the oxide semiconductor layer has a region serving as a channel forming region of the transistor; the first conductive layer has a region serving as a gate electrode of the transistor; the second conductive layer has a region serving as a source electrode or drain electrode of the transistor; the third conductive layer has a first region, a second region, and a third region; the first region overlaps with the second insulating layer, the third insulating layer, and the fourth insulating layer; the first region serves as an image of the EL element. The second region does not overlap with the third insulating layer, but overlaps with the channel forming region through the second and fourth insulating layers; the third region does not overlap with the fourth insulating layer, the third insulating layer, or the second insulating layer; in the third region, the third conductive layer has a region in contact with the second conductive layer; the third insulating layer functions as a color filter; below the second region, in the region overlapping with the channel forming region, the upper surface of the second insulating layer is in contact with the lower surface of the fourth insulating layer; and the oxide semiconductor layer comprises an In-O based oxide semiconductor.

3. The display device as requested in item 1 or 2, wherein, At the periphery of the third region, the upper surface of the second insulating layer is in contact with the lower surface of the fourth insulating layer.

4. The display device as requested in item 1 or 2, wherein: The third conductive layer has a fourth region; the fourth region has a region that overlaps with the fifth insulating layer; the fifth insulating layer has a region that forms a black matrix; And the fifth insulating layer is different in color from the third insulating layer.

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