Apparatus and method for two-step read of resistive random access memory

Abstract

An apparatus is provided, comprising a memory array and a control circuit. The memory array includes non-volatile memory cells, each of which includes a resistive random access memory element. The control circuit is configured to: receive a read command specifying an address of one of a first group of the non-volatile memory cells; perform a first read on the first group of the non-volatile memory cells using a first predetermined read reference value to provide first read data; while performing the first read, retrieve a second predetermined read reference value corresponding to the specified address from a memory; and in response to a condition relating to the first read data being met, perform a second read on the first group of the non-volatile memory cells using the second predetermined read reference value to provide second read data.

Description

Apparatus and Method for Two-Step Read of Resistive Random Access Memory Cross-Reference to Related Applications This application claims priority to U.S. Provisional Patent Application No. 63 / 504,665, filed on May 26, 2023, entitled "APPARATUS AND METHOD FOR TWO-STEP READ OF RESISTIVE RANDOM ACCESS MEMORY", the entire content of which is incorporated herein by reference. The present invention relates to an apparatus and method for two-step read of resistive random access memory. Memory is widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can be non-volatile memory or volatile memory. Non-volatile memory allows storage and retention of information even when the non-volatile memory is not connected to a power source (e.g., a battery pack). An example of non-volatile memory is magnetoresistive random access memory (MRAM), which uses magnetization to represent stored data as compared to some other memory technologies that use electric charge to store data. Generally, MRAM includes a large number of magnetic memory cells formed on a semiconductor substrate, where each memory cell represents a bit of data. One bit of data is written to a memory cell by changing the magnetization direction of a magnetic element within the memory cell, and one bit is read by measuring the resistance of the memory cell (low resistance generally represents a "0" bit and high resistance generally represents a "1" bit). As used herein, the magnetization direction is the direction of orientation of the magnetic moment. Although MRAM is a promising technology, there are still many challenges. Provided is an apparatus that includes a memory array and a control circuit. The memory array includes non-volatile memory cells, each of the non-volatile memory cells including a resistive random access memory element. The control circuit is configured to: receive a read command specifying an address of a first group of the non-volatile memory cells; perform a first read on the first group of the non-volatile memory cells using a first predetermined read reference value to provide first read data; while performing the first read, retrieve a second predetermined read reference value corresponding to the specified address from a memory; and in response to satisfying a condition regarding the first read data, perform a second read on the first group of the non-volatile memory cells using the second predetermined read reference value to provide second read data. Describes a technique for fast, two-step reading of resistive random access memory cells, such as MRAM cells. In one embodiment, codewords are read from a group of memory cells using a two-step reading procedure. As used herein, a "codeword" includes a predetermined number of data bits (e.g., 16 bits, 64 bits, 1024 bits, etc.). In one embodiment, a codeword includes a number of bits that can be encoded and decoded by an (generally on-die) error correction coding (ECC) engine. In one embodiment, a memory array includes multiple codewords, and each codeword has an associated address. In one embodiment, a first reading of a codeword is performed using a first predetermined read reference value, which is used to distinguish a first state (e.g., 0) of each bit in the codeword from a second state (e.g., 1). As used herein, the first predetermined read reference value is also referred to as the "global read reference value". In one embodiment, the global read reference value is selected for reading all codewords of the memory array. In one embodiment, the global read reference value can be determined during wafer sorting and has a value that results in the lowest number of bit errors for all codewords of the memory array. In one embodiment, a small, fast memory (e.g., a content addressable memory) stores a table (e.g., a lookup table) of codeword addresses and corresponding second read reference values. As used herein, the second predetermined read reference value is also referred to as the "individual read reference value". In one embodiment, each individual read reference value is selected for reading the corresponding codeword of the memory array. In one embodiment, each individual read reference value can be determined during wafer sorting and has a value that results in the lowest number of bit errors for the corresponding codeword. In one embodiment, when the first reading of the codeword is performed using the global read reference value, the lookup table is searched to determine if there is an entry for the encoded address. If there is such an entry, the individual read reference value corresponding to the codeword address is retrieved from the lookup table. In one embodiment, if the first reading fails (e.g., the ECC engine cannot successfully decode the read bits), and if the lookup table includes an entry for the codeword address, a second reading of the codeword is performed using the corresponding individual read reference value. In one embodiment, however, if the lookup table does not include an entry for the codeword address, the memory controller can perform further read failure handling (e.g., using a self-reference reading technique to read the specified codeword). Without wishing to be bound by any particular theory, it is believed that the two-step reading technique described below can result in reading more bits without the need to perform a self-reference read, which requires multiple write operations and can increase write errors and reduce durability. In this regard, without wishing to be bound by any particular theory, it is believed that the two-step reading technique described below can improve reading reliability. Without wishing to be bound by any particular theory, it is believed that the two-step reading technique described below can minimize latency by using a fast lookup memory and searching for the individual read reference value during the first read operation. In this regard, without wishing to be bound by any particular theory, it is believed that if the first read fails, the second read can be quickly started, and thus the speed can be very fast. Figure 1A is a schematic perspective view of a prior MRAM memory cell 10 using field-induced switching. Generally, the MRAM memory cell 10 includes a magnetic tunnel junction (MTJ) 12, which includes an upper ferromagnetic layer 14, a lower ferromagnetic layer 16, and a tunnel barrier (TB) 18, which is an insulating layer located between the two ferromagnetic layers. In this example, the upper ferromagnetic layer 14 is a free layer (FL) having a switchable magnetization direction. The lower ferromagnetic layer 16 is a pinned (or fixed) layer (PL) having a magnetization direction that does not change. When the magnetization direction in the free layer 14 is parallel to the magnetization direction of the fixed layer 16, the resistance (R P ) (referred to herein as "parallel resistance R P ") is relatively low, at least in part due to spin-dependent scattering of minority electrons. When the magnetization direction in the free layer 14 is antiparallel to the magnetization direction of the fixed layer 16, the resistance (R AP ) (referred to herein as "antiparallel resistance R AP ") is relatively high, at least in part due to spin-dependent scattering of minority and majority electrons. The memory state ("0" or "1") of the MRAM memory cell 10 is read by measuring the resistance of the MRAM memory cell 10. In this regard, the conductors 20 / 22 attached to the MRAM memory cell 10 are used to read MRAM data. The magnetization direction in the free layer 14 changes in response to the current 24 flowing in the digit line 26 and in response to the current 28 flowing in the write line 20, and these currents respectively generate magnetic fields 30 and 32. FIG. 1A depicts the situation where the current 24 in the digit line 26 flows out of the page and the current 28 in the write line 20 flows from left to right. Thus, the magnetic fields 30 and 32 are orthogonal to each other, which will cause the magnetization direction in the free layer 14 to switch from parallel to antiparallel with respect to the magnetization direction of the fixed layer 16. By reversing the polarity of the current 28 in the write line 20 while maintaining the constant polarity of the current 24 in the digit line 26, the orientation of the bit is switched. The field-induced switching technique described above for the MRAM memory cell 10 of FIG. 1A has some practical limitations, especially when the design requires the MRAM memory cell to be scaled down to a smaller size. For example, because this technique requires two sets of magnetic field write lines, the array of MRAM memory cells is vulnerable to bit interference (i.e., adjacent cells may inadvertently change in response to the write current directed to a given cell). Furthermore, reducing the physical size of the MRAM memory cell results in a decrease in the magnetic stability against magnetization switching due to thermal fluctuations. To enhance the stability of the bit, a magnetic material with a large magnetic anisotropy (and thus a large switching field) can be used for the free layer, but the current required to generate a magnetic field strong enough to switch the bit is impractical in existing applications. Another technique for programming an MRAM memory cell is spin-transfer-torque (STT) switching. FIG. 1B is a schematic diagram of the STT switching technique for the MRAM memory cell 50, which includes a magnetic tunnel junction 52 that includes an upper ferromagnetic layer 54, a lower ferromagnetic layer 56, and a tunneling barrier 58, and the tunneling barrier is an insulating layer located between the two ferromagnetic layers. In this example, the lower ferromagnetic layer 56 is the free layer with a switchable magnetization direction. The upper ferromagnetic layer 54 is a pinned or fixed layer with a magnetization direction that is not easily changed. When the magnetization direction in the free layer 56 is parallel to the magnetization direction of the fixed layer 54, the parallel resistance R across the MRAM memory cell 50 P is relatively low. When the magnetization direction in the free layer 56 is antiparallel to the magnetization direction of the fixed layer 54, the antiparallel resistance R across the MRAM memory cell 50 APis relatively high. The memory state ("0" or "1") of the memory cell 50 is read by measuring the resistance of the MRAM memory cell 50. In this regard, the conductors 60 / 62 attached to the MRAM memory cell 50 are used to read MRAM data. By design, both the parallel and anti-parallel configurations remain stable during the stationary state and / or during the read operation (at a sufficiently low read current). In the remaining text and figures, the direction of the write current is defined as the direction of the electron flow. Therefore, the term write current refers to the electron flow. To "set" the bit value of the MRAM memory cell (i.e., to select the magnetization direction of the free layer), a write current 64 is applied from the conductor 60 to the conductor 62. Since the fixed layer 54 is a ferromagnetic metal, the electrons in the write current 64 become spin-polarized when passing through the fixed layer 54. Although the spin orientation of the conducting electrons in a ferromagnetic metal is collinear with the magnetization direction, substantially most of them will have a specific orientation parallel to the magnetization direction, thus generating a net spin-polarized current. (Electron spin refers to the angular momentum, which is proportional to the magnetic moment of the electron but anti-parallel to the magnetic moment of the electron in direction. However, for the sake of discussion, this directional difference will not be used hereafter.) When the spin-polarized electrons tunnel across the tunneling energy barrier 58, conservation of angular momentum causes a torque to be applied to both the free layer 56 and the fixed layer 54. However, this torque (by design) is not sufficient to affect the magnetization direction of the fixed layer 54. On the contrary, if the initial magnetization direction of the free layer 56 is anti-parallel to the fixed layer 54, then this torque (by design) is sufficient to switch the magnetization direction of the free layer 56 to be parallel to the magnetization direction of the fixed layer 54. The parallel magnetization then remains stable before or after this write current is turned off. On the contrary, if the magnetization directions of the free layer 56 and the fixed layer 54 are initially parallel, the magnetization direction of the free layer 56 can be switched by STT by applying a write current in the opposite direction to the above case, making it anti-parallel to the magnetization direction of the fixed layer 54. Therefore, by the same STT physics, by wisely choosing the direction (polarity) of the write current, the magnetization direction of the free layer 56 can be deterministically set to either of the two stable orientations. The MRAM memory cell 50 of FIG. 1B uses a material in which the magnetization directions of both the fixed layer and the free layer are in-plane directions. In contrast, FIG. 1C depicts a schematic diagram of an STT-switching MRAM memory cell 70, in which the magnetization directions of both the fixed layer and the free layer are in the perpendicular direction. The MRAM memory cell 70 includes a magnetic tunnel junction 72, which includes an upper ferromagnetic layer 74, a lower ferromagnetic layer 76, and a tunneling barrier 78, which is an insulating layer located between the two ferromagnetic layers. In this example, the lower ferromagnetic layer 76 is the free layer with a switchable magnetization direction. The upper ferromagnetic layer 74 is the pinned or fixed layer, and it has a magnetization direction that is not easily changed. When the magnetization direction in the free layer 76 is parallel to the magnetization direction of the fixed layer 74, the resistance R across the MRAM memory cell 70 P is relatively low. When the magnetization direction in the free layer 76 is antiparallel to the magnetization direction of the fixed layer 74, the resistance R across the MRAM memory cell 70 AP is relatively high. The way to read the memory state ("0" or "1") of the MRAM memory cell 70 is by measuring the resistance of the MRAM memory cell 70. In this regard, the conductors 80 / 82 attached to the MRAM memory cell 70 are used to read the MRAM data. By design, both the parallel and antiparallel configurations remain stable during the stationary state and / or during the read operation (at a sufficiently low read current). To "set" the bit value of the MRAM memory cell (i.e., select the magnetization direction of the free layer), a write current 84 is applied from the conductor 80 to the conductor 82, and the MRAM memory cell 70 operates as discussed above with respect to FIG. 1B. Compared with the earliest MRAM memory cells (using the magnetic field generated by the current-carrying conductors adjacent to the MRAM memory cells), the STT-switching technology requires relatively less power, practically eliminates the problem of adjacent bit interference, and is more favorable for scaling up the cell density (reducing the size of the MRAM memory cell). The latter issue is also beneficial for STT MRAM, where the magnetization directions of the free layer and the fixed layer are perpendicular to the film plane rather than in-plane directions. However, in practice, STT switching requires the write current to flow completely through the tunneling barrier, which can have a negative impact on the long-term reliability of the STT MRAM memory cell due to the necessary stress of the medium-to-high write voltage across the tunneling barrier. FIG. 1D depicts an alternative MRAM memory cell 100 that uses a spin current to switch a free layer using spin orbit torque (SOT). The spin of an electron is an intrinsic angular momentum, distinct from the angular momentum resulting from the electron's orbital motion. In solids, the spins of many electrons act together to affect the magnetic and electronic properties of materials, such as conferring a permanent magnetic moment on the material in a ferromagnet. In many materials, the directions of electron spins up and down are equal, and the transport properties do not depend on spin. However, various techniques can be used to generate a group of spin-polarized electrons, creating an excess of spin-up or spin-down electrons to change the properties of the material. This group of spin-polarized electrons moving in a common direction through a common material is called a spin current. As described herein, spin currents can be used to operate MRAM memory cells. Generally, when a charge current is applied in a transverse (in-plane) direction, the spin Hall effect (SHE) can be used to generate a spin current flowing in a longitudinal (perpendicular to the plane) direction. The spin polarization direction of the spin current generated by this spin Hall effect is orthogonal to the in-plane direction of the charge current. The MRAM memory cell 100 includes three terminals A, B, and C, a magnetic tunnel junction 102, and a SHE material 120. In one embodiment, the magnetic tunnel junction 102 includes a free layer, a tunneling barrier, and a fixed layer. In another embodiment, the magnetic tunnel junction 102 includes a fixed layer 106, an interlayer coupling (ILC) layer 108, a reference layer (RL) 110, a tunneling barrier 112, and a free layer 114. The interlayer coupling layer 108 promotes strong antiferromagnetic (i.e., anti-parallel) coupling between the fixed layer 106 and the reference layer 110, such that their net magnetic moments mostly cancel, thus greatly reducing the unwanted stray field on the free layer. The spin Hall effect layer 104 includes a heavy metal with strong SHE, such as platinum, tantalum, or tungsten. The magnetization direction of the free layer 114 switches between up and down. The advantage of the SOT switching design using the spin Hall effect is that the write current 116 only passes through the spin Hall effect layer 104 and does not flow through the tunneling barrier 112. Thus, the aforementioned long-term degradation of the tunneling barrier 112 is eliminated by the switching current in the previous STT switching design for MRAM memory cells. FIG. 1E depicts a schematic diagram of the voltage control of a voltage-controlled magnetic anisotropy (VCMA) MRAM memory cell 120. The VCMA memory cell 120 is structurally similar to the STT switching MRAM memory cell 70 of FIG. 1C, but there are some differences. The MRAM memory cell 120 includes a magnetic tunnel junction 122, which includes an upper ferromagnetic layer 124, a lower ferromagnetic layer 126, a spacer layer (SP) 128, a tunneling barrier 138, and a reference layer 140. The upper ferromagnetic layer 124 is also referred to as the bias layer 124, and the lower ferromagnetic layer 126 is also referred to as the free layer 126. When the magnetization direction in the free layer 126 is parallel to the magnetization direction of the reference layer 140, the resistance R across the MRAM memory cell 120 P is relatively low. When the magnetization direction in the free layer 126 is antiparallel to the magnetization direction of the reference layer 140, the resistance R across the MRAM memory cell 120 AP is relatively high. The memory state ("0" or "1") of the MRAM memory cell 120 is read by measuring the resistance of the MRAM memory cell 120. In this regard, the conductors 142 / 144 attached to the MRAM memory cell 120 are used to read MRAM data. The read procedure is the same as the read procedure of the MRAM memory cell 70 of FIG. 1C, except that the read polarity is selected to be opposite to the write polarity. In one embodiment, the write procedure of the MRAM memory cell 120 is as follows: (1) Read the MRAM memory cell 120 to determine its state, (2) If the MRAM memory cell 120 is in the desired write state, then terminate the write procedure, (3) Otherwise, apply a write voltage to the MRAM memory cell 120 with a polarity that reduces the magnetic anisotropy of the free layer to near zero (when applying the write voltage, the free layer will precess around the magnetic field direction defined by the magnetic bias layer 124), (4) Remove the write voltage after ½ precession cycle, and (5) Repeat steps 1 to 4 until the state is correctly written or until the write procedure times out. In an embodiment, the materials and interfaces of the free layer 126, the spacer layer 128, and the tunneling barrier 130 are selected to provide a large VCMA coefficient for the FL 126 to maximize the change in the free layer magnetic anisotropy with the applied voltage. This may require using materials that increase the resistance of the tunneling barrier 130. To make the switching have sufficient reliability, the free layer 126 generally requires a small non-zero in-plane bias field. In one embodiment, the bias field is generated by the bias layer 124. Alternatively, the in-plane field can be supplied by a magnet outside the MRAM memory cell 120 or by an Oersted field generated by passing a current through the wiring close to the memory cell. FIG. 2A depicts example current-versus-voltage characteristics of MRAM memory cells such as MRAM memory cells 10, 50, 70, and 100 of FIGS. 1A-1D, respectively. For simplicity, the discussion of FIG. 2A will refer to MRAM memory cell 50 of FIG. 1B. In one embodiment, MRAM memory cell 50 can switch reversibly between a "parallel state" (P) (depicted by a solid line in FIG. 2A) and an "antiparallel state" (AP) (depicted by a dashed line in FIG. 2A). In the parallel state P, the magnetization direction in free layer 56 is parallel to the magnetization direction of fixed layer 54. In the antiparallel state AP, the magnetization direction in free layer 56 is antiparallel to the magnetization direction of fixed layer 54. If MRAM memory cell 50 is initially in the antiparallel state AP and a write electron current 64 is applied from conductor 60 to conductor 62, then MRAM memory cell 50 will switch to the parallel state P. In the embodiment depicted in FIG. 2A, MRAM memory cell 50 switches from the antiparallel state AP to the parallel state P at a write voltage V AP-P of approximately 1.12V between conductor 62 and conductor 60. Conversely, if MRAM memory cell 50 is initially in the parallel state P and a write electron current 64 is applied from conductor 62 to conductor 60, then MRAM memory cell 50 will switch to the antiparallel state AP. In the embodiment depicted in FIG. 2A, MRAM memory cell 50 switches from the parallel state P to the antiparallel state AP at a write voltage V P-AP of approximately 0.36V between conductor 62 and conductor 60. The state of an MRAM memory cell such as MRAM memory cell 50 of FIG. 1B can be determined by applying a read reference (e.g., a read reference voltage V rd ) across the MRAM memory cell (e.g., between conductors 60 and 62 of MRAM memory cell 50). The applied read reference V rd generates a current proportional to the resistance of the MRAM memory cell. In the embodiment depicted in FIG. 2A, at a read reference V rd of approximately 0.56V, MRAM memory cell 50 has an antiparallel resistance R AP in the antiparallel state AP and a parallel resistance R P in the parallel state P. Therefore, by detecting the resistance of the MRAM memory cell at the read reference V rd and then comparing the detected resistance with the threshold resistance value R T , the state of each MRAM memory cell can be determined. If the resistance detected by the MRAM memory cell is greater than the threshold resistance value R T , it is determined that the MRAM memory cell is in the anti-parallel state AP; and if the resistance detected by the MRAM memory cell is less than the threshold resistance value R T , it is determined that the MRAM memory cell is in the parallel state P. Because the anti-parallel resistance R AP value and the parallel resistance R P value of each MRAM memory cell remain relatively constant, this read technique (referred to herein as "single-reference read") is very effective for reading each MRAM memory cell. However, in a group of MRAM memory cells (e.g., in a memory array of MRAM memory cells), the variation ranges of the anti-parallel resistance R AP value and the parallel resistance R P are often quite large. In addition, as depicted in FIG. 2B, in a group of memory cells, the anti-parallel resistance R AP value and the parallel resistance R P value often overlap as well. Due to this overlap phenomenon, the single-reference read of a group of memory cells can only accurately distinguish a limited number of bits. For simplicity, in the remaining description, the term "codeword" is used to describe a group of multiple memory cells that store a predetermined number of data bits (e.g., 16 bits, 64 bits, 1024 bits, or some other number of data bits). In one embodiment, the codeword includes several bits that can be encoded and decoded by an (generally on-die) error correction coding (ECC) engine. For example, FIG. 2C depicts the bit error rate (BER) of a large group of memory cells (e.g., all memory cells in a memory array including a large number of memory cells) relative to the read reference V rdThe graph indicates that for the entire group of memory cells, using an approximately 0.73V "optimal" read reference V rdo can achieve a minimum bit error rate of approximately 7%. Although a single read reference V rdo can be used to successfully read some codewords, for other codewords, using a single read reference V rdo the number of bit errors that occur may exceed the maximum number of bit errors that can be corrected by the ECC engine. In such cases, alternative read techniques are generally used to read the codewords, such as self-reference reading. For example, a self-reference reading technique performs a first read on a memory cell, then writes to a first memory state, performs a second read, and then compares the results of the first read and the second read. If the two read results are the same, it is determined that the memory cell was initially in the first memory state and remains in the first memory state. However, if the two read results are different, it is determined that the memory cell was initially in the second memory state but is now in the first memory state. As a result, a write operation is required to restore the memory cell to the second memory state. Although such self-reference reading techniques can be used to successfully read codewords that cannot be successfully read using a single reference read, self-reference reading requires at least two reads and one write operation, and may require additional write operations. Therefore, such self-reference reading techniques take a long time to complete, are prone to write errors, and may also reduce the durability of the memory cells. To overcome these deficiencies, a two-step read technique for reading MRAM memory cells is proposed. Specifically, a technique for fast, two-step reading of resistive random access memory cells (such as MRAM cells) is described. In one embodiment, a two-step read procedure is used to read a codeword with a specified address from a group of memory cells. In one embodiment, a global read reference value is used to perform the first read of the codeword. In one embodiment, when performing the first read, a lookup table is searched to determine if there is an entry for the specified address. In one embodiment, the lookup table includes codeword addresses and corresponding individual read reference values. In one embodiment, if the lookup table includes an entry for the specified address, the corresponding individual read reference value for the codeword is used to perform a second read of the codeword. In one embodiment, the global read reference value is a selected read reference value used to read all the codewords of the memory array. In one embodiment, the global read reference value can be determined during wafer sorting and has a value that results in the lowest number of bit errors for all the codewords of the memory array. In one embodiment, individual read reference values are selected for reading corresponding codewords of the memory array. In one embodiment, the individual read reference values can be determined during wafer sorting and have values that result in the lowest number of bit errors in the codewords. FIG. 3A is a flowchart of an embodiment of a procedure 300a for a lookup table of individual read reference values for establishing groups of codewords. In one embodiment, the procedure 300a can be executed by a system control circuit described below. In one embodiment, the lookup table is addressed by codeword addresses. In one embodiment, the group of codewords includes all codewords of the memory array. In another embodiment, the group of codewords includes less than all codewords of the memory array. For simplicity, in the remaining description, it is assumed that the group of codewords includes m codewords CW i , where i = 0, 1, 2, ..., m-1. Additionally, for simplicity, the remaining description uses the term "all codewords" to mean all codewords CW i in the group of m codewords, and uses the term "each codeword CW i " to mean each codeword CW i in the group of m codewords. In step 302, data is written to all codewords CW i . In one embodiment, all bits of the codeword CW i are written to a first memory state (e.g., 0). Alternatively, all bits of the codeword CW i can be written to a second memory state (e.g., 1). In step 304, each codeword CW i is read sequentially using a plurality of candidate read reference values. In one embodiment, each codeword CW rdj is read sequentially using n candidate read reference values v i , where j = 0, 1, 2, ..., n-1. For example, the candidate read reference values v rdj can be selected based on simulation results, empirical evidence, or a combination of both, or by some other method. In step 306, based on the read results of step 304, for each codeword CW iand each candidate read reference value v rdj to determine the failure bit count FB ij Alternatively, for each codeword CW i and each candidate read reference value v rdj to determine the bit error rate BER ij FIG. 4A depicts in tabular form an example where m = 8 and n = 4. In the illustrated example, when reading using the candidate read reference value v rd0 the codeword CW 0 has a failure bit count FB 00 when reading using the candidate read reference value v rd2 the codeword CW 1 has a failure bit count FB 12 when reading using the candidate read reference value v rd1 the codeword CW 5 has a failure bit count FB 51 and so on. FIG. 4B depicts the table of FIG. 4A with example numerical failure bit count values. For example, when reading using the candidate read reference value v rd2 the codeword CW 2 has a failure bit count FB 22 = 3, when reading using the candidate read reference value v rd0 the codeword CW 4 has a failure bit count FB 40 = 4, when reading using the candidate read reference value v rd1 the codeword CW 6 has a failure bit count FB 61= 2, and so on. Referring again to FIG. 3A, at step 308, for each codeword CW i determine a corresponding individual read reference value v rdi . In one embodiment, the codeword CW i has the individual read reference value v rdi with the lowest failure bit count FB ij , for j = 0, 1, 2, ..., n - 1. Thus, using the example values of FIG. 4B, the corresponding individual read reference value v rdi is: Referring again to FIG. 3A, at step 310, determine the global read reference value v i for all codewords CW rdg . In one embodiment, the global read reference value v i for all codewords CW rdg is a read reference value v rdj that results in the lowest sum of failure bit counts FB ij , for i = 0, 1, 2, ..., m - 1. Thus, using the example values of FIG. 4B, the read reference value v rd1 results in the lowest sum (20 failure bits), and thus the global read reference value v i for all codewords CW rdg = v rd1 . Referring again to FIG. 3A, at step 312, specify the expected maximum failure bit count FB i for each codeword CW M . For example, the expected maximum failure bit count FB M can be 2 bits, 3 bits, etc. In step 314, when using the global read reference value v rdg to read a codeword, any codeword CW i identified as having a failure bit count FB M greater than the expected maximum failure bit count FB ij (i.e., FB ij > FB M ). For example, referring again to the example values of FIG. 4B, if the expected maximum failure bit count FB M = 2 bits, then when using the global read reference value v rdg = v rd1 to read a codeword, the codewords CW 2 , CW 5 and CW 7 each have a failure bit count FB M greater than the expected maximum failure bit count FB ij . Alternatively, if the expected maximum failure bit count FB M = 5 bits, then when using the global read reference value v rdg = v rd1 to read a codeword, the codeword CW 5 has a failure bit count FB M greater than the expected maximum failure bit count FB ij . Referring again to FIG. 3A, in step 316, for each codeword CW i identified in step 314, an entry in the lookup table is created. In one embodiment, each lookup table entry includes the address of each codeword CW i identified in step 314, and the identified codeword CW i corresponding individual read reference value v rdi . FIG. 4C depicts an example lookup table 400c, which includes items established at step 316 of procedure 300a, using the example data of FIG. 4B and an expected maximum failure bit count FB M = 2 bits. Specifically, the lookup table 400c includes a first item that includes the address of the codeword CW 2 and its corresponding individual read reference value v rd0 ; a second item that includes the address of the codeword CW 5 and its corresponding individual read reference value v rd3 ; and a third item that includes the address of the codeword CW 7 and its corresponding individual read reference value v rd2 . FIG. 4D depicts an example lookup table 400d, which includes items established at step 316 of procedure 300a, using the example data of FIG. 4B and an expected maximum failure bit count FB M = 5 bits. Specifically, the lookup table 400d includes a single item that includes the address of the codeword CW 5 and its corresponding individual read reference value v rd3 . Thus, without wishing to be bound by any particular theory, it is believed that these examples illustrate that as the expected maximum failure bit count FB M decreases, the number of lookup table entries generally increases because when reading codewords using the global read reference value v rdg , more codewords CW i can have a failure bit count FB M greater than the expected maximum failure bit count FB ij . In the above example method 300a, at step 302, all codewords CW iBits are written to a first memory state (e.g., 0) or a second memory state (e.g., 1). However, for some memory devices, when the codeword is written to the first memory state, the codeword may have a first failure bit count, and when the codeword is written to the second memory state, it may have a second failure bit count. In some embodiments, the first failure bit count may be higher or lower than the second failure bit count. That is, depending on the data written to the codeword, the codeword may have a higher failure bit count. FIG. 3B is a flowchart of an embodiment of an alternative procedure 300b for a lookup table that is used to establish individual read reference values for groups of codewords. Example procedure 300b is similar to example procedure 300a of FIG. 3A, but includes writing all bits of each codeword CW i to both a first memory state and a second memory state. In one embodiment, procedure 300b may be performed by the system control circuitry described below. In step 318, during a first write operation, all bits of the codeword CW i are written to a first memory state (e.g., 0). In step 320, during a first read operation, each codeword CW i is read sequentially using a plurality of candidate read reference values. In one embodiment, using n candidate read reference values v rdj , j = 0, 1, 2,..., n - 1, each codeword CW i is read sequentially. For example, the candidate read reference values v rdj may be selected based on simulation results, empirical evidence, or a combination of both, or by some other method. In step 322, during a second write operation, all bits of the codeword CW i are written to a second memory state (e.g., 1). In step 324, during a second read operation, each codeword CW i is read sequentially using the same plurality of candidate read reference values used in step 320. In step 326, based on the read results of step 320 and the read results of step 304, for each codeword CW i and each candidate read reference value v rdj , a failure bit count FB is determined ij . In one embodiment, for each codeword CW i , the determined failure bit count FB ij is the larger of the failure bit counts from the first read operation and the second read operation. Alternatively, for each codeword CW i and each candidate read reference value v rdj , the bit error rate BER ij can be determined. In one embodiment, for each codeword CW i , the determined bit error rate BER ij is the larger of the bit error rates from the first read operation and the second read operation. The remaining steps 308 to 316 of procedure 300b are the same as those of procedure 300a, but use the failure bit count FB ij determined in step 326, which is based on two separate write operations and read operations for each codeword CW i . Without wishing to be bound by any particular theory, it is believed that procedure 300b can result in identifying individual read reference values that are effective for both the first memory state and the second memory state. In steps 302, 318, and 322 of the above example procedures 300a and 300b, all bits of the codeword CW i are written in their entirety to either the first memory state or the second memory state. That is, all bits of all codewords CW i are written to either the first memory state or the second memory state. Those of ordinary skill in the art will understand that the codeword bits can alternatively be written using a predetermined random bit pattern (e.g., "0101010...", "0100010...", "11110000...", or some other predetermined random bit pattern). In one embodiment, the above example procedures 300a and 300b can be executed once. For example, the above procedures 300a and 300b can be executed at wafer sorting, and the lookup table entries established in step 316 can be stored in a lookup table, which is stored in the memory on the memory die. In one embodiment, the lookup table can be stored in a small, fast memory structure such as a content addressable memory (CAM) or other type of memory. In other embodiments, the above example procedures 300a and 300b can be executed more than once. For example, the above example procedures 300a and 300b can be initially executed at wafer sorting to establish initial entries in the lookup table, and can then be executed one or more additional times during the lifetime of the memory die to establish updated or additional entries in the lookup table. FIG. 5 is a flowchart of one embodiment of a procedure 500 for reading codewords. In one embodiment, procedure 500 can be executed by the system control circuitry described below. In step 502, a read command is received. For example, a host device can send a read command to the memory controller. In one embodiment, the read command specifies one or more codewords CW i whose addresses are to be read. For simplicity, the following description assumes that the received read command specifies a single address ADD i for a single codeword CW i . In step 504, the codeword CWi at the specified address ADD i is read using a global read reference value, such as the global read reference value v determined in step 310 of procedure 300a of FIG. 3A or procedure 300b of FIG. 3B. rdg . In step 506, a search is performed on the lookup table established using procedure 300a of FIG. 3A or procedure 300b of FIG. 3B (e.g., lookup table 400c of FIG. 4C or lookup table 400d of FIG. 4D) to determine whether the lookup table includes an entry for the specified address ADD i . In step 508, it is determined whether the lookup table includes a matching address ADD i . If it is determined in step 508 that the lookup table does not include a matching address ADD i , then in step 510 the match flag I m is set equal to 0. If it is determined in step 508 that the lookup table includes the matching address ADD i , then in step 512, the corresponding individual read reference value v of the codeword at the address ADD i is retrieved from the lookup table. rdi In step 514, the match flag I m is set equal to 1. In one embodiment, steps 506 to 514 are performed in parallel with the read operation performed in step 504. In one embodiment, steps 506 to 514 are performed while the read operation is being performed in step 504. In one embodiment, the time required to complete steps 506 to 514 is less than or equal to the time required to complete the read operation performed in step 504. In step 516, the read data from step 504 is decoded (e.g., using an ECC engine). The ECC engine can generally successfully correct a maximum number of bit errors ECC M . (For example, ECC M = 5 bits, 7 bits, or some other maximum number of bits). If the data read in step 504 includes less than or equal to ECC M bit errors, then the ECC engine can successfully correct the errors and the ECC operation will pass. However, if the data read in step 504 includes more than ECC M bit errors, then the ECC engine cannot successfully correct the errors and the ECC operation will fail. In step 518, it is determined whether the ECC operation in step 516 has passed. If it is determined in step 518 that the ECC engine has successfully decoded the data read in step 504, then in step 520 the decoded data is provided to the host. However, if it is determined in step 518 that the ECC engine cannot successfully decode the data read in step 504, then in step 522 it is determined whether the match flag I m = 1. If it is determined in step 522 that the match flag I m is not equal to 1, then a failure handling operation can be performed in step 524. In one embodiment, the failure handling operation can include performing an overwrite read operation on the codeword CW i . However, if it is determined in step 522 that the match flag I m is equal to 1, then in step 526, the codeword CWi at the specified address ADD i is read again, but this time using the corresponding individual read reference value v retrieved from the lookup table in step 512 rdi . In step 528, the match flag I m is set equal to 0, and then the program 500 returns to step 516 to decode the read data, and in this case, the data read in step 526 is used. In step 518, it is determined whether the ECC operation in step 516 passes. If it is determined in step 518 that the ECC engine successfully decodes the data read in step 504, then in step 520, the decoded data is provided to the host. However, if it is determined in step 518 that the ECC engine fails to successfully decode the data read in step 504, then in step 522, it is determined whether the match flag I m = 1. Since the match flag I m is reset to 0 in step 528, the failure handling operation can be performed in step 524, such as those described above. Without wishing to be bound by any particular theory, it is believed that the program 500 can improve and reduce the time required to read the codeword. Specifically, the global read reference value v rdg is used to first read the specified codeword CW i . Without wishing to be bound by any particular theory, it is believed that in many cases, even if the lookup table includes the item of the address ADD i of the specified codeword CW i , this read can be successful. However, if the first read is unsuccessful and if the lookup table includes the item of the address ADD i of the specified codeword CW i , then the corresponding individual read reference value v retrieved from the lookup table rdi is used to secondarily read the specified codeword CW i。Without wishing to be bound by any particular theory, it is believed that this second read will succeed because the second read uses individual read reference values v i that are specifically selected for the designated codeword CW rdi 。 However, if the second read is unsuccessful, failure handling operations (such as performing an overwrite read on the designated codeword CW i ) can be used to successfully read the codeword. Without wishing to be bound by any particular theory, it is believed that because the lookup table is searched in parallel with the first read operation and any matching individual read reference values v rdi are retrieved, the second read operation can be performed quickly and does not require trial and error attempts to find alternative read reference values that can successfully read the designated codeword CW i 。 In addition, without wishing to be bound by any particular theory, it is believed that the described procedure can eliminate or substantially reduce the number of overwrite read operations required to read the codewords on the memory die. FIG. 6 is a flowchart of an embodiment of a procedure 600 for reading codewords. In one embodiment, procedure 600 can be performed by the system control circuitry described below. In step 602, a command to read a first codeword from a memory array is received, the memory array including a plurality of codewords that commonly have a corresponding first predetermined read reference value, each codeword having a corresponding second predetermined read reference value. In step 604, the first codeword is read using the first predetermined read reference value to provide first read data. In step 606, while reading the first codeword, the second predetermined read reference value corresponding to the first codeword is retrieved from a lookup table. In step 608, an error correction code algorithm is used to decode the first read data. In step 610, it is determined that the error correction code algorithm cannot correctly decode the first read data. In step 612, the first codeword is read using the retrieved second predetermined read reference value to provide second read data. FIG. 7 is a block diagram depicting an example of a memory system 700 that can implement the techniques described herein. Memory system 700 includes a memory array 702, which can include any of the memory cells described above. The array terminal lines of memory array 702 include layers of word lines organized into columns and layers of bit lines organized into rows. However, other orientations can also be implemented. Memory system 700 includes column control circuitry 704, the output 706 of which is connected to respective word lines of memory array 702. Column control circuitry 704 receives a group of M column address signals and one or more various control signals from system control logic circuitry 708, and generally may include circuitry such as column decoder 710, array terminal driver 712, and block selection circuitry 714 for both read and write operations. Memory system 700 also includes row control circuitry 716, the input / output 718 of which is connected to respective bit lines of memory array 702. Row control circuitry 718 receives a group of N row address signals and one or more various control signals from system control logic 708, and generally may include circuitry such as row decoder 720, array terminal receiver or driver 722, block selection circuitry 724, and read / write circuitry, and I / O multiplexer. System control logic 708 receives data and commands from a host and provides output data and status to the host. In other embodiments, system control logic 708 receives data and commands from a separate controller circuit and provides output data to the controller circuit, where the controller circuit communicates with the host. System control logic 708 may include one or more state machines, registers, and other control logic for controlling the operation of memory system 700. In one embodiment, system control logic 708 includes a memory structure (not shown) for storing the lookup tables described above, such as lookup tables 400c and 400d in FIGS. 4C and 4D, respectively. In one embodiment, the memory structure is a small, fast memory structure. In one embodiment, the memory structure is a content addressable memory. Other memory structures may be used. In other embodiments, a portion of memory array 702 may be used to store the lookup tables described above, such as lookup tables 400c and 400d in FIGS. 4C and 4D, respectively. In one embodiment, all of the components depicted in FIG. 7 are disposed on a single integrated circuit. For example, system control logic 708, row control circuitry 716, and column control circuitry 704 are formed on the surface of a substrate, and memory array 702 is formed on or above the substrate. In one embodiment, one or more of memory array 702, column control circuitry 704, row control circuitry 716, and system control logic 708 constitute a system control circuit that includes hardware and / or software configured to implement methods 300a, 300b, 500, and 600 in FIGS. 3A, 3B, 5, and 6, respectively. Although the techniques described above and the example methods 300a, 300b, 500, and 600 in FIGS. 3A, 3B, 5, and 6, respectively, have been described with reference to MRAM memory cells, those of ordinary skill in the art will understand that the techniques can be used with any resistive switching memory cell, including MRAM memory cells, phase change memory cells, reversible resistive switching random access memory (ReRAM) memory cells, and other resistive switching memory cells. Additionally, the techniques described above and the example methods 300a, 300b, 500, and 600 in FIGS. 3A, 3B, 5, and 6, respectively, can be used with a block of multiple resistive switching memory cells. One embodiment includes a device that includes a memory array and a control circuit. The memory array includes non-volatile memory cells, each of the non-volatile memory cells including a resistive random access memory element. The control circuit is configured to: receive a read command specifying an address of a first group of the non-volatile memory cells; perform a first read on the first group of the non-volatile memory cells using a first predetermined read reference value to provide first read data; while performing the first read, retrieve a second predetermined read reference value corresponding to the specified address from a memory; and in response to satisfying a condition regarding the first read data, perform a second read on the first group of the non-volatile memory cells using the second predetermined read reference value to provide second read data. One embodiment includes a method that includes: receiving a command to read a first codeword from a memory array that includes a plurality of codewords that collectively include a corresponding first predetermined read reference value, each codeword having a corresponding second predetermined read reference value, each of the codewords including a corresponding second predetermined read reference value; reading the first codeword using the first predetermined read reference value to provide first read data; while reading the first codeword, retrieving the second predetermined read reference value corresponding to the first codeword from a look-up table; decoding the first read data using an error correction code algorithm; determining that the error correction code algorithm cannot correctly decode the first read data; and reading the first codeword using the retrieved second predetermined read reference value to provide second read data. One embodiment includes a system that includes a control circuit configured to: receive a command from a host device to read a first group of non-volatile memory cells in a memory array including a plurality of groups of memory cells; perform a first read on the first group of non-volatile memory cells using a first predetermined read reference value; retrieve a second predetermined read reference value from a look-up table; and selectively perform a second read on the first group of non-volatile memory cells using the second predetermined read reference value only if data read during the first read cannot be correctly decoded. The retrieving step is performed in parallel with the first read step. The first predetermined read reference value minimizes the failure bit count of all groups of memory cells. The second predetermined read reference minimizes the failure bit count of the first group of memory cells. For the purposes of this document, references in this specification to "an embodiment", "one embodiment", "some embodiments", or "another embodiment" may be used to describe different embodiments or the same embodiment. For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some instances, when an element is said to be connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intervening element. When an element is said to be directly connected to another element, there is no intervening element between the element and the other element. Two devices are "in communication" if they are directly or indirectly connected such that they can convey electronic signals between them. For the purposes of this document, the term "based on" may be construed as "based at least in part on". For the purposes of this document, without additional context, the use of numerical terms such as "first" object, "second" object, and "third" object may not imply an order of the objects, and may instead be used for identification purposes to identify different objects. For the purposes of this document, a "set" of objects may refer to a "set" of one or more of the objects. The above-described embodiments have been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen in order to best explain the principles of the claimed technology and its practical application, thereby enabling those of ordinary skill in the art to best utilize the invention in various embodiments and to contemplate various modifications suitable for a particular use. It is intended that the scope be defined by the appended claims. 10: MRAM memory cell 12: Magnetic tunnel junction 14: Upper ferromagnetic layer, free layer 16: Lower ferromagnetic layer, fixed layer 18: Tunneling barrier 20: Conductor, write line 22: Conductor 24: Current 26: Digital line 28: Current 30, 32: Magnetic field 50: MRAM memory cell 52: Magnetic tunnel junction 54: Upper ferromagnetic layer, fixed layer 56: Lower ferromagnetic layer, free layer 58: Tunneling barrier 60, 62: Conductor 64: Write current, write electron current 70: MRAM memory cell 72: Magnetic tunnel junction 74: Upper ferromagnetic layer, fixed layer 76: Lower ferromagnetic layer, free layer 78: Tunneling barrier 80, 82: Conductor 84: Write current 100: MRAM memory cell 102: Magnetic tunnel junction 104: Spin Hall effect layer 106: Fixed layer 108: Interlayer coupling layer 110: Reference layer 112: Tunneling barrier 114: Free layer 116: Write current 120: SHE material, MRAM memory cell 122: Magnetic tunnel junction 124: Upper ferromagnetic layer, bias layer 126: Lower ferromagnetic layer, free layer 128: Spacer layer 130: Tunneling barrier 138: Tunneling barrier 140: Reference layer 142, 144: Conductor 300a, 300b: Process, method 302, 304, 306, 308, 310, 312, 314, 316, 318, 320, 322, 324, 326: Steps 400c, 400d: Lookup table 500: Process, method 502, 504, 506, 508, 510, 512, 514, 516, 518, 520, 522, 524, 526, 528: Steps 600: Process, method 602, 604, 606, 608, 610, 612: Steps 700: Memory system 702: Memory array 704: Column control circuitry 706: Output 708: System control logic circuitry 710: Column decoder 712: Array terminal driver 714: Block select circuitry 716: Row control circuitry 718: Input / output, row control circuitry 720: Row decoder 722: Array terminal receiver or driver 724: Block select circuitry A: Terminal B: Terminal C: Terminal Elements with similar numbers refer to common components in different diagrams. [Fig. 1A] is a block diagram of an MRAM memory cell. [Fig. 1B] is a block diagram of an MRAM memory cell. [Fig. 1C] is a block diagram of an MRAM memory cell. [Fig. 1D] is a block diagram of an MRAM memory cell. [Fig. 1E] is a block diagram of an MRAM memory cell. [Fig. 2A] depicts an example current versus voltage characteristic of an MRAM memory cell. [Fig. 2B] is a graph of example anti-parallel resistance values and parallel resistance values in a group of memory cells. [Fig. 2C] depicts a graph of bit error rate versus read reference for a large group of memory cells in a memory array. [Fig. 3A] is a flowchart of an embodiment of a procedure for a lookup table for individual read reference values for a group of codewords to be established. [Fig. 3B] is a flowchart of an alternative procedure for a lookup table for individual read reference values for a group of codewords to be established. [Fig. 4A] is a table depicting example codewords and failure bit counts of example candidate read reference values. [Fig. 4B] depicts a graph of the example numerical failure bit count values of the table of Fig. 4A. [Fig. 4C] depicts an example lookup table including entries established using the procedure of Fig. 3A, using the example data of Fig. 4B, and a desired maximum failure bit count of two bits. [Fig. 4D] depicts an example lookup table including entries established using the procedure of Fig. 3A, using the example data of Fig. 4B, and a desired maximum failure bit count of five bits. [Fig. 5] is a flowchart of an embodiment of a procedure for reading codewords. [Fig. 6] is a flowchart of another embodiment of a procedure for reading codewords. [Fig. 7] is a block diagram of a memory system using one of the reading techniques described herein.

Claims

1. An electronic device comprising: a memory array including a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells including a resistive random access memory element; and a control circuit configured to: receive a read command specifying an address of one of a first group of the non-volatile memory cells; perform a first read on the first group of the non-volatile memory cells using a first predetermined read reference value to provide first read data; while performing the first read, retrieve a second predetermined read reference value corresponding to the specified address from a memory, wherein a time required to retrieve the second predetermined read reference value is less than or equal to a time required to perform the first read; and in response to satisfying a condition relating to the first read data, perform a second read on the first group of the non-volatile memory cells using the second predetermined read reference value to provide second read data.

2. The electronic device as requested in item 1, wherein the first predetermined read reference value is selected from a plurality of candidate read reference values.

3. The electronic device as described in Request 1, wherein: The memory array comprises a plurality of groups of such non-volatile memory cells; and the first predetermined read reference value is selected based on the result of reading all such groups of such non-volatile memory cells using a plurality of candidate read reference values.

4. The electronic device of claim 3, wherein the first predetermined read reference value is selected by: determining, for each candidate read reference value, the total number of bit errors caused by reading each group of the non-volatile memory cells; and setting the first predetermined read reference value to the candidate read reference value having a minimum total number of bit errors.

5. The electronic device as requested in item 1, wherein the second predetermined read reference value is selected from a plurality of candidate read reference values.

6. The electronic device as requested in item 1, wherein: The memory array comprises a plurality of groups of such non-volatile memory cells; and the second predetermined read reference value is selected based on the result of reading the first group of such non-volatile memory cells using a plurality of candidate read reference values.

7. The electronic device of claim 6, wherein the second predetermined read reference value is selected by: determining, for each candidate read reference value, the total number of bit errors caused by reading the first group of non-volatile memory cells; and setting the second predetermined read reference value to the candidate read reference value having a minimum total number of bit errors.

8. The electronic device of claim 1, wherein the resistive random access memory element includes a magnetoresistive random access memory element.

9. The electronic device of claim 1, wherein the memory array comprises: a plurality of first conductive lines; and a plurality of second conductive lines, each of the plurality of non-volatile memory cells being connected between one of the first conductive lines and one of the second conductive lines.

10. The electronic device of claim 1, wherein the memory includes a lookup table configured to store addresses and corresponding second predetermined read reference values.

11. The electronic device of claim 1, wherein the memory includes a content-addressable memory.

12. The electronic device as requested in item 1, wherein: The device further includes a means configured to decode data read from the non-volatile memory cells; and the condition being met includes the inability to correctly decode the first read data.

13. The electronic device of claim 12, wherein the device includes an error correction coding engine.

14. A method for operating an electronic device, comprising: receiving a command to read a first codeword from a memory array, the memory array comprising a plurality of codewords, the plurality of codewords collectively comprising a corresponding first predetermined read reference value, each of the codewords comprising a corresponding second predetermined read reference value; using the first predetermined read reference value to read the first codeword to provide first read data; while reading the first codeword, retrieving the second predetermined read reference value corresponding to the first codeword from a lookup table, wherein a time required to retrieve the second predetermined read reference value from the lookup table is less than or equal to a time required to complete reading the first codeword; using an error correction code algorithm to decode the first read data; determining that the error correction code algorithm cannot correctly decode the first read data; and using the retrieved second predetermined read reference value to read the first codeword to provide second read data.

15. The method of claim 14, further comprising: using the error correction code algorithm to decode the second read data; and determining that the error correction code algorithm can correctly decode the second read data.

16. The method of request 14, wherein the lookup table contains a content-addressable memory.

17. The method of claim 14, wherein the memory array comprises a plurality of nonvolatile memory cells, each of the plurality of nonvolatile memory cells comprising a magnetoresistive random access memory element.

18. An electronic system comprising: a control circuit configured to: receive from a host device a command to read a first group of non-volatile memory cells in a memory array comprising a plurality of memory cell groups; perform a first read on the first group of non-volatile memory cells using a first predetermined read reference value; retrieve a second predetermined read reference value from a lookup table; and selectively perform a second read on the first group of non-volatile memory cells using the second predetermined read reference value only if data read during the first read cannot be correctly decoded, wherein: The fetching step is performed in parallel with the first read step, wherein the time required for the fetching step is less than or equal to the time required for the first read step; the first predetermined read reference value minimizes the failure bit count of one of the groups of memory cells; and the second predetermined read reference minimizes the failure bit count of one of the first groups of memory cells.

19. The electronic system of claim 18, wherein each of the non-volatile memory cells includes a magnetoresistive random access memory element.

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