Electronic device

Abstract

This disclosure provides an electronic device including a wafer, a first insulating layer, a first metal layer, and a second insulating layer. The first insulating layer surrounds the wafer and has a first opening. The first metal layer is electrically connected to the wafer. The second insulating layer is disposed between the first metal layer and the first insulating layer. The first opening penetrates the first insulating layer, and the depth of the first opening is greater than the thickness of the wafer.

Description

Technical Field

[0001] The invention relates to an electronic device. Prior Art

[0002] In the process of manufacturing electronic devices, warping of products caused by different physical properties of different materials, such as different thermal expansion coefficients, is a problem that needs to be overcome. Summary of the Invention

[0003] The present disclosure provides an electronic device with good quality.

[0004] According to an embodiment of the present disclosure, an electronic device includes a chip, a first insulating layer, a first conductive layer, and a second insulating layer. The first insulating layer surrounds the chip and has a first through-hole. The first conductive layer is electrically connected to the chip. The second insulating layer is disposed between the first conductive layer and the first insulating layer. The first through-hole penetrates the first insulating layer, and the depth of the first through-hole is greater than the thickness of the chip. Simple diagram description

[0005] FIG1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. 2A to 2E are schematic diagrams of a partial manufacturing method of an electronic device according to some embodiments of the present disclosure. 3A to 3E are schematic diagrams of a partial manufacturing method of an electronic device according to some embodiments of the present disclosure. Implementation Method

[0006] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0007] In the following description and claims, words such as “including” and “comprising” are open-ended words and should be interpreted as meaning “including but not limited to…”.

[0008] In this disclosure, when a structure (or layer, component, or substrate) is located on / above another structure (or layer, component, or substrate), or when one structure (or layer, component, or substrate) is connected to another structure (or layer, component, or substrate), the two structures may be adjacent and directly connected, or they may be adjacent but not directly connected. Indirect connection means that at least one intermediate structure (or intermediate layer, intermediate component, intermediate substrate, or intermediate spacer) exists between the two structures. The lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure may be composed of a single or multiple layers of physical or non-physical structures, without limitation. In this disclosure, when a structure is "disposed on" another structure, it may mean that the structure is "directly" on the other structure, or it may mean that the structure is "indirectly" on the other structure, i.e., at least one structure is interposed between the two structures.

[0009] While the terms "first," "second," "third," etc. may be used to describe various components, these terms are not intended to limit the components to these terms. These terms are used solely to distinguish a single component from other components within the specification. The claims may not use the same terms, but may be replaced with "first," "second," "third," etc., in the order in which the components are declared in the claims. Therefore, in the following description, the first component may be the second component in a claim.

[0010] As used herein, the terms "about," "approximately," "substantially," and "roughly" generally mean within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The quantities given here are approximate, meaning that even without the specific use of "about," "approximately," "substantially," or "roughly," the meanings of "about," "approximately," "substantially," or "roughly" are implied. Furthermore, the phrases "ranging from a first value to a second value" or "ranging between a first value and a second value" mean that the range includes the first value, the second value, and any other values ​​therebetween.

[0011] The electrical connection or coupling described in this disclosure may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of two circuit components are directly connected or connected to each other via a conductor segment. In the case of indirect connection, the endpoints of the two circuit components are connected by a switch, diode, capacitor, inductor, resistor, other suitable element, or a combination of the above elements, but are not limited to these.

[0012] In this disclosure, thickness, length, and width can be measured using an optical microscope, while thickness can be measured using cross-sectional images obtained through an electron microscope, but this is not a limitation. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If a first value is equal to a second value, this implies that there may be an error of approximately 10%, 5%, or 3% between the first and second values.

[0013] It should be noted that the following embodiments may be constructed by disassembling, replacing, recombining, or combining features from various embodiments to create other embodiments without departing from the spirit of the present disclosure. Features from various embodiments may be mixed and matched as needed, as long as they do not violate the spirit of the invention or conflict with it.

[0014] FIG1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Electronic device 100 includes multiple device regions 102 and non-device regions 104. The device regions 102 are arranged in an array and separated from each other, with non-device regions 104 distributed between the device regions 102. In some embodiments, the device region 102 may include at least a chip, a wiring layer, and packaging material. The chip may be a light-emitting chip, a semiconductor chip, or the like. In some embodiments, the semiconductor chip may define an electronic circuit composed of active components, passive components, or a combination thereof, such as a logic circuit or a memory circuit. In some embodiments, electronic device 100 may be a high-frequency component, a light-emitting component, a packaged component, or the like. The non-device region 104 may include dicing lines, and the electronic device 100 may be diced along the dicing lines to separate multiple independent electronic devices. In some embodiments, after dicing, the structure of the non-device region 104 may partially remain in the independent electronic devices or may not exist in the independent electronic devices.

[0015] In some embodiments, individual components in the electronic device 100 are primarily supported by a substrate 110. Furthermore, necessary connectors can be fabricated on the substrate 110 to achieve the required electrical connections between the components. The connectors herein can be understood as wiring layers, but are not limited to such. The substrate 110 can be a glass substrate, a silicon substrate, a sapphire substrate, etc., and has panel-level dimensions. For example, the substrate 110 can be a G3.5-generation glass substrate with dimensions of approximately 610 mm x 720 mm, but is not limited to such. In other embodiments, the substrate 110 can be a G3-generation glass substrate, a G4-generation glass substrate, a G4.5-generation glass substrate, a G5-generation glass substrate, a G5.5-generation glass substrate, or a later-generation glass substrate. This embodiment attaches a chip to a panel-level substrate, fabricates a wiring layer on the panel-level substrate, and packages the chip. Therefore, this embodiment can be used as a fan-out panel-level package (FOPLP). Because fan-out panel-level packaging uses a panel-level substrate 110, it can significantly increase production capacity compared to wafer-level packaging. At the same time, the panel-level substrate 110 has a rectangular outline, which can significantly improve the utilization rate of the substrate 110 compared to wafer-level packaging. Therefore, the electronic device 100 can be used to meet high production capacity requirements.

[0016] Figures 2A to 2E are schematic diagrams of partial manufacturing methods of electronic devices according to some embodiments of the present disclosure. The structures shown in Figures 2A to 2E correspond to the cross-section taken along line II in Figure 1 , but the manufacturing method of the electronic device is not limited thereto. In Figure 2A , a substrate 110 is first provided, and a first metal layer 120 is formed on the substrate 110, and a first insulating layer 130 is formed on the first metal layer 120. The first metal layer 120 can be distributed in the device region 102 to establish the required electrical transmission path in the device region 102. In some embodiments, the method for manufacturing the first metal layer 120 may include depositing a metal material on the substrate 110 and patterning the metal material to form the first metal layer 120. The method for patterning the metal material may include photolithography or other alternative methods.

[0017] The first insulating layer 130 can be fabricated by forming an insulating material on the substrate 110 so that the insulating material covers the first metal layer 120 and the substrate 110. The first insulating layer 130 can completely cover the entire area of ​​the substrate 110. In some embodiments, the insulating material of the first insulating layer 130 includes, but is not limited to, ABF (Ajinomoto build-up film) glue, epoxy resin, molding compound, or other build-up materials. In some embodiments, the first insulating layer 130 can be a prefabricated film that can be adhered to the substrate 110 and cover the first metal layer 120. Furthermore, the film-like first insulating layer 130 is sufficiently flexible to extend along the contour of the first metal layer 120. In some embodiments, the first insulating layer 130 can include a matrix and a filler material distributed within the matrix, such as silica filler or glass fiber.

[0018] In Figure 2B, the first insulating layer 130 is then patterned to form a first opening 132 and a first hole 134. Herein, the term "hole" may be understood as a structure formed in the device region 102 by patterning the insulating layer, which can be filled and / or covered by subsequent film layers. The term "opening" may be understood as a structure formed in the non-device region 104 by patterning the insulating layer, which can be exposed in subsequent steps, but is not limited thereto. The method for patterning the first insulating layer 130 includes laser drilling. In some embodiments, the laser beam used for laser drilling may have a wavelength in the range of 266nm to 355nm, but is not limited thereto. Specifically, parameters such as the energy and focal length of the laser beam used for laser drilling can be adjusted based on the film layer to be patterned and the desired pattern to be formed. A cleaning step may be performed after the laser drilling step to remove residual debris. The cleaning step may use, for example, plasma or a suitable cleaning agent to remove residual debris. In some embodiments, the device planarity may be inspected before laser drilling. For example, an automated optical inspection (AOI) system is used to inspect the overall flatness of the device. This allows laser drilling to be performed in areas with poor flatness to form the first opening 132. In other words, the position of the first opening 132 can be adjusted based on the actual device state. Furthermore, the first hole 134 is located on the first metal layer 120 to expose a portion of the first metal layer 120.

[0019] In some embodiments, the laser-drilled first insulating layer 130 may have a roughened surface. Therefore, the sidewalls S132 of the first opening 132 and the sidewalls S134 of the first hole 134 of the first insulating layer 130 may have a different roughness than the top surface T130 of the first insulating layer 130. Specifically, both the sidewalls S132 and S134 are rougher than the top surface T130. In some embodiments, the surface roughness of the sidewalls S132 and S134 may be between 1500 nm (nanometers) and 6000 nm (nanometers), while the surface roughness of the top surface T130 may be between 600 nm (nanometers) and 1300 nm (nanometers). Furthermore, the profiles of the first opening 132 and the first hole 134 may be inverted trapezoidal. For example, the lower base width B132 of the first opening 132 is smaller than the upper base width U132, and the same is true for the first hole 134. The sidewalls S132 of the first insulating layer 130 at the first opening 132 and the sidewalls S134 at the first hole 134 may be slightly curved in cross-section, but may also be straight lines. Furthermore, the angle θ1 between the sidewalls S132 of the first insulating layer 130 at the first opening 132 and the bottom surface B130 of the first insulating layer 130 may be greater than 30 degrees and less than or equal to 75 degrees. The first hole 134 may also have similarly inclined sidewalls. In some embodiments, due to the use of laser drilling, the surfaces of the sidewalls S132 and S134 may contain charred material, but this charred material may also be removed during the cleaning process.

[0020] In FIG2C , a second metal layer 140 and a second insulating layer 150 are successively formed on the first insulating layer 130. The manufacturing method of the second metal layer 140 is substantially similar to the manufacturing method of the first metal layer 120, and the layout of the second metal layer 140 can differ from that of the first metal layer 120 to achieve the desired electrical transmission path. The second metal layer 140 is at least partially located within the first hole 134 and is electrically connected to the first metal layer 120 through the first hole 134. The second insulating layer 150 is formed in a substantially similar manner to the first insulating layer 130. The second insulating layer 150 covers the second metal layer 140 and the first insulating layer 130 outside the second metal layer 140, so that the second metal layer 140 is located between the first insulating layer 130 and the second insulating layer 150. In addition, the second insulating layer 150 can extend to the first opening 132 in the first insulating layer 130, contacting the substrate 110 below the first insulating layer 130. The material of the second insulating layer 150 can be similar to or the same as that of the first insulating layer 130.

[0021] In FIG2D , the second insulating layer 150 is patterned to form a second opening 152 and a second hole 154. In some embodiments, the method for patterning the second insulating layer 150 can be similar to the method for patterning the first insulating layer 130. The second hole 154 can expose a portion of the second metal layer 140 to provide a path for electrical connection between the second metal layer 140 and a subsequently formed metal layer. The second opening 152 corresponds to the first opening 132 and exposes the first opening 132.

[0022] In this embodiment, the second opening 152 has an inverted trapezoidal profile similar to the first opening 132 , and the size of the second opening 152 is larger than that of the first opening 132 . Therefore, the second opening 152 can expose the sidewall S132 of the first insulating layer 130 in the first opening 132 . For example, the lower base width B152 of the second opening 152 can be smaller than the upper base width U152 of the second opening 152 , and the lower base width B152 of the second opening 152 can be larger than the upper base width U132 of the first opening 132 . In other words, the minimum width of the second opening 152 can be larger than the maximum width of the first opening 132 . In this way, the first opening 132 and the second opening 152 can be connected together, forming a through-hole with a stepped profile.

[0023] FIG2E shows that, after the step in FIG2D , a third metal layer 160 and a third insulating layer 170 are sequentially formed on the second insulating layer 150 to form the connector RDL1 of the electronic device 100A. The manufacturing method for the third metal layer 160 is generally similar to the manufacturing method for the first metal layer 120 and the second metal layer 140 described above, while the manufacturing method for the third insulating layer 170 is generally similar to the manufacturing method for the first insulating layer 130 and the second insulating layer 150 described above. For example, the third metal layer 160 may extend to the second hole 154 in the second insulating layer 150, and the third insulating layer 170 may be patterned to have a third opening 172. The third metal layer 160 is electrically connected to the second metal layer 140 through the second hole 154. The third opening 172 of the third insulating layer 170 exposes the second opening 152 of the second insulating layer 150. In this embodiment, the third opening 172 is larger than the second opening 152. For example, the minimum width of the third opening 172 is greater than the maximum width of the second opening 152, and the third opening 172 exposes the sidewall of the second insulating layer 150 in the second opening 152. Therefore, the first opening 132, the second opening 152, and the third opening 172 form a through hole with a stepped profile.

[0024] In FIG2E , electronic device 100A includes a connector RDL1, wherein connector RDL1 comprises multiple insulating layers, including a first insulating layer 130 and a second insulating layer 150. First insulating layer 130 has a first opening 132, and the sidewalls S132 of first opening 132 and the top surface T130 of first insulating layer 130 have different roughnesses. Second insulating layer 150 is disposed on first insulating layer 130 and has a second opening 152. Second opening 152 exposes the sidewalls S132 of first insulating layer 130 at the first opening 132. If stress occurs during the manufacturing process of electronic device 100A, first opening 132 and second opening 152 provide channels for stress release, preventing structural deformation or warping caused by stress during the manufacturing process. Therefore, the provision of first opening 132 and second opening 152 improves the manufacturing yield of electronic device 100A.

[0025] In some embodiments, when manufacturing the electronic device 100A, the locations of the first opening 132, the second opening 152, and the third opening 172 can be pre-set. In some embodiments, the locations of the first opening 132, the second opening 152, and the third opening 172 can be adjusted based on the actual device conditions. For example, before fabricating each insulating layer, the overall flatness of the device can be inspected, and the locations of the first opening 132, the second opening 152, and the third opening 172 can be determined based on the inspection results. For example, before fabricating the insulating layer, an automated optical inspection (AOI) system can be used to inspect the overall flatness of the device. Furthermore, the first opening 132, the second opening 152, and the third opening 172 can be located at locations where inspection results indicate warping or relatively severe warping. This makes subsequent steps less likely to cause misalignment, uneven film thickness, and other issues due to structural warping. In some embodiments, if the flatness inspection results indicate no significant warping, the corresponding insulating layer may not have buffer openings.

[0026] The connector RDL1 can serve as a wiring layer for the device, providing the necessary conductive transmission path. Specifically, the connector RDL1 also includes a first metal layer 120, a second metal layer 140, and a third metal layer 160. The first metal layer 120 is disposed between the substrate 110 and the first insulating layer 130, the second metal layer 140 is disposed between the first insulating layer 130 and the second insulating layer 150, and the third metal layer 160 is disposed between the second insulating layer 150 and the third insulating layer 170. The first hole 134 in the first insulating layer 130 exposes a portion of the first metal layer 120. The second metal layer 140 can extend into the first hole 134 in the first insulating layer 130 to electrically connect to the first metal layer 120. Similarly, the third metal layer 160 can extend into the second hole 154 in the second insulating layer 150 to electrically connect to the second metal layer 140. In addition, the third hole 174 in the third insulating layer 170 can expose a portion of the third metal layer 160. The number of metal layers and insulating layers can be adjusted according to the required wiring plan, but FIG2E takes four metal layers and four insulating layers as an example for illustration.

[0027] Although not shown, electronic device 100A may also include electronic components, such as a semiconductor chip. The semiconductor chip may be disposed on substrate 110 and electrically connected to connector RDL1. The semiconductor chip may be bonded to substrate 110 after connector RDL1 is fabricated, employing a wiring layer-first (RDL-first) manufacturing method. In some embodiments, the semiconductor chip disposed on substrate 110 may be a die in a die package. Therefore, electronic device 100A may further include an encapsulation material (not shown), such as a molding compound, to encapsulate the semiconductor chip.

[0028] Figures 3A to 3E are schematic diagrams of partial manufacturing methods of electronic devices according to some embodiments of the present disclosure. The structures shown in Figures 3A to 3E correspond to a cross-section of the electronic device taken along line II in Figure 1 , but the manufacturing method of the electronic device is not limited thereto. In Figure 3A , a substrate 110 is provided, a semiconductor chip 220 is attached to the substrate 110, and a first insulating layer 230 is formed on the substrate 110. The semiconductor chip 220 can be attached to the substrate 110 via an adhesive layer (not shown). Corresponding to the layout of Figure 1 , the semiconductor chip 220 can be located in a device region 102, with a non-device region 104 located between adjacent device regions 102. In some embodiments, the semiconductor chip 220 can be attached to the substrate 110 with the active surface facing up or facing down. The first insulating layer 230 can encapsulate the semiconductor chip 220. In some embodiments, the material of the first insulating layer 230 may include an encapsulation material such as a molding compound or epoxy resin. In some embodiments, the first insulating layer 230 may include a matrix and a filler material distributed within the matrix. Furthermore, when forming the first insulating layer 230, the insulating material of the first insulating layer 230 can first be completely covered with the semiconductor wafer 220, and then a polishing step can be performed to expose the bonding member 222 on the semiconductor wafer 220. Therefore, the first insulating layer 230 can have a first hole 230V, and the bonding member 222 on the semiconductor wafer 220 can penetrate the first insulating layer 230 and be exposed. However, the first hole 230V does not require additional steps to be formed.

[0029] In FIG3B , the first insulating layer 230 is then patterned to form a first opening 232 in the non-device area 104. In this embodiment, the method for patterning the first insulating layer 230 may include laser drilling. In other words, the method for forming the first opening 232 is substantially similar to the method for forming the first opening 132 in the aforementioned embodiment. Therefore, after patterning the first insulating layer 230 by laser drilling in this embodiment, a cleaning step may be further performed to remove debris generated during the laser drilling process. In this embodiment, the first opening 232 formed by laser drilling may have an inverted trapezoidal profile. The lower base width B232 of the first opening 232 may be smaller than the upper base width U232. In this embodiment, the roughness of the sidewalls S232 of the first insulating layer 230 in the first opening 232 may be greater than the roughness of the top surface T230 of the first insulating layer 230. In some embodiments, the surface roughness of the sidewalls S232 can be between 1500 nm (nanometers) and 6000 nm (nanometers), while the surface roughness of the top surface T230 can be between 600 nm (nanometers) and 1300 nm. Furthermore, the angle θ2 between the sidewalls S232 of the first opening 232 and the bottom surface B230 of the first insulating layer 230 can be greater than 30 degrees and less than or equal to 75 degrees. In some embodiments, due to the use of laser drilling, the surface of the sidewalls S232 may contain charred material, but this charred material can also be removed during the cleaning process.

[0030] In FIG3C , a first metal layer 240 and a second insulating layer 250 are sequentially formed on the first insulating layer 230. The method for forming the first metal layer 240 can refer to the method for forming the first metal layer 120 in the aforementioned embodiment. The first metal layer 240 can be electrically connected to the semiconductor wafer 220 via corresponding bonding members 222. The second insulating layer 250 can be formed entirely on the substrate 110 to cover the first metal layer 240 and the first insulating layer 130. For example, in the step of FIG3C , the second insulating layer 250 can extend into the first opening 232 to contact the substrate 110.

[0031] Next, in FIG3D , the second insulating layer 250 is patterned to form a second opening 252 and a second hole 254. The second insulating layer 250 can be patterned similarly to the patterning of the first insulating layer 130 in the aforementioned embodiment. In this embodiment, the second opening 252 can penetrate the first opening 232 to form a through-hole. The size of the second opening 252 can be larger than that of the first opening 232, so that the first insulating layer 230 is completely exposed at the sidewall S232 of the first opening 232. For example, the bottom width B252 of the second opening 252 can be smaller than the top width U252 of the second opening 252, and the bottom width B252 of the second opening 252 can be larger than the top width U232 of the first opening 232. In other words, the minimum width of the second opening 252 can be larger than the maximum width of the first opening 232. In this way, the first opening 232 and the second opening 252 can be connected together to form a through-hole with a stepped profile.

[0032] Figure 3E shows an electronic device 100B having a connector RDL2 formed sequentially on the second insulating layer 250, including a second metal layer 260, a third insulating layer 270, a third metal layer 280, and a fourth insulating layer 290. The connector RDL2 can serve as a wiring layer to implement the electrical transmission path required by the semiconductor chip 220. In this embodiment, the connector RDL2 is fabricated after the semiconductor chip 220 is attached to the substrate 110, thus embodying a chip-first manufacturing method, but this is not limiting. The manufacturing methods for the second metal layer 260 and the third metal layer 280 can refer to those of the previous embodiment, while the manufacturing methods for the third insulating layer 270 and the fourth insulating layer 290 can be similar to those for the first insulating layer 230 and the second insulating layer 250. The third insulating layer 270 can be patterned to have a third opening 272, and the fourth insulating layer 290 can be patterned to have a fourth opening 292. The third opening 272 penetrates the first opening 232 and the second opening 252, and the fourth opening 292 penetrates the first opening 232, the second opening 252, and the third opening 272 to form a through hole. Furthermore, because the openings farther from the substrate 110 have larger dimensions, the through hole formed by the fourth opening 292 penetrating the first opening 232, the second opening 252, and the third opening 272 has a stepped profile.

[0033] The first opening 232, the second opening 252, the third opening 272, and the fourth opening 292 can serve as a buffer structure. For example, the provision of the first opening 232, the second opening 252, the third opening 272, and the fourth opening 292 can relieve stress generated by temperature and pressure fluctuations during the manufacturing process of the electronic device 100B, thereby reducing the risk of warping of the substrate 110. Consequently, the electronic device 100B can maintain good flatness during the manufacturing process, which helps ensure the accuracy of the patterning step and improves the process yield.

[0034] In summary, the electronic device and its manufacturing method according to the disclosed embodiments can disconnect the insulating layer in the connector to provide a buffer. Consequently, the electronic device is less likely to warp due to stress during the manufacturing process, which helps improve the manufacturing yield of the electronic device.

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

[0036] 100, 100A, 100B: Electronic devices 102: Component area 104: Non-component area 110:Substrate 120, 240: first metal layer 130, 230: first insulating layer 132, 232: First opening 152, 252: Second opening 172, 272: The third opening 134, 230V: First hole 140, 260: second metal layer 150, 250: second insulation layer 154, 254: Second hole 160, 280: third metal layer 170, 270: third insulating layer 174: The third hole 180: Fourth metal layer 190, 290: fourth insulating layer 220:Semiconductor wafer 292: The fourth opening B130, B230: bottom surface B132, B232, B152, B252: bottom width RDL1, RDL2: Connectors S132, S134, S232: side wall T130, T230: top surface II: Line U132, U232, U152, U252: Upper base width θ1, θ2: Angle

Claims

1. An electronic device comprising: chip; A first insulating layer surrounds the wafer and has a first opening; A first metal layer is electrically connected to the wafer; A second insulating layer is disposed between the first metal layer and the first insulating layer, wherein the first opening penetrates the first insulating layer and the depth of the first opening is greater than the thickness of the wafer.

2. The electronic device of claim 1, wherein the wafer includes a bonding member, and the first metal layer is electrically connected to the bonding member.

3. The electronic device of claim 1, wherein the second insulating layer has a second opening, and at least a portion of the first metal layer fills the second opening.

4. The electronic device of claim 3, wherein in a cross-section of the electronic device, the second opening has a first side and a second side, the second side being adjacent to the wafer than the first side, and the length of the second side being less than the length of the first side.

5. The electronic device as claimed in claim 3, wherein in a cross-section of the electronic device, the second opening has a sidewall, and the sidewall is arc-shaped.

6. The electronic device as claimed in claim 1, further comprising: A third insulating layer is disposed on the first metal layer, wherein the third insulating layer has a third opening.

7. The electronic device as claimed in claim 6, further comprising: A second metal layer is disposed on the third insulating layer, and at least a portion of the second metal layer fills the third opening.

8. The electronic device of claim 6, wherein in a cross-section of the electronic device, the third opening has a third side and a fourth side, the fourth side being adjacent to the wafer than the third side, and the length of the fourth side being less than the length of the third side.

9. The electronic device as claimed in claim 6, wherein in a cross-section of the electronic device, the third opening has a sidewall, and the sidewall is arc-shaped.

10. The electronic device as claimed in claim 1, wherein the wafer is a semiconductor wafer.

11. The electronic device as claimed in claim 1, wherein the first insulating layer is a single-layer structure.

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