Semiconductor device structure and forming method thereof

Abstract

A semiconductor device structure and a method for forming the same are described. The structure includes a gate dielectric layer disposed above a substrate, a gate electrode layer disposed above the gate dielectric layer, and a first gate spacer disposed adjacent to the gate dielectric layer. The first gate spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite to the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface to the outer surface of the first gate spacer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device structure, particularly a semiconductor device structure including an oxidized gate spacer. Prior Art

[0002] The semiconductor integrated circuit (IC) industry has grown exponentially. Technological advancements in IC materials and IC design have produced multiple IC generations, with each IC generation having smaller and more complex circuits than the previous one. During the development of ICs, the geometric dimensions that can be achieved by the process (e.g., the smallest components (or lines)) decrease, while the functional density (e.g., the number of interconnected components per chip area) generally increases. This miniaturization process provides advantages by increasing production efficiency and reducing related costs. This miniaturization also increases the complexity of IC processes and manufacturing.

[0003] Therefore, there is a need to improve IC processes and manufacturing. Summary of the Invention

[0004] This disclosure provides a semiconductor device structure. The semiconductor device structure includes a gate dielectric layer, a gate electrode layer, and a first gate spacer. The gate dielectric layer is disposed over a substrate. The gate electrode layer is disposed over the gate dielectric layer. The first gate spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface to the outer surface of the first gate spacer.

[0005] This disclosure provides a method of forming a semiconductor device structure. The method of forming a semiconductor device structure includes forming a sacrificial gate structure and a gate spacer over a portion of a fin structure formed over a substrate, the fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately; removing a plurality of portions of the fin structure to expose a portion of the substrate; removing a portion of each of the second semiconductor layers and replacing with a dielectric spacer; forming source / drain regions on opposite sides of the sacrificial gate structure; removing the sacrificial gate structure and the second semiconductor layers to expose the gate spacer and the dielectric spacer; performing an oxidation process on the gate spacer and the dielectric spacer such that a plurality of portions of the gate spacer are oxidized; and forming a gate dielectric layer and a gate electrode layer over the oxidized gate spacer.

[0006] The present disclosure provides a method for forming a semiconductor device structure. The method for forming a semiconductor device structure includes forming a sacrificial gate structure over a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers; depositing a gate spacer structure on the sacrificial gate structure; removing a plurality of portions of the fin structure to expose a portion of the substrate; recessing the second semiconductor layers to form a plurality of cavities; forming a plurality of dielectric spacers in the cavities; forming source / drain regions from the portion of the substrate; removing the sacrificial gate structure and the second semiconductor layers; forming an interface layer on a portion of each of the first semiconductor layers; and introducing fluorine into the gate spacer and the dielectric spacers. Brief Description of the Drawings

[0007] Embodiments of the present disclosure can be understood in more detail by reading the following detailed description and examples and in conjunction with the corresponding drawings. It should be noted that, in accordance with industry standard practices, various feature components are not drawn to scale. In fact, for clarity of discussion, the dimensions of various feature components can be arbitrarily increased or decreased. FIG. 1, FIG. 2, FIG. 3, FIG. 4, and FIG. 5 are perspective views of various sites for manufacturing a semiconductor device structure according to some embodiments. FIG. 6, FIG. 7, FIG. 8, and FIG. 9 are cross-sectional side views of various sites for manufacturing a semiconductor device structure taken along line A-A of FIG. 5 according to some embodiments. FIG. 10 is a perspective view of the semiconductor device structure of FIG. 9 according to some embodiments. FIG. 11, FIG. 12, FIG. 13, FIG. 14, FIG. 15, FIG. 16, FIG. 17, FIG. 18, FIG. 19, FIG. 20, FIG. 21, FIG. 22, FIG. 23, FIG. 24, FIG. 25, FIG. 26, FIG. 27, and FIG. 28 are cross-sectional side views of various sites for manufacturing a semiconductor device structure taken along line A-A of FIG. 5 according to some embodiments. FIG. 16-1, FIG. 16-2, FIG. 16-3, FIG. 17-1, FIG. 17-2, FIG. 27-1, and FIG. 27-2 are enlarged views of a portion of a semiconductor device structure showing oxidation profiles according to some embodiments. FIG. 29 shows a portion of the semiconductor device structure of FIG. 28 according to some embodiments. Embodiments

[0008] This disclosure provides many different embodiments or examples for implementing different features of the present case. The following disclosure describes specific embodiments of each component and its arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if this disclosure describes a first feature formed on or above a second feature, it means that it may include embodiments where the first feature and the second feature are in direct contact, and may also include embodiments where additional features are formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. Additionally, the following different embodiments of this disclosure may reuse the same reference symbols and / or markings. These repetitions are for the purpose of simplification and clarity, and are not intended to limit a specific relationship between the different embodiments and / or structures discussed.

[0009] In addition, there are spatial-related terms used herein. For example, "below", "beneath", "lower", "above", "over", "on", "top", "higher", and similar terms are used to facilitate the description of the relationship between one element or feature and another (or other) element or feature in the drawings. These spatial-related terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. Moreover, if the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatial-related terms used herein can be interpreted in the same way accordingly.

[0010] Although embodiments of the present disclosure are discussed with respect to nanoscale channel FETs, such as gate all around (GAA) FETs (e.g., Horizontal Gate All Around (HGAA) FETs or Vertical Gate All Around (VGAA) FETs), implementations of some aspects of the present disclosure can be used in other processes and / or other devices, such as planar FETs, FinFETs, and other suitable devices. Other modifications that would be readily understood by one of ordinary skill in the art are contemplated to be within the scope of the present disclosure. In the case of employing a gate all around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more lithography processes (including double patterning or multiple patterning processes) can be used to pattern the structure. Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes, thereby allowing the generation of patterns with pitches smaller than those achievable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0011] Figures 1 to 29 show exemplary processes for manufacturing a semiconductor device structure 100 in accordance with embodiments of the present disclosure. It should be understood that for additional embodiments of the method, additional operations can be provided before, during, and after the processes shown in Figures 1 to 29, and some of the operations described below can be replaced or eliminated. The order of the operations / processes is not limited and can be interchanged.

[0012] FIG. 1 to FIG. 5 are perspective views of various stations for manufacturing a semiconductor device structure 100 according to some embodiments. As shown in FIG. 1, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed above the front surface of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material, such as (but not limited to) silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimonide phosphide (GaSbP), gallium arsenide antimonide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) provided between two silicon layers for reinforcement. On the one hand, the insulating layer is an oxygen-containing layer.

[0013] The substrate 101 may include various regions that have been doped with impurities, such as dopants having p-type or n-type conductivity. According to the circuit design, the dopants may be, for example, phosphorus for an n-type field effect transistor (NFET) and boron for a p-type field effect transistor (PFET).

[0014] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructure channels in a multi-gate device, such as a nanostructure channel FET. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either the first semiconductor layer 106 or the second semiconductor layer 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0015] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (such as epitaxy). For example, the epitaxial growth of the layers of the semiconductor layer stack 104 can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0016] The first semiconductor layer 106 or plural portions thereof can form a nanostructured channel of the semiconductor device structure 100 at a subsequent process site. The term "nanostructure" is used herein to refer to any material portion having nanoscale or even micron-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of this portion. Thus, this term refers to elongated material portions with circular and generally circular cross-sections, as well as beam-shaped or bar-shaped material portions including, for example, cylindrical or generally rectangular cross-sections. The nanostructured channel of the semiconductor device structure 100 can be surrounded by a gate electrode. The semiconductor device structure 100 can include nanostructured transistors. The nanostructured transistors can be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate surrounding a channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0017] Each first semiconductor layer 106 can have a thickness in the range of about 5 nm and about 30 nm. Each second semiconductor layer 108 can have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in the range of about 2 nm and about 50 nm. Three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately as shown in FIG. 1, which is for illustrative purposes and is not intended to limit beyond what is specifically recited in the claims. It can be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100.

[0018] As shown in FIG. 2, the fin structure 112 is formed by the semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106 and 108 and a well portion 116 formed by the substrate 101. The fin structure 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 by using multiple patterning operations including lithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The lithography process can include forming a photoresist layer (not shown) above the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, an electron beam (e-beam) lithography process can be used to perform patterning of the photoresist layer to form the mask element. The etching process passes through the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101 in unprotected areas to form trenches 114, leaving a plurality of extended fin structures 112. The trenches 114 extend in the X direction. Dry etching (e.g., RIE), wet etching, and / or a combination thereof can be used to etch the trenches 114.

[0019] As shown in FIG. 3, after the fin structure 112 is formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the insulating material 118. Then, a planarization operation (e.g., chemical mechanical polishing (CMP) method) and / or an etch-back method are performed such that the tops of the fin structures 112 are exposed. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-K dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD).

[0020] As shown in FIG. 4, the insulating material 118 is recessed to form the isolation region 120. The recess of the insulating material 118 exposes plural portions of the fin structure 112, such as the semiconductor layer stack 104. The recess of the insulating material 118 reveals the trench 114 between the adjacent fin structures 112. The isolation region 120 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material 118 can be flush with or lower than the surface of the second semiconductor layer 108 that contacts the well portion 116 formed by the substrate 101.

[0021] As shown in FIG. 5, one or more sacrificial gate structures 130 (only one is shown) are formed over the semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 can include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a capping layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the capping layer 136 can be formed by sequentially depositing blanket layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the capping layer 136, and then patterning these layers into the sacrificial gate structure 130. Although one sacrificial gate structure 130 is shown, in some embodiments two or more sacrificial gate structures 130 can be arranged along the X direction.

[0022] The sacrificial gate dielectric layer 132 can include one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 can include silicon, such as polysilicon or amorphous silicon. The capping layer 136 can include more than one layer, such as an oxide layer and a nitride layer. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as the channel region of the semiconductor device structure 100.

[0023] Figures 6 to 9 are cross-sectional side views of respective sites of a semiconductor device structure 100 taken along line segment A-A of Figure 5 according to some embodiments. As shown in Figure 6, a first gate spacer 138 is deposited on the exposed surface of the semiconductor device structure 100. For example, the first gate spacer 138 is deposited on the fin structure 112, the isolation region 120, and the sacrificial gate structure 130. The first gate spacer 138 can be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiCON, and / or combinations thereof. In one embodiment, the first gate spacer 138 is SiCN or SiOC. The first gate spacer 138 can be formed by any suitable process. In some embodiments, the first gate spacer 138 is a conformal layer formed by a conformal process, such as an atomic layer deposition (ALD) process.

[0024] As shown in Figure 7, a second gate spacer 139 is deposited on the first gate spacer 138. The second gate spacer 139 can include any suitable dielectric material, such as SiO x, SiON, SiN, SiCON, or SiCO. The first gate spacer 138 and the second gate spacer 139 can include the same material. In some embodiments, the first gate spacer 138 and the second gate spacer 139 can include materials with different chemical properties from each other. For example, the first gate spacer 138 can be SiCN or SiOC, and the second gate spacer 139 can be SiCON. The second gate spacer 139 can have a thickness ranging from about 0.5 nm to about 5 nm. The second gate spacer 139 can be formed by any suitable process. In some embodiments, the second gate spacer 139 is deposited by CVD, PECVD, or electron cyclotron resonance CVD (ECR-CVD). The plasma source can be an inductively coupled plasma source or a capacitively coupled plasma source. The plasma power can be in the range of about 100 W to about 500 W, and the deposition temperature can be in the range of about 100 degrees Celsius to about 600 degrees Celsius. In some embodiments, a material layer is deposited, and a processing process is performed to form the second gate spacer 139. For example, a layer such as an amorphous silicon layer, a silicon carbide layer, a SiCN layer, or a SiCON layer is first deposited on the first gate spacer 138, and then the layer is exposed to a processing gas to form the second gate spacer 139. The processing gas can be an oxygen-containing gas, a nitrogen-containing gas, or a combination thereof. In some embodiments, the processing gas includes N 2O, NH 3, O 2, or a combination of N 2 and O 2.

[0025] As shown in FIG. 8, the horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed. In some embodiments, the horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed through an anisotropic etching process. The anisotropic etching process can be a selective etching process that generally does not affect the mask layer 136, the semiconductor layer stack 104, and the isolation region 120. The first gate spacer 138 and the second gate spacer 139 can have a combined thickness T1 in the range of about 4 nm to about 10 nm. The thickness range applies to a single gate spacer (i.e., the first gate spacer 138 and the second gate spacer 139 are formed of the same material).

[0026] As shown in FIG. 9, a plurality of portions of the fin structure 112 not covered by the sacrificial gate structure 130 and the first gate spacer 138 and the second gate spacer 139 are recessed to a level above the top surface of the isolation region 120, recessed to the top surface of the isolation region 120, or recessed below the top surface of the isolation region 120. The recessing of the plurality of portions of the fin structure 112 can be accomplished by an etching process. The etching process can be a dry etching, such as RIE, NBE, etc., or a wet etching, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant.

[0027] FIG. 10 is a perspective view of the semiconductor device structure 100 of FIG. 9 according to some embodiments. FIGS. 11 to 20 are cross-sectional side views of various sites for manufacturing the semiconductor device structure taken along line A-A of FIG. 10 according to some embodiments. As shown in FIG. 11, the edge portions of each of the second semiconductor layers 108 of the semiconductor layer stack 104 are horizontally removed in the X direction. The removal of the edge portions of the second semiconductor layers 108 forms cavities. In some embodiments, a plurality of portions of the second semiconductor layer 108 are removed through a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, a wet etchant can be used to selectively etch the second semiconductor layer 108, such as (but not limited to) ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution.

[0028] After removing the edge portions of each of the second semiconductor layers 108, a dielectric layer is deposited in the cavity to form a dielectric spacer 144. The dielectric spacer 144 may be made of a low-k dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. In one embodiment, the dielectric spacer 144 includes SiONC. The dielectric spacer 144 may be formed by first forming a conformal dielectric layer using a conformal deposition process (e.g., ALD), and subsequently removing portions of the conformal dielectric layer other than the dielectric spacer 144 by anisotropic etching. During the anisotropic etching process, the first semiconductor layer 106 protects the dielectric spacer 144. The remaining second semiconductor layers 108 cover (capped) between the dielectric spacers 144 along the X direction. The dielectric spacer 144 may have a thickness T2 in the range of about 4 nm to about 10 nm. In some embodiments, the thickness T2 of the dielectric spacer 144 and the combined thickness T1 of the first gate spacer 138 and the second gate spacer 139 may be different from each other.

[0029] As shown in FIG. 12, the source / drain (S / D) regions 146 are formed from the well portions 116. The S / D regions 146 may grow vertically and horizontally to form facets, which may correspond to the crystal planes of the material applied to the well portions 116. In the present disclosure, the source region and the drain region may be used interchangeably, and their structures are substantially the same. In addition, depending on the context, the source / drain region may refer to the source or the drain individually or collectively. The S / D regions 146 may be made of one or more layers of Si, SiP, SiC, and SiCP for n-type FETs (NFETs) or Si, SiGe, and Ge for p-type FETs (PFETs). For p-channel FETs, p-type dopants (e.g., boron (B)) may also be included in the S / D regions 146. The S / D regions 146 may be formed by an epitaxial growth method using CVD, ALD, or MBE.

[0030] As shown in FIG. 13, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the second gate spacer 139, the isolation region 120, and the S / D region 146. The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, etc. or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the CESL 162 is a single layer, as shown in FIG. 13. In some embodiments, the CESL 162 includes two or more layers. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162. The material of the ILD layer 164 may include a compound containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. An organic material (such as a polymer) may also be used for the ILD layer 164. The ILD layer 164 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the ILD layer 164 is formed, a heat treatment may be performed on the semiconductor device structure 100 to anneal the ILD layer 164.

[0031] After the ILD layer 164 is formed, a planarization operation (such as CMP) is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, as shown in FIG. 13.

[0032] As shown in FIG. 14, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms an opening between the first gate spacers 138 and an opening between the first semiconductor layers 106. The ILD layer 164 protects the S / D region 146 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can first be removed by any suitable process, such as dry etching, wet etching, or a combination thereof, and then the sacrificial gate dielectric layer 132 is removed, which can also be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant (such as a tetramethylammonium hydroxide (TMAH) solution) can be used to selectively remove the sacrificial gate electrode layer 134 without removing the first gate spacers 138, the ILD layer 164, and the CESL 162.

[0033] The second semiconductor layer 108 can be removed using dry etching, wet etching, or a combination thereof. In an embodiment where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemicals used in the selective wet etching process remove the SiGe, with little effect on the Si, the dielectric material of the first gate spacer 138, and the dielectric spacer 144. In one embodiment, the second semiconductor layer 108 can be removed using a wet etchant, such as (but not limited to) hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), or phosphoric acid (H3PO4).

[0034] As shown in FIG. 15, an interfacial layer (IL) 178 is formed to surround the exposed surface of the first semiconductor layer 106. The IL 178 can comprise or be made of an oxygen-containing material or a silicon-containing material, such as silicon oxide, silicon oxynitride, silicon nitride, hafnium silicate, etc. In one embodiment, the IL 178 is silicon oxide. The IL 178 can be formed by CVD, ALD, a cleaning process, or any suitable process. The IL 178 can have a thickness of about 0.5 nm to about 1.5 nm.

[0035] As shown in FIG. 16, plural portions of the first gate spacer 138 and the dielectric spacer 144 are oxidized by an oxidation process 147. The oxidation process 147 can be any suitable oxidation process capable of driving oxygen atoms or oxygen radicals into the first gate spacer 138 and the dielectric spacer 144 and individually transforming the plural portions of the first gate spacer 138 and the dielectric spacer 144 into an oxidized first gate spacer 138' and an oxidized dielectric spacer 144'. For example, the oxidation process can use reactive species (e.g., from a remote plasma generator) generated in-situ in a chamber or upstream of the chamber by an oxygen-containing gas (e.g., O2, H2O, NO, etc.). Exemplary reactive species can include oxygen plasma or neutral radical species of oxygen, such as oxygen radicals or atomic oxygen. In some embodiments, the first gate spacer 138 and the dielectric spacer 144 can be further exposed to H2, N2, NH3, etc., which can be used as dilution gases and / or assist the oxidation process. Other suitable oxidation processes can also be used, such as a dry thermal oxidation process or a wet oxidation process. In some exemplary embodiments employing a wet oxidation process, the first gate spacer 138 and the dielectric spacer 144 can be exposed to water vapor or steam as an oxidant at a pressure of about 1 Torr to about 40 ATM and within a temperature range of about 200 °C to about 900 °C, such as about 400 °C to about 600 °C, and for a time of about 1 minute to about 2 hours.

[0036] The temperature of the oxidation process 147 can cause oxygen atoms or radicals to diffuse laterally and vertically in the first gate spacer 138 and the dielectric spacer 144. FIGS. 16-1 and 16-2 are enlarged views of a part of the semiconductor device structure 100, showing oxidation profiles corresponding to the contours of the individual oxidized first gate spacer 138' and oxidized dielectric spacer 144'. In an embodiment where the first gate spacer 138 is formed of SiCN, the nitrogen (N) concentration or carbon (C) concentration gradually decreases from the outer surface 138o' to the inner surface 138i' of the oxidized first gate spacer 138', while the oxygen (O) concentration gradually increases from the inner surface 138i' to the outer surface 138o' of the oxidized first gate spacer 138', as shown in FIG. 16-1. In some embodiments, the oxidized first gate spacer 138' has a first oxygen concentration, and the first gate spacer 138 disposed between the oxidized first gate spacer 138' and the second gate spacer 139 has a second oxygen concentration lower than the first oxygen concentration.

[0037] Similarly, in embodiments where the dielectric spacer 144 is formed of SiCN or SiOCN, the nitrogen (N) or carbon (C) concentration gradually decreases from the outer surface 144o' to the inner surface 144i' of the oxidized dielectric spacer 144', while the oxygen (O) concentration gradually increases from the inner surface 144i' to the outer surface 144o' of the oxidized dielectric spacer 144', as shown in FIG. 16-2. In some embodiments, the oxidized dielectric spacer 144' has a first oxygen concentration, and the dielectric spacer 144 disposed between the oxidized dielectric spacer 144' and the dielectric spacer 144 has a second oxygen concentration lower than the first oxygen concentration.

[0038] In some embodiments, the oxidized dielectric spacer 144' has a first oxygen concentration, and the oxidized first gate spacer 138' has a second oxygen concentration greater than the first oxygen concentration.

[0039] In various embodiments, after the oxidation process 147, the oxidized first gate spacer 138' and the dielectric spacer 144' may have about 10 at.% or less nitrogen, about 20 at.% or less carbon, and about 35 at.% or more oxygen. In some embodiments, after the oxidation process 147, the oxidized first gate spacer 138' may have an oxygen atom percentage increasing from 15 to 20 at.% to about 35 to 65 at.%. In some embodiments, the atomic percentages of carbon, nitrogen, and oxygen in the oxidized first gate spacer 138' may be different from the atomic percentages of carbon, nitrogen, and oxygen in the oxidized dielectric spacer 144'. High oxygen concentration and low carbon and / or nitrogen concentration will result in a lower k-value (e.g., 4.5 or lower) of the oxidized first gate spacer 138' and the dielectric spacer 144'. As a result, the parasitic capacitance is reduced and the overall device performance is improved.

[0040] In some embodiments, after the oxidation process 147, the oxidized portions of the first gate spacer 138 and the dielectric spacer 144 may include materials substantially the same as the IL 178. In some embodiments, the IL 178 is further oxidized after the oxidation process 147, and the IL 178, the oxidized first gate spacer 138', and the oxidized dielectric spacer 144 include materials substantially the same.

[0041] In some alternative embodiments, an oxidation process 147 is performed such that the first gate spacer 138 is completely oxidized. In some embodiments, an oxidation process 147 is performed such that oxygen atoms or radicals further diffuse into the second gate spacer 139, converting a part or the whole of the second gate spacer 139 into an oxidized second gate spacer 139'. In this case, the entire first gate spacer 138 is oxidized, and the oxidized second gate spacer 139' may follow the same oxidation profile as the oxidized first gate spacer 138'. In some embodiments, the deposited first gate spacer 138 includes SiCN, and the oxidized first gate spacer 138' after the oxidation process 147 includes SiO2. In the case where the second gate spacer 139 is formed of SiCON, the nitrogen (N) or carbon (C) concentration gradually decreases from the outer surface 139o' to the inner surface 139i' of the oxidized second gate spacer 139', while the oxygen (O) concentration gradually increases from the inner surface 139i' to the outer surface 139o' of the oxidized second gate spacer 139'. FIG. 16-3 is an enlarged view of a part of the semiconductor device structure 100, showing the oxidation profiles corresponding to the contours of the oxidized first gate spacer 138' and the second gate spacer 139'. In some embodiments, the oxidized first gate spacer 138' may have an oxygen atom percentage increasing from 15 to 20 at.% to about 35 to 65 at.%, and the oxidized second gate spacer 139' may have an oxygen atom percentage increasing from 5 at.% or less to about 20 to 65 at.%.

[0042] In some embodiments, the oxidized dielectric spacer 144' has a first oxygen concentration, and the oxidized second gate spacer 139' has a second oxygen concentration greater than the first oxygen concentration. In some embodiments, the oxidized first gate spacer 138' has a third oxygen concentration greater than the first and second oxygen concentrations.

[0043] In some alternative embodiments, a single layer is used for the gate spacers (i.e., the first gate spacer 138 and the second gate spacer 139 comprise the same material), and both the gate spacer and the dielectric spacer 144 can be partially or fully oxidized after the oxidation process 147. FIG. 17 shows an embodiment in which the gate spacer 137 and the dielectric spacer 145 are fully oxidized after the oxidation process 147. FIGS. 17-1 and 17-2 are enlarged views of a portion of the semiconductor device structure 100 according to some embodiments, showing the fully oxidized gate spacer 137 and dielectric spacer 145. In some embodiments, the deposited gate spacer and dielectric spacer comprise SiCN or SiCON, and the oxidized gate spacer 137 and dielectric spacer 145 after the oxidation process 147 comprise SiO₂, showing the chemical bond conversion from Si-C-Si and Si-N-Si to Si-O-Si. In some embodiments, after the oxidation process 147, the gate spacer 137, the dielectric spacer 145, and the IL 178 comprise substantially the same material (e.g., silicon oxide). In this case, the composition percentage of silicon oxide can be about a [Si]:[O] ratio of 1:2. Although the gate spacer 137 and the dielectric spacer 145 are fully or substantially oxidized, in some cases, trace amounts of nitrogen and carbon can still be detected in the gate spacer 137 and / or the dielectric spacer 145. For example, the gate spacer 137 can have a nitrogen atom percentage of about 1 at.% or less, and a carbon atom percentage of about 3 at.% or less. Similarly, the dielectric spacer 145 can have a nitrogen atom percentage of about 1 at.% or less, and a carbon atom percentage of about 3 at.% or less.

[0044] In some alternative embodiments, after forming the IL 178, an ion implantation process 149 is performed on the semiconductor device structure 100. Specifically, the ion implantation process 149 is performed such that most of the ionic species (dopants) are implanted into the first gate spacer 138, the IL 178, and the dielectric spacer 144. Subsequently, the implanted regions of the first gate spacer 138, the IL 178, and the dielectric spacer 144 are oxidized (FIG. 19) to form a dielectric or oxidized region. The ion implantation process 149 changes the material properties of the first gate spacer 138, the IL 178, and the dielectric spacer 144 such that the implanted regions can be oxidized at a faster rate. For example, the implanted dopants can be selected to increase the oxidation rate of the implanted regions by transforming the implanted regions into an amorphous state. Additionally or alternatively, the implanted dopants can be selected to reduce the temperature of the subsequent oxidation process, which in turn increases the reaction rate of the oxidation process. Additionally or alternatively, the implanted dopants can be selected to promote the oxidation of the implanted regions while preventing the loss of the dielectric region during the subsequent gate replacement process.

[0045] The ion implantation process 149 can employ one or more ion species. In some embodiments, the ion implantation process 149 employs a first group of ion species (“Group 1”), which includes fluorine (F) or an atom having an atomic radius of about 0.5 times to about 1.5 times the atomic radius of a silicon atom, a second group of ion species (“Group 2”), which includes noble gases such as neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), or any combination thereof, and a third group of ion species (“Group 3”), which includes oxygen (O). When implanting the F ion species, the first group of ion species (e.g., F) can be employed to promote the growth of oxides on the first gate spacer 138, IL 178, and dielectric spacer 144. The second group of ion species (e.g., Ar) can be employed to lower the activation energy of oxygen and to promote the chemical reaction between the implanted ions and the first gate spacer 138, IL 178, and dielectric spacer 144. As a result, the oxidation rate of the implanted region is increased. The third group of ion species can be employed to supply oxygen into the implanted region, which enhances the oxidation of the first gate spacer 138, IL 178, and dielectric spacer 144.

[0046] The ion implantation process 149 can be a zero-degree tilt implantation process performed in a low temperature range (e.g., 25 degrees Celsius to about 150 degrees Celsius). Although the various ion species can be distributed over the implanted region in both the lateral and vertical directions, the implant dose and ion kinetic energy of each group of ion species can be selected to achieve a desired implant concentration profile in the target region. Each group of ion species can be implanted with a kinetic energy in the range of about 0.3 keV to about 10 keV, such as about 0.5 keV to about 5 keV, and the implant dose of each group of ion species can be in the range of about 1E10 12 atoms / cm 2 to about 3E10 22 atoms / cm 2, such as about 1E10 16 atoms / cm 2 to about 6E10 15 atoms / cm 2, which can vary depending on the mass of the ion and the intended purpose.

[0047] In some embodiments, an annealing process may be performed to oxidize the implanted region. The annealing process may be controlled to have a minimal impact on the amorphous implanted region. In some embodiments, the annealing process is an RTA that heats the semiconductor device structure 100 to a target temperature range of about 600 degrees Celsius to about 1200 degrees Celsius. The annealing process may be performed in an environment including O2, H2O, NO, H2, N2, NH3, Ar, He, etc. or any combination thereof, and at a pressure of about 1 torr to about 40 ATM. The annealing process may cause the implanted ionic species to further diffuse into the first gate spacer 138, IL 178, and dielectric spacer 144.

[0048] As shown in FIG. 19, after the ion implantation process 149, the semiconductor device structure 100 undergoes an oxidation process 151 to further oxidize the implanted region and convert the implanted region into a dielectric or oxidized region (e.g., oxidized first gate spacer 138' and oxidized dielectric spacer 144'). During the oxidation process, the implanted region may be partially or completely oxidized. Due to the chemical / physical effects provided by the implanted ionic species, the implanted region is oxidized at a faster rate. The oxidation process may be the oxidation process 147 discussed above or any suitable oxidation process.

[0049] As shown in FIG. 20, after the oxidation process 147, the gate dielectric layer 170 is formed on the IL 178 and surrounds the exposed portion of the first semiconductor layer 106, and the gate electrode layer 172 is formed on top of the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 can be collectively referred to as the gate structure 174. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed by CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 can include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 can be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode layer 172 can also be deposited above the top surface of the ILD layer 164. Then, by using, for example, CMP, the gate dielectric layer 170 and the gate electrode layer 172 formed above the ILD layer 164 are removed until the top surface of the ILD layer 164 is exposed.

[0050] It should be understood that the semiconductor device structure 100 can undergo further processes to form conductive contacts in the ILD layer 164 that are electrically connected to the S / D regions 164 and to form conductive contacts that are electrically connected to the gate electrode layer 172. An interconnect structure can be formed above the semiconductor device structure 100 to provide a circuit path to the devices formed on the substrate 101.

[0051] FIGS. 21 to 26 are cross-sectional side views of various sites of a semiconductor device structure taken along line segment A-A of FIG. 5 according to some alternative embodiments. After removing the sacrificial gate structure 130 and the second semiconductor layer 108 (e.g., FIG. 14), a redundant hard mask layer 148 is formed on the exposed surfaces of the first gate spacer 138, the first semiconductor layer 106, and the dielectric spacer 144. The redundant hard mask layer 148 also fills the openings between the first semiconductor layers 106. The redundant hard mask layer 148 protects the dielectric spacer 144 from being oxidized during subsequent oxidation processes. The redundant hard mask layer 148 may include oxides, nitrides, dielectrics, or any combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the redundant hard mask layer 148 is formed of a material different from that of the first gate spacer 138. In some embodiments, the redundant hard mask layer 148 may be formed of a material having an etching selectivity relative to the dielectric spacer 144.

[0052] In FIG. 22, the redundant hard mask layer 148 on the first gate spacer 138 is removed. Any suitable etching process may be used to remove the redundant hard mask layer 148. The etching process may be time-controlled such that the redundant hard mask layer 148 on the first gate spacer 138 is removed, while the redundant hard mask layer 148 between the first semiconductor layers 106 is not substantially affected. The first gate spacer 138 is exposed after the etching process.

[0053] In FIG. 23, the first gate spacer 138 is subjected to an oxidation process, such as oxidation process 147 described above. The first gate spacer 138 may be partially or completely oxidized in a manner similar to that discussed above with reference to FIGS. 16-1, 16-3, and 17. A portion of the exposed surface of the topmost first semiconductor layer 106 may also be oxidized after the oxidation process 147. Additionally or alternatively, a thin oxide layer may be formed on the exposed surface of the topmost first semiconductor layer 106 after the oxidation process 147. FIG. 23 shows an embodiment in which the first gate spacer 138 is completely oxidized to become the oxidized first gate spacer 138'. Similarly, the oxidized first gate spacer 138' may have an oxidation profile corresponding to the oxidation profile of the oxidized first gate spacer 138' discussed above with reference to FIGS. 16-1, 16-3, and 17. In an embodiment where the first gate spacer 138 is formed of SiCN, the nitrogen (N) or carbon (C) concentration gradually decreases from the outer surface 138o' to the inner surface 138i' of the oxidized first gate spacer 138', while the oxygen (O) concentration gradually increases from the inner surface 138i' to the outer surface 138o' of the oxidized first gate spacer 138'.

[0054] In FIG. 24, the redundant hard mask layer 148 between the first semiconductor layers 106 is removed. The redundant hard mask layer 148 can be removed by an etching process using an etchant that selectively removes the redundant hard mask layer 148 with little impact on the oxidized first gate spacers 138, dielectric spacers 144, and the first semiconductor layers 106. The etching process can be anisotropic such that the redundant hard mask layer 148 on the exposed surface of the topmost first semiconductor layer 106 is also removed.

[0055] In FIG. 25, an interface layer (IL) 278, such as IL 178, is formed to surround the exposed surface of the first semiconductor layer 106. IL 278 can be formed in a manner similar to IL 178 discussed above with reference to FIG. 15.

[0056] In FIG. 26, a gate dielectric layer 270 (such as gate dielectric layer 170) is formed on IL 278 and surrounds the exposed portion of the first semiconductor layer 106, and a gate electrode layer 272 (such as gate electrode layer 172) is formed above the gate dielectric layer 270. The gate dielectric layer 270 and the gate electrode layer 272 can be formed in a manner similar to the gate dielectric layer 170 and the gate electrode layer 172 discussed above with reference to FIG. 20. In this way, the first gate spacers 138 and the second gate spacers 139 are partially or completely oxidized, while the material of the dielectric spacers 144 remains substantially unchanged before and after the oxidation process.

[0057] Figures 27 and 28 are cross-sectional side views of various sites of a semiconductor device structure taken along line segment A-A of Figure 5 according to some alternative embodiments. After forming IL 178 (e.g., Figure 15), a plurality of portions of the first gate spacer 138 and the dielectric spacer 144 are fluorinated by a fluorination process 153 and transformed into a fluorinated first gate spacer 238 and a fluorinated dielectric spacer 244. The fluorination process 153 can be any suitable fluorination process. In some embodiments, the fluorination process is a fluorine soak process. The fluorine soak process can include exposing the first gate spacer 138 and the dielectric spacer 144 to a fluorine-containing precursor at a process temperature below about 100 degrees Celsius. In some embodiments, the fluorine-containing precursor includes HF, CF4, F2, C2F6, a combination of HF and F2, or other suitable fluorine-containing precursors. The process temperature can be in the range of about 20 degrees Celsius to about 250 degrees Celsius, and the process pressure can be in the range of about 0.1 Torr to about 10 Torr. The first gate spacer 138 and the dielectric spacer 144 can be exposed to the fluorine-containing precursor for a duration in the range of about 15 seconds to about 30 minutes. In some embodiments, the fluorine-containing precursor is F2, and the first gate spacer 138 and the dielectric spacer 144 can be exposed to F2 for a duration in the range of about 5 minutes to about 20 minutes.

[0058] Alternatively, the fluorination process (e.g., from a remote plasma generator) can be performed by exposing the first gate spacer 138 and the dielectric spacer 144 to active species generated from a fluorine-containing precursor (e.g., F2) in situ in the reaction chamber or upstream of the reaction chamber. Exemplary active species can include fluorine plasma or neutral radical species of fluorine, such as fluorine radicals or atomic fluorine.

[0059] In some embodiments, before the fluorination process, a plasma treatment process may be performed on the deposited first gate spacer 138 and dielectric spacer 144. The plasma treatment process includes exposing the first gate spacer 138 and dielectric spacer 144 to a hydrogen-containing plasma. The hydrogen-containing plasma may be formed by activating a hydrogen-containing gas with a low-power plasma source or a remote plasma source. The hydrogen-containing gas may be any suitable hydrogen-containing gas. In some embodiments, the hydrogen-containing gas is hydrogen gas (H2). In some embodiments, the low-power plasma source is a capacitively coupled plasma source, and the plasma power ranges from about 10 W to about 250 W. The plasma generated by the capacitively coupled plasma source or remote plasma source includes more hydrogen radicals than ions. Additionally, the process temperature of the plasma treatment process is relatively low, such as from about 20 degrees Celsius to about 100 degrees Celsius. As a result, the hydrogen radicals replace the methyl terminal group or attach to the dangling Si bonds to form Si-H bonds. The plasma treatment process allows for the generation of more Si-H bonds, such that the subsequent fluorination process can be performed at a relatively low energy, such as at a low temperature (e.g., about 150 degrees Celsius or below) without plasma. The low-energy fluorination process can avoid causing the fluorine-containing precursor to become an etchant.

[0060] After the fluorination process 153, the fluorinated first gate spacer 238 and dielectric spacer 244 may include from about 2 at.% to about 20 at.% of fluorine, such as about 10 at.% or less of fluorine. FIGS. 27-1 and 27-2 are enlarged views of a portion of the semiconductor device structure 100, showing the fluorination profiles corresponding to the individual fluorinated first gate spacer 238 and fluorinated dielectric spacer 244. As shown in FIG. 27-1, the fluorinated first gate spacer 238 has an outer surface 238o and an inner surface 238i. The fluorine concentration decreases from the outer surface 238o to the inner surface 238i because the outer surface 238o is exposed to the fluorine-containing precursor. In some embodiments, the fluorinated first gate spacer 238 has a first fluorine concentration, and the first gate spacer 138 disposed between the fluorinated first gate spacer 238 and the second gate spacer 139 has a second fluorine concentration lower than the first fluorine concentration. In some cases, the first gate spacer 138 is not fluorinated and thus has little or no fluorine.

[0061] Similarly, the fluorinated dielectric spacer 244 has an outer surface 244o and an inner surface 244i, and the concentration of fluorine decreases from the outer surface 244o to the inner surface 244i. The fluorinated dielectric spacer 244 may have a first fluorine concentration, and the dielectric spacer 144 between the fluorinated dielectric spacer 244 and the S / D region 146 may have a second fluorine concentration lower than the first fluorine concentration. In some cases, the dielectric spacer 144 is not fluorinated and thus has little or no fluorine.

[0062] In some embodiments, each fluorinated dielectric spacer 244 may include a fluorine concentration smaller than that of the first fluorinated gate spacer 238.

[0063] The K values of the first fluorinated gate spacer 238 and the dielectric spacer 244 may increase by about 0.1 to about 0.5. As a result, the leakage current decreases and the thermal stability is improved. In some embodiments, the first fluorinated gate spacer 238 and the dielectric spacer 244 may be formed of the same or different materials (e.g., SiCN or SiCON), and may include about 2 at.% to about 20 at.% of carbon, and about 0 at.% to about 20 at.% of nitrogen. In the case where the first fluorinated gate spacer 238 and the dielectric spacer 244 include oxygen, the atomic percentage of oxygen may be about 15 at.% to about 35 at.%. In some embodiments, the carbon, nitrogen, and oxygen components may not have a significant gradient in the first fluorinated gate spacer 238. However, the dielectric spacer 244 may have a fluorine concentration gradient, where the fluorine concentration near the S / D region 146 is relatively low. In some embodiments, the atomic percentages of carbon, nitrogen, and oxygen in the first fluorinated gate spacer 238 may be different from those in the fluorinated dielectric spacer 244. The above atomic percentage ranges also apply to a single gate spacer (i.e., the first gate spacer 138 and the second gate spacer 139 are formed of the same material).

[0064] The remaining first gate spacer 138 and / or the second gate spacer 139 may be used as a capping layer for the first fluorinated gate spacer 238. Similarly, the remaining dielectric spacer 144 may be used as a capping layer for the fluorinated dielectric spacer 244. Subsequent processes (e.g., etching or epitaxial growth processes) may cause the fluorine in the first fluorinated gate spacer 238 and the dielectric spacer 144 to be released, which may damage the exposed surface of the semiconductor device structure 100.

[0065] In some embodiments, one or more processes are selectively performed to further incorporate fluorine into the second gate spacer 139. The second gate spacer 139 may not be completely fluorinated to maintain the mechanical strength of the second gate spacer 139. Additionally, subsequent processes (such as etching and heat treatment) may cause the release of fluorine in the second gate spacer 139, which may damage the exposed surfaces of the semiconductor device structure 100. In the case where the second gate spacer 139 is fluorinated, the CESL 162 can also be used as a capping layer for the fluorinated second gate spacer 139. The one or more processes for incorporating fluorine into the second gate spacer 139 may be the same as or different from the one or more processes for incorporating fluorine into the first gate spacer 138. In some embodiments, the plasma treatment process and the fluorination process described above with reference to FIG. 27 are performed to fluorinate the second gate spacer 139. In some embodiments, a fluorination process with higher energy is performed to fluorinate the second gate spacer 139 without performing the plasma treatment process. In some embodiments, the first gate spacer 138 is fluorinated by a fluorination process with higher energy without the plasma treatment process, and the second gate spacer 139 is fluorinated by the plasma treatment process and the fluorination process described in FIG. 27. During the fluorination process with higher energy, a small portion of the first gate spacer 138 may be removed by fluorine, and other components of the semiconductor device structure 100 are protected by the first gate spacer 138. During the fluorination of the second gate spacer 139, the components of the semiconductor device structure 100 are exposed. Therefore, a plasma treatment process and a fluorination with low energy are performed to fluorinate the second gate spacer 139 to protect other components of the semiconductor device structure 100. In other words, in some embodiments, different processes are used to fluorinate the first gate spacer 138 and the second gate spacer 139 to protect other components of the semiconductor device structure 100.

[0066] In some embodiments, the fluorination of the first gate spacer 138, the second gate spacer 139, and / or the dielectric spacer 144 can be enhanced by maintaining the fluorinated layer in a nitrogen environment immediately after the fluorination process, exposing the fluorinated layer to a water-free environment immediately after the fluorination process, and forming a capping layer on the fluorinated layer immediately after the fluorination process. For example, after the fluorination process 153, the semiconductor device structure 100 can be transferred to another reaction chamber / system for subsequent processes (e.g., forming the gate dielectric layer 270) in a container filled with nitrogen. The subsequent processes do not use water. In other words, a wet etching process may not be performed immediately after the fluorination process. Immediately after the fluorination process 153, a gate dielectric layer 270 is formed on the fluorinated first gate spacer 238 and dielectric spacer 244 as a capping layer for the fluorinated first gate spacer 238 and dielectric spacer 244. Through these enhancements, the fluorine concentration in the fluorinated layer is significantly higher than that in the non-enhanced fluorinated layer.

[0067] In FIG. 28, a gate dielectric layer 270 (e.g., gate dielectric layer 170)) is formed on the IL 178 and surrounds the exposed portion of the first semiconductor layer 106, and a gate electrode layer 272 (e.g., gate electrode layer 172) is formed on top of the gate dielectric layer 270. The gate dielectric layer 270 and the gate electrode layer 272 can be formed in a manner similar to that of the gate dielectric layer 170 and the gate electrode layer 172 discussed above with reference to FIG. 20.

[0068] FIG. 29 shows a portion 200 of the semiconductor device structure 100 of FIG. 28 according to some embodiments. In some embodiments, the IL 178 can also be fluorinated by the process described in FIG. 27, and fluorine can diffuse to the interface between the IL 178 and the first semiconductor layer 106 and form Si-F bonds. In some embodiments, fluorine has a first concentration at the interface between the IL 178 and the first semiconductor layer 106 and a second concentration between the top and bottom surfaces of the first semiconductor layer 106, where the first concentration is greater than the second concentration. Fluorine can repair the defects at the interface between the IL 178 and the first semiconductor layer 106. In some embodiments, fluorine replaces the oxygen vacancies at the interface between the IL 178 and the first semiconductor layer 106, which in turn increases the interfacial state density (Dit).

[0069] Embodiments of the present disclosure provide semiconductor device structures having fully or partially oxidized gate spacers and oxidized dielectric spacers between channel layers. In some alternative embodiments, the gate spacers and dielectric spacers are fluorinated. An increase in the oxygen or fluorine content in the oxidized or fluorinated gate spacers and dielectric spacers results in a decrease in the mechanical strength of the gate spacers and dielectric spacers, thereby resulting in a decrease in the dielectric constant (K) value of the gate spacers and dielectric spacers. As a result, leakage current is reduced, and thermal stability and parasitic capacitance are improved.

[0070] One embodiment is a semiconductor device structure. The semiconductor device structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent to the gate dielectric layer, wherein the first gate spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface to the outer surface of the first gate spacer.

[0071] In some embodiments, the semiconductor device structure further includes a plurality of semiconductor layers and dielectric spacers. The semiconductor layers are vertically stacked over the substrate, wherein the gate electrode layer surrounds a portion of each of the semiconductor layers. The dielectric spacer is between two adjacent semiconductor layers in the semiconductor layers, wherein the dielectric spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface of the dielectric spacer, and the dielectric spacer includes an oxygen concentration that decreases from the inner surface to the outer surface of the dielectric spacer.

[0072] In some embodiments, the semiconductor device structure further includes a second gate spacer disposed on the outer surface of the first gate spacer, wherein the second gate spacer includes an inner surface in contact with the outer surface of the first gate spacer and an outer surface opposite the inner surface, and the second gate spacer includes an oxygen concentration that decreases from the inner surface to the outer surface of the second gate spacer.

[0073] In some embodiments, each of the first gate spacer and the second gate spacer includes SiCON.

[0074] In some embodiments, the dielectric spacer includes SiCON.

[0075] In some embodiments, the first gate spacer has an increasing nitrogen or carbon concentration from the inner surface to the outer surface of the first gate spacer.

[0076] In some embodiments, the semiconductor device structure further includes an interface layer in contact with each of the semiconductor layers, wherein the interface layer and the dielectric spacer include the same material.

[0077] In some embodiments, the oxygen concentration of the dielectric spacer is smaller than the oxygen concentration of the first gate spacer.

[0078] Another embodiment is a method of forming a semiconductor device structure. The method of forming a semiconductor device structure includes forming a sacrificial gate structure and a gate spacer over a portion of a fin structure formed over a substrate, the fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately. The method of forming a semiconductor device structure further includes removing a plurality of portions of the fin structure to expose a portion of the substrate, removing a portion of each of the second semiconductor layers, and replacing with a dielectric spacer, forming source / drain regions on opposite sides of the sacrificial gate structure, removing the sacrificial gate structure and the second semiconductor layers to expose the gate spacer and the dielectric spacer, performing an oxidation process on the gate spacer and the dielectric spacer such that a plurality of portions of the gate spacer are oxidized, and forming a gate dielectric layer and a gate electrode layer over the oxidized gate spacer.

[0079] In some embodiments, the oxidation process is performed such that the entire gate spacer is oxidized.

[0080] In some embodiments, the gate spacer has an oxygen concentration that gradually changes along the thickness of the gate spacer.

[0081] In some embodiments, the method of forming a semiconductor device structure further includes, after removing the sacrificial gate structure and the second semiconductor layers and before the oxidation process, forming an interface layer on a plurality of exposed surfaces of each of the first semiconductor layers.

[0082] In some embodiments, the oxidation process is performed such that a plurality of portions of the dielectric spacer are oxidized.

[0083] In some embodiments, each of the dielectric spacers has an oxygen concentration that gradually changes along the thickness of the dielectric spacer.

[0084] In some embodiments, the method of forming a semiconductor device structure further includes, after removing the sacrificial gate structure and the second semiconductor layers and before the oxidation process, forming a redundant hard mask layer on each of the gate spacer and the dielectric spacer.

[0085] In some embodiments, the method of forming a semiconductor device structure further includes selectively removing a redundant hard mask layer from the gate spacer after forming the hard mask layer and before the oxidation process.

[0086] In some embodiments, the method of forming a semiconductor device structure further includes removing the redundant hard mask layer of each of the dielectric spacers after the oxidation process; and forming an interface layer on a plurality of exposed surfaces of each of the first semiconductor layers before forming a gate dielectric layer and a gate electrode layer over the oxidized gate spacers.

[0087] Another embodiment is a method of forming a semiconductor device structure. The method of forming a semiconductor device structure includes forming a sacrificial gate structure over a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers, depositing a gate spacer structure on the sacrificial gate structure, removing a plurality of portions of the fin structure to expose a portion of the substrate, recessing the second semiconductor layers to form a plurality of cavities, forming a plurality of dielectric spacers in the cavities, forming source / drain regions from the portion of the substrate, removing the sacrificial gate structure and the second semiconductor layers, forming an interface layer on a portion of each of the first semiconductor layers, and introducing fluorine into the gate spacer and the dielectric spacer.

[0088] In some embodiments, the gate spacer structure includes a first gate spacer and a second gate spacer, wherein the first gate spacer is disposed adjacent to the sacrificial gate structure, and the second gate spacer is disposed away from the sacrificial gate structure and is doped with fluorine such that the first gate spacer has a first fluorine concentration and the second gate spacer has a second fluorine concentration lower than the first fluorine concentration.

[0089] In some embodiments, the method of forming a semiconductor device structure includes introducing fluorine into the interface between the interface layer and the first semiconductor layer during introducing fluorine into the gate spacer and the dielectric spacer.

[0090] The foregoing text outlines the features of many embodiments, enabling those of ordinary skill in the art to better understand the present disclosure from various aspects. Those of ordinary skill in the art should understand that and can easily design or modify other processes and structures based on the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present disclosure. Various changes, substitutions, or modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure.

[0091] 100: Semiconductor device structure 101: Substrate 104: Semiconductor layer stack 106: First semiconductor layer 108: Second semiconductor layer 112: Fin structure 114: Trench 116: Well region 118: Insulating material 120: Isolation region 130: Sacrificial gate structure 132: Sacrificial gate dielectric layer A - A: Line segment 134: Sacrificial gate electrode layer 136: Capping layer 138: First gate spacer 139: Second gate spacer T1: Combined thickness 144: Dielectric spacer T2: Thickness 146: Source / drain region 162: Contact etch stop layer 164: Interlayer dielectric layer 178: Interface layer 138’: Oxidized first gate spacer 144’: Oxidized dielectric spacer 147: Oxidation process 138o’: Outer surface 138i’: Inner surface 144o’: Outer surface 144i’: Inner surface 139o’: Outer surface 139i’: Inner surface 137: Gate spacer 145: Dielectric spacer 149: Ion implantation process 151: Oxidation process 170: Gate dielectric layer 172: Gate electrode layer 174: Gate structure 148: Redundant hard capping layer 278: Interface layer 270: Gate dielectric layer 272: Gate electrode layer 153: Fluorination process 238: Fluorinated first gate spacer 244: Fluorinated dielectric spacer 238o: Outer surface 238i: Inner surface 244o: Outer surface 244i: Inner surface 200: Portion

Claims

1. A semiconductor device structure, comprising: A gate dielectric layer is disposed on top of a substrate; A gate electrode layer is disposed above the gate dielectric layer; a first gate spacer is disposed adjacent to the gate dielectric layer, wherein the first gate spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite to the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface to the outer surface, wherein the first gate spacer has a nitrogen or carbon concentration that gradually increases from the inner surface to the outer surface. A source / drain region is disposed adjacent to the gate electrode layer; and a dielectric spacer is disposed between the gate dielectric layer and the source / drain region, wherein the dielectric spacer includes a first dielectric spacer interface with the gate dielectric layer and a second dielectric spacer between the first dielectric spacer and the source / drain region, wherein the first dielectric spacer includes an inner surface interface with the gate dielectric layer and an outer surface interface with the second dielectric spacer, the first dielectric spacer includes a nitrogen or carbon concentration that gradually increases from the inner surface to the outer surface of the first dielectric spacer, and the second dielectric spacer has a fixed nitrogen or carbon concentration.

2. The semiconductor device structure as described in claim 1, further comprising: A plurality of semiconductor layers are vertically stacked above the substrate, wherein the gate electrode layer surrounds a portion of each of the semiconductor layers, and the first dielectric spacer includes an oxygen concentration that decreases from the inner surface of the first dielectric spacer to the outer surface.

3. The semiconductor device structure as described in claim 1 further includes: A second gate spacer is disposed on the outer surface of the first gate spacer, wherein the second gate spacer includes an inner surface in contact with the outer surface of the first gate spacer and an outer surface opposite to the inner surface, and the second gate spacer includes an oxygen concentration that decreases from the inner surface to the outer surface of the second gate spacer.

4. A method for forming a semiconductor device structure, comprising: A sacrificial gate structure and a gate spacer are formed over a portion of a fin structure formed over a substrate, the fin structure comprising alternating stacked plurality of first semiconductor layers and plurality of second semiconductor layers; the plurality of portions of the fin structure are removed to expose a portion of the substrate; A portion of each of the aforementioned second semiconductor layers is removed and replaced with a dielectric spacer; a source / drain region is formed on opposite sides of the aforementioned sacrificial gate structure; the aforementioned sacrificial gate structure and the aforementioned second semiconductor layers are removed to expose the aforementioned gate spacer and the aforementioned dielectric spacer. An oxidation process is performed on the gate spacer and the dielectric spacer to oxidize a plurality of portions of the gate spacer; and a gate dielectric layer and a gate electrode layer are formed on the oxidized gate spacer, wherein the gate spacer has a nitrogen or carbon concentration that gradually increases from an inner surface of the gate spacer facing the gate dielectric layer to an outer surface of the gate spacer opposite the inner surface, wherein the dielectric spacer includes a first dielectric spacer at the interface with the gate dielectric layer and a second dielectric spacer between the first dielectric spacer and the source / drain region, wherein the first dielectric spacer includes an inner surface at the interface with the gate dielectric layer and an outer surface at the interface with the second dielectric spacer, and the first dielectric spacer includes a nitrogen or carbon concentration that gradually increases from the inner surface of the first dielectric spacer to the outer surface, and the second dielectric spacer has a fixed nitrogen or carbon concentration.

5. A method for forming a semiconductor device structure as described in claim 4, wherein the oxidation process described above is performed such that the entire gate spacer is oxidized.

6. A method for forming a semiconductor device structure as described in claim 4, wherein the oxidation process described above is performed such that a plurality of portions of the dielectric spacers are oxidized.

7. The method for forming the semiconductor device structure as described in claim 4 further includes: After removing the sacrificial gate structure and the second semiconductor layer, and prior to the oxidation process, a redundant hard mask layer is formed on each of the gate spacer and the dielectric spacer.

8. The method for forming the semiconductor device structure as described in claim 7 further includes: After the above-mentioned hard mask layer is formed and before the above-mentioned oxidation process, the redundant hard mask layer is selectively removed from the above-mentioned gate spacer.

9. The method for forming the semiconductor device structure as described in claim 8 further includes: After the above oxidation process, the redundant hard mask layer of each of the above dielectric spacers is removed; Before forming the gate dielectric layer and the gate electrode layer over the oxidized gate spacer, an interface layer is formed on the plurality of exposed surfaces of each of the first semiconductor layers.

10. A method for forming a semiconductor device structure, comprising: A sacrificial gate structure is formed above a fin structure comprising a complex first semiconductor layer and a complex second semiconductor layer; A gate spacer is deposited on the sacrificial gate structure; multiple portions of the fin structure are removed to expose a portion of a substrate; the second semiconductor layer is recessed to form multiple cavities; multiple dielectric spacers are formed in the cavities; a source / drain region is formed from the portion of the substrate; the sacrificial gate structure and the second semiconductor layer are removed; an interface layer is formed on a portion of each of the first semiconductor layers; Fluorine is incorporated into the gate spacer and the dielectric spacer, wherein the gate spacer has a nitrogen or carbon concentration that gradually increases from an inner surface of the gate spacer facing the interface layer to an outer surface of the gate spacer opposite the inner surface; and a gate dielectric layer and a gate electrode layer are formed around the first semiconductor layer, wherein each of the dielectric spacers includes a first dielectric spacer at the interface of the gate dielectric layer and a second dielectric spacer between the first dielectric spacer and the source / drain region, wherein the first dielectric spacer includes an inner surface at the interface of the gate dielectric layer and an outer surface at the interface of the second dielectric spacer, and the first dielectric spacer includes a nitrogen or carbon concentration that gradually increases from the inner surface of the first dielectric spacer to the outer surface, and the second dielectric spacer has a fixed nitrogen or carbon concentration.

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