Semiconductor processing method

Abstract

Exemplary methods for semiconductor processing may include providing a deposition precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The deposition precursor may include a silicon-containing precursor. Methods may include providing a doped precursor to a processing region of a semiconductor processing chamber. The doped precursor may include a phosphorus-containing precursor. Methods may include generating a plasma effluent of the deposition precursor and the doped precursor. Methods may include depositing a silicon-containing material on a substrate. The silicon-containing material may be characterized by a stress greater than or about -50 MPa.

Description

Doped Silicon-Containing Materials with Enhanced Electrical, Mechanical, and Etch Characteristics This application claims the benefit of priority of U.S. Patent Application No. 18 / 192,573, filed on March 29, 2023, entitled "DOPED SILICON-CONTAINING MATERIALS WITH INCREASED ELECTRICAL, MECHANICAL, AND ETCH CHARACTERISTICS", the content of which is incorporated herein by reference in its entirety. The present invention relates to methods of semiconductor processing. More specifically, the present invention relates to methods for producing doped silicon-containing materials for semiconductor structures. Integrated circuits are fabricated by creating a complex patterned material layer on a substrate surface. Creating a patterned material on a substrate requires controlled methods of forming and removing materials. As device dimensions continue to shrink, the aspect ratio of structures and / or material layers increases, and it becomes challenging to maintain the dimensions of these structures and the properties of these material layers. Developing silicon-containing materials, for example, that can have desired electrical and mechanical properties, is a challenge. Additionally, as the number of material layers patterned or removed during processing increases, creating materials that can have improved removal rates and / or removal selectivity for other exposed materials becomes an even greater challenge. Accordingly, there is a need for improved systems and methods that can be used to produce high-quality devices and structures. These and other needs are met by the present invention. Exemplary methods of semiconductor processing can include providing a deposition precursor to a processing region of a semiconductor processing chamber. A substrate can be disposed within the processing region. The deposition precursor can include a silicon-containing precursor. The method can include providing a dopant precursor to the processing region of the semiconductor processing chamber. The dopant precursor can include a phosphorus-containing precursor. The method can include generating a plasma effluent of the deposition precursor and the dopant precursor. The method can include depositing a silicon-containing material on the substrate. The silicon-containing material can be characterized by a stress greater than or about -50 MPa. In some embodiments, the silicon-containing precursor can be or include tetraethyl orthosilicate (TEOS). The deposition precursor can further include an oxygen-containing precursor. The oxygen-containing precursor can be or include nitrous oxide (N 2 O). The plasma effluent of the deposition precursor and the dopant precursor can be generated at a plasma power less than or about 2000 W. The silicon-containing material can be characterized by a leakage current less than or about 5.0E-08 A / cm at 9 MV / cm 2 The silicon-containing material can be characterized by a leakage current of 0.001 A / cm 2Have a breakdown voltage greater than or about 6.0 MV / cm. The silicon-containing material may be characterized by a wet etch rate ratio (WERR) greater than or about 2.0. The method may include annealing the silicon-containing material. Annealing the silicon-containing material may include exposing the silicon-containing material to a temperature greater than or about 600 °C. Embodiments of the present invention may encompass semiconductor processing methods. The method may include providing a silicon precursor and an oxygen precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The method may include providing a dopant precursor to the processing region of the semiconductor processing chamber. The dopant precursor may include a phosphorus-containing precursor. The method may include generating a plasma effluent of the silicon precursor, the oxygen precursor, and the dopant precursor. The method may include depositing a silicon-containing material on the substrate. The silicon-containing material may be characterized by a stress greater than or about -50 MPa. The silicon-containing material may be characterized by a wet etch rate ratio (WERR) greater than or about 2.0. In some embodiments, the dopant precursor may be or include phosphine (PH 3 ). The flow rate of the dopant precursor may be less than or about 500 sccm. The silicon-containing material may be characterized by a phosphorus content less than or about 5 at.%. The silicon-containing material may be deposited on a polysilicon material. The method may include annealing the silicon-containing material at a temperature greater than or about 600 °C for greater than or about 5 minutes. After annealing, the phosphorus content in the silicon-containing material may be reduced by less than or about 1.0 at.%. Embodiments of the present invention may encompass semiconductor processing methods. The method may include providing a deposition precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The method may include providing a dopant precursor to the processing region of the semiconductor processing chamber. The dopant precursor may include a phosphorus-containing precursor. The method may include generating a plasma effluent of the deposition precursor and the dopant precursor. The method may include depositing a silicon-containing material on the substrate. The silicon-containing material may be characterized by a phosphorus content less than or about 3 at.%. The silicon-containing material may be characterized by a stress greater than or about -50 MPa. The silicon-containing material may be characterized by a wet etch rate ratio (WERR) greater than or about 2.0. In some embodiments, the silicon-containing material may include phosphorus-doped silicon oxide. The silicon-containing material may be characterized by a leakage current less than or about 1.0E-09 A / cm 2 . The silicon-containing material may be characterized by a breakdown voltage greater than or about 6.0 MV / cm at 0.001 A / cm 2 . The present invention can provide many benefits compared to conventional systems and technologies. For example, embodiments of the present invention can produce silicon-containing materials, such as silicon- and oxygen-containing materials, characterized by an increased wet etch rate ratio (WERR) and compressive stress. Additionally, the present invention can produce silicon-containing materials with adjustable film properties, having increased electrical and mechanical properties. These and other embodiments, along with many of their advantages and features, are described in more detail by the following specification and the accompanying drawings. As device dimensions continue to shrink, many material layers can be reduced in thickness and size to scale the device. As structures become closer together within the device and the material layers are made smaller, silicon-containing materials can fail to maintain desired electrical, mechanical, and etching properties. For example, as silicon-containing materials are made more compressive, the wet etch rate ratio (WERR) can degrade, which can lead to problems during etching operations, such as memory hole formation in 3D NAND applications. Additionally, as the material layers are made smaller, silicon-containing materials can suffer reduced electrical capabilities, such as increased leakage current and / or reduced breakdown voltage. Further, for these silicon-containing materials to be incorporated into semiconductor integration, the processing can include a post-process annealing treatment, which can expose the structure to temperatures of over 600 °C or higher. Many materials, including silicon-containing materials, can be impacted by this annealing, which can result in peeling due to poor adhesion. The present invention overcomes these problems by performing the deposition of silicon-containing materials with dopant precursors provided with and deposited before the deposition precursors. Dopant precursors, such as phosphorus precursors, can provide silicon-containing materials with desired electrical, mechanical, and etching properties. For example, the incorporation of dopants in the silicon-containing materials can break the tradeoff between stress and WERR. Additionally, the incorporation of dopants in the silicon-containing materials can provide silicon-containing materials characterized by low leakage current and high breakdown voltage, while maintaining a low level of film defects during deposition and / or subsequent processing. Although the remainder of the disclosure will routinely specify a particular deposition process that utilizes the disclosed technology and will describe one type of semiconductor processing chamber, it will be readily understood that the described processes can be performed in any number of semiconductor processing chambers and for any number of processing operations where films can be incorporated as described. Accordingly, the present invention should not be regarded as limited to use in these particular deposition processes or chambers. Before describing a method of semiconductor processing according to the present invention, the present disclosure will discuss one possible chamber that can be used to perform the processes of embodiments according to the present invention. Figure 1 The figure shows a cross-sectional view of an exemplary processing chamber 100 in accordance with some embodiments of the present invention. This illustration may depict an overview of a system incorporating one or more aspects of the present invention, and / or it may be specifically configured to perform one or more operations in accordance with embodiments of the present invention. Additional details of the chamber 100 or the methods performed will be described further below. The chamber 100 can be utilized to form a film layer in accordance with some embodiments of the present invention, however, it will be understood that the methods can be similarly performed in any chamber in which film formation can occur. The processing chamber 100 can include a chamber body 102, a substrate support 104 disposed inside the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and enclosing the substrate support 104 within a processing volume 120. A substrate 103 can be provided to the processing volume 120 through an opening 126, which can be conventionally sealed using a slit valve or door for processing. The substrate 103 can rest on a surface 105 of the substrate support during processing. The substrate support 104 can be rotatable, as indicated by arrow 145, along an axis 147, and a shaft 144 of the substrate support 104 can be located on the axis 147. Alternatively, the substrate support 104 can be lifted for rotation when necessary during a deposition process. A plasma profile modifier 111 can be disposed in the processing chamber 100 to control the plasma distribution across a substrate 103 disposed on the substrate support 104. The plasma profile modifier 111 can include a first electrode 108, which can be disposed adjacent to the chamber body 102 and can separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 can be part of the lid assembly 106, or it can be a separate sidewall electrode. The first electrode 108 can be an annular or toroidal member, and it can be a toroidal electrode. The first electrode 108 can be a continuous loop around the perimeter of the processing chamber 100 surrounding the processing volume 120, or it can be discontinuous at selected locations (if desired). The first electrode 108 can also be a perforated electrode, such as a perforated torus or a mesh electrode, or it can be a plate electrode, such as, for example, a second gas distributor. One or more isolators 110a, 110b can contact the first electrode 108 and electrically and thermally separate the first electrode 108 from the gas distributor 112 and the chamber body 102. The isolators 110a, 110b can be dielectric materials, such as ceramics or metal oxides, such as alumina and / or aluminum nitride. The gas distributor 112 can define holes 118 for distributing a processing precursor into the processing volume 120. The gas distributor 112 can be coupled to a first source of power 142, such as an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that can be coupled to the processing chamber. In some embodiments, the first source of power 142 can be an RF power source. The gas distributor 112 can be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 can also be formed by conductive and non-conductive components. For example, the body of the gas distributor 112 can be conductive while the panel of the gas distributor 112 can be non-conductive. The gas distributor 112 can be powered, such as by the power source 142 of the first source as shown in FIG. 1, or the gas distributor 112 can be coupled to ground in some embodiments. The first electrode 108 can be coupled to the first tuning circuit 128, and the first tuning circuit 128 can control the ground path of the processing chamber 100. The first tuning circuit 128 can include the first electronic sensor 130 and the first electronic controller 134. The first electronic controller 134 can be or include a variable capacitor or other circuit elements. The first tuning circuit 128 can be or include one or more inductors 132. The first tuning circuit 128 can be any circuit such that it can have a variable or controllable impedance under the plasma conditions present in the processing volume 120 during processing. In some embodiments as illustrated, the first tuning circuit 128 can include a first circuit branch and a second circuit branch in parallel between ground and the first electronic sensor 130. The first circuit branch can include the first inductor 132A. The second circuit branch can include the second inductor 132B, which is in series with the first electronic controller 134. The second inductor 132B can be disposed between the first electronic controller 134 and the node connecting the first and second circuit branches to the first electronic sensor 130. The first electronic sensor 130 can be a voltage or current sensor and can be coupled to the first electronic controller 134, which can provide a degree of closed-loop control of the plasma conditions inside the processing volume 120. The second electrode 122 can be coupled to the substrate support 104. The second electrode 122 can be embedded within the substrate support 104 or coupled to the surface of the substrate support 104. The second electrode 122 can be a plate, a perforated plate, a mesh, a wire mesh, or any other conductive element distribution arrangement. The second electrode 122 can be a tuning electrode and can be coupled to the second tuning circuit 136 by a wire 146, such as a cable having a selected resistance (such as 50 ohms), and is disposed, for example, in the shaft 144 of the substrate support 104. The second tuning circuit 136 can have the second electronic sensor 138 and the second electronic controller 140, which can be the second variable capacitor. The second electronic sensor 138 can be a voltage or current sensor and can be coupled to the second electronic controller 140 to provide further control of the plasma conditions in the processing volume 120. The third electrode 124 can be coupled to the substrate support 104. The third electrode 124 can be a bias electrode and / or an electrostatic chucking electrode. The third electrode can be coupled to a second source of power 150 through a filter 148, and the filter 148 can be an impedance matching circuit. The second source of power 150 can be a DC power source, a pulsed DC power source, an RF bias power source, a pulsed RF power source, or a bias power source, or a combination of these power sources or other power sources. In some embodiments, the second source of power 150 can be an RF bias power source. The substrate support 104 can also include one or more heating elements configured to heat the substrate to a processing temperature, which can be between about 25 °C and about 800 °C or greater. The lid assembly 106 and the substrate support 104 of FIG. 1 can be used in any processing chamber for plasma or heat treatment. In operation, the processing chamber 100 can provide real-time control of the plasma conditions in the processing volume 120. The substrate 103 can be placed on the substrate support 104, and process gases can flow through the lid assembly 106 using the inlet 114 according to any desired flow schedule. The gas can leave the processing chamber 100 through the outlet 152. A power source can be coupled to the gas distributor 112 to establish a plasma in the processing volume 120. The substrate is subjected to an electrical bias using the third electrode 124 in some embodiments. When the plasma is energized in the processing volume 120, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. Then, the electronic controllers 134, 140 can be used to adjust the flow characteristics of the ground path represented by the two tuning circuits 128 and 136. A set point can be transmitted to the first tuning circuit 128 and the second tuning circuit 136 to provide independent control of the deposition rate and plasma density uniformity from the center to the edge. In embodiments where both of the electronic controllers can be variable capacitors, an electronic sensor can adjust the variable capacitors to independently maximize the deposition rate and minimize the thickness non-uniformity. The tuning circuits 128, 136 may each have a variable impedance, which may be adjusted using respective electronic controllers 134, 140. Where the electronic controllers 134, 140 are variable capacitors, the capacitance range of each variable capacitor, and the inductance of the first inductor 132A and the second inductor 132B, may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum value within the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at a minimum or maximum value, the first tuning circuit 128 will have a high impedance, resulting in a plasma shape with a minimum aerial or lateral coverage above the substrate support. When the capacitance of the first electronic controller 134 approaches a value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma will grow to a maximum value, effectively covering the entire working area of the substrate support 104. When the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape will shrink from the chamber walls and the aerial coverage of the substrate support will decrease. The second electronic controller 140 may have a similar effect, as the capacitance of the second electronic controller 140 may be varied, increasing and decreasing the aerial coverage of the plasma above the substrate support. The electronic sensors 130, 138 may be used to tune the respective circuits 128, 136 in a closed loop. Depending on the type of sensor used, a set point for current or voltage may be installed in each sensor, and the sensor may be provided with control software that determines the adjustment for each respective electronic controller 134, 140 to minimize the deviation from the set point. Thus, the plasma shape may be selected and dynamically controlled during processing. It will be understood that although the foregoing discussion is based on electronic controllers 134, 140 that may be variable capacitors, any electronic component with an adjustable characteristic may be used to provide the tuning circuits 128 and 136 with an adjustable impedance. No. 2 FIG. shows an exemplary operation in a processing method 200 according to some embodiments of the present invention. The method 200 may be implemented in various processing chambers, including the processing chamber 100 described above, and any other chamber in which the operations may be performed. The method 200 may include a number of optional operations, which may or may not be explicitly related to some embodiments of the method according to the present invention. For example, many operations are illustrated to provide a broader scope of structure formation, but are not critical to the technology, or may be performed by alternative methods that may be readily appreciated. Method 200 may include additional operations before the operations listed. For example, the additional processing operations may include forming a structure on a semiconductor substrate, which may include both forming and removing materials. The previous processing operations may be performed in the chamber in which method 200 may be performed, or before delivering the substrate into the semiconductor processing chamber in which method 200 may be performed, the processing may be performed in one or more other processing chambers. In any case, method 200 may optionally include delivering a semiconductor substrate to the processing region of a semiconductor processing chamber, such as the processing chamber 100 described above, or may include other chambers such as the components described above. The substrate may be deposited on a substrate support, which may be a pedestal, such as substrate support 104, and it may reside in the processing region of the chamber, such as the processing volume 120 described above. Method 200 is diagrammatically shown in Figure 3A-3B the operations in the figure, which are illustrated to connect the operations of method 200. It will be understood that FIGS. 3A-3B only illustrate partial graphical views of an exemplary structure 300, and the substrate 305 may contain any number of additional materials and features with various characteristics and aspects, as illustrated in the figure. In operation 205, one or more deposition precursors may be delivered to the processing region of the semiconductor processing chamber. As shown in FIG. 3A, for example, the material to be deposited may be a silicon-containing material 315 used in semiconductor processing. In an embodiment, the silicon-containing material 315 may be deposited on another material 310, such as a polysilicon material or a silicon- and nitrogen-containing material in a 3D NAND application. The deposition precursors may include any number of precursors, including silicon-containing precursors and oxygen-containing precursors, and any other deposition precursors useful in forming silicon-containing materials. The deposition precursors may flow together or separately. For example, in an exemplary embodiment where a silicon- and oxygen-containing material may be formed, the silicon-containing precursor and the oxygen-containing precursor may be delivered to the processing region of the processing chamber. As discussed later, plasma-enhanced deposition may be performed in some embodiments of the present invention, which may facilitate material reaction and deposition. In an embodiment, the silicon-containing precursor may be or include one or more of silicon-containing precursors useful in semiconductor processing such as silane and disilane, etc. For example, the silicon-containing precursor may be a silicon- and oxygen-containing precursor, such as tetraethoxysilane (TEOS), octamethylcyclotetrasiloxane (OMCTS), or any other silicon-containing precursor useful in semiconductor processing. The oxygen-containing precursor may be or include molecular oxygen (O 2 )), ozone (O 3 )), nitrous oxide (N 2 O), or any other oxygen-containing precursor useful in semiconductor processing. The present invention may include additionally providing a dopant precursor at operation 210. The dopant precursor may be provided with other deposition precursors, such as a silicon-containing precursor and / or an oxygen-containing precursor. In an embodiment, the dopant precursor may be a phosphorus-containing precursor, which may facilitate the incorporation of phosphorus in the deposited silicon-containing material 315. The phosphorus-containing precursor may be or include phosphine (PH 3 ), diphosphine (P 2 H 6 ), triethyl phosphate (TEPO), trimethyl phosphate (TMP), triethyl phosphate (TEP), tributyl phosphate (TBP), or one or more of any other phosphorus-containing precursors useful in semiconductor processing. Depending on the deposition precursor, the flow rate of the dopant precursor may be adjusted to control the incorporation of the dopant in the deposited silicon-containing material 315. For example, in the case of a phosphorus dopant, when the flow rate of other deposition precursors may be greater than several hundred mg / min or sccm, the dopant precursor may flow at a flow rate less than or about 1000 sccm, and may be delivered at a flow rate less than or about 900 sccm, less than or about 800 sccm, less than or about 700 sccm, less than or about 600 sccm, less than or about 500 sccm, less than or about 400 sccm, less than or about 350 sccm, less than or about 300 sccm, less than or about 250 sccm, less than or about 200 sccm, less than or about 150 sccm, less than or about 100 sccm, or less. In additional embodiments, a carrier gas may flow into the processing region of the semiconductor processing chamber in combination with the deposition precursor and / or the dopant precursor. In an embodiment, the carrier gas may be one or more of carrier gases such as helium, argon, and molecular nitrogen (N 2 ), and the like. In an embodiment, the flow rate of the carrier gas may be greater than or about 1000 sccm, greater than or about 1500 sccm, greater than or about 2000 sccm, greater than or about 2500 sccm, greater than or about 3000 sccm, greater than or about 4000 sccm, greater than or about 5000 sccm, greater than or about 6000 sccm, or greater. For some embodiments, increasing the carrier gas flow rate may be beneficial to the mechanical properties of this film. In addition, the presence of the carrier gas may also make it easier to strike the plasma. The delivered precursors can all be used to form a plasma in the processing region of the semiconductor processing chamber in operation 215. The plasma is generated by providing RF power to the gas distributor or pedestal to generate a plasma in the processing region, however any other processing chamber capable of generating a plasma can be used similarly. The plasma can be generated at less than or about 2000 W, and can be generated at less than or about 1750 W, less than or about 1500 W, less than or about 1250 W, less than or about 1000 W, less than or about 800 W, less than or about 600 W, less than or about 400 W, or less. During operation 215 of method 200, an additional power source, a bias power source, can be used and coupled to the pedestal as previously described to provide a bias to the plasma generated above the substrate 305. This can attract the plasma effluent to the substrate 305. The applied bias power can be relatively low to limit damage to the structure 300. Thus, in some embodiments, the plasma power delivered to the pedestal by the plasma power source can be less than or about 1000 W, and the delivered power can be less than or about 900 W, less than or about 800 W, less than or about 700 W, less than or about 600 W, less than or about 500 W, less than or about 400 W, less than or about 300 W, less than or about 200 W, or less. Additionally, by adjusting the applied power and bias power, densification of the silicon-containing material 315 deposited during method 200 can occur. Without being limited to any particular theory, higher plasma power can increase dopant incorporation as the dopant-hydrogen bonding energy, such as between phosphorus and hydrogen, can be reduced compared to the silicon-hydrogen bonding energy. As shown in Figure 3B, in operation 220, the silicon-containing material 315 can be deposited on the substrate 305, such as on the material 310, which includes dopants within the deposited silicon-containing material 315. For example, the silicon-containing material 315 can be phosphorus-doped silicon oxide. In some embodiments, by incorporating dopant precursors, the stress within this film can be controlled while producing a film with reduced leakage current and increased breakdown voltage. The silicon-containing material 315 would be useful in 3D NAND applications, especially in 3D NAND applications with increased levels of silicon oxide and polysilicon layers. Specifically, the increased levels in 3D NAND require silicon oxide with a high etch rate to aid in the formation of more vertical memory holes during the etching operation. Depending on the structure 300, the thickness of the silicon-containing material 315 can be less than or about 30 nm, and the thickness of the silicon-containing material 315 can be less than or about 28 nm, less than or about 26 nm, less than or about 24 nm, less than or about 22 nm, less than or about 20 nm, less than or about 18 nm, less than or about 16 nm, or less. Due to the reactions carried out in some embodiments, the semiconductor processing chamber, pedestal, or substrate 305 can be maintained at a temperature greater than or about 250 °C, and in some embodiments can be maintained at a temperature greater than or about 300 °C, greater than or about 320 °C, greater than or about 340 °C, greater than or about 360 °C, greater than or about 380 °C, greater than or about 400 °C, greater than or about 420 °C, greater than or about 440 °C, greater than or about 460 °C, greater than or about 480 °C, greater than or about 500 °C, greater than or about 520 °C, greater than or about 540 °C, greater than or about 560 °C, greater than or about 580 °C, greater than or about 600 °C, greater than or about 620 °C, greater than or about 640 °C, or greater. By increasing the temperature, the deposition rate of the material can be decreased. Conversely, by decreasing the temperature, the deposition rate of the material can be increased. Thus, in some embodiments, the semiconductor processing chamber, pedestal, or substrate 305 can be maintained at a temperature less than or about 700 °C, and in some embodiments can be maintained at a temperature less than or about 680 °C, less than or about 660 °C, less than or about 640 °C, less than or about 620 °C, less than or about 600 °C, less than or about 580 °C, less than or about 560 °C, less than or about 540 °C, less than or about 520 °C, or less. The semiconductor processing chamber can be maintained at a pressure greater than or about 500 mTorr, and in some embodiments can be maintained at a pressure greater than or about 600 mTorr, greater than or about 700 mTorr, greater than or about 800 mTorr, greater than or about 900 mTorr, greater than or about 1 Torr, greater than or about 2 Torr, greater than or about 3 Torr, greater than or about 4 Torr, greater than or about 5 Torr, greater than or about 6 Torr, greater than or about 7 Torr, greater than or about 8 Torr, greater than or about 9 Torr, greater than or about 10 Torr, greater than or about 11 Torr, greater than or about 12 Torr, greater than or about 13 Torr, greater than or about 14 Torr, greater than or about 15 Torr, or greater. Similarly, in some embodiments, the semiconductor processing chamber can be maintained at a pressure less than or about 30 Torr, and in some embodiments maintained at a pressure less than or about 28 Torr, less than or about 26 Torr, less than or about 24 Torr, less than or about 22 Torr, less than or about 20 Torr, less than or about 15 Torr, less than or about 10 Torr, less than or about 8 Torr, less than or about 6 Torr, or less. At higher pressures, the deposition rate can increase, while at lower pressures, the deposition rate can decrease. The dopant can be included in any amount or concentration and can be included in less than or about 5 at.% in the deposited silicon-containing material 315, and in some embodiments can be included in less than or about 4.8 at.%, less than or about 4.6 at.%, less than or about 4.4 at.%, less than or about 4.2 at.%, less than or about 4 at.%, less than or about 3.8 at.%, less than or about 3.6 at.%, less than or about 3.4 at.%, less than or about 3.2 at.%, less than or about 3 at.%, less than or about 2.8 at.%, less than or about 2.6 at.%, less than or about 2.4 at.%, less than or about 2.2 at.%, less than or about 2 at.%, less than or about 1.8 at.%, less than or about 1.6 at.%, less than or about 1.4 at.%, less than or about 1.2 at.%, less than or about 1 at.%, or less. The silicon-containing material 315 can be deposited with high compressive stress. Unlike low-stress materials that are characterized by internal stress levels close to neutral stress (i.e., 0 MPa), high-stress materials are characterized by internal stress levels significantly greater than 0 MPa (i.e., high positive (tensile) stress) or significantly less than 0 MPa (i.e., high negative (compressive) stress). The feature can be that the high positive stress of the tensile stress can cause the expansion of adjacent materials, which can create an outward thrust on adjacent substrate features. The feature can be that the high negative stress of the compressive stress can cause the contraction of adjacent materials, which can create an inward pull on adjacent substrate features. In other words, higher stress materials can be characterized by having a stress level with an absolute value significantly greater than 0 MPa. Thus, when a material is characterized by a stress level of "greater than -1000 MPa", this refers to the absolute value of this stress level and includes levels such as -1500 MPa, -2000 MPa, and the like. Similarly, when a material is characterized by a stress level of "less than -1000 MPa", this refers to a stress level close to neutral stress (i.e., 0 MPa) and includes levels such as -500 MPa, -100 MPa, and the like, but does not extend to positive values greater than or about 1000 MPa. Exemplary stress values for the silicon-containing material 315 can include greater than or about -50 MPa or greater, where more negative stress values mean the material has more stress, and stress values closer to 0 MPa have less stress. Additional exemplary stress value ranges can include greater than or about -60 MPa, greater than or about -70 MPa, greater than or about -80 MPa, greater than or about -90 MPa, greater than or about -100 MPa, greater than or about -110 MPa, greater than or about -120 MPa, greater than or about -130 MPa, greater than or about -140 MPa, greater than or about -150 MPa, or greater. By doping the silicon-containing material 315, a trade-off between stress and the wet etch rate ratio (WERR) can be achieved. More specifically, compared to conventional silicon-containing materials characterized by an increased WERR, such as undoped silicon and oxygen materials, the silicon-containing material including a phosphorus dopant according to the present invention can be characterized by high compressive stress. Additionally, unlike tensile silicon-containing materials, the compressive silicon-containing materials of the present invention can experience increased adhesion and reduced peeling. The silicon-containing material 315 can be characterized by a WERR greater than or about 2.0, and can be characterized by a WERR greater than or about 2.1, greater than or about 2.2, greater than or about 2.3, greater than or about 2.4, greater than or about 2.5, greater than or about 2.6, greater than or about 2.7, greater than or about 2.8, greater than or about 2.9, greater than or about 3.0, greater than or about 3.1, greater than or about 3.2, or greater. Incorporation of the dopant can increase the WERR while also increasing the compressive stress of the silicon-containing material 315. The increased WERR can be attributed to a reduced bonding energy between the dopant and oxygen compared to that between silicon and oxygen. For example, when the dopant includes phosphorus, the bonding energy between phosphorus and oxygen is 335 kJ / mol, while the bonding energy between silicon and oxygen is 452 kJ / mol. Leakage current and dielectric breakdown can be affected by the atomic concentration in the material being produced. However, by producing the material according to an embodiment of the present invention, the leakage current at 9 MV / cm can be maintained at less than or about 5.0E-8 A / cm 2 and can be maintained at less than or about 4.0E-8 A / cm 2 less than or about 3.0E-8 A / cm 2 less than or about 2.8E-8 A / cm 2 less than or about 2.6E-8 A / cm 2 less than or about 2.4E-8 A / cm 2 less than or about 2.2E-8 A / cm 2 , less than or about 2.0E-8 A / cm 2 , less than or about 1.8E-8 A / cm 2 , or less. Further, the breakdown voltage of this film at 0.001 A / cm 2 can be maintained at greater than or about 6.0 MV / cm, and can be maintained at greater than or about 6.5 MV / cm, greater than or about 7.0 MV / cm, greater than or about 7.5 MV / cm, greater than or about 8.0 MV / cm, greater than or about 8.5 MV / cm, greater than or about 9.0 MV / cm, greater than or about 9.5 MV / cm, greater than or about 10.0 MV / cm, greater than or about 10.5 MV / cm, greater than or about 11.0 MV / cm, greater than or about 11.5 MV / cm, greater than or about 2.0 MV / cm, greater than or about 12.5 MV / cm, greater than or about 13.0 MV / cm, greater than or about 13.5 MV / cm, greater than or about 14.0 MV / cm, or higher. In optional operation 225, method 200 may include annealing substrate 305. When deposition may be performed at a first temperature, thermal annealing may be performed at a second temperature higher than the first temperature. For example, thermal annealing may be performed at a temperature greater than or about 480 °C, and thermal annealing may be performed at greater than or about 500 °C, greater than or about 510 °C, greater than or about 520 °C, greater than or about 530 °C, greater than or about 540 °C, greater than or about 550 °C, greater than or about 560 °C, greater than or about 570 °C, greater than or about 580 °C, greater than or about 590 °C, greater than or about 600 °C, greater than or about 650 °C, greater than or about 700 °C, greater than or about 750 °C, greater than or about 800 °C, greater than or about 850 °C, or higher. The thermal annealing may be performed for a time period greater than or about 0.5 minute, and may be greater than or about 1 minute, greater than or about 2 minutes, greater than or about 3 minutes, greater than or about 4 minutes, greater than or about 5 minutes, greater than or about 6 minutes, greater than or about 8 minutes, greater than or about 10 minutes, or greater. During optional operation 225, the dopant concentration may be maintained in the silicon-containing material 315. The maintained dopant concentration may indicate that the dopants are bonded and incorporated within the silicon-containing material 315, and thus will not migrate during further processing operations. For example, in a subsequent annealing of optional operation 225, the phosphorus content in the silicon-containing material may be reduced by less than or about 1.0 at.%, and may be reduced by less than or about 0.9 at.%, less than or about 0.8 at.%, less than or about 0.7 at.%, less than or about 0.6 at.%, less than or about 0.5 at.%, or less. In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of the various embodiments of the invention. However, certain embodiments may be practiced without some of these details and with additional details by those of ordinary skill in the art to which the invention pertains. Having disclosed several embodiments, those of ordinary skill in the art to which the invention pertains will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. In addition, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the invention. Therefore, the foregoing description should not be construed as limiting the scope of the invention. Where numerical ranges are provided, unless the context clearly dictates otherwise, it is understood that each intermediate value between the upper and lower limits of the range to the smallest fraction of the unit of the lower limit is also explicitly disclosed. Any narrower range between any stated value or unstated intermediate value in the stated range, as well as any other stated or intermediate value in the stated range, is also included. The upper and lower limits of those smaller ranges can be independently included or excluded within the range, and each range within the invention that includes any one of the limits, excludes any one of the limits, or includes both limits, depending on any explicit exclusion of limits in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of the included limits are also included. As used herein and in the appended claims, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" include the plural forms. Thus, for example, reference to "a precursor" includes a plurality of such precursors, and reference to "the material" includes reference to one or more materials and equivalents known to those of ordinary skill in the art to which the present invention pertains, and so forth. Also, the terms "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and the appended claims, are intended to specify the presence of the stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups. 100: Chamber 102: Chamber body 103: Substrate 104: Substrate support 105: Surface of the substrate support 106: Cover assembly 108: First electrode 110a: Isolator 110b: Isolator 111: Plasma profile modulator 112: Gas distributor 114: Inlet 118: Hole 120: Processing volume 122: Second electrode 124: Third electrode 126: Opening 128: First tuning circuit 130: First electronic sensor 132A: First inductor 132B: Second inductor 134: First electronic controller 136: Second tuning circuit 138: Second electronic sensor 140: Second electronic controller 142: Power source of the first source 144: Shaft 145: Arrow 146: Wire 147: Axis 148: Filter 150: Power source of the second source 152: Outlet 200: Method 205, 210, 215, 220, 225: Operations 300: Structure 305: Substrate 310: Material 315: Silicon-containing material The essence and advantages of the disclosed technology can be further understood by referring to the remainder of the specification and the drawings. FIG. 1 shows a schematic cross-sectional view of an exemplary plasma system according to some embodiments of the present invention. FIG. 2 shows operations in a semiconductor processing method according to some embodiments of the present invention. FIGS. 3A-3B show exemplary schematic cross-sectional structures, which include material layers and are produced according to some embodiments of the present invention. Several illustrations are included as the subject matter. It will be understood that the illustrations are for illustrative purposes and are not to be regarded as to scale unless expressly stated as such. Additionally, as the subject matter, the illustrations are provided to aid understanding and may not include all aspects or information compared to real-world representations, and may include exaggerated materials for illustrative purposes. In the accompanying illustrations, similar components and / or features may have the same element symbols. Furthermore, various components of the same type may be distinguished by a letter following the element symbol, which letter differentiates the similar components. If only the primary element symbol is used in the specification, this description may apply to any of the similar components having the same primary element symbol, regardless of the letter. Domestic deposit information (please note in the order of deposit institution, date, number) None Foreign deposit information (please note in the order of deposit country, institution, date, number) None 200: Method 205, 210, 215, 220, 225: Operations

Claims

1. A semiconductor processing method comprising the steps of: providing a plurality of deposition precursors to a processing region of a semiconductor processing chamber, wherein a substrate is disposed within the processing region, and wherein the deposition precursors comprise a silicon-containing precursor and an oxygen-containing precursor; providing a doped precursor to the processing region of the semiconductor processing chamber, wherein the doped precursor comprises a phosphorus-containing precursor; generating plasma effluents of the deposition precursors and the doped precursor; and depositing a silicon-containing material on the substrate, wherein the silicon-containing material is characterized by a stress greater than or about -50 MPa.

2. The semiconductor processing method as described in claim 1, wherein the silicon-containing precursor comprises tetraethoxysilane (TEOS).

3. The semiconductor processing method as described in claim 1, wherein the oxygen-containing precursor comprises nitrous oxide (N2O).

4. The semiconductor processing method as claimed in claim 1, wherein the plasma effluents of the deposited precursors and the doped precursors are generated at a plasma power of less than or about 2000 W.

5. The semiconductor processing method as claimed in claim 1, wherein the silicon-containing material is characterized by a leakage current of less than or about 5.0E-08 A / cm2 at 9 MV / cm.

6. The semiconductor processing method as claimed in claim 1, wherein the silicon-containing material is characterized by a breakdown voltage greater than or about 6.0 MV / cm at 0.001 A / cm2.

7. The semiconductor processing method as claimed in claim 1, wherein the silicon-containing material is characterized by a wet etch rate ratio (WERR) greater than or about 2.

0.

8. The semiconductor processing method as described in claim 1 further includes the step of: annealing the silicon-containing material.

9. The semiconductor processing method as claimed in claim 8, wherein annealing the silicon-containing material comprises exposing the silicon-containing material to a temperature greater than or about 600 °C.

10. A semiconductor processing method comprising the steps of: providing a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed within the processing region; providing a dopant precursor to the processing region of the semiconductor processing chamber, wherein the dopant precursor comprises a phosphorus-containing precursor; generating a plasma effluent of the silicon-containing precursor, the oxygen-containing precursor, and the dopant precursor; and depositing a silicon-containing material on the substrate, wherein the silicon-containing material is characterized by a phosphorus content of less than or about 5 at.%, wherein the silicon-containing material is characterized by a stress greater than or about -50 MPa, and wherein the silicon-containing material is characterized by a wet etch rate ratio (WERR) greater than or about 2.

0.

11. The semiconductor processing method as described in claim 10, wherein the dopant precursor comprises phosphine (PH3).

12. The semiconductor processing method as described in claim 10, wherein the flow rate of the dopant precursor is less than or about 500 sccm.

13. The semiconductor processing method as described in claim 10, wherein the silicon-containing material is deposited on a polycrystalline silicon material.

14. The semiconductor processing method as described in claim 10 further comprises the step of: annealing the silicon-containing material at a temperature greater than or about 600 °C for greater than or about 5 minutes.

15. The semiconductor processing method as described in claim 14, wherein after annealing, the phosphorus content in the silicon-containing material is reduced to less than or about 1 at.%.

16. A semiconductor processing method comprising the steps of: providing a deposition precursor comprising a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed within the processing region; providing a dopant precursor to the processing region of the semiconductor processing chamber, wherein the dopant precursor comprises a phosphorus-containing precursor; generating plasma effluents of the deposition precursor and the dopant precursor; and depositing a silicon-containing material on the substrate, wherein the silicon-containing material is characterized by a phosphorus content of less than or about 3 at.%, wherein the silicon-containing material is characterized by a stress of greater than or about -50 MPa, and wherein the silicon-containing material is characterized by a wet etch rate ratio (WERR) of greater than or about 2.

0.

17. The semiconductor processing method as described in claim 16, wherein the silicon-containing material comprises phosphorus-doped silicon oxide.

18. The semiconductor processing method as described in claim 16, wherein: The silicon-containing material is characterized by a leakage current of less than or about 1.0E-09 A / cm2; and the silicon-containing material is characterized by a breakdown voltage of greater than or about 6.0 MV / cm at 0.001 A / cm2.

Images