Block distribution method, computer device and computer-readable storage medium

Abstract

This invention discloses a tile distribution method, a computer device, and a computer-readable storage medium, comprising: determining the load level corresponding to each of a plurality of tiles through the front-end of a tile rendering (TBR) architecture; the load level is used to characterize the number of primitives present in the tile; passing the load level corresponding to each tile to the back-end of the TBR architecture; for each tile, determining the target processor core corresponding to the tile from at least two processor cores based on the status indicators corresponding to each processor core in the status indicator group corresponding to the tile through the back-end of the TBR architecture; wherein the arrangement order of the status indicators in the status indicator group corresponding to the tile is related to the load level of the tile.

Description

Technical Field

[0001] [Related Applications]

[0002] The embodiments of the present invention are based on and claim priority from Chinese patent application number 202310457192.8, application date April 25, 2023, and application name “Tile Distribution Method, Device, Equipment and Storage Medium”. The entire contents of the Chinese patent application are incorporated herein by reference.

[0003] The present invention relates to the field of, but is not limited to, image processing technology, and in particular to a block distribution method, computer equipment, and computer-readable storage media. Prior Art

[0004] A graphics processing unit (GPU) is a specialized graphics rendering device used to process and display computerized graphics. GPUs are built with a highly parallel architecture that provides more efficient processing of a range of complex algorithms than a typical general-purpose central processing unit (CPU). For example, these algorithms may correspond to the representation of two-dimensional or three-dimensional computerized graphics.

[0005] However, when GPUs render graphics, especially under power and system bandwidth constraints, they often employ a tile-based rendering (TBR) scheme. This scheme divides the screen into image tiles (also known as tiles) so that each tile fits within the on-chip cache. For example, if the on-chip cache can store 512kB of data, the screen can be divided into tiles such that each tile contains less than or equal to 512kB of pixel data. This method allows the scene to be rendered by dividing the screen into tiles that can be rendered into the on-chip cache, rendering each tile of the scene individually into the on-chip cache, storing the rendered tiles from the on-chip cache into the frame buffer, and repeating this rendering and storing process for each tile of the screen. Consequently, the screen can be rendered tile by tile to render each tile of the scene. As can be seen, the TBR scheme is a deferred graphics rendering method widely used in mobile devices due to its low power consumption.

[0006] Currently, in the rendering process of the traditional TBR architecture, there is an uneven distribution of workload between the processor cores, which results in low overall rendering performance. Summary of the Invention

[0007] In view of this, embodiments of the present invention at least provide a tile distribution method, a computer device, and a computer-readable storage medium.

[0008] The technical solution of the embodiment of the present invention can be implemented as follows: An embodiment of the present invention provides a tile distribution method, which is applied to a graphics processor including at least two processor cores, wherein the graphics processor performs a tile distribution process based on a tile rendering TBR architecture, comprising: determining, through a front-end portion of the TBR architecture, a load level corresponding to each of a plurality of tiles; the load level being used to characterize the number of primitives present in the tile; transmitting the load level corresponding to each of the tiles to a back-end portion of the TBR architecture; and for each tile, determining, through the back-end portion of the TBR architecture, a target processor core corresponding to the tile from the at least two processor cores based on a status indicator corresponding to each of the processor cores in a status indicator group corresponding to the tile; wherein an arrangement order of status indicators in the status indicator group corresponding to the tile is related to the load level of the tile.

[0009] An embodiment of the present invention provides a tile distribution device, which is applied to a graphics processor including at least two processor cores. The graphics processor performs a tile distribution process based on a tile rendering (TBR) architecture, including: The front end portion is configured to determine a load level corresponding to each of the plurality of tiles; the load level is used to represent the number of graphic elements present in the tile; The front-end portion is configured to transmit the load level corresponding to each of the tiles to the back-end portion of the TBR architecture; a backend portion configured to determine, for each of the tiles, a target processor core corresponding to the tile from the at least two processor cores based on a status indicator corresponding to each of the processor cores in the status indicator group corresponding to the tile; The arrangement order of the status indicators of the status indicator group corresponding to the block is related to the load level of the block.

[0010] An embodiment of the present invention provides a computer device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, some or all of the steps in the above method are implemented.

[0011] An embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, part or all of the steps in the above method are implemented.

[0012] An embodiment of the present invention provides a computer program product, comprising a computer program or instructions, which, when executed by a processor, implements some or all of the steps in the above method.

[0013] In the embodiment of the present invention, the load level of each tile is counted during the distribution process of the graphics processor based on the TBR architecture, and the load level of each tile is transmitted to the back-end part, and then the target processor core for processing the current tile is determined among at least two processor cores based on the load level. In this way, compared with the scheme in the related art that uses the tile position as the distribution basis or the scheme that uses the tile number as the distribution basis, a targeted tile distribution process can be achieved, thereby balancing the load of each processor core in the graphics processor; at the same time, in the process of determining the target processor core of the current tile based on the load level, the arrangement order of the status indicators of the status indicator group corresponding to the tile is related to the load level of the tile. In this way, the probability of each processor core being called with the same probability can be increased, thereby further improving the load balancing capability and enhancing the rendering performance of the graphics processor as a whole.

[0014] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit the technical solutions of the present invention. Simple diagram description

[0015] The drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present invention and, together with the specification, are used to illustrate the technical solutions of the present invention.

[0016] FIG1 is a schematic diagram of a typical TBR pipeline flow chart provided by an embodiment of the present invention.

[0017] FIG2 is a first schematic diagram of an implementation flow of a tile distribution method provided by an embodiment of the present invention.

[0018] FIG3 is a second schematic diagram of an implementation flow of a tile distribution method provided by an embodiment of the present invention.

[0019] FIG4 is a third schematic diagram of an implementation flow of a tile distribution method provided by an embodiment of the present invention.

[0020] FIG5A is a fourth schematic diagram of an implementation flow of a tile distribution method provided by an embodiment of the present invention.

[0021] FIG5B is a fifth flowchart of an implementation method of a tile distribution method provided by an embodiment of the present invention.

[0022] FIG6 is a sixth schematic diagram of an implementation flow of a tile distribution method provided by an embodiment of the present invention.

[0023] FIG. 7 is a seventh schematic diagram of an implementation flow of a tile distribution method provided by an embodiment of the present invention.

[0024] FIG8 is a schematic diagram of a traditional TBR architecture provided by an embodiment of the present invention.

[0025] FIG9 is a schematic diagram of a tile distribution process in a related art provided by an embodiment of the present invention.

[0026] FIG10 is a schematic diagram of an actual rendering scene provided by an embodiment of the present invention.

[0027] FIG11 is a schematic diagram of the execution time of each processor core in an actual rendering scenario provided by an embodiment of the present invention.

[0028] FIG12 is a schematic diagram of primitive coverage provided by an embodiment of the present invention.

[0029] FIG13 is a schematic diagram of load interval division provided by an embodiment of the present invention.

[0030] FIG14 is a structural diagram of a state machine provided by an embodiment of the present invention.

[0031] FIG15 is a schematic diagram of a tile distribution process according to an embodiment of the present invention.

[0032] FIG16 is a schematic diagram of the composition structure of a tile distribution device provided by an embodiment of the present invention.

[0033] FIG17 is a schematic diagram of a hardware entity of a computer device provided in an embodiment of the present invention. Implementation Method

[0034] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0035] In the following description, references to "some embodiments" describe a subset of all possible embodiments. However, it should be understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. The terms "first / second / third" are used to distinguish similar objects and do not represent a specific ordering of the objects. It should be understood that the specific order or sequence of "first / second / third" can be interchanged where permitted, so that the embodiments of the present invention described herein can be implemented in an order other than that illustrated or described herein.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention pertains. The terms used herein are for the purpose of describing the present invention only and are not intended to limit the present invention.

[0037] Tile-based rendering is the process of subdividing a computer graphics image into a regular grid in optical space and rendering each portion of the grid, or tile, separately. The advantage of this design is that it reduces memory and bandwidth consumption compared to immediate-mode rendering systems, which draw the entire frame immediately. This makes tiled rendering systems common in low-power hardware devices. Tile-based rendering is sometimes also called a sort-middle architecture because it sorts geometry in the middle of the graphics pipeline rather than near the end. TBR is the most common architecture used in mobile GPUs and has significant advantages in reducing power consumption.

[0038] A typical TBR pipeline process is shown in Figure 1. The TBR pipeline process is divided into a front-end part 110 and a back-end part 120. The front-end part 110 includes a vertex processing part 111, a graphics processing part 112, and a tiling part 113; the back-end part 120 includes a rasterization part 121, a hidden surface removal (HSR) part 122, a pixel shading part 123, and an output merging part 124.

[0039] The front-end 110 performs vertex and primitive transformations (vertex processing), graphics processing (including clipping and cull), and then, during the tiling phase, completes screen segmentation, records the graphics data covering the tiles, and writes this generated information to the system memory 130. This allows the system memory 130 to store tile information (primitive lists) and vertex information (vertex data). The primitive list is a fixed-length array equal to the length of the tile. Each element in the array is a linked list containing pointers to all triangles intersecting the current tile, with the pointers pointing to the vertex data. The vertex data stores vertex and vertex attribute data.

[0040] The backend 120 performs operations such as rasterization, depth testing, and pixel shading, ultimately outputting the result to the render target. Because each tile requires relatively little data, the required depth, texture, or color data can be loaded into the GPU's on-chip static random-access memory (SRAM), typically the on-chip memory 140 in the figure. For example, the hidden surface removal component 122 can store depth data in the depth buffer cache within the on-chip memory 140, the pixel shading component 123 can store texture data in the texture cache within the on-chip memory 140, and the output merging component 124 can store color data in the color buffer cache within the on-chip memory 140.

[0041] During the rendering process, the rendering object (image) is divided into multiple tiles, so that the on-chip memory 140 can accommodate all the data for each tile. After at least one drawing command arrives at the GPU, the front-end 110 processes each drawing command in sequence and stores the corresponding tile and vertex information in the system memory 130 until the data stored in the system memory 130 reaches a preset threshold or at least one drawing command has been processed. The back-end 120 reads the corresponding vertex information from the system memory 130 on a tile-by-tile basis and performs subsequent processing. This improves rendering efficiency by switching from accessing the system memory 130 to accessing the on-chip memory 140.

[0042] TBR GPUs typically use universal shader cores to perform fragment shading. Specifically, each universal shader core is responsible for shading the fragments of a small on-screen tile. Each tile constructs a primitive list to record which primitives cover that tile's area. Therefore, the size of each tile's primitive list determines the workload of that tile's rendering. However, within a complete image, the size of the primitive list varies from tile to tile, resulting in an uneven workload among the universal shader cores.

[0043] Based on this, an embodiment of the present invention provides a tile distribution method that can be executed by a processor of a computer device. The computer device may refer to a server, laptop, tablet, desktop, smart TV, set-top box, mobile device (e.g., mobile phone, portable video player, personal digital assistant, dedicated messaging device, portable gaming device), or other device with data processing capabilities.

[0044] FIG2 is a schematic diagram of a first implementation flow of a tile distribution method provided by an embodiment of the present invention. The method can be executed by a processor of a computer device and will be described in conjunction with the steps shown in FIG2 .

[0045] Step S201: Determine a load level corresponding to each of a plurality of tiles through the front end of the TBR architecture; the load level is used to represent the number of graphics elements in the tile.

[0046] In some embodiments, the front-end portion of the TBR architecture may include the vertex processing portion 111, graphics processing portion 112, and tile portion 113 in Figure 1. The aforementioned multiple tiles are obtained by the front-end portion after dividing the screen into tiles. Generally speaking, each tile has the same tile range on the screen, and the tile size must meet the storage requirements of the on-chip memory.

[0047] In some embodiments, for each tile, the load level corresponding to the tile is used to represent the number of graphics elements present in the tile. Since the front-end can determine the position of each graphics element on the screen and, after completing the tile division, can also obtain the tile range corresponding to each tile, the number of graphics elements present in each tile can be determined. Therefore, the load level corresponding to the tile can be determined based on the number of graphics elements corresponding to the tile.

[0048] In some embodiments, the number of primitives falling into a tile can be used directly as the load level. For example, if two primitives fall into the first tile and five primitives fall into the second tile, the load level of the first tile can be set to 2, the load level of the second tile can be set to 5, and so on. In other embodiments, a quantity range can be set for each load level, and the load level corresponding to the quantity range within which the number of primitives falling into the tile falls is used as the load level of the tile.

[0049] Step S202: Transmit the load level corresponding to each tile to the backend of the TBR architecture.

[0050] In some embodiments, the load level corresponding to each tile can be stored in the system memory by the front-end part of the TBR architecture, and then the back-end part of the TBR architecture can obtain the load level corresponding to each tile from the system memory.

[0051] Step S203: For each of the tiles, determine, by the backend portion of the TBR architecture, a target processor core corresponding to the tile from the at least two processor cores based on the status indicator corresponding to each of the processor cores in the status indicator group corresponding to the tile.

[0052] In some embodiments, for each tile, the status indicator group corresponding to the tile includes a status indicator corresponding to each processor core, and the indicator code of the status indicator corresponding to each processor core is used to represent the operating state of the processor core. Exemplarily, the operating state of the processor core may include an idle state and a busy state. In the process of determining a target processor core from at least two processor cores, the idle processor core may be selected as the target processor core based on the operating state of each processor core.

[0053] In other embodiments, for each of the blocks, within the state indicator group corresponding to the block, multiple state indicators have a fixed arrangement order. In the process of determining a target processor core from the at least two processor cores, each state indicator can be sequentially traversed according to the fixed arrangement order of the multiple state indicators, and the first processor core whose operating state is idle is selected as the target processor core.

[0054] In some embodiments, the target processor core is used to process the rendering task corresponding to the tile.

[0055] The arrangement order of the status indicators of the status indicator group corresponding to the block is related to the load level of the block.

[0056] In some embodiments, status indicator groups corresponding to different load levels have status indicators corresponding to processor cores in different order. For example, see Table 1, which shows the order of status indicators corresponding to multiple status indicator groups.

[0057] Table 1 Load level Status indicator group Load level 1 Core1 Core4 Core3 Core2 Load level 2 Core2 Core1 Core4 Core3 Load level 3 Core3 Core2 Core1 Core4 Load level 4 Core4 Core3 Core2 Core1

[0058] The order of the processor cores in the status indicator group corresponding to load level 1 is "1432," the order of the processor cores in the status indicator group corresponding to load level 2 is "2143," the order of the processor cores in the status indicator group corresponding to load level 3 is "3214," and the order of the processor cores in the status indicator group corresponding to load level 4 is "4321." It can be seen that the order of the status indicators corresponding to the processor cores in the status indicator group for each load level is different.

[0059] In other embodiments, the status indicator groups corresponding to different load levels may have the same or different arrangement order for the status indicators corresponding to the processor cores within the status indicator groups. For example, see Table 2, which shows the arrangement order of the status indicators corresponding to multiple status indicator groups.

[0060] Table 2 Load level Status indicator group Load level 1 Core1 Core2 Load level 2 Core2 Core1 Load level 3 Core1 Core2 Load level 4 Core2 Core1

[0061] The order of the processor cores in the status indicator groups corresponding to load levels 1 and 3 is 12, and the order of the processor cores in the status indicator groups corresponding to load levels 2 and 4 is 21. It can be seen that the order of the status indicators corresponding to the processor cores in the status indicator groups for different load levels can be the same or different.

[0062] In some embodiments, the method further includes: obtaining a state machine based on the load level corresponding to each of the tiles through the backend portion of the TBR architecture; the state machine includes a state indicator group corresponding to each of the load levels.

[0063] The backend has multiple state machines pre-set, each corresponding to a different number of load levels. After the backend of the TBR architecture determines the load level corresponding to each tile, it can retrieve the state machine corresponding to the current number of load levels from the pre-set multiple state machines based on the number of load levels.

[0064] For example, there may be a first state machine, a second state machine, and a third state machine; wherein the first state machine corresponds to two load levels, the second state machine corresponds to four load levels, and the third state machine corresponds to eight load levels. In the case of obtaining eight tiles, wherein the load levels corresponding to each tile are (2, 3, 1, 2, 4, 2, 3, 4), it can be seen that the number of load levels of the tiles is four. Therefore, the second state machine can be selected, that is, four load levels and a state indicator group corresponding to each of the four load levels.

[0065] It should be noted that the status indicator groups corresponding to each load level in different state machines can be the same or different. In other words, the status indicator group corresponding to load level 1 in the first state machine, the status indicator group corresponding to load level 1 in the second state machine, and the status indicator group corresponding to load level 1 in the third state machine can be the same or different.

[0066] In the embodiment of the present invention, the load level of each tile is counted during the distribution process of the graphics processor based on the TBR architecture, and the load level of each tile is transmitted to the back-end part, and then the target processor core for processing the current tile is determined among at least two processor cores based on the load level. In this way, compared with the schemes in the related art that use the tile position as the distribution basis or the schemes that use the tile number as the distribution basis, a targeted tile distribution process can be implemented, thereby balancing the load of each processor core in the graphics processor; at the same time, in the process of determining the target processor core of the current tile based on the load level, the arrangement order of the status indicators of the status indicator group corresponding to the tile is related to the load level of the tile, which can increase the probability of each processor core being called with the same probability, thereby further improving the load balancing capability and enhancing the rendering performance of the graphics processor as a whole.

[0067] In some embodiments, the arrangement order of the status indicators includes a bit sequence of the status indicator corresponding to each of the processor cores. For each bit sequence, the number of processor cores in the set of processor cores corresponding to the bit sequence is the same, and the set of processor cores corresponding to the bit sequence includes the processor cores corresponding to the bit sequence in the status indicator group corresponding to each load level.

[0068] For example, referring to Table 2, although the order of the processor cores in the status indicator groups corresponding to load levels 1 and 3 is "12," and the order of the processor cores in the status indicator groups corresponding to load levels 2 and 4 is "21," meaning that the order of the processor cores in the status indicator groups is the same, for the two bit orders (including "1" and "2"), the number of processor cores in the set of processor cores corresponding to bit order "1" (processor core 1, processor core 2) is 2; and the number of processor cores in the set of processor cores corresponding to bit order "2" (processor core 1, processor core 2) is 2. Thus, during step S203, the probability of each processor core being called is the same, improving the load balancing capability of the image processor to a certain extent.

[0069] FIG3 is a second schematic diagram of a flowchart for implementing a tile distribution method according to an embodiment of the present invention. This method can be executed by a processor of a computer device. Based on FIG2 , step S201 in FIG2 can be updated to S301 to S302, which will be described in conjunction with the steps shown in FIG3 .

[0070] Step S301: For each of the tiles, the front end of the TBR architecture determines the number of tiles that fall within the tile range based on the position of each tile and the tile range of the tile.

[0071] In some embodiments, after the front-end processes the geometry data and obtains the corresponding primitive data, the positions of each primitive can be obtained. Furthermore, after performing block processing, the tile range corresponding to each tile can also be obtained. Subsequently, for each tile, based on the positions of each primitive and the tile range of that tile, the number of primitives falling within the tile range can be determined. The positions of the primitives are expressed as trilateral equations.

[0072] Step S302: Determine the load level corresponding to each of the blocks based on the number of graphics elements corresponding to each of the blocks.

[0073] In some embodiments, the number of primitives that can fall directly into a tile may be used as the load level of the tile.

[0074] In some embodiments, the above-mentioned determination of the load level corresponding to each of the blocks based on the number of graphics elements corresponding to each of the blocks can be achieved through steps S3021 to S3022.

[0075] Step S3021: Acquire multiple preset levels and the quantity interval corresponding to each preset level.

[0076] In some embodiments, the number of the multiple preset levels is fixed. In other embodiments, the number of the multiple preset levels is dynamically changed and is related to the rendering condition parameters of the current rendering environment. Please refer to the implementation process provided in the embodiment of Figure 4.

[0077] Step S3022: For each of the blocks, a preset level corresponding to a quantity interval into which the number of graphics elements corresponding to the block falls is used as the load level corresponding to the block.

[0078] Exemplarily, the multiple preset levels obtained include a first preset level and a second preset level, wherein the quantity interval corresponding to the first preset level is [0,4], and the quantity interval corresponding to the second preset level is (4,+∞). When 2 graphic elements fall into the first block and 5 graphic elements fall into the second block, the load level of the first block can be directly set to the first preset level, and the load level of the second block can be set to the second preset level.

[0079] In an embodiment of the present invention, after obtaining the number of primitives in each tile, that is, after determining the rendering workload borne by each tile, the load of each tile is graded based on the number of primitives. Then, in the subsequent process of distributing the tiles to the processor core, the workload of each tile can be taken into account, thereby improving the load balancing capability of the graphics processor.

[0080] FIG4 is a third schematic diagram of a flowchart for implementing a tile distribution method according to an embodiment of the present invention. This method can be executed by a processor of a computer device. Based on FIG3 , step S3021 in FIG3 can be updated to S401 to S403 , which will be described in conjunction with the steps shown in FIG4 .

[0081] Step S401: Obtain rendering condition parameters of the current rendering environment.

[0082] In some embodiments, the rendering condition parameters include at least one of the following: hardware parameters and rendering target parameters, the hardware parameters are used to characterize the hardware performance of the graphics processor, and the rendering target parameters are used to characterize the computational complexity of the rendering object.

[0083] In some embodiments, the hardware parameters include at least one of the following: the number of processor cores and the read and write speed of the memory.

[0084] In some embodiments, the rendering target parameters include at least one of the following: the size of the rendering object and the number of tiles.

[0085] Step S402: Determine the number of the plurality of preset levels based on the rendering condition parameters.

[0086] In some embodiments, when the hardware parameters represent better hardware performance of the graphics processor, the number of the multiple preset levels is greater; when the hardware parameters represent worse hardware performance of the graphics processor, the number of the multiple preset levels is smaller.

[0087] The greater the number of processor cores, the better the GPU's hardware performance. The faster the memory read and write speed, the better the GPU's hardware performance, and accordingly, the greater the number of preset levels. While increasing the number of preset levels will introduce a certain degree of hardware load compared to a smaller number of levels, the GPU's higher hardware performance allows for more detailed tile load division without impacting other rendering tasks, resulting in a more balanced distribution of tiles across the GPU's cores.

[0088] In some embodiments, when the hardware parameters represent a greater amount of computation required to render the object, the number of the multiple preset levels is greater; and when the hardware parameters represent a lesser amount of hardware performance of the graphics processor, the number of the multiple preset levels is less.

[0089] The greater the number of tiles, the greater the computational effort required to render the object; the larger the size of the rendering object, the greater the computational effort required to render the object, and accordingly, the greater the number of preset levels. Compared to a solution employing a smaller number of levels, this approach can mitigate the problem of load imbalance caused by the large overall computational effort required to render the object, and the inability of a smaller number of levels to effectively differentiate between a large number of tiles / primitives. In other words, the above-described embodiment can improve the level of detail in tile load partitioning, thereby enabling a more balanced distribution of tiles to the GPU cores.

[0090] Step S403: Based on the number of the plurality of preset levels, obtain the plurality of preset levels and the number interval corresponding to each of the preset levels.

[0091] In some embodiments, the number of the preset levels may be 2 to the power of n, where n is a positive integer. For example, the number of the preset levels may be 2, 4, 8, ..., and so on.

[0092] For each number of preset levels, a set of quantity intervals corresponding to each preset level can be preset, and the set of quantity intervals includes the quantity intervals corresponding to each preset level. For example, if the number of preset levels is "2," a first preset level and a second preset level corresponding to the number "2" can be preset, as can a first quantity interval corresponding to the first preset level and a second quantity interval corresponding to the second preset level. For example, if the number of preset levels is "4," a first preset level and a first quantity interval corresponding to the number "2," a second preset level and a second quantity interval corresponding to the second preset level, a third preset level and a third quantity interval corresponding to the number "2," and a fourth preset level and a fourth quantity interval corresponding to the number "2" can be preset.

[0093] In an embodiment of the present invention, by obtaining the rendering condition parameters of the current rendering environment, combining them with hardware parameters and rendering target parameters, the number of multiple preset levels is determined, and then the number of load levels is dynamically changed, thereby achieving self-adjustment of the load level division accuracy. As a result, a trade-off can be made between load balancing capability and rendering speed, thereby improving rendering efficiency overall.

[0094] FIG5A is a fourth flow chart illustrating an implementation of a tile distribution method according to an embodiment of the present invention. This method can be executed by a processor of a computer device. Based on FIG2 , S202 in FIG2 can be updated to S501 to S502, which will be described in conjunction with the steps shown in FIG5A .

[0095] Step S501: When the front end of the TBR architecture writes the tile information of each tile into the system memory, the load level corresponding to each tile is written into the tile header information of the corresponding tile information.

[0096] Step S502: For each tile, in response to a rendering event for the tile, read tile header information of tile information corresponding to the tile from the system memory through the backend portion of the TBR architecture, and obtain the load level corresponding to the tile from the tile header information.

[0097] In some embodiments, please refer to Figure 5B, which shows a flowchart diagram 5 of the tile distribution method provided in an embodiment of the present invention. Based on Figure 5A, before step S501, the method may also include step S503. Accordingly, steps S501 to S502 can be updated to S504 to S505, which will be explained in conjunction with the steps shown in Figure 5A.

[0098] Step S503: Encode the load level corresponding to each of the tiles through the front end of the TBR architecture to obtain a coding value of at least one bit.

[0099] In some embodiments, the load level may be binary-encoded to obtain the encoded value of the at least one bit. For example, when the load levels include 1 and 2, encoding the load levels may yield two encoded values, 00 and 01, respectively; when the load levels include 1, 2, 3, and 4, encoding the load levels may yield four encoded values, 00, 01, 10, and 11, respectively, and so on.

[0100] Step S504: When the front end of the TBR architecture writes the tile information of each tile into the system memory, write the encoding value of at least one bit corresponding to each tile into the tile header information of the corresponding tile information.

[0101] Step S505: For each tile, in response to a rendering event for the tile, read tile header information of tile information corresponding to the tile from the system memory via the backend portion of the TBR architecture, and decode the encoded value of at least one bit in the tile header information to obtain a load level corresponding to the tile.

[0102] In some embodiments, decoding the encoded value of at least one bit in the tile header information to obtain the load level corresponding to the tile is the inverse of the process of encoding the load level to obtain the at least one bit encoded value. Based on the above example, if the encoded values ​​are 00 and 01, then decoding the encoded values ​​yields load levels 1 and 2, respectively. If the encoded values ​​are 00, 01, 10, and 11, then decoding the encoded values ​​yields load levels 1, 2, 3, and 4, respectively.

[0103] In the embodiment of the present invention, by encoding the load level, the transmission cost can be reduced as much as possible during the process of transmitting the load level to the back-end part, the transmission efficiency can be improved, and the rendering efficiency can be improved.

[0104] Figure 6 is a sixth schematic flow diagram of an implementation of a tile distribution method provided by an embodiment of the present invention. This method can be executed by a processor of a computer device. Based on any of the above embodiments, taking Figure 2 as an example, S203 in Figure 2 can be updated to S601 through S602, which will be explained in conjunction with the steps shown in Figure 6.

[0105] Step S601: Traverse the status indicators according to the arrangement order of the status indicators corresponding to the tiles through the backend part of the TBR architecture.

[0106] For example, referring to the arrangement order of status indicators corresponding to multiple status indicator groups shown in Table 1, when the block belongs to load level 2, the processor cores corresponding to these four processor cores can be traversed in the order of processor core 2, processor core 1, processor core 4, and processor core 3.

[0107] Each status indicator can be configured with a first value, which indicates that the processor core corresponding to the status indicator is in an idle state (dispatching state); each status indicator can be configured with a second value, which indicates that the processor core corresponding to the status indicator is in a busy state (non-dispatching state). In some embodiments, the initial state of each status indicator is configured as the first value.

[0108] In some embodiments, the first value may be set to 0, and the second value may be set to 1. The present invention is not limited to this.

[0109] Step S602: The processor core corresponding to the first status indicator having the first value is used as the target processor core.

[0110] In some embodiments, the method further includes steps S603 to S604.

[0111] Step S603: Allocate the rendering task corresponding to the tile to the target processor core.

[0112] Step S604: In response to allocating the rendering task corresponding to the tile to the target processor core, updating the status indicator corresponding to the target processor core in the status indicator group corresponding to the tile to the second value.

[0113] For example, please refer to Table 3, which shows a status table of a status indicator group, which corresponds to Table 1.

[0114] Table 3 Load level Status indicator group Load level 1 0 0 0 0 Load level 2 1 0 0 0 Load level 3 1 1 1 0 Load level 4 0 0 0 0

[0115] If the current tile belongs to load level 2, the processor cores corresponding to these four processor cores can be traversed in the order of processor core 2, processor core 1, processor core 4, and processor core 3. In this case, the first status indicator with the first value is the status indicator corresponding to processor core 1, and the rendering task corresponding to the current tile is assigned to processor core 1. In response to assigning the rendering task corresponding to the current tile to processor core 1, the status indicator corresponding to processor core 1 corresponding to the tile is updated to the second value.

[0116] In some embodiments, the method further includes step S605.

[0117] Step S605: In response to each of the status indicators in the status indicator group corresponding to the tile being the second value, resetting each of the status indicators in the status indicator group corresponding to the tile to the first value.

[0118] If the current tile belongs to load level 3, the status indicators corresponding to the four processor cores can be traversed in the order of processor core 3, processor core 2, processor core 1, and processor core 4. In this case, the first status indicator with the first value is the status indicator corresponding to processor core 4, and the rendering task corresponding to the current tile is assigned to processor core 4. In response to assigning the rendering task corresponding to the current tile to processor core 4, the status indicator corresponding to processor core 4 corresponding to the tile is updated to the second value.

[0119] At this time, a state table of a state indicator group as shown in Table 4 can be obtained.

[0120] Table 4 Load level Status indicator group Load level 1 0 0 0 0 Load level 2 1 0 0 0 Load level 3 1 1 1 1 Load level 4 0 0 0 0

[0121] Since the status indicators corresponding to the four processor cores corresponding to load level 3 are all the second value "1" at this time, the status indicators corresponding to the four processor cores corresponding to load level 3 are reset to the first value "0", and a status table of a status indicator group is obtained as shown in Table 5.

[0122] Table 5 Load level Status indicator group Load level 1 0 0 0 0 Load level 2 1 0 0 0 Load level 3 0 0 0 0 Load level 4 0 0 0 0

[0123] In an embodiment of the present invention, the method for updating each status indicator in the status indicator group can reduce the load imbalance problem caused by the continuous distribution of tiles to a certain processor core.

[0124] Considering that two bits are reserved in the tile header information of each tile during the front-end portion's storage of tile information in system memory, FIG7 is a flowchart illustrating a seventh embodiment of a tile distribution method according to an embodiment of the present invention. This method can be executed by a processor of a computer device. The steps illustrated in FIG7 will be described below.

[0125] Step S301: For each of the tiles, the front end of the TBR architecture determines the number of tiles that fall within the tile range based on the position of each tile and the tile range of the tile.

[0126] Step S701: Obtain a first preset level and a corresponding first quantity interval, a second preset level and a corresponding second quantity interval, a third preset level and a corresponding third quantity interval, and a fourth preset level and a corresponding fourth quantity interval.

[0127] Step S702: For each of the tiles, based on the number of graphics elements corresponding to the tile, determine a target preset level among the first preset level, the second preset level, the third preset level, and the fourth preset level as the load level corresponding to the tile.

[0128] Among them, the target preset level is the preset level corresponding to the quantity interval into which the number of graphic elements corresponding to the block falls.

[0129] Step S703: Encode the load level corresponding to each of the tiles through the front end of the TBR architecture to obtain a two-bit encoding value.

[0130] Step S704: Write the two-bit code value corresponding to each tile into the reserved bit in the tile header information of the tile information of each tile.

[0131] Step S705: For each tile, read tile header information of the tile information of the tile from the system memory through the backend portion of the TBR architecture, and decode the encoded value of two bits of the reserved bit in the tile header information to obtain the load level corresponding to the tile.

[0132] Step S203: For each of the tiles, determine, by the backend portion of the TBR architecture, a target processor core corresponding to the tile from the at least two processor cores based on the status indicator corresponding to each of the processor cores in the status indicator group corresponding to the tile.

[0133] Here, the above-mentioned step S301 and step 203 correspond to step S301 in the embodiment of Figure 3 and step 203 in the embodiment of Figure 2, respectively. When implementing, reference may be made to the specific implementation methods in the above-mentioned embodiments.

[0134] In an embodiment of the present invention, considering that in the process of storing the tile information of each tile in the system memory at the front end, there are two bits of reserved bits in the tile header information of the tile information of each tile, the number of load levels is set to 4, and the load levels are encoded to obtain a 2-bit encoding value, thereby effectively utilizing the above-mentioned reserved bits. Compared with the existing TBR architecture, the embodiment of the present invention does not affect the reading and writing processes of the system memory.

[0135] The following describes the application of the tile distribution method provided by an embodiment of the present invention in a practical scenario, primarily involving an image processor with four processor cores. Of course, the embodiment of the present invention does not limit the number of processor cores in the image processor; the following examples are merely intended to more clearly illustrate the implementation process of the present invention.

[0136] In a traditional TBR architecture, the front-end (FrontEnd) 810 generates primitive rendering data and writes it to memory 840. The back-end (BackEnd) 820 splits the image into tiles and distributes them to different GPU cores. Each GPU core reads the primitive data from memory for the corresponding tile, as shown in Figure 8. Load balancing across different GPU cores is closely related to the tile distribution strategy. The tile distributor 830 should not only distribute tiles to different GPU cores as evenly as possible but also control the operating time of each GPU core through tile distribution, thereby reducing GPU performance degradation caused by some GPU cores working too long while others work too short.

[0137] For tile distribution, existing designs typically divide the screen into tiles first, then assign a fixed area on the screen (containing several tiles) to a GPU core for processing. In practice, this involves establishing a mapping between each area divided into the screen and each GPU core, and using this as the basis for tile distribution.

[0138] Please refer to Figure 9, which illustrates the tile distribution process in related art. First, the screen is divided into 16 tiles, t0 through t15. These tiles are then grouped, as shown in Figure 9, into groups of four tiles. Tiles in the same group are distributed to the same GPU core. For the distribution process shown in Figure 9, the tile division results are shown in Table 6.

[0139] Table 6 GPU0 t0,t1,t2,t3 GPU1 t4,t5,t6,t7 GPU2 t8,t9,t10,t11 GPU3 t12,t13,t14,t15

[0140] The above tile distribution ensures that each GPU core processes the same number of tiles, thereby balancing the workload of each GPU core. However, this approach has significant limitations because the distribution algorithm only considers spatial averaging and does not take into account the influence of time (or load).

[0141] Taking the actual rendering scene shown in Figure 10 as an example, Figure 10 shows the triangles that each tile should render. Different tiles have different loads. Among them, t0 to t3 have a larger load, and t4 to t15 have a relatively sparse load. According to the above distribution algorithm, t0 to t3 are sent to the same GPU core (that is, GPU 0), resulting in the overall load of GPU0 being much larger than that of other GPU cores. As a result, the execution time of the GPU core is extremely unbalanced and performance issues are prominent.

[0142] Please refer to Figure 11, which shows the execution time of each processor core in an actual rendering scenario. Among them, the execution time of GPU0 far exceeds the execution time of GPU1, GPU2 and GPU3.

[0143] The present invention improves upon the screen-based tile distribution algorithm used in related technologies and proposes a tile load-based distribution algorithm. This algorithm incorporates the calculation of the tile load factor and uses it as an influencing factor in the tile distribution process to adjust the tile distribution strategy. This improves the load balance across multiple GPU cores on a TBR architecture, thereby enhancing overall performance.

[0144] The embodiment of the present invention is based on the TBR architecture. By adding a load statistics part to the TBR front end and utilizing the existing tile header transmission mechanism, load information is sent from the TBR front end to the TBR back end. The load information is then used in the tile distribution stage to reasonably distribute tiles to each GPU core for execution.

[0145] In some embodiments, the front-end counts the number of times each tile is covered by a primitive during tile segmentation. As shown in Figure 12, the loads of tiles covered by each primitive are calculated based on the three-sided equation of the graph, thereby calculating the loads from T0 to T8. The load of T0 is 1 (including P3), the load of T1 is 2 (including P0 and P3), the load of T2 is 2 (including P0 and P3), the load of T3 is 2 (including P0 and P3), the load of T4 is 4 (including P0, P1, P2, and P3), the load of T5 is 2 (including P1 and P2), the load of T6 is 1 (including P0), the load of T7 is 3 (including P0, P1, and P2), and the load of T8 is 2 (including P1 and P2).

[0146] In some embodiments, the tile payload isn't simply recorded and transmitted to the backend. A large payload would occupy many bits, requiring not only increased storage space but also increased memory read and write bandwidth. To reduce unnecessary hardware overhead, the tile payload is encoded after the last primitive in the tile is counted.

[0147] By testing and statistically analyzing a large number of benchmark points, we extracted four load intervals (corresponding to the numerical intervals in the above embodiment). See Figure 13 for a schematic diagram of the load interval divisions. The load conditions of less than or equal to threshold 1 and greater than threshold 3 are rare, while the loads of most tiles fall within the middle two load intervals. The corresponding codes for the four load intervals are shown in Table 7.

[0148] Table 7 Workload Encode Workload <= threshold 1 00 Threshold 1 < Workload <= Threshold 2 01 Threshold 2 < Workload <= Threshold 3 10 Workload > Threshold 3 11

[0149] As shown in Table 7, the encoded tile payload only occupies 2 bits, which can be easily stuffed into the tile header and then written to memory.

[0150] In some embodiments, the TBR backend reads each tile header from memory, decodes the workload of the tile, and distributes the workload to different GPU cores based on the workload.

[0151] Based on the above implementation scenario, the following test platform uses a system with four GPU cores. In the tile dispatcher, a state machine is constructed based on the tile workload (TWL). This state machine contains four 4-bit 0-1 status indicator groups. The four groups represent the number of TWLs encoded, which is four (status indicator group 0: TWL_00, status indicator group 1: TWL_01, status indicator group 2: TWL_10, and status indicator group 3: TWL_11). The 4 bits represent the number of cores in the system. The cores are swizzled between status indicator groups to ensure that the same number of tiles is sent to each core. The state machine structure is shown in Figure 14.

[0152] After reading a tile's header and parsing its workload encoding value, the corresponding group is found based on the encoding value, and then the indicator bits of each core are traversed from left to right. If the core's indicator is 0, the tile can be distributed to this core, and then the core's indicator is set to 1; when the indicators of all cores in a group have been set to 1, they are all reset to 0 to prepare for the next round of distribution.

[0153] Please refer to Figure 15 for a schematic diagram of the tile distribution process. The screen in Figure 15 includes 16 tiles (t0 to t15). If tiles 0 to 3 are simply sent to core 0, tiles 4 to 7 to core 1, tiles 8 to 9 to core 2, and tiles 10 to 15 to core 3, then cores 0 and 3 will be underloaded, while cores 1 and 2 will be overloaded, resulting in an extremely unbalanced distribution of rendering tasks. Using the tile distribution method provided in the above embodiment, the distribution process from t0 to t15 may include: T0: TWL=TWL_00, check the indicator code of status indicator group 0 (group0_core_mask), select core0 as the distribution target, and set group0_core_mask=1000b; T1: TWL=TWL_01, check the indicator code of status indicator group 1 (group1_core_mask), select core1 as the distribution object, and set group1_core_mask=1000b; T2: TWL=TWL_01, check the indicator code of status indicator group 1 (group1_core_mask), select core2 as the distribution target, and set group1_core_mask=1100b; T3: TWL=TWL_01, check the indicator code of status indicator group 1 (group1_core_mask), select core3 as the distribution target, and set group0_core_mask=1110b; T4: TWL=TWL_10, check the indicator code of status indicator group 2 (group2_core_mask), select core2 as the distribution target, and set group2_core_mask=1000b; T5: TWL=TWL_11, check the indicator code of status indicator group 3 (group3_core_mask), select core3 as the distribution target, and set group3_core_mask=1000b; T6: TWL=TWL_11, check the indicator code of status indicator group 3 (group3_core_mask), select core0 as the distribution target, and set group3_core_mask=1100b; T7: TWL=TWL_10, check the indicator code of status indicator group 2 (group2_core_mask), select core3 as the distribution target, and set group2_core_mask=1100b; T8: TWL=TWL_10, check the indicator code of status indicator group 2 (group2_core_mask), select core0 as the distribution target, and set group2_core_mask=1110b; T9: TWL=TWL_10, check the indicator code of status indicator group 2 (group2_core_mask), select core1 as the distribution object, set group2_core_mask=1111b, reset group2_core_mask=0000b; T10: TWL=TWL_10, check the indicator code of status indicator group 3 (group3_core_mask), select core1 as the distribution object, and set group3_core_mask=1110b; T11: TWL=TWL_11, check the indicator code of status indicator group 2 (group2_core_mask), select core3 as the distribution object, and set group2_core_mask=1111b; T12: TWL = TWL_01, check the indicator code of status indicator group 1 (group1_core_mask), select core0 as the distribution object, set group1_core_mask = 1111b, reset group1_core_mask = 0000b; T13: TWL=TWL_00, check the indicator code of status indicator group 0 (group0_core_mask), select core1 as the distribution target, and set group0_core_mask=1100b; T14: TWL=TWL_01, check the indicator code of status indicator group 1 (group1_core_mask), select core1 as the distribution object, and set group1_core_mask=1000b; T15: TWL = TWL_01, check the indicator code of status indicator group 1 (group1_core_mask), select core2 as the distribution target, and set group1_core_mask = 1100b.

[0154] In the end, the four cores are allocated the same number of tiles, and after comparison, it can be concluded that the load of the four cores is not much different.

[0155] In actual application testing, we've found that larger render targets and / or a greater number of tiles, combined with increased TWL encoding, result in finer tile load distribution and more balanced tile distribution. This increased encoding also incurs certain memory overhead and changes in dispatcher scheduling. In actual hardware, this trade-off can be made based on factors such as memory read / write capacity and the number of cores.

[0156] This embodiment of the present invention focuses on balancing the execution time of all GPU cores. By adding a load statistics function to the tiler stage, the TWL load of each core within the current frame is counted and encoded, and then sent to the backend, which uses this load information to distribute tiles. This algorithm avoids the drawbacks of traditional algorithms that rely on tile number for distribution. With minimal effort, the tile distributor identifies tile load and distributes them in a targeted manner, essentially achieving load balancing across all GPU cores and thus improving overall GPU rendering performance.

[0157] Compared with related technical solutions, the embodiments of the present invention achieve the statistics and transmission of the load of each tile at a very low cost. At the same time, by introducing load as an influencing factor in tile distribution, the working time of some GPU cores will not be too long or too short, thereby improving hardware utilization efficiency. At the same time, a new group-core distribution arrangement is proposed to further reduce the load imbalance problem caused by the continuous distribution of tiles to a certain core.

[0158] Based on the aforementioned embodiments, an embodiment of the present invention provides a tile distribution device, which includes various parts and can be implemented by a processor in a computer device; of course, it can also be implemented by a detailed logic circuit.

[0159] FIG16 is a schematic diagram of the structure of a tile distribution device provided by an embodiment of the present invention. As shown in FIG16 , the tile distribution device 1600 includes: a front-end part 1610 and a back-end part 1620, wherein: The front-end portion 1610 is configured to determine a load level corresponding to each of the plurality of tiles; the load level being used to characterize the number of primitives present in the tile; The front-end portion 1610 is configured to transmit the load level corresponding to each of the tiles to the back-end portion of the TBR architecture; The back-end part 1620 is configured to determine, for each of the tiles, a target processor core corresponding to the tile from the at least two processor cores based on the status indicators corresponding to each of the processor cores in the status indicator group corresponding to the tile; wherein the arrangement order of the status indicators in the status indicator group corresponding to the tile is related to the load level of the tile.

[0160] In this embodiment and other embodiments, "part" can be part of the circuit, part of the processor, part of the program or software, etc., and of course it can also be a unit, a module, or a non-modular one.

[0161] In some embodiments, the arrangement order of the status indicators includes the bit sequence of the status indicator corresponding to each of the processor cores; for each of the bit sequences, the number of processor cores in the set of processor cores corresponding to the bit sequence is the same, and the set of processor cores corresponding to the bit sequence includes the processor cores corresponding to the bit sequence in the status indicator group corresponding to each of the load levels.

[0162] In some embodiments, the front-end part 1610 is further configured to: for each of the tiles, determine the number of tiles that fall within the tile range based on the position of each tile and the tile range of the tile; and determine the load level corresponding to each tile based on the number of tiles corresponding to each tile.

[0163] In some embodiments, the front-end part 1610 is further configured to: obtain multiple preset levels and the quantity interval corresponding to each preset level; for each of the tiles, the preset level corresponding to the quantity interval into which the number of graphic elements corresponding to the tile falls is used as the load level corresponding to the tile.

[0164] In some embodiments, the front-end part 1610 is further configured to: obtain rendering condition parameters of the current rendering environment; the rendering condition parameters include at least one of the following: hardware parameters and rendering target parameters, the hardware parameters are used to characterize the hardware performance of the graphics processor, and the rendering target parameters are used to characterize the computational amount of the rendering object; based on the rendering condition parameters, determine the number of the multiple preset levels; based on the number of the multiple preset levels, obtain the multiple preset levels and the number interval corresponding to each of the preset levels.

[0165] In some embodiments, the hardware parameters include at least one of the following: the number of processor cores and the read and write speed of the memory; the rendering target parameters include at least one of the following: the size of the rendering object and the number of tiles.

[0166] In some embodiments, the front-end part 1610 is further configured to: in the process of writing the tile information of each of the tiles into the system memory, write the load level corresponding to each of the tiles into the tile header information of the corresponding tile information; the back-end part 1620 is further configured to: for each of the tiles, in response to a rendering event for the tile, read the tile header information of the tile information corresponding to the tile from the system memory, and obtain the load level corresponding to the tile from the tile header information.

[0167] In some embodiments, the front-end part 1610 is further configured to: encode the load level corresponding to each of the tiles to obtain a coding value of at least one bit; write the coding value of at least one bit corresponding to each of the tiles into the tile header information of the corresponding tile information; the back-end part 1620 is further configured to: read the tile header information of the tile information corresponding to the tile from the system memory, and decode the coding value of at least one bit in the tile header information to obtain the load level corresponding to the tile.

[0168] In some embodiments, the back-end part 1620 is further configured to: traverse each of the status indicators according to the arrangement order of the status indicators corresponding to the tiles; and take the processor core corresponding to the first status indicator with the first value as the target processor core.

[0169] In some embodiments, the back-end part 1620 is further configured to: assign the rendering task corresponding to the tile to the target processor core; in response to assigning the rendering task corresponding to the tile to the target processor core, update the status indicator corresponding to the target processor core in the status indicator group corresponding to the tile to the second value.

[0170] In some embodiments, the back-end portion 1620 is further configured to: in response to each of the status indicators in the status indicator group corresponding to the tile being the second value, reset each of the status indicators in the status indicator group corresponding to the tile to the first value.

[0171] In some embodiments, the back-end portion 1620 is further configured to: obtain a state machine based on the load level corresponding to each of the tiles; the state machine includes a state indicator group corresponding to each of the load levels.

[0172] In some embodiments, the front-end part 1610 is further configured to: obtain a first preset level and a corresponding first quantity interval, a second preset level and a corresponding second quantity interval, a third preset level and a corresponding third quantity interval, a fourth preset level and a corresponding fourth quantity interval; for each of the tiles, based on the number of graphic elements corresponding to the tile, determine a target preset level among the first preset level, the second preset level, the third preset level and the fourth preset level as the load level corresponding to the tile; the target preset level is the preset level corresponding to the quantity interval into which the number of graphic elements corresponding to the tile falls.

[0173] In some embodiments, the front-end portion 1610 is further configured to: encode the load level corresponding to each tile to obtain a two-bit encoded value; and write the two-bit encoded value corresponding to each tile into a reserved bit in the tile header information of the tile information of each tile. The back-end portion 1620 is further configured to, for each tile, read the tile header information of the tile information of the tile from the system memory, and decode the two-bit encoded value of the reserved bit in the tile header information to obtain the load level corresponding to the tile.

[0174] The description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. In some embodiments, the functions or components of the device provided by the embodiments of the present invention can be configured to perform the methods described in the above method embodiments. For technical details not disclosed in the device embodiments of the present invention, please refer to the description of the method embodiments of the present invention for understanding.

[0175] It should be noted that in embodiments of the present invention, if the aforementioned tile distribution is implemented in the form of a software functional module and sold or used as a standalone product, it can also be stored on a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of the present invention, or the portion that contributes to the relevant art, can be embodied in the form of a software product. This software product, stored on a storage medium, includes instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in various embodiments of the present invention. The aforementioned storage media include various media capable of storing program code, such as a flash drive, a removable hard drive, a read-only memory (ROM), a magnetic disk, or an optical disk. Thus, the embodiments of the present invention are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, or firmware.

[0176] An embodiment of the present invention provides a computer device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, some or all of the steps in the above method are implemented.

[0177] An embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements some or all of the steps in the above-described method. The computer-readable storage medium may be transient or non-transient.

[0178] An embodiment of the present invention provides a computer program comprising computer-readable code. When the computer-readable code is run in a computer device, a processor in the computer device executes some or all of the steps in the above-mentioned method.

[0179] An embodiment of the present invention provides a computer program product comprising a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps of the above-described method. The computer program product can be implemented using hardware, software, or a combination thereof. In some embodiments, the computer program product is embodied as a computer storage medium. In other embodiments, the computer program product is embodied as a software product, such as a software development kit (SDK).

[0180] It should be noted that the above descriptions of the various embodiments tend to emphasize the differences between them, and reference can be made to the similarities and similarities between them. The descriptions of the above embodiments of the apparatus, storage medium, computer program, and computer program product are similar to the descriptions of the above-mentioned method embodiments, and have similar beneficial effects as the method embodiments. For technical details not disclosed in the embodiments of the apparatus, storage medium, computer program, and computer program product of the present invention, please refer to the descriptions of the method embodiments of the present invention for an understanding.

[0181] FIG17 is a schematic diagram of the hardware entity of a computer device provided in an embodiment of the present invention. As shown in FIG17 , the hardware entity of the computer device 1700 includes: a processor 1701 and a memory 1702, wherein the memory 1702 stores a computer program that can be run on the processor 1701. When the processor 1701 executes the program, the steps of the method of any of the above embodiments are implemented.

[0182] Memory 1702 stores computer programs that can be run on the processor. Memory 1702 is configured to store instructions and applications executable by processor 1701. It can also cache data to be processed or processed by processor 1701 and various parts of computer device 1700 (for example, image data, audio data, voice communication data, and video communication data). This can be achieved through flash memory (FLASH) or random access memory (RAM).

[0183] When the processor 1701 executes the program, the steps of any of the above-mentioned tile distribution methods are implemented. The processor 1701 generally controls the overall operation of the computer device 1700.

[0184] An embodiment of the present invention provides a computer storage medium storing one or more programs, which can be executed by one or more processors to implement the steps of the tile distribution method of any of the above embodiments.

[0185] It should be noted that the description of the above storage media and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage media and device embodiments of the present invention, please refer to the description of the method embodiments of the present invention for an understanding.

[0186] The processor can be at least one of an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a central processing unit (CPU), a controller, a microcontroller, and a microprocessor. It is understood that the electronic device implementing the functions of the processor can also be other electronic devices, and the embodiments of the present invention are not specifically limited thereto.

[0187] The computer storage media / memory mentioned above may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), flash memory, magnetic surface mount memory, optical disc, or compact disc read-only memory (CD-ROM); or various terminals including any one or any combination of the above-mentioned memory types, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0188] It should be understood that references throughout this specification to "one embodiment" or "an embodiment" mean that specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present invention. Therefore, the appearance of "in one embodiment" or "in an embodiment" throughout this specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of the present invention, the order of execution of the aforementioned steps / processes does not necessarily imply a specific order of execution. The order of execution of the steps / processes is determined by their functionality and inherent logic and does not constitute any limitation on the implementation of the embodiments of the present invention. The serial numbers of the aforementioned embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0189] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a..." does not preclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0190] In the several embodiments provided herein, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are illustrative. For example, the division of units is a logical functional division. In actual implementation, other division methods may be used, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interface. The indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0191] The units described above as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0192] In addition, the functional units in the various embodiments of the present invention may all be integrated into a single processing unit, each unit may be independently configured as a unit, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or a combination of hardware and software functional units. Those skilled in the art will appreciate that all or part of the steps in the aforementioned method embodiments may be accomplished by hardware associated with program instructions. The aforementioned program may be stored in a computer-readable storage medium. When executed, the program executes the steps of the aforementioned method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as a mobile storage device, a read-only memory (ROM), a magnetic disk, or an optical disk.

[0193] Alternatively, if the integrated unit described above is implemented as a software functional module and sold or used as a standalone product, it can also be stored on a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the relevant art, can be embodied in the form of a software product. This computer software product, stored on a storage medium, includes instructions for enabling a computer device (such as a personal computer, server, or network device) to execute all or part of the methods described in various embodiments of the present invention. The aforementioned storage media includes various media capable of storing program code, such as removable storage devices, ROMs, magnetic disks, or optical disks.

[0194] The above description is merely an embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

[0195] Industrial Applicability

[0196] In this embodiment, the load level of each tile is counted during the distribution process of the graphics processor based on the TBR architecture, and the load level of each tile is transmitted to the back-end part. Then, based on the load level, the target processor core for processing the current tile is determined among at least two processor cores. In this way, compared with the schemes in the related art that use tile position as the distribution basis or the schemes that use tile number as the distribution basis, a targeted tile distribution process can be implemented, thereby balancing the load of each processor core in the graphics processor. At the same time, in the process of determining the target processor core for the current tile based on the load level, the arrangement order of the status indicators of the status indicator group corresponding to the tile is related to the load level of the tile. In this way, the probability of each processor core being called with the same probability can be increased, thereby further improving the load balancing capability and enhancing the rendering performance of the graphics processor as a whole.

[0197] 110: front end 111:Vertex processing part 112: Graphics processing part 113: Block part 120: Backend 121: Rasterization part 122:Hide surface removal 123: Pixel coloring part 124: Output merged part 130: System memory 140: On-chip memory 810: front end 820: backend part 830: Tile Distributor 840:Memory 1600: Tile distribution device 1610: front end 1620: Backend 1700: Computer equipment 1701: Processor 1702: Memory S201, S202, S203, S301, S302, S3021, S3022, S401, S402, S403, S501, S502, 503, S504, S505, S701, S702, S703, S704, S705: Steps

Claims

1. A tile distribution method, applied to a graphics processor including at least two processor cores, wherein the graphics processor performs the tile distribution process based on a tile rendering (TBR) architecture, the tile distribution method comprising the following steps: The load level corresponding to each of the multiple tiles is determined through the front-end portion of the TBR architecture; the load level is used to characterize the number of primitives present in the tile. The load level corresponding to each of the aforementioned tiles is passed to the back-end portion of the TBR architecture; For each of the aforementioned tiles, the backend portion of the TBR architecture determines the target processor core corresponding to the tile from at least two processor cores based on the status indicator corresponding to each processor core in the status indicator group corresponding to the tile; wherein, the arrangement order of the status indicators in the status indicator group corresponding to the tile is related to the load level of the tile; the arrangement order of the status indicators includes the position order of the status indicator corresponding to each processor core; for each position order, the number of each processor core in the processor core set corresponding to the position order is the same, and the processor core set corresponding to the position order includes the processor core corresponding to the position order in the status indicator group corresponding to each load level.

2. The tile distribution method as described in claim 1, wherein, The method of determining the load level corresponding to each of the multiple blocks through the front-end portion of the TBR architecture includes the following steps: For each block, the front-end portion of the TBR architecture determines the number of elements falling within the block range based on the position of each element and the block range of the block; Based on the number of elements corresponding to each block, the load level corresponding to each block is determined.

3. The tile distribution method as described in claim 2, wherein, The method of determining the load level corresponding to each block based on the number of primitives corresponding to each block includes the following steps: obtaining multiple preset levels and the quantity range corresponding to each preset level; For each of the aforementioned blocks, a preset level corresponding to the number range into which the number of elements corresponding to the block falls is used as the load level corresponding to the block.

4. The tile distribution method as described in claim 3, wherein, The step of obtaining multiple preset levels and the quantity range corresponding to each preset level includes the following steps: obtaining rendering condition parameters of the current rendering environment; the rendering condition parameters include at least one of the following: hardware parameters and rendering target parameters, wherein the hardware parameters are used to characterize the hardware performance of the graphics processor, and the rendering target parameters are used to characterize the computational load of the rendering object; determining the quantity of the multiple preset levels based on the rendering condition parameters; and obtaining the multiple preset levels and the quantity range corresponding to each preset level based on the quantity of the multiple preset levels.

5. The tile distribution method as described in claim 4, wherein, The hardware parameters include at least one of the following: the number of processor cores and the read / write speed of memory; the rendering target parameters include at least one of the following: the size of the rendering object and the number of tiles.

6. The tile distribution method as described in any one of claims 1 to 5, wherein, The step of passing the load level corresponding to each tile to the backend of the TBR architecture includes the following steps: During the process of the frontend of the TBR architecture writing the tile information of each tile into the system memory, the load level corresponding to each tile is written into the tile header information of the corresponding tile information; For each tile, in response to a rendering event for the tile, the backend of the TBR architecture reads the tile header information of the tile corresponding to the tile from the system memory, and obtains the load level corresponding to the tile from the tile header information.

7. The tile distribution method as described in claim 6, wherein, The tile distribution method further includes the following steps: The load level corresponding to each tile is encoded by the front-end part of the TBR architecture to obtain at least one bit of encoded value. The step of writing the load level corresponding to each of the maps into the map header information of the corresponding map information includes: writing at least one bit of the encoded value corresponding to each of the maps into the map header information of the corresponding map information; the step of reading the map header information of the map information corresponding to the map from the system memory through the back-end part of the TBR architecture, and obtaining the load level corresponding to the map from the map header information includes: reading the map header information of the map information corresponding to the map from the system memory through the back-end part of the TBR architecture, and decoding at least one bit of the encoded value in the map header information to obtain the load level corresponding to the map.

8. The tile distribution method as described in any one of claims 1 to 5, wherein, The process of determining the target processor core corresponding to the patch from at least two processor cores based on the status indicator corresponding to each processor core in the status indicator group corresponding to the patch by the back-end portion of the TBR architecture includes the following steps: The backend portion of the TBR architecture iterates through each of the status indicators according to the arrangement order of each status indicator corresponding to the block; The processor core corresponding to the first status indicator with the first value is taken as the target processor core.

9. The tile distribution method as described in claim 8, wherein, The tile distribution method further includes the following steps: Assign the rendering task corresponding to the tile to the target processor core; In response to assigning the rendering task corresponding to the tile to the target processor core, update the status indicator corresponding to the target processor core in the status indicator group corresponding to the tile to the second value.

10. The tile distribution method as described in claim 9, wherein, The tile distribution method further includes the following steps: In response to each of the status indicators in the status indicator group corresponding to the tile being the second value, each of the status indicators in the status indicator group corresponding to the tile is reset to the first value.

11. The tile distribution method as described in any one of claims 1 to 5, wherein, The tile distribution method further includes the following steps: The backend portion of the TBR architecture obtains a state machine based on the load level corresponding to each tile; the state machine includes a group of state indicators corresponding to each load level.

12. The tile distribution method as described in claim 2, wherein, The step of determining the load level corresponding to each map block based on the number of primitives corresponding to each map block includes the following steps: obtaining a first preset level and its corresponding first quantity range, a second preset level and its corresponding second quantity range, a third preset level and its corresponding third quantity range, and a fourth preset level and its corresponding fourth quantity range; for each map block, based on the number of primitives corresponding to the map block, determining a target preset level as the load level corresponding to the map block from the first preset level, the second preset level, the third preset level, and the fourth preset level; the target preset level is the preset level corresponding to the quantity range into which the number of primitives corresponding to the map block falls.

13. The tile distribution method as described in claim 12, wherein, The step of transmitting the load level corresponding to each of the aforementioned tiles to the back end of the TBR architecture includes the following steps: encoding the load level corresponding to each of the aforementioned tiles through the front end of the TBR architecture to obtain a two-bit encoded value; Write the two-bit encoded value corresponding to each of the above-mentioned blocks into the reserved bits in the block header information of the block information of each of the above-mentioned blocks; For each of the above-mentioned blocks, read the block header information of the block information of the above-mentioned blocks from the system memory through the back-end part of the TBR architecture, and decode the encoded value of the two bits of the reserved bits in the block header information to obtain the load level corresponding to the block.

14. A computer device comprising a memory and a processor, the memory storing a computer program executable on the processor, the processor executing the computer program to implement the steps of any one of the tile distribution methods described in requests 1 to 13.

15. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the tile distribution method described in any one of requests 1 to 13.

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