Memory circuit and method of operating the same

Abstract

A memory circuit includes a memory array comprising a plurality of non-volatile memory cells arranged along a plurality of access lines extending in a lateral direction. The memory circuit includes a first access circuit physically disposed on a first side of the memory array in the lateral direction. The memory circuit also includes a second access circuit physically disposed on a second side of the memory array in the lateral direction, opposite to the first side. When each of the non-volatile memory cells is programmed with at least a first current and a second current, the first current and the second current flow through the first path and the second path, respectively. The first path includes at least a portion of the first side, and the second path includes at least a portion of the second side.

Description

Memory Device with Dual-Sided Access Circuit and Method of Operating the Same None Due to the continuous increase in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid development. In most cases, this increase in integration density is caused by the repeated reduction of the minimum feature size, which allows more components to be integrated into a given area. None The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify an embodiment of the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature do not directly contact. In addition, an embodiment of the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. In addition, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", "top", "bottom", and the like may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Many modern electronic devices contain memory devices. Memory devices generally include volatile memory devices or non-volatile memory devices. Non-volatile memory devices can store the data they store without power, while volatile memory devices lose their data memory contents when power is turned off. Magnetoresistive random-access memory (MRAM) devices are a promising candidate for the next generation of non-volatile electronic memory devices because they have advantages over current electronic memory devices. Compared with current non-volatile memory devices (such as flash random-access memory devices), MRAM devices are generally faster and have better durability. Compared with current volatile memory devices (such as dynamic random-access memory (DRAM) devices and static random-access memory (SRAM) devices), MRAM devices generally have similar performance and density but lower power consumption. Generally, an MRAM device includes a plurality of MRAM cells formed as a memory array. An MRAM cell can include a magnetic tunnel junction (MTJ) disposed between conductive electrodes (such as an upper electrode and a lower electrode). The MTJ can include a pinned layer separated from a free layer by a tunneling barrier layer. The magnetic orientation of the pinned layer is static (i.e., fixed), while the magnetic orientation of the free layer can switch between a parallel configuration and an anti-parallel configuration relative to the magnetic orientation of the pinned layer. The parallel configuration provides a low-resistance state that stores a data digit as a first data state (such as logic "1"). The anti-parallel configuration provides a high-resistance state that stores a data digit as a second data state (such as logic "0"). Each MRAM cell of the memory array can be programmed via respective upper and lower electrodes. Additionally, to achieve different data states, a programming voltage can be applied to the MRAM cell by connecting the corresponding bit line to the upper electrode with the lower electrode coupled to ground or by connecting the corresponding source line to the lower electrode with the upper electrode coupled to ground. Thus, current can conduct through the MRAM cell in opposite directions. For example, a first current can flow through a first path extending from the bit line, through the MRAM cell, and to the source line to write a first data state; while a second current can flow through a second path extending from the source line, through the MRAM cell, and to the bit line to write a second data state. This programming voltage is typically provided or delivered by a driver circuit that is operatively coupled to the memory array and physically placed beside the memory array, and the generated current typically flows to ground via a pull-down circuit that is also operatively coupled to the memory array and physically placed beside the memory array. In the prior art, the driver circuit and the pull-down circuit are typically formed on the same side of the memory array. As the size of the memory array increases (e.g., as the number of word lines increases / the length of the bit lines increases), due mainly to an increase in the voltage (IR) drop along the extended bit lines, MRAM cells formed further away from the driver circuit and the pull-down circuit typically suffer from insufficient programming voltage. For this reason, some techniques have been proposed to place the driver circuit and the pull-down circuit on opposite sides of the memory array. In other words, regardless of the direction of current flow, the programming voltage is applied to one side of the memory array (via the driver circuit), and the generated current flows to ground on the other side of the memory array (via the pull-down circuit). However, the electrodes of each of the MRAM cells are typically coupled to or formed as metal lines. As the size of the technology node shrinks, the size of these metal lines also shrinks accordingly. Consequently, the metal lines (or the corresponding write paths) can exhibit higher resistance, which results in the voltage drop problem remaining unresolved. Therefore, existing MRAM devices are not entirely satisfactory in some aspects. One embodiment of the present disclosure provides various embodiments of a memory device or circuit including a memory array, wherein one or more driver circuits and one or more pull-down circuit entities are formed on the same side of the memory array having a plurality of memory cells. In one aspect of one embodiment of the present disclosure, the memory device includes one driver circuit disposed on a first side of the memory array and two pull-down circuits respectively disposed on the first side and the second side of the memory array. In another aspect of one embodiment of the present disclosure, the memory device includes two driver circuits respectively disposed on the first side and the second side of the memory array and one pull-down circuit disposed on the first side or the second side of the memory array. In yet another aspect of one embodiment of the present disclosure, the memory device includes two driver circuits respectively disposed on the first side and the second side of the memory array and two pull-down circuits respectively disposed on the first side and the second side of the memory array. Accordingly, each memory cell of the memory array can be programmed via at least a first current and a second current, which can flow in respectively different directions. Thus, the equivalent resistance of the conduction (e.g., programming or reading) path on any one of the memory cells can be significantly reduced, which can advantageously increase the write / read margin of the disclosed memory device. FIG. 1 illustrates a block diagram of a memory device 100 according to various embodiments of the present disclosure. In the illustrated embodiment of FIG. 1, the memory device 100 includes a memory array 102, a column decoder 104, a row decoder 106, an input / output (I / O) circuit 108, and control logic circuitry 110. Although not shown in FIG. 1, all elements of the memory device 100 may be coupled to each other and to the control logic circuitry 110. Although in the illustrated embodiment of FIG. 1, for purposes of clarity of illustration, each element is shown as a separate block, in some other embodiments, some or all of the elements shown in FIG. 1 may be integrated together. For example, the memory array 102 may include embedded I / O circuitry (such as 108). The memory array 102 is a hardware element for storing data. In various embodiments, the memory array 102 is embodied as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or storage units) 103. The memory array 102 includes a plurality of columns R 1 、R 2 、R 3 、……、R M each extending in a first direction (e.g., the X direction), and a plurality of rows C 1 , C 2 , C 3 , ……, C N . Each of the columns and rows may include one or more conductive (e.g., metal) structures that act as access lines. Each memory cell 103 is configured at the intersection of a corresponding column and a corresponding row and can be operated according to the voltage or current through the respective conductive structures of the row and the column. For example, each of the columns may include one or more corresponding word lines (WLs), and each of the rows may include one or more corresponding bit lines (BLs) and one or more source lines (SLs). In some embodiments, each memory cell 103 is embodied as an MRAM cell, the details of which will be discussed in FIG. 2. However, it should be understood that the memory array 102 may include any of various other non-volatile memory cells, such as (for example) spin-transfer torque random-access memory (STT-RAM) cells, ferroelectric random-access memory (FeRAM) cells, resistive random-access memory (RRAM) cells, phase-change random-access memory (PCRAM) cells, etc., while remaining within the scope of an embodiment of the present disclosure. The column decoder 104 is a hardware component that can receive the column address of the memory array 102 and assert a conductive structure (e.g., word line WL) at that column address. The row decoder 106 is a hardware component that can receive the row address of the memory array 102 and assert a conductive structure (e.g., BL and source line SL) at that row address. The I / O circuit 108 is a hardware component that can access (e.g., read, program) each of the memory cells 103 asserted via the column decoder 104 and the row decoder 106. The control logic circuit 110 is a hardware component that can control the coupled components (e.g., 102 to 108). It should be understood that the configuration of the components shown in FIG. 1 is for illustrative purposes only and does not limit the physical layout of these components. For example, although the I / O circuit 108 is shown as being configured on the first side of the memory array 102, according to various embodiments of the present disclosure, the I / O circuit 108 may include multiple sub-components or sub-circuits (such as one or more driver circuits, one or more pull-down circuits) physically disposed on different sides of the memory array 102. Additionally, such sub-components may be physically disposed between the row decoder 106 and the memory array 102. In some embodiments, the driver circuit and the pull-down circuit may sometimes be referred to as access circuits. FIG. 2 illustrates a schematic diagram of an MRAM cell 200 according to various embodiments of the present disclosure. The MRAM cell 200 may be an implementation of the memory cell 103 in FIG. 1. The MRAM cell 200 includes a magnetic memory component, such as an MTJ device 210 and a switching device 220. In one embodiment of the present disclosure, the MTJ device 210 may sometimes be referred to as a memory cell. The MTJ device 210 includes a fixed or pinned layer 212, a tunneling barrier layer or insulator layer 214, and a free layer 216. The magnetization of the free layer 216 freely rotates to point in one of two directions. For the fixed layer 212, an antiferromagnetic layer may be used to fix or pin its magnetization in a specific direction. The insulator layer 214 is sandwiched between the free layer 216 and the fixed layer 212. The free layer 216 is connected to a bit line (BL) 230, and the bit line 230 provides a voltage to the free layer during a read or write operation. The fixed layer 212 is connected to the drain of the switching device 220. The switching device 220 is used to read from or write to the MTJ device 210. Example embodiments of the switching device 220 include a metal oxide semiconductor (MOS) transistor, a MOS diode, and / or a bipolar transistor. The gate of the switching device 220 is connected to a word line (WL) 240, and the word line 240 can activate the memory cell for a read or write operation. In some other embodiments, the word line 240 may include a read word line and a write word line, where the read word line is activated for a read operation, and the write word line is activated for a write operation. The source of the switching device 220 is connected to a source line (SL) 250, and the source line 250 can drive the fixed layer 212 with a voltage during a read or write operation when activated by the word line 240. The source line 250 may include a common source line (CSL), which may be connected to a plurality of memory cells (such as 103) that are connected to the same word line 240. A controller (such as the control logic circuit 110) may provide a turn-on voltage (such as V DD or V CC )。 The data in the MTJ device 210 is represented by the magnetization direction of the free layer 216 relative to the fixed layer 212. For example, when the magnetizations of the free layer 216 and the fixed layer 212 are programmed to be parallel ("P") and the magnetic moments have the same polarity, the MTJ device 210 can exhibit a low resistance. When the magnetizations of the free layer 216 and the fixed layer 212 are programmed to be antiparallel ("AP") and the magnetic moments have opposite polarities, the MTJ device 210 can exhibit a high resistance. During the read operation of the MRAM cell 200, current can flow from the source line 250 to the bit line 230. When the resistance of the MTJ device 210 is low or the magnetizations of the free layer 216 and the fixed layer 212 are parallel, the current flowing through the MRAM cell 200 can be high (sometimes referred to as the logic 0 state). When the resistance of the MTJ device 210 is high or the magnetizations of the free layer 216 and the fixed layer 212 are antiparallel, the current flowing through the MRAM cell 200 can be low (sometimes referred to as the logic 1 state). Current flowing out of the bit line 230 can be provided to a sense amplifier, which can compare the sense amplifier with a reference current from a reference cell. The reference cell can have a resistance that is the average of two different states of the MTJ device 210. For example, the resistance of the reference cell can be set to the average of the parallel state and the antiparallel state. The sense amplifier can then compare the current output of the MTJ device 210 with the current output of the reference cell. If the current output of the MTJ device 210 is less than the reference cell, this means that the resistance in the MTJ device 210 is high, and a logic 1 state is read from the MTJ device 210. If the current output of the MTJ device 210 is greater than the reference cell, this means that the resistance in the MTJ device 210 is low, and a logic 0 state is read from the MTJ device 210. FIG. 3 illustrates an example schematic diagram 300 (hereinafter referred to as "memory device 300") of a portion of the memory device 100 shown in FIG. 1 according to some embodiments of the present disclosure. As a brief overview, the memory device 300 includes a driver circuit and a first pull-down circuit disposed on a first side of the memory array 102 and a second pull-down circuit disposed on a second opposite side of the memory array 102. A memory cell (e.g., 103A) implemented as an MRAM cell 200 (FIG. 2) is shown in the memory array 102. In some embodiments, the driver circuit and the pull-down circuit can be part of the I / O circuit 108. The memory device 300 of FIG. 3 is simplified for illustrative purposes, and thus, it should be understood that some elements of FIG. 1 may be omitted in FIG. 3. As shown, the memory device 300 includes a driver circuit 310, a first pull-down circuit 320, and a second pull-down circuit 330. According to some embodiments, the driver circuit 310 and the first pull-down circuit 320 are physically disposed (or otherwise formed) on a first side of the memory array 102 along the Y direction, for example, while the second pull-down circuit 330 is physically disposed on a second side of the memory array 102 along the Y direction. Additionally, the driver circuit 310 includes sub-circuits 310A and 310B; the first pull-down circuit 320 includes sub-circuits 320A and 320B; and the second pull-down circuit 330 includes sub-circuits 330A and 330B. In some embodiments, sub-circuit 310A of the driver circuit 310 includes two p-type transistors 312 and 314 connected in series with each other; sub-circuit 310B of the driver circuit 310 includes one p-type transistor 313; sub-circuit 320A of the first pull-down circuit 320 includes two n-type transistors 322 and 324 connected in series with each other; sub-circuit 320B of the first pull-down circuit 320 includes one n-type transistor 324; sub-circuit 330A of the second pull-down circuit 330 includes two n-type transistors 332 and 334 connected in series with each other; and sub-circuit 330B of the second pull-down circuit 330 includes one n-type transistor 334. Sub-circuits 310A and 310B of the driver circuit 310 are each configured to selectively couple a programming voltage (e.g., VBL) to the memory cell 103A via a bit line BL or a source line SL, while sub-circuits 320A and 320B of the first pull-down circuit 320 and sub-circuits 330A and 330B of the second pull-down circuit 330 are each configured to selectively couple the memory cell 103A to ground via a bit line BL or a source line SL. The p-type transistors 312 to 313 of the driver circuit 310 are gated (e.g., activated) by respective control signals to couple the programming voltage to the memory cell 103A. For example, the p-type transistors 312 to 313 can each be turned on in response to the corresponding control signal being asserted to a logic low state. The n-type transistors 322 to 324 of the first pull-down circuit 320 are gated (e.g., activated) by respective control signals to couple the memory cell 103A to ground. Similarly, the n-type transistors 332 to 334 of the second pull-down circuit 330 are gated (e.g., activated) by respective control signals to couple the memory cell 103A to ground. For example, the n-type transistors 322 to 324 and 332 to 334 can each be turned on in response to the corresponding control signal being asserted to a logic high state. In some embodiments, the respective logic states of these control signals can be configured based on the logic state to be programmed into the memory cell 103A. In some embodiments, sub-circuits 310A and 310B of the driver circuit 310 can be alternately activated (e.g., when transistors 312 and 314 are turned on simultaneously and transistor 313 is turned off) to couple the programming voltage to the memory cell 103A; sub-circuits 320A and 320B of the first pull-down circuit 320 can be alternately activated (e.g., when transistors 322 and 324 are turned off simultaneously and transistor 324 is turned on) to couple the memory cell 103A to ground; and sub-circuits 330A and 330B of the second pull-down circuit 330 can be alternately activated (e.g., when transistors 332 and 334 are turned on simultaneously and transistor 334 is turned off) to couple the memory cell 103A to ground. For example, to program a logic 0 to the memory cell 103A (from the AP state to the P state), sub-circuits 310A, 320B, and 330B are activated, while sub-circuits 310B, 320A, and 330A are deactivated. Thus, the programming voltage can be coupled to the memory cell 103A via the bit line BL (and sub-circuit 310A), and the memory cell 103A can be coupled to ground via the source line SL (and via sub-circuits 320B and 330B respectively). Equivalently, two conduction paths 351 and 353 can flow through the memory cell 103A. The conduction path 351 extends from the sub-circuit 310A, passes through the memory cell 103A and the sub-circuit 320B and reaches ground; while the conduction path 353 extends from the sub-circuit 310A, passes through the memory cell 103A and the sub-circuit 330B and reaches ground. In other words, the conduction path 351 extends from the first side of the memory array 102 to the first side of the memory array 102, and the conduction path 353 extends from the first side of the memory array 102 to the second side of the memory array 102. In another example, to program a logic 1 to the memory cell 103A (from the P state to the AP state), sub-circuits 310B, 320A, and 330A are activated, while sub-circuits 310A, 320B, and 330B are deactivated. Thus, the programming voltage can be coupled to the memory cell 103A via the source line SL (and sub-circuit 310B), and the memory cell 103A can be coupled to ground via the bit line BL (and via sub-circuits 320A and 330A respectively). Equivalently, two conduction paths 371 and 373 can flow through the memory cell 103A. The conduction path 371 extends from the sub-circuit 310B, passes through the memory cell 103A and the sub-circuit 320A and reaches ground; while the conduction path 373 extends from the sub-circuit 310B, passes through the memory cell 103A and the sub-circuit 330A and reaches ground. In other words, the conduction path 371 extends from the first side of the memory array 102 to the first side of the memory array 102, and the conduction path 373 extends from the first side of the memory array 102 to the second side of the memory array 102. FIG. 4 illustrates another exemplary schematic diagram 400 (hereinafter referred to as "memory device 400") of a portion of the memory device 100 shown in FIG. 1 according to some embodiments of the present disclosure. As a brief overview, the memory device 400 includes a first driver circuit disposed on a first side of the memory array 102, a second driver circuit disposed on a second opposite side of the memory array 102, and a pull-down circuit. A memory cell (e.g., 103A), implemented as an MRAM cell 200 (FIG. 2), is shown in the memory array 102. In some embodiments, the driver circuit and the pull-down circuit may be part of the I / O circuit 108. The memory device 400 of FIG. 4 is simplified for illustrative purposes, and thus, it should be understood that some elements of FIG. 1 may be omitted in FIG. 4. As shown, the memory device 400 includes a first driver circuit 410, a second driver circuit 420, and a pull-down circuit 430. According to some embodiments, the first driver circuit 410 is physically disposed (or otherwise formed) on a first side of the memory array 102, e.g., along the Y direction, while the second driver circuit 420 and the pull-down circuit 430 are physically disposed on a second side of the memory array 102, e.g., along the Y direction. Additionally, the first driver circuit 410 includes sub-circuits 410A and 410B; the second driver circuit 420 includes sub-circuits 420A and 420B; and the pull-down circuit 430 includes sub-circuits 430A and 430B. In some embodiments, the sub-circuit 410A of the first driver circuit 410 includes two p-type transistors 412 and 414 connected in series with each other; the sub-circuit 410B of the first driver circuit 410 includes a p-type transistor 416; the sub-circuit 420A of the second driver circuit 420 includes two p-type transistors 422 and 424 connected in series with each other; the sub-circuit 420B of the second driver circuit 420 includes a p-type transistor 426; the sub-circuit 430A of the pull-down circuit 430 includes two n-type transistors 432 and 434 connected in series with each other; and the sub-circuit 430B of the pull-down circuit 430 includes an n-type transistor 436. The sub-circuits 410A and 410B of the first driver circuit 410 and the sub-circuits 420A and 420B of the second driver circuit 420 are each configured to selectively couple a programming voltage (e.g., VBL) to the memory cell 103A via a bit line BL or a source line SL, while the sub-circuits 430A and 430B of the pull-down circuit 430 are each configured to selectively couple the memory cell 103A to ground via a bit line BL or a source line SL. The p-type transistors 412 to 416 of the first driver circuit 410 are gated (e.g., activated) by respective control signals to couple a programming voltage to the memory cell 103A. Similarly, the p-type transistors 422 to 426 of the second driver circuit 420 are gated (e.g., activated) by respective control signals to couple a programming voltage to the memory cell 103A. For example, the p-type transistors 412 to 416 and 422 to 426 may each turn on in response to the corresponding control signal being asserted to a logic low state. The n-type transistors 432 to 436 of the pull-down circuit 430 are gated (e.g., activated) by respective control signals to couple the memory cell 103A to ground. For example, the n-type transistors 432 to 436 may each turn on in response to the corresponding control signal being asserted to a logic high state. In some embodiments, the respective logic states of these control signals may be configured based on the logic state to be programmed into the memory cell 103A. In some embodiments, the sub-circuits 410A and 410B of the first driver circuit 410 may be alternately activated to couple a programming voltage to the memory cell 103A; the sub-circuits 420A and 420B of the second driver circuit 420 may be alternately activated to couple a programming voltage to the memory cell 103A; and the sub-circuits 430A and 430B of the pull-down circuit 430 may be alternately activated to couple the memory cell 103A to ground. For example, to program a logic 0 into the memory cell 103A (from the AP state to the P state), the sub-circuits 410A, 420A, and 430B are activated, while the sub-circuits 410B, 420B, and 430A are deactivated. Thus, the programming voltage can be coupled to the memory cell 103A via the bit line BL (and via the sub-circuits 410A and 420A respectively), and the memory cell 103A can be coupled to ground via the source line SL (and the sub-circuit 430B). Equivalently, two conduction paths 451 and 453 can flow through the memory cell 103A. The conduction path 451 extends from the sub-circuit 410A, passes through the memory cell 103A and the sub-circuit 430B and reaches ground; and the conduction path 453 extends from the sub-circuit 420A, passes through the memory cell 103A and the sub-circuit 430B and reaches ground. In other words, the conduction path 451 extends from the first side of the memory array 102 to the second side of the memory array 102, and the conduction path 453 extends from the second side of the memory array 102 to the second side of the memory array 102. In another example, to program a logic 1 into memory cell 103A (from the P state to the AP state), sub-circuits 410B, 420B, and 430A are activated, while sub-circuits 410A, 420A, and 430B are deactivated. Thus, the programming voltage can be coupled to memory cell 103A via the source line SL (and via sub-circuits 410B and 420B respectively), and memory cell 103A can be coupled to ground via the bit line BL (and sub-circuit 430A). Equivalently, two conduction paths 471 and 473 can flow through memory cell 103A. Conduction path 471 extends from sub-circuit 410B, passes through memory cell 103A and sub-circuit 430A and reaches ground; while conduction path 473 extends from sub-circuit 420B, passes through memory cell 103A and sub-circuit 430A and reaches ground. In other words, conduction path 471 extends from the first side of memory array 102 to the second side of memory array 102, and conduction path 473 extends from the second side of memory array 102 to the second side of memory array 102. FIG. 5 illustrates another exemplary schematic diagram 500 (hereinafter referred to as "memory device 500") of a portion of the memory device 100 shown in FIG. 1 according to some embodiments of the present disclosure. As a brief overview, memory device 500 includes a first driver circuit and a pull-down circuit disposed on the first side of memory array 102 and a second driver circuit disposed on the second opposite side of memory array 102. A memory cell (e.g., 103A) implemented as an MRAM cell 200 (FIG. 2) is shown in memory array 102. In some embodiments, the driver circuit and the pull-down circuit can be part of the I / O circuit 108. The memory device 500 of FIG. 5 is simplified for illustrative purposes, and thus, it should be understood that some elements of FIG. 1 may be omitted in FIG. 5. As shown, memory device 500 includes a first driver circuit 510, a second driver circuit 520, and a pull-down circuit 530. According to some embodiments, the first driver circuit 510 and the pull-down circuit 530 are physically disposed (or otherwise formed) on the first side of memory array 102, for example, along the Y direction, while the second driver circuit 520 is physically disposed on the second side of memory array 102, for example, along the Y direction. Additionally, the first driver circuit 510 includes sub-circuits 510A and 510B; the second driver circuit 520 includes sub-circuits 520A and 520B; and the pull-down circuit 530 includes sub-circuits 530A and 530B. In some embodiments, sub - circuit 510A of the first driver circuit 510 includes two p - type transistors 512 and 514 connected in series with each other; sub - circuit 510B of the first driver circuit 510 includes one p - type transistor 516; sub - circuit 520A of the second driver circuit 520 includes two p - type transistors 522 and 524 connected in series with each other; sub - circuit 520B of the second driver circuit 520 includes one p - type transistor 526; sub - circuit 530A of the pull - down circuit 530 includes two n - type transistors 532 and 534 connected in series with each other; and sub - circuit 530B of the pull - down circuit 530 includes one n - type transistor 536. Sub - circuits 510A and 510B of the first driver circuit 510 and sub - circuits 520A and 520B of the second driver circuit 520 are each configured to selectively couple a programming voltage (e.g., VBL) to the memory cell 103A via the bit line BL or the source line SL, while sub - circuits 530A and 530B of the pull - down circuit 530 are each configured to selectively couple the memory cell 103A to ground via the bit line BL or the source line SL. The p - type transistors 512 to 516 of the first driver circuit 510 are gated (e.g., activated) by respective control signals to couple the programming voltage to the memory cell 103A. Similarly, the p - type transistors 522 to 526 of the second driver circuit 520 are gated (e.g., activated) by respective control signals to couple the programming voltage to the memory cell 103A. For example, the p - type transistors 512 to 516 and 522 to 526 can each be turned on in response to the corresponding control signal being asserted to a logic - low state. The n - type transistors 532 to 536 of the pull - down circuit 530 are gated (e.g., activated) by respective control signals to couple the memory cell 103A to ground. For example, the n - type transistors 532 to 536 can each be turned on in response to the corresponding control signal being asserted to a logic - high state. In some embodiments, the respective logic states of these control signals can be configured based on the logic state to be programmed into the memory cell 103A. In some embodiments, sub - circuit 510A and sub - circuit 510B of the first driver circuit 510 can be alternately activated to couple the programming voltage to the memory cell 103A; sub - circuit 520A and sub - circuit 520B of the second driver circuit 520 can be alternately activated to couple the programming voltage to the memory cell 103A; and sub - circuit 530A and sub - circuit 530B of the pull - down circuit 530 can be alternately activated to couple the memory cell 103A to ground. For example, in order to program a logic 0 into memory cell 103A (from the AP state to the P state), sub-circuits 510A, 520A, and 530B are activated, while sub-circuits 510B, 520B, and 530A are deactivated. Thus, the programming voltage can be coupled to memory cell 103A via bit line BL (and via sub-circuits 510A and 520A respectively), and memory cell 103A can be coupled to ground via source line SL (and sub-circuit 530B). Equivalently, two conduction paths 551 and 553 can flow through memory cell 103A. Conduction path 551 extends from sub-circuit 510A, passes through memory cell 103A and sub-circuit 530B and reaches ground; while conduction path 553 extends from sub-circuit 520A, passes through memory cell 103A and sub-circuit 530B and reaches ground. In other words, conduction path 551 extends from the first side of memory array 102 to the first side of memory array 102, and conduction path 553 extends from the second side of memory array 102 to the first side of memory array 102. In another example, in order to program a logic 1 into memory cell 103A (from the P state to the AP state), sub-circuits 510B, 520B, and 530A are activated, while sub-circuits 510A, 520A, and 530B are deactivated. Thus, the programming voltage can be coupled to memory cell 103A via source line SL (and via sub-circuits 510B and 520B respectively), and memory cell 103A can be coupled to ground via bit line BL (and sub-circuit 530A). Equivalently, two conduction paths 571 and 573 can flow through memory cell 103A. Conduction path 571 extends from sub-circuit 510B, passes through memory cell 103A and sub-circuit 530A and reaches ground; while conduction path 573 extends from sub-circuit 520B, passes through memory cell 103A and sub-circuit 530A and reaches ground. In other words, conduction path 571 extends from the first side of memory array 102 to the first side of memory array 102, and conduction path 573 extends from the second side of memory array 102 to the first side of memory array 102. FIG. 6 illustrates another exemplary schematic diagram 600 (hereinafter referred to as "memory device 600") of a portion of the memory device 100 shown in FIG. 1 according to some embodiments of the present disclosure. As a brief overview, the memory device 600 includes a first driver circuit and a first pull-down circuit disposed on a first side of the memory array 102, and a second driver circuit and a second pull-down circuit disposed on a second opposite side of the memory array 102. A memory cell (e.g., 103A), implemented as an MRAM cell 200 (FIG. 2), is shown in the memory array 102. In some embodiments, the driver circuit and the pull-down circuit may be part of the I / O circuit 108. The memory device 600 of FIG. 6 is simplified for illustrative purposes, and thus, it should be understood that some elements of FIG. 1 may be omitted in FIG. 6. As shown, the memory device 600 includes a first driver circuit 610, a second driver circuit 620, a first pull-down circuit 630, and a second pull-down circuit 640. According to some embodiments, the first driver circuit 610 and the first pull-down circuit 630 are physically disposed (or otherwise formed) on a first side of the memory array 102, for example, along the Y direction, while the second driver circuit 620 and the second pull-down circuit 640 are physically disposed on a second side of the memory array 102, for example, along the Y direction. Additionally, the first driver circuit 610 includes sub-circuits 610A and 610B; the second driver circuit 620 includes sub-circuits 620A and 620B; the first pull-down circuit 630 includes sub-circuits 630A and 630B; and the second pull-down circuit 640 includes sub-circuits 640A and 640B. In some embodiments, sub - circuit 610A of the first driver circuit 610 includes two p - type transistors 612 and 614 connected in series with each other; sub - circuit 610B of the first driver circuit 610 includes one p - type transistor 616; sub - circuit 620A of the second driver circuit 620 includes two p - type transistors 622 and 624 connected in series with each other; sub - circuit 620B of the second driver circuit 620 includes one p - type transistor 626; sub - circuit 630A of the first pull - down circuit 630 includes two n - type transistors 632 and 634 connected in series with each other; sub - circuit 630B of the pull - down circuit 630 includes one n - type transistor 636; sub - circuit 640A of the second pull - down circuit 640 includes two n - type transistors 642 and 644 connected in series with each other; and sub - circuit 640B of the second pull - down circuit 640 includes one n - type transistor 646. Sub - circuits 610A and 610B of the first driver circuit 610 and sub - circuits 620A and 620B of the second driver circuit 620 are each configured to selectively couple a programming voltage (e.g., VBL) to the memory cell 103A via the bit line BL or the source line SL, while sub - circuits 630A and 630B of the pull - down circuit 630 and sub - circuits 640A and 640B of the pull - down circuit 640 are each configured to selectively couple the memory cell 103A to ground via the bit line BL or the source line SL. The p - type transistors 612 to 616 of the first driver circuit 610 are gated (e.g., activated) by respective control signals to couple the programming voltage to the memory cell 103A. Similarly, the p - type transistors 622 to 626 of the second driver circuit 620 are gated (e.g., activated) by respective control signals to couple the programming voltage to the memory cell 103A. For example, the p - type transistors 612 to 616 and 622 to 626 may each turn on in response to the corresponding control signal being asserted to a logic - low state. The n - type transistors 632 to 636 of the first pull - down circuit 630 are gated (e.g., activated) by respective control signals to couple the memory cell 103A to ground. Similarly, the n - type transistors 642 to 646 of the second pull - down circuit 640 are gated (e.g., activated) by respective control signals to couple the memory cell 103A to ground. For example, the n - type transistors 632 to 636 and 642 to 646 may each turn on in response to the corresponding control signal being asserted to a logic - high state. In some embodiments, the respective logic states of these control signals may be configured based on the logic state to be programmed into the memory cell 103A. In some embodiments, sub-circuits 610A and 610B of the first driver circuit 610 may be alternately activated to couple a programming voltage to the memory cell 103A; sub-circuits 620A and 620B of the second driver circuit 620 may be alternately activated to couple a programming voltage to the memory cell 103A; sub-circuits 630A and 630B of the first pull-down circuit 630 may be alternately activated to couple the memory cell 103A to ground; and sub-circuits 640A and 640B of the second pull-down circuit 640 may be alternately activated to couple the memory cell 103A to ground. For example, to program a logic 0 to the memory cell 103A (from the AP state to the P state), sub-circuits 610A, 620A, 630B, and 640B are activated, while sub-circuits 610B, 620B, 630A, and 640A are deactivated. Thus, the programming voltage can be coupled to the memory cell 103A via the bit line BL (and via sub-circuits 610A and 620A respectively), and the memory cell 103A can be coupled to ground via the source line SL (and via sub-circuits 630B and 640B respectively). Equivalently, two conduction paths 651 and 653 can flow through the memory cell 103A. The conduction path 651 extends from the sub-circuit 610A, passes through the memory cell 103A and the sub-circuit 630B and reaches ground; while the conduction path 653 extends from the sub-circuit 620A, passes through the memory cell 103A and the sub-circuit 640B and reaches ground. In other words, the conduction path 651 extends from the first side of the memory array 102 to the first side of the memory array 102, and the conduction path 653 extends from the second side of the memory array 102 to the second side of the memory array 102. In another example, to program a logic 1 to the memory cell 103A (from the P state to the AP state), sub-circuits 610B, 620B, 630A, and 640A are activated, while sub-circuits 610A, 620A, 630B, and 640B are deactivated. Thus, the programming voltage can be coupled to the memory cell 103A via the source line SL (and via sub-circuits 610B and 620B respectively), and the memory cell 103A can be coupled to ground via the bit line BL (and via sub-circuits 630A and 640A respectively). Equivalently, two conduction paths 671 and 673 can flow through the memory cell 103A. The conduction path 671 extends from the sub-circuit 610B, passes through the memory cell 103A and the sub-circuit 630A and reaches ground; while the conduction path 673 extends from the sub-circuit 620B, passes through the memory cell 103A and the sub-circuit 640A and reaches ground. In other words, the conduction path 671 extends from the first side of the memory array 102 to the first side of the memory array 102, and the conduction path 673 extends from the second side of the memory array 102 to the second side of the memory array 102. FIG. 7 illustrates another exemplary schematic diagram 700 (hereinafter referred to as "memory device 700") of a portion of the memory device 100 shown in FIG. 1 according to some embodiments of the present disclosure. The memory device 700 is substantially similar to the memory device 400 (FIG. 4), except that the transistors in each of the sub-circuits 410A, 420A, and 430A can be activated by different control signals. The memory device 400, for example, includes a first driver circuit 410 disposed on a first side of the memory array 102 and a second driver circuit 420 and a pull-down circuit 430 disposed on a second side of the memory array 102. Therefore, the following discussion of the memory device 700 will focus on the differences. For the sub-circuit 410A, the transistor 412 is gated by the control signal MX1, and the transistor 414 is gated by the control signal S1B; and for the sub-circuit 410B, the transistor 416 is gated by the control signal S1. Similarly, the transistors 422 and 424 of the sub-circuit 420A are gated by the control signals S1B and MX1, respectively, and the transistor 426 of the sub-circuit 420B is gated by the control signal S1; and the transistors 432 and 434 of the sub-circuit 430A are gated by the control signals S1B and MX1, respectively, and the transistor 436 of the sub-circuit 430B is gated by the control signal S1. In some embodiments, the logic state of the signal MX1 can be configured based on determining that a set of rows of memory cells will be programmed / read, and the logic state of the signal S1 / S1B can be configured based on determining that a certain memory cell will be programmed / read. Thus, the signal MX1 and the signal S1 / S1B can have different pulse widths. For example, the pulse width of the signal MX1 is wider than the pulse width of the signal S1 / S1B. Additionally, the control signals S1 and S1B are logically inverted with respect to each other. Thus, the sub-circuits in any of the first driver circuit 410, the second driver circuit 420, and the pull-down circuit 430 can be alternately activated. Using FIG. 7 as a representative example, the signal MX1 can be pulled to the logic low state, followed by the signal S1B being pulled to the logic state (while the signal S1 is pulled to the logic high state). In some other embodiments, the signal MX1 and the signal S1B can be pulled down simultaneously. Therefore, the sub-circuits 410A, 420A, and 430B can be activated, while the sub-circuits 410B, 420B, and 430A can be deactivated. Thus, the sub-circuits 410A and 420A can each couple the programming voltage (VBL) to the memory cell 103A, and the sub-circuit 430B can couple the memory cell 103A to ground, thereby writing a logic 0 to the memory cell 103A. FIG. 8 illustrates another exemplary schematic diagram 800 (hereinafter referred to as "memory device 800") of a portion of the memory device 100 shown in FIG. 1 according to some embodiments of the present disclosure. The memory device 800 is substantially similar to the memory device 500 (FIG. 5), except that the transistors in each of the sub-circuits 510A, 520A, and 530A can be activated by different control signals. The memory device 500, for example, includes a first driver circuit 510 and a pull-down circuit 530 disposed on a first side of the memory array 102 and a second driver circuit 520 disposed on a second side of the memory array 102. Therefore, the following discussion of the memory device 800 will focus on the differences. For the sub-circuit 510A, the transistor 512 is gated by the control signal MX1, and the transistor 514 is gated by the control signal S1B; and for the sub-circuit 510B, the transistor 516 is gated by the control signal S1. Similarly, the transistors 522 and 524 of the sub-circuit 520A are gated by the control signals S1B and MX1, respectively, and the transistor 526 of the sub-circuit 520B is gated by the control signal S1; and the transistors 532 and 534 of the sub-circuit 530A are gated by the control signals MX1 and S1B, respectively, and the transistor 536 of the sub-circuit 530B is gated by the control signal S1. In some embodiments, the logical state of the signal MX1 can be configured based on determining that a set of rows of memory cells will be programmed / read, and the logical state of the signals S1 / S1B can be configured based on determining that a certain memory cell will be programmed / read. Thus, the signal MX1 and the signals S1 / S1B can have different pulse widths. For example, the pulse width of the signal MX1 is wider than the pulse width of the signals S1 / S1B. Additionally, the control signals S1 and S1B are logically inverted with respect to each other. Thus, the sub-circuits in any of the first driver circuit 510, the second driver circuit 520, and the pull-down circuit 530 can be alternately activated. Using FIG. 8 as a representative example, the signal MX1 can be pulled to the logical low state, followed by the signal S1B being pulled to the logical state (while the signal S1 is pulled to the logical high state). In some other embodiments, the signals MX1 and S1B can be pulled down simultaneously. Thus, the sub-circuits 510A, 520A, and 530B can be activated, while the sub-circuits 510B, 520B, and 530A can be deactivated. Consequently, the sub-circuits 510A and 520A can each couple a programming voltage (VBL) to the memory cell 103A, and the sub-circuit 530B can couple the memory cell 103A to ground, thereby writing a logical 0 to the memory cell 103A. FIG. 9 illustrates another example schematic diagram 900 (hereinafter referred to as "memory device 900") of a portion of the memory device 100 shown in FIG. 1 according to some embodiments of the present disclosure. The memory device 900 is substantially similar to the memory device 600 (FIG. 6), except that the transistors in each of the sub-circuits 610A, 620A, 630A, and 640A can be activated by different control signals. The memory device 600, for example, includes a first driver circuit 610 and a first pull-down circuit 630 disposed on a first side of the memory array 102, and a second driver circuit 620 and a second pull-down circuit 640 disposed on a second side of the memory array 102. Therefore, the following discussion of the memory device 900 will focus on the differences. For the sub-circuit 610A, the transistor 612 is gated by the control signal MX1, and the transistor 614 is gated by the control signal S1B; and for the sub-circuit 610B, the transistor 616 is gated by the control signal S1. Similarly, the transistors 622 and 624 of the sub-circuit 620A are gated by the control signals S1B and MX1, respectively, and the transistor 626 of the sub-circuit 620B is gated by the control signal S1; the transistors 632 and 634 of the sub-circuit 630A are gated by the control signals MX1 and S1B, respectively, and the transistor 636 of the sub-circuit 630B is gated by the control signal S1; and the transistors 642 and 644 of the sub-circuit 640A are gated by the control signals S1B and MX1, respectively, and the transistor 646 of the sub-circuit 640B is gated by the control signal S1. In some embodiments, the logic state of the signal MX1 can be configured based on determining that a set of rows of memory cells is to be programmed / read, and the logic state of the signal S1 / S1B can be configured based on determining that a certain memory cell is to be programmed / read. Thus, the signal MX1 and the signal S1 / S1B can have different pulse widths. For example, the pulse width of the signal MX1 is wider than the pulse width of the signal S1 / S1B. Additionally, the control signals S1 and S1B are logically inverted with respect to each other. Thus, the sub-circuits of any of the first driver circuit 610, the second driver circuit 620, the first pull-down circuit 630, and the second pull-down circuit 640 can be alternately activated. Using FIG. 9 as a representative example, signal MX1 can be pulled to a logic low state, and紧接着 signal S1B is pulled to a logic state (while signal S1 is pulled to a logic high state). In some other embodiments, signals MX1 and S1B can be pulled down simultaneously. Thus, sub - circuits 610A, 620A, 630B, and 640B can be activated, while sub - circuits 610B, 620B, 630A, and 640A can be de - activated. Consequently, sub - circuits 610A and 620A can each couple a programming voltage (VBL) to memory cell 103A, and sub - circuits 630B and 640B can each couple memory cell 103A to ground, thereby writing a logic 0 to memory cell 103A. FIG. 10 illustrates another exemplary schematic diagram 1000 (hereinafter referred to as "memory device 1000") of a portion of the memory device 100 shown in FIG. 1 according to some embodiments of the present disclosure. Memory device 1000 is substantially similar to memory device 900 (FIG. 9), except that memory device 1000 further includes sub - circuits 1010 and 1020 to further reduce the conduction resistance. Memory device 900, for example, includes a first driver circuit 610 and a first pull - down circuit 630 disposed on a first side of the memory array 102 and controlled by signals MX1 / S1B / S1, and a second driver circuit 620 and a second pull - down circuit 640 disposed on a second side of the memory array 102 and controlled by signals MX1 / S1B / S1. Therefore, the following discussion of memory device 1000 will focus on the differences. As shown, sub - circuits 1010 and 1020 are physically disposed on the same side (i.e., the first side along the Y - direction) of the memory array 102 as sub - circuits 610A - B and 630A - B. It should be understood that sub - circuits 1010 and 1020 can be disposed on the second side of the memory array 102 (i.e., the same side as sub - circuits 620A - B and 640A - B) while remaining within the scope of an embodiment of the present disclosure. Additionally, sub - circuit 1010 includes p - type transistors 1012 and 1014 gated by signals MX1 and S1B respectively; and sub - circuit 1020 includes n - type transistors 1022 and 1024 gated by signals MX1 and S1B respectively. In some embodiments, sub - circuit 1010 is used to couple a programming voltage (VBL) to memory cell 103A; and sub - circuit 1020 is used to couple memory cell 103A to ground. In some embodiments, sub - circuit 1010 can be activated simultaneously with sub - circuits 610A, 620A, 630B, and 640B, and thus, at least one additional conduction path can be formed to extend through memory cell 103A (e.g., extending from sub - circuit 1010, through memory cell 103A and sub - circuit 630B and reaching ground). FIG. 11 illustrates another exemplary schematic diagram 1100 (hereinafter referred to as "memory device 1100") of a portion of the memory device 100 shown in FIG. 1 according to some embodiments of the present disclosure. The memory device 1100 is substantially similar to the memory device 1000 (FIG. 10), except that the memory device 1000 further includes sub-circuits 1010 and 1020 to further reduce the conduction resistance. The memory device 1000 includes, for example, a first driver circuit 610 and a first pull-down circuit 630 controlled by signals MX1 / S1B / S1, and a second driver circuit 620 and a second pull-down circuit 640 controlled by signals MX1 / S1B / S1. Therefore, the following discussion of the memory device 1000 will focus on the differences. As shown, the additional sub-circuits 1010 and 1020 can be physically disposed on the third side of the memory array. For example, the sub-circuits 1010 and 1020 can be disposed along the X direction on one of the sides of the memory array 102. FIG. 12 illustrates the waveforms of the above-mentioned signals S1, S1B, and MX1 according to some embodiments of the present disclosure. For example, the respective waveforms of the signals S1, S1B, and MX1 are illustrated when writing a logic 0 to a corresponding memory cell (e.g., 103A) and writing a logic 1 to a corresponding memory cell (e.g., 103A). When writing a logic 0, the signal MX1 can be pulled low, and then the signal S1 is pulled high (while the logic inverted signal S1B is pulled low). When writing a logic 1, the signal MX1 can be pulled high, and then the signal S1 is pulled low (while the logic inverted signal S1B is pulled high). FIG. 13 illustrates a flowchart of an exemplary method 1300 for operating a memory device according to some embodiments. The memory device includes access circuits physically disposed on opposite sides of a memory array. For example, at least some operations of the method 1300 can be performed to write / read a memory cell (e.g., 103A) based on at least two conduction paths. Therefore, in the following discussion of the method 1300, the reference numerals used in the above figures (e.g., FIGS. 1 to 12) can be reused. It should be noted that the method 1300 is only an example and is not intended to limit an embodiment of the present disclosure. Therefore, it should be understood that additional operations can be provided before, during, and after the method 1300 of FIG. 13, and some other operations can be briefly described herein. Method 1300 begins with operation 1310, in which a plurality of access circuits are activated that are physically disposed on opposite sides of the memory array. In some embodiments, the memory array (e.g., 102) includes a plurality of memory cells (e.g., MRAM cells 103) disposed above a plurality of rows and a plurality of columns. Along each row, a subset of the memory cells are coupled to each other via bit lines and source lines, each of the bit lines and source lines extending along the Y direction; and along each column, another subset of the memory cells are coupled to each other via word lines, the word lines extending along the X direction. In one aspect of an embodiment of the present disclosure (e.g., the memory device 300 of FIG. 3), a first access circuit (e.g., 310) is physically disposed on a first side of the memory array 102 along the Y direction, a second access circuit (e.g., 320) is physically disposed on the first side of the memory array 102 along the Y direction, and a third access circuit (e.g., 330) is physically disposed on a second side of the memory array 102 along the Y direction. In another aspect of an embodiment of the present disclosure (e.g., the memory device 400 of FIG. 4), a first access circuit (e.g., 410) is physically disposed on a first side of the memory array 102, a second access circuit (e.g., 420) is physically disposed on a second side of the memory array 102, and a third access circuit (e.g., 430) is physically disposed on a second side of the memory array 102. In yet another aspect of an embodiment of the present disclosure (e.g., the memory device 500 of FIG. 5), a first access circuit (e.g., 510) is physically disposed on a first side of the memory array 102, a second access circuit (e.g., 520) is physically disposed on a second side of the memory array 102, and a third access circuit (e.g., 530) is physically disposed on a first side of the memory array 102. In yet another aspect of an embodiment of the present disclosure (e.g., the memory device 600 of FIG. 6), a first access circuit (e.g., 610) is physically disposed on a first side of the memory array 102, a second access circuit (e.g., 620) is physically disposed on a second side of the memory array 102, a third access circuit (e.g., 630) is physically disposed on a first side of the memory array 102, and a fourth access circuit (e.g., 640) is physically disposed on a second side of the memory array 102. To access (e.g., program, read) a memory array, multiple access circuits may be activated. Specifically, each access circuit may include two sub-circuits, and the two sub-circuits may be alternately activated based on the logical state to be programmed into the corresponding memory cell. In the case where at least two of the access circuits are disposed on opposite sides of the memory array 102, each memory cell of the memory array 102 may be programmed / read via at least two conduction paths, which can advantageously reduce the equivalent resistance along the conduction paths. In the following discussion of method 1300, the memory device 300 (Figure 3) is used as a representative example. When writing a logical 0, the sub-circuit 310A of the access circuit 310, the sub-circuit 320B of the access circuit 320, and the sub-circuit 330B of the access circuit 330 are activated, while the other sub-circuit (310B, 320A, 330A) of each of the access circuits is deactivated. When writing a logical 1, the sub-circuit 310B of the access circuit 310, the sub-circuit 320A of the access circuit 320, and the sub-circuit 330A of the access circuit 330 are activated, while the other sub-circuit (310A, 320B, 330B) of each of the access circuits is deactivated. Method 1300 proceeds to operation 1320, in which a voltage is provided to the memory cell. Continuing with the same example above, when the memory cell is selected for programming, the voltage may be a programming voltage (VBL). Based on the logical state to be programmed, different sub-circuits of the access circuit may be activated to couple the programming voltage to the memory cell. When the sub-circuits 310A, 320B, and 330B are activated (e.g., writing a logical 0 to the memory cell), the programming voltage may be coupled to the memory cell via its corresponding bit line. When the sub-circuits 310B, 320A, and 330A are activated (e.g., writing a logical 1 to the memory cell), the programming voltage may be coupled to the memory cell via its corresponding source line. Method 1300 proceeds to operations 1330 and 1340. In operation 1330, a first conduction current is conducted through the memory cell, and in operation 1340, a second conduction current is conducted through the memory cell. In some embodiments, operations 1330 and 1340 may be performed simultaneously. Still regarding the same example above (when writing a logic 0 to the memory cell), sub-circuits 310A, 320B, and 330B are activated. Thus, a first conduction path (e.g., 351) and a second conduction path (e.g., 353) can be formed. The first conduction path extends from sub-circuit 310A, passes through memory cell 103A and sub-circuit 320B, and reaches ground. The second conduction path extends from sub-circuit 310A, passes through memory cell 103A and sub-circuit 330B, and reaches ground. When writing a logic 1 to the memory cell, sub-circuits 310B, 320A, and 330A are activated. Thus, a first conduction path (e.g., 371) and a second conduction path (e.g., 373) can be formed. The first conduction path extends from sub-circuit 310B, passes through memory cell 103A and sub-circuit 320A, and reaches ground. The second conduction path extends from sub-circuit 310B, passes through memory cell 103A and sub-circuit 330A, and reaches ground. In one aspect of an embodiment of the present disclosure, a memory circuit is disclosed. The memory circuit includes a memory array that includes a plurality of non-volatile memory cells, where the non-volatile memory cells are arranged along a plurality of access lines that extend in a lateral direction. The memory circuit includes a first access circuit that is physically disposed on a first side of the memory array in the lateral direction. The memory circuit includes a second access circuit that is physically disposed on a second side of the memory array in the lateral direction, the second side being opposite to the first side. When each of the non-volatile memory cells is to be programmed by at least a first current and a second current, the first current and the second current flow through a first path and a second path, respectively. The first path includes at least a portion on the first side, and the second path includes at least a portion on the second side. In another aspect of an embodiment of the present disclosure, a memory circuit is disclosed. The memory circuit includes a plurality of non-volatile memory cells disposed above a plurality of bit lines extending along a lateral direction. The memory circuit includes a first access circuit physically disposed on a first side of the non-volatile memory cells in the lateral direction, wherein the first access circuit includes a first sub-circuit and a second sub-circuit. The memory circuit includes a second access circuit physically disposed on a second side of the non-volatile memory cells in the lateral direction, the second side being opposite to the first side, wherein the second access circuit includes a third sub-circuit and a fourth sub-circuit. The first sub-circuit is configured to couple a programming voltage to a corresponding one of the plurality of non-volatile memory cells, and the second sub-circuit and the fourth sub-circuit are each configured to supplement a conduction path from the programming voltage to ground when programming a first logic state to a corresponding non-volatile memory cell. The second sub-circuit is configured to couple the programming voltage to a corresponding non-volatile memory cell, and the first sub-circuit and the third sub-circuit are each configured to supplement another conduction path from the programming voltage to ground when programming a second logic state to a corresponding non-volatile memory cell. In yet another aspect of an embodiment of the present disclosure, a method for operating a memory circuit is disclosed. The method includes activating (i) a first access circuit physically disposed on a first side of the non-volatile memory cells; (ii) a second access circuit physically disposed on the first side of the non-volatile memory cells; and (iii) a third access circuit physically disposed on a second side of the non-volatile memory cells. The method includes providing a voltage to the non-volatile memory cells. The method includes conducting a first current flowing through a first conduction path that extends from the voltage, through the first access circuit, the non-volatile memory cells, the second access circuit, and to ground. The method includes conducting a second current flowing through a second conduction path that extends from the programming voltage, through the first access circuit, the non-volatile memory cells, the third access circuit, and to ground. As used herein, the terms "about" and "approximately" generally indicate a value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" can indicate a value of a given quantity that varies within, for example, 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value). The foregoing has outlined features of several embodiments such that those skilled in the art may better understand various aspects of an embodiment of the present disclosure. Those skilled in the art should appreciate that they can readily use an embodiment of the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of an embodiment of the present disclosure, and various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of an embodiment of the present disclosure. 100, 300, 400, 500, 600, 700, 800, 900, 1000, 1100: Memory device 102: Memory array 103, 103A: Memory cell 104: Column decoder 106: Row decoder 108: I / O circuit 110: Control logic circuit 200: MRAM cell 210: MTJ device 212: Fixed layer 214: Insulating layer 216: Free layer 220: Switching device 230, BL: Bit line 240, WL: Word line 250, SL: Source line 310: Driver circuit 310A, 310B, 320A, 320B, 330A, 330B, 410A, 410B, 420A, 420B, 430A, 430B, 510A, 510B, 520A, 520B, 530A, 530B, 610A, 610B, 620A, 620B, 630A, 630B, 640A, 640B, 1010, 1020: Sub - circuit 312, 314, 313, 412, 414, 416, 422, 424, 426, 512, 514, 516, 522, 524, 526, 612, 614, 616, 622, 624, 626: p - type transistor 320, 630: First pull - down circuit 322, 323, 324, 332, 333, 334, 432, 434, 436, 532, 534, 536, 632, 634, 636, 642, 644, 646: n - type transistor 330, 640: Second pull - down circuit 351, 353, 371, 373, 451, 453, 471, 473, 551, 553, 571, 573, 651, 653, 671, 673: Conduction path 410, 510, 610: First driver circuit 420, 520, 620: Second driver circuit 430, 530: Pull - down circuit 1012, 1014, 1022, 1024: Transistor 1300: Method 1310, 1320, 1330, 1340: Operation C 1 ,C 2,C 3 ,C N : Row MTJ: Magnetic tunnel junction MX1, S1, S1B: Control signal R 1 ,R 2 ,R 3 ,R M : Column VBL: Programmed voltage X, Y: Directions Aspects of an embodiment of the present disclosure may be best understood when reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased. FIG. 1 illustrates a block diagram of a memory device according to some embodiments. FIG. 2 illustrates a schematic diagram of a memory cell of the memory device according to some embodiments. FIG. 3 illustrates an example schematic diagram of a portion of the memory device of FIG. 1, the memory device including a plurality of access circuits physically disposed on opposite sides of a memory array. FIG. 4 illustrates another example schematic diagram of a portion of the memory device of FIG. 1, the memory device including a plurality of access circuits physically disposed on opposite sides of a memory array. FIG. 5 illustrates yet another example schematic diagram of a portion of the memory device of FIG. 1, the memory device including a plurality of access circuits physically disposed on opposite sides of a memory array. FIG. 6 illustrates yet another example schematic diagram of a portion of the memory device of FIG. 1, the memory device including a plurality of access circuits physically disposed on opposite sides of a memory array. FIG. 7 illustrates yet another example schematic diagram of a portion of the memory device of FIG. 1, the memory device including a plurality of access circuits physically disposed on opposite sides of a memory array. FIG. 8 illustrates yet another example schematic diagram of a portion of the memory device of FIG. 1, the memory device including a plurality of access circuits physically disposed on opposite sides of a memory array. FIG. 9 illustrates yet another example schematic diagram of a portion of the memory device of FIG. 1, the memory device including a plurality of access circuits physically disposed on opposite sides of a memory array. FIG. 10 illustrates yet another example schematic diagram of a portion of the memory device of FIG. 1, the memory device including a plurality of access circuits physically disposed on opposite sides of a memory array. FIG. 11 illustrates yet another example schematic diagram of a portion of the memory device of FIG. 1, the memory device including a plurality of access circuits physically disposed on opposite sides of a memory array. FIG. 12 illustrates an example waveform of a plurality of control signals for operating the memory device of FIG. 1, the memory device including a plurality of access circuits physically disposed on opposite sides of a memory array. FIG. 13 illustrates an example flowchart of a method for operating a memory device, the memory device including a plurality of access circuits physically disposed on opposite sides of a memory array. Domestic registration information (please note in the order of registration institution, date, number) None Foreign registration information (please note in the order of registration country, institution, date, number) None 102: Memory array 103A: Memory cell 300: Memory device 310: Driver circuit 310A, 310B, 320A, 320B, 330A, 330B: Sub-circuits 312, 313, 314: p-type transistors 320: First pull-down circuit 322, 323, 324, 332, 333, 334: n-type transistors 330: Second pull-down circuit 351, 353, 371, 373: Conductive paths BL: Bit line MTJ: Magnetic tunnel junction SL: Source line VBL: Programming voltage WL: Word line X, Y: Directions

Claims

1. A memory circuit, comprising: A memory array includes a plurality of non-volatile memory cells, wherein the non-volatile memory cells are arranged along a plurality of access lines extending in a lateral direction; a first access circuit is physically disposed on a first side of the memory array in the lateral direction; and a second access circuit is physically disposed on a second side of the memory array in the lateral direction, the second side being opposite to the first side; wherein when one of the non-volatile memory cells is simultaneously programmed by a first current and a second current, the first current and the second current flow through a first path and a second path, respectively, and wherein the first path includes at least a portion of the first side, and the second path includes at least a portion of the second side.

2. The memory circuit as claimed in claim 1, wherein each of the non-volatile memory cells includes a magnetic tunneling junction component.

3. The memory circuit as claimed in claim 1, wherein the first access circuit includes a first sub-circuit and a second sub-circuit, and the second access circuit includes a third sub-circuit, wherein the first sub-circuit and the second sub-circuit are operatively forming part of the first path, and the first sub-circuit and the third sub-circuit are operatively forming part of the second path.

4. The memory circuit as claimed in claim 1, wherein the first access circuit includes a first sub-circuit, and the second access circuit includes a second sub-circuit and a third sub-circuit, wherein the first sub-circuit and the third sub-circuit are operatively forming part of the first path, and the second sub-circuit and the third sub-circuit are operatively forming part of the second path.

5. The memory circuit as claimed in claim 1, wherein the first access circuit includes a first sub-circuit and a second sub-circuit, and the second access circuit includes a third sub-circuit, wherein the first sub-circuit and the second sub-circuit are operatively forming part of the first path, and the third sub-circuit and the second sub-circuit are operatively forming part of the second path.

6. The memory circuit as claimed in claim 1, wherein the first access circuit includes a first sub-circuit and a second sub-circuit, and the second access circuit includes a third sub-circuit and a fourth sub-circuit, wherein the first sub-circuit and the second sub-circuit are operatively forming part of the first path, and the third sub-circuit and the fourth sub-circuit are operatively forming part of the second path.

7. The memory circuit as claimed in claim 1, wherein the first path and the second path both extend from the first side or the second side, both extend through a corresponding one of the non-volatile memory cells, and then separate toward the first side and the second side, respectively.

8. The memory circuit as claimed in claim 1, wherein the first current and the second current have the same direction, and the direction is used to determine a logic state programmed into a corresponding one of the non-volatile memory cells.

9. A memory circuit, comprising: A plurality of non-volatile memory cells are disposed above a plurality of bit lines extending in a lateral direction; a first access circuit is physically disposed on a first side of the non-volatile memory cells in the lateral direction, wherein the first access circuit includes a first sub-circuit and a second sub-circuit; and a second access circuit is physically disposed on a second side of the non-volatile memory cells in the lateral direction, the second side being opposite to the first side, wherein the second access circuit includes a third sub-circuit and a fourth sub-circuit. The first sub-circuit is used to couple a programmed voltage to a corresponding one of the non-volatile memory cells, and when a first logic state is programmed to the corresponding non-volatile memory cell, the second sub-circuit and the fourth sub-circuit are each used to provide a corresponding one of a plurality of conduction paths from the programmed voltage to ground; and the second sub-circuit is used to couple the programmed voltage to the corresponding non-volatile memory cell, and when a second logic state is programmed to the corresponding non-volatile memory cell, the first sub-circuit and the third sub-circuit are each used to provide a corresponding one of the conduction paths from the programmed voltage to ground.

10. A method for operating a memory circuit, comprising the steps of: programming a non-volatile memory cell, comprising: activating (i) a first access circuit physically disposed on a first side of the non-volatile memory cell; (ii) a second access circuit physically disposed on the first side of the non-volatile memory cell; and (iii) a third access circuit physically disposed on a second side of the non-volatile memory cell; providing a programming voltage to the non-volatile memory cell; and simultaneously conducting a first current flowing through a first conduction path and a second current flowing through a second conduction path, the first conduction path extending from the programming voltage, passing through the first access circuit, the non-volatile memory cell, and the second access circuit and reaching ground, and the second conduction path extending from the programming voltage, passing through the first access circuit, the non-volatile memory cell, and the third access circuit and reaching ground.

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