Chip assembly and electronic device

Abstract

A chip assembly includes a first chip and a first thermally conductive element. The first chip includes a first chip surface having a first chip area. The first thermally conductive element includes a first heat inflow surface having a first thermally conductive area, wherein the first heat inflow surface is connected to the first chip surface, and the area ratio of the first thermally conductive area to the first chip area is less than 0.85. This satisfies heat dissipation and electrical requirements.

Description

[Technical Field]

[0001] This disclosure relates to a chip assembly and an electronic device, and more particularly to a chip assembly and electronic device including a thermally conductive element. [Previous Technology]

[0002] With the development trend of current technology, the number of chips in electronic devices is increasing and the component density is increasing. As a result, the heat dissipation and electrical design of electronic devices are facing severe challenges. For example, the radio frequency module in electronic devices needs to meet the heat dissipation requirements while avoiding the problem of de-sense.

[0003] Based on the above, in today's chip component and electronic device market, there is an urgent need to develop a chip component and electronic device that can simultaneously meet heat dissipation requirements, electrical specifications, and have low cost advantages. [Summary of the Invention]

[0004] This disclosure provides a chip assembly and an electronic device. The chip assembly includes a first chip and a first heat-conducting element, the first heat-conducting element being connected to the first chip along a stacking direction. By having the area of ​​the first heat-conducting element in a specific area ratio to the area of ​​the first chip, or by having the projected area of ​​the first heat-conducting element in a specific projection ratio to the projected area of ​​the first chip when viewed along the stacking direction, the heat dissipation and electrical requirements of the chip assembly and its first chip are simultaneously met.

[0005] According to one embodiment of the present disclosure, a wafer assembly is provided, comprising a first wafer and a first thermal conductive element. The first wafer includes a first wafer surface having a first wafer area. The first thermal conductive element includes a first heat inflow surface having a first thermally conductive area, wherein the first heat inflow surface is connected to the first wafer surface, and the area ratio of the first thermally conductive area to the first wafer area is less than 0.85.

[0006] According to another embodiment of the present disclosure, a wafer assembly is provided, having a stacking direction and including a first wafer and a first thermal conductive element. The first thermal conductive element is connected to the first wafer along the stacking direction. Viewed along the stacking direction, the projected area of ​​the first thermal conductive element does not exceed the projected area of ​​the first wafer, and a first projection ratio of the projected area of ​​the first thermal conductive element to the projected area of ​​the first wafer is less than 0.85.

[0007] In another embodiment of the present disclosure, an electronic device is provided, comprising the chip assembly of the foregoing embodiments.

Implementation Method

[0009] Several embodiments of this disclosure will now be described with reference to the drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the disclosure. That is, these practical details are not essential in the embodiments of this disclosure. Furthermore, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simple schematic manner; and repeated elements may be denoted by the same number.

[0010] Furthermore, the terms "first" and "second" are used only to describe different components and do not limit the components themselves. Therefore, the first component can also be referred to as the second component. Moreover, the combination of components in this article is not a combination that is generally known, conventional, or familiar in this field. Whether the components themselves are familiar cannot be used to determine whether their combination relationship is easily completed by someone with ordinary knowledge in the technical field.

[0011] Figure 1A illustrates a schematic diagram of a chip assembly 100 according to the first embodiment of this disclosure, which is also a front view viewed along the second direction y1. Referring to Figure 1A, the chip assembly 100 includes a first chip 111 and a first heat-conducting element 114. The first chip 111 includes a first chip surface 112, whose normal is parallel to the stacking direction z1 and has a first chip area. The first heat-conducting element 114 includes a first heat inflow surface 115, whose normal is parallel to the stacking direction z1 and has a first heat-conducting area. The first heat inflow surface 115 is directly connected to the first chip surface 112, and the area ratio of the first heat-conducting area to the first chip area is less than 0.85. This satisfies both the heat dissipation and electrical requirements of the chip assembly 100 and its first chip 111. Furthermore, according to this disclosure, "chip" can be "chipset" and can be a packaged product including at least one integrated circuit, and according to this disclosure, "chip assembly" can be a module or part of a module including at least one of the aforementioned chips.

[0012] Figure 1B illustrates a schematic diagram of the first projection ratio of the chip assembly 100 in Figure 1A, and is also a top view of the first chip 111 and the first heat-conducting element 114 viewed along the stacking direction z1. Further, referring to Figures 1A and 1B, the chip assembly 100 has a stacking direction z1 and includes the first chip 111 and the first heat-conducting element 114, with the first heat-conducting element 114 directly connected to the first chip 111 along the stacking direction z1. Viewed along the stacking direction z1, the projected area of ​​the first heat-conducting element 114 does not exceed the projected area of ​​the first chip 111, and the first projection ratio of the projected area of ​​the first heat-conducting element 114 to the projected area of ​​the first chip 111 is less than 0.85. This balances the heat dissipation and electrical requirements of the chip assembly 100 and its first chip 111. Specifically, the first heat-conducting element 114 is aligned with the first wafer 111 in the positive direction of the first direction x1 (i.e., the right side of the first wafer 111 in Figure 1B). The first projection ratio is defined as 0 on the right side of the first wafer 111 in Figure 1B and extends or covers the left side of the first wafer 111 in Figure 1B to a value less than 0.85. Furthermore, the area ratio of the first heat-conducting area of ​​the wafer assembly 100 in the first embodiment to the area of ​​the first wafer is less than 0.85, as shown in Figure 1B.

[0013] Figures 1C, 1D, and 1E illustrate schematic diagrams of the first projection ratio of a chip assembly according to other embodiments of this disclosure. Referring to Figure 1C, the first heat conductor 114c is aligned with the left side of the first chip 111 in Figure 1C, and the first projection ratio is defined as 0 on the left side of the first chip 111 in Figure 1C, extending to the right side but not reaching 0.85. Referring to Figure 1D, the first heat conductor 114d is aligned with the upper side of the first chip 111 in Figure 1D, and the first projection ratio is defined as 0 on the upper side of the first chip 111 in Figure 1D, extending to the lower side but not reaching 0.85. Referring to Figure 1E, the first heat conductor 114e is aligned with the lower side of the first chip 111 in Figure 1E, and the first projection ratio is defined as 0 on the lower side of the first chip 111 in Figure 1E, extending to the upper side but not reaching 0.85. Furthermore, it should be understood that the first wafer, the first heat-conducting element, the second wafer, and the second heat-conducting element of the wafer assembly according to this disclosure are not limited to square or rectangular shapes, and the specific implementation of their spacing, dimensional relationship, alignment, and first projection ratio is not limited to Figures 1B to 1E.

[0014] Specifically, referring to Figures 1A and 1B, the area ratio of the first heat-conducting area to the area of ​​the first wafer can be greater than 0.5 and less than 0.85. Viewed along the stacking direction z1, the first projection ratio of the projected area of ​​the first heat-conducting element 114 to the projected area of ​​the first wafer 111 can be greater than 0.5 and less than 0.85. This helps to further suppress crosstalk between the first wafer 111 and adjacent wafers (e.g., the second wafer 131). Furthermore, the aforementioned area ratio can be greater than 0.6 and less than 0.85, and the aforementioned first projection ratio can be greater than 0.6 and less than 0.85. Additionally, the aforementioned area ratio can be greater than 0.7 and less than 0.8, and the aforementioned first projection ratio can be greater than 0.7 and less than 0.8.

[0015] The first heat-conducting element 114 may further include a first heat outlet surface 116, which is disposed opposite to the first heat inflow surface 115. The chip assembly 100 may further include a first absorbing material 118, which is an electromagnetic wave absorber (EMI absorber), and the first heat outlet surface 116 is directly connected to the first absorbing material 118. In this way, the arrangement of the first absorbing material 118 helps to absorb interference signals from adjacent chips and assists in heat dissipation, and can thus reduce the thickness t4 and amount of the first heat-conducting element 114, thereby achieving a design that balances heat dissipation, electrical performance and low cost.

[0016] The thermal conductivity of the first thermally conductive element 114 can be equal to or greater than 0.5 W / mK, and the insertion loss (Insertion Loss, Transmission Loss, S21 parameter) of the first absorbing material 118 can be less than -10 dB. This improves the heat dissipation and electrical characteristics of the first chip 111. Specifically, the first thermally conductive element 114 can be a thermal interface material (TIM), such as a thermal pad, thermal putty, or thermal grease, and its thermal conductivity can be equal to or greater than 5 W / mK. The first absorbing material 118 can be applied or sprayed; its insertion loss for electromagnetic waves at 2.4 GHz can be less than -10 dB, and its insertion loss for electromagnetic waves at 5.0 GHz can be less than -15 dB.

[0017] The chip assembly 100 may further include a circuit board 150, wherein the circuit board 150, the first chip 111, and the first heat-conducting component 114 are sequentially connected along the stacking direction z1. Furthermore, the first chip 111 may be a radio frequency (RF) chip, or a RF chipset. This helps the first chip 111 meet heat dissipation requirements and solve the problem of de-sense degradation. For example, the first chip 111 may be a WiSoC (Wi-Fi System-on-a-Chip), and this disclosure is not limited thereto.

[0018] The chip assembly 100 may further include a shielding cover 170, with the first heat outlet surface 116 indirectly connected to the shielding cover 170. The shielding cover 170 is an electromagnetic shielding cover and includes a top surface region 174 and a plurality of side surface regions 176. The top surface region 174, the side surface regions 176, and the circuit board 150 are connected to form a closed shielding space 178. The first chip 111, the first heat-conducting element 114, and the first absorbing material 118 are disposed in the shielding space 178. The circuit board 150, the first chip 111, the first heat-conducting element 114, and the shielding cover 170 are sequentially connected along the stacking direction z1. Furthermore, the distance d7 between the shielding cover 170 and the circuit board 150 may be equal to or less than 4 mm, and the thickness t4 of the first heat-conducting element 114 may be less than 1 mm. In this way, the first heat-conducting element 114, the first absorbing material 118, and the shielding cover 170 form an effective heat conduction path for the first chip 111 and can reduce electromagnetic interference.

[0019] The chip assembly 100 may further include a fourth heat-conducting element 124. Specifically, the circuit board 150, the first chip 111, the first heat-conducting element 114, the first absorbing material 118, the shielding cover 170, the fourth heat-conducting element 124, and the heat sink 180 are sequentially connected along the stacking direction z1, wherein the heat sink 180 may be a finned heat sink, and the present disclosure is not limited thereto. In this way, the heat conduction path is extended outside the limited shielding space 178, thereby enhancing heat dissipation.

[0020] The chip assembly 100 may further include a second chip 131 and a second heat-conducting element 134. The second chip 131 is disposed separately from the first chip 111 along the vertical direction of the stacking direction z1. The circuit board 150, the second chip 131, the second heat-conducting element 134, and the shield 170 are sequentially connected along the stacking direction z1. This helps to design for the individual needs of the first chip 111 and the second chip 131, thereby improving the heat dissipation and electrical characteristics of the chip assembly 100. Furthermore, the second chip 131 may be a memory, such as double data rate synchronous dynamic random access memory (DDR SDRAM), and this disclosure is not limited thereto. In addition, when viewed along the stacking direction z1, the second projection ratio of the projected area of ​​the second heat-conducting element 134 to the projected area of ​​the second chip 131 may be between 0.5 and 1, and the second projection ratio in the first embodiment is specifically 1, as shown in Figure 1B, where the projected area of ​​the second heat-conducting element 134 overlaps with the projected area of ​​the second chip 131.

[0021] Circuit board 150, first chip 111, first heat-conducting component 114, first absorbing material 118, shielding cover 170, fourth heat-conducting component 124, and heat sink 180 are sequentially connected along the stacking direction z1. Circuit board 150, second chip 131, second heat-conducting component 134, first absorbing material 118, shielding cover 170, heat-conducting component 144, and heat sink 180 are sequentially connected along the stacking direction z1. The first chip 111 and the second chip 131 are both indirectly connected to the first absorbing material 118. This reduces process complexity.

[0022] The first heat-conducting element 114 can approach or even align with the side of the first wafer 111 that is away from the second wafer 131. This helps to reduce interference between the first wafer 111 and the second wafer 131. Specifically, the second wafer 131 is disposed in the negative direction of the first direction x1 of the first wafer 111, and the first heat-conducting element 114 is aligned with the first wafer 111 in the positive direction of the first direction x1 (as shown in Figures 1A and 1B), wherein the first direction x1, the second direction y1, and the stacking direction z1 are perpendicular to each other.

[0023] When viewed along the stacking direction z1, the projected area of ​​the first heat-conducting component 114 along the first direction x1 can be aligned with the projected area of ​​the first wafer 111 along the first direction x1. This reduces interference and design complexity. Furthermore, when viewed along the stacking direction z1, the projected area of ​​the first heat-conducting component 114 along the second direction y1 can be aligned with or not aligned with the projected area of ​​the first wafer 111 along the second direction y1.

[0024] Figure 2 illustrates a schematic diagram of a wafer assembly 200 according to the second embodiment of this disclosure, which is also a front view viewed along the second direction y1. Referring to Figure 2, the wafer assembly 200 has a stacking direction z1 and includes a first wafer 111 and a first heat-conducting element 114. The first wafer 111 includes a first wafer surface 112, whose normal is parallel to the stacking direction z1 and has a first wafer area. The first heat-conducting element 114 includes a first heat inflow surface 115, whose normal is parallel to the stacking direction z1 and has a first heat-conducting area. The first heat inflow surface 115 is directly connected to the first wafer surface 112 along the stacking direction z1, and the area ratio of the first heat-conducting area to the first wafer area is less than 0.85. Viewed along the stacking direction z1, the projected area of ​​the first heat-conducting element 114 does not exceed the projected area of ​​the first wafer 111, and the first projection ratio of the projected area of ​​the first heat-conducting element 114 to the projected area of ​​the first wafer 111 is less than 0.85.

[0025] In detail, in the second embodiment, the circuit board 150, the first chip 111, the first heat-conducting element 114, the first absorbing material 218, the shielding cover 170, the fourth heat-conducting element 124, and the heat sink 180 are sequentially connected along the stacking direction z1. The circuit board 150, the second chip 131, the second heat-conducting element 134, the second absorbing material 238, the shielding cover 170, the heat-conducting element 144, and the heat sink 180 are sequentially connected along the stacking direction z1. The first chip 111 and the second chip 131 are indirectly connected to the first absorbing material 218 and the second absorbing material 238, respectively. According to the embodiments of this disclosure, the first chip and the second chip may both be connected to the first absorbing material, or the first chip and the second chip may be connected to the first absorbing material and the second absorbing material, respectively.

[0026] The volume ratio of the first heat-conducting element 114 to the volume of the first absorbing material 218 can be greater than 1 and less than 1.7, wherein the volume of the first heat-conducting element 114 is the thickness t4 multiplied by the area of ​​the first heat outlet surface 116, and the volume of the first absorbing material 218 is the thickness t8 multiplied by the area of ​​the first absorbing surface 219. This achieves more efficient heat dissipation characteristics. Furthermore, viewed along the stacking direction z1, the first absorbing projection ratio of the projected area of ​​the first absorbing material 218 to the projected area of ​​the first wafer 111 can be between 0.5 and 1.5, and in the second embodiment, the first absorbing projection ratio is specifically 1.

[0027] Figure 3 illustrates a schematic diagram of a wafer assembly 300 according to a third embodiment of this disclosure, which is also a front view viewed along the second direction y1. Referring to Figure 3, the wafer assembly 300 has a stacking direction z1 and includes a first wafer 311 and a first heat-conducting element 314. The first wafer 311 includes a first wafer surface 312, whose normal is parallel to the stacking direction z1 and has a first wafer area. The first heat-conducting element 314 includes a first heat inflow surface 315, whose normal is parallel to the stacking direction z1 and has a first heat-conducting area. The first heat inflow surface 315 is directly connected to the first wafer surface 312 along the stacking direction z1, and the area ratio of the first heat-conducting area to the first wafer area is less than 0.85. Viewed along the stacking direction z1, the projected area of ​​the first heat-conducting element 314 does not exceed the projected area of ​​the first wafer 311, and the first projection ratio of the projected area of ​​the first heat-conducting element 314 to the projected area of ​​the first wafer 311 is less than 0.85.

[0028] In detail, the chip assembly 300 further includes a first absorbing material 318, wherein the circuit board 350, the first chip 311, the first heat-conducting component 314, the shielding cover 370 and the first absorbing material 318 are sequentially connected along the stacking direction z1. This increases design flexibility while ensuring heat dissipation and electrical characteristics.

[0029] In the third embodiment, the first heat-conducting element 314 further includes a first heat outlet surface 316, which is disposed opposite to the first heat inflow surface 315, and the first heat outlet surface 316 is indirectly connected to the first absorbing material 318. The circuit board 350, the first chip 311, the first heat-conducting element 314, the shielding cover 370, the first absorbing material 318, the fourth heat-conducting element 324 and the heat sink 380 are sequentially connected along the stacking direction z1. The circuit board 350, the second chip 331, the second heat-conducting element 334, the shielding cover 370, the second absorbing material 338, the heat-conducting element 344 and the heat sink 380 are sequentially connected along the stacking direction z1, wherein the first chip 311 and the second chip 331 are indirectly connected to the first absorbing material 318 and the second absorbing material 338, respectively. The volume ratio of the first heat-conducting element 314 to the volume of the first absorbing material 318 is greater than 1 and less than 1.7.

[0030] Figure 4 illustrates a schematic diagram of a wafer assembly 400 according to the fourth embodiment of this disclosure, which is also a front view viewed along the second direction y1. Referring to Figure 4, the wafer assembly 400 includes a first wafer 411 and a first heat-conducting element 414. The first wafer 411 includes a first wafer surface 412, the normal of which is parallel to the stacking direction z1 and has a first wafer area. The first heat-conducting element 414 includes a first heat inflow surface 415, the normal of which is parallel to the stacking direction z1 and has a first heat-conducting area. The first heat inflow surface 415 is indirectly connected to the first wafer surface 412, and the area ratio of the first heat-conducting area to the first wafer area is less than 0.85.

[0031] Furthermore, the chip assembly 400 has a stacking direction z1 and includes a first chip 411 and a first heat-conducting element 414, the first heat-conducting element 414 being indirectly connected to the first chip 411 along the stacking direction z1. When viewed along the stacking direction z1, the projected area of ​​the first heat-conducting element 414 does not exceed the projected area of ​​the first chip 411, and the first projection ratio of the projected area of ​​the first heat-conducting element 414 to the projected area of ​​the first chip 411 is less than 0.85.

[0032] In detail, the chip assembly 400 further includes a first absorbing material 418, which is directly connected between the first heat inflow surface 415 and the first chip surface 412. This increases design flexibility while ensuring heat dissipation and electrical characteristics.

[0033] In the fourth embodiment, the first heat-conducting element 414 further includes a first heat outlet surface 416, which is disposed opposite to the first heat inflow surface 415, and the first heat outlet surface 416 is indirectly connected to the first absorbing material 418. The circuit board 450, the first chip 411, the first absorbing material 418, the first heat-conducting element 414, the shield 470, the fourth heat-conducting element 424 and the heat sink 480 are sequentially connected along the stacking direction z1. The circuit board 450, the second chip 431, the first absorbing material 418, the second heat-conducting element 434, the shield 470, the heat-conducting element 444 and the heat sink 480 are sequentially connected along the stacking direction z1, wherein the first chip 411 and the second chip 431 are both directly connected to the first absorbing material 418.

[0034] Figure 5 illustrates a schematic diagram of a wafer assembly 500 according to the fifth embodiment of this disclosure, which is also a front view viewed along the second direction y1. Referring to Figure 5, the wafer assembly 500 has a stacking direction z1 and includes a first wafer 511 and a first heat-conducting element 514. The first wafer 511 includes a first wafer surface 512, whose normal is parallel to the stacking direction z1 and has a first wafer area. The first heat-conducting element 514 includes a first heat inflow surface 515, whose normal is parallel to the stacking direction z1 and has a first heat-conducting area. The first heat inflow surface 515 is directly connected to the first wafer surface 512 along the stacking direction z1, and the area ratio of the first heat-conducting area to the first wafer area is less than 0.85. Viewed along the stacking direction z1, the projected area of ​​the first heat-conducting element 514 does not exceed the projected area of ​​the first wafer 511, and the first projection ratio of the projected area of ​​the first heat-conducting element 514 to the projected area of ​​the first wafer 511 is less than 0.85.

[0035] In detail, the first heat-conducting element 514 further includes a first heat outlet surface 516, which is disposed opposite to the first heat inlet surface 515, and the first heat outlet surface 516 is directly connected to the first microwave absorbing material 518.

[0036] The shielding cover 570 is an electromagnetic shielding cover and includes a top surface area 574 and four side surface areas 576. The top surface area 574, the side surface areas 576 and the circuit board 550 are connected to form a closed shielding space 578. The first chip 511, the first heat-conducting component 514, the first wave-absorbing material 518, the second chip 531 and the second heat-conducting component 534 are disposed in the shielding space 578. The top surface area 574 includes a main body portion 573 and a recessed portion 571, wherein the distance between the recessed portion 571 and the circuit board 550 is less than the distance d7 between the main body portion 573 and the circuit board 550.

[0037] In the fifth embodiment, the circuit board 550, the first chip 511, the first heat-conducting element 514, the first absorbing material 518, the recessed portion 571 of the shielding cover 570, the fourth heat-conducting element 524, and the heat sink 580 are sequentially connected along the stacking direction z1. The circuit board 550, the second chip 531, the second heat-conducting element 534, the first absorbing material 518, the main body 573 of the shielding cover 570, the heat-conducting element 544, and the heat sink 580 are sequentially connected along the stacking direction z1, and the thickness t4 of the first heat-conducting element 514 is less than the thickness t5 of the second heat-conducting element 534. Therefore, by reducing the distance between the first chip 511 and the recessed portion 571 of the shielding cover 570, the thickness t4 of the first heat-conducting element 514 can be reduced, thus shortening the heat dissipation path and helping to improve the heat dissipation capacity of the first chip 511.

[0038] Figure 6 illustrates a schematic diagram of a wafer assembly 600 according to a sixth embodiment of this disclosure, which is also a front view viewed along the second direction y1. Referring to Figure 6, the wafer assembly 600 has a stacking direction z1 and includes a first wafer 611 and a first heat-conducting element 614. The first wafer 611 includes a first wafer surface 612, whose normal is parallel to the stacking direction z1 and has a first wafer area. The first heat-conducting element 614 includes a first heat inflow surface 615, whose normal is parallel to the stacking direction z1 and has a first heat-conducting area. The first heat inflow surface 615 is directly connected to the first wafer surface 612 along the stacking direction z1, and the area ratio of the first heat-conducting area to the first wafer area is less than 0.85. Viewed along the stacking direction z1, the projected area of ​​the first heat-conducting element 614 does not exceed the projected area of ​​the first wafer 611, and the first projection ratio of the projected area of ​​the first heat-conducting element 614 to the projected area of ​​the first wafer 611 is less than 0.85.

[0039] In detail, the first heat-conducting element 614 further includes a first heat outlet surface 616, which is disposed opposite to the first heat inlet surface 615, and the first heat outlet surface 616 is directly connected to the first absorbing material 618.

[0040] The chip assembly 600 further includes a third heat conductor 623, wherein the third heat conductor 623, the circuit board 650, the first chip 611, and the first heat conductor 614 are sequentially connected along the stacking direction z1. Thereby, the first chip 611 conducts heat to the third heat conductor 623 through the through-holes on the circuit board 650, which helps to enhance heat dissipation.

[0041] In the sixth embodiment, the heat sink 680, the third heat conductor 623, the circuit board 650, the first chip 611, the first heat conductor 614, the first absorbing material 618 and the shield 670 are connected sequentially along the stacking direction z1. The circuit board 650, the second chip 631, the second heat conductor 634, the first absorbing material 618 and the shield 670 are connected sequentially along the stacking direction z1. The first chip 611 and the second chip 631 are both indirectly connected to the first absorbing material 618.

[0042] For other details regarding the chip components 200, 300, 400, 500, and 600 in the second to sixth embodiments, please refer to the description of the chip component 100 in the first embodiment, which will not be elaborated here.

[0043] Figure 7 illustrates a schematic diagram of an electronic device 700 according to the seventh embodiment of this disclosure. Referring to Figure 7, the electronic device 700 includes a chip assembly according to this disclosure, such as one of the aforementioned chip assemblies 100, 200, 300, 400, 500, and 600. Specifically, the electronic device 700 may be a smartphone, and this disclosure is not limited thereto. Therefore, by improving the heat dissipation and electrical characteristics of the chip assembly 100 in the electronic device 700, the performance and reliability of the electronic device 700 are enhanced.

[0044] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0008] Figure 1A illustrates a schematic diagram of a chip assembly according to a first embodiment of the present disclosure; Figure 1B illustrates a schematic diagram of a first projection ratio of the chip assembly in Figure 1A; Figures 1C, 1D, and 1E illustrate schematic diagrams of a first projection ratio of a chip assembly according to other embodiments of the present disclosure; Figure 2 illustrates a schematic diagram of a chip assembly according to a second embodiment of the present disclosure; Figure 3 illustrates a schematic diagram of a chip assembly according to a third embodiment of the present disclosure; Figure 4 illustrates a schematic diagram of a chip assembly according to a fourth embodiment of the present disclosure; Figure 5 illustrates a schematic diagram of a chip assembly according to a fifth embodiment of the present disclosure; Figure 6 illustrates a schematic diagram of a chip assembly according to a sixth embodiment of the present disclosure; and Figure 7 illustrates a schematic diagram of an electronic device according to a seventh embodiment of the present disclosure.

Claims

1. A chip assembly, comprising: a first chip including a first chip surface having a first chip area; and a first thermal conductive member including a first heat inflow surface and a first heat outflow surface, wherein the first heat outflow surface is disposed opposite to the first heat inflow surface, the first heat inflow surface having a first thermally conductive area, the first heat inflow surface being connected to the first chip surface, and the area ratio of the first thermally conductive area to the first chip area being greater than 0.5 and less than 0.85; and a first absorbing material connected to the first heat outflow surface.

2. The wafer assembly as claimed in claim 1, wherein the volume ratio of the first thermal conductive element to the volume of the first absorbing material is greater than 1 and less than 1.

7.

3. The wafer assembly as claimed in claim 1, wherein the thermal conductivity of the first thermal conductive element is equal to or greater than 0.5 W / mK, and the insertion loss of the first absorbing material is less than -10 dB.

4. The wafer assembly as claimed in claim 1, wherein the wafer assembly has a stacking orientation, and the first thermal conductive element is connected to the first wafer along the stacking orientation; wherein, Viewed along the stacking direction, the projected area of ​​the first heat-conducting component does not exceed the projected area of ​​the first wafer.

5. The wafer assembly as claimed in claim 4, wherein, when viewed along the stacking direction, the projected area of ​​the first thermal conductive element along a first direction is aligned with the projected area of ​​the first wafer along the first direction, the first direction and the stacking direction being perpendicular to each other.

6. The chip assembly as claimed in claim 4 further comprises: a circuit board, wherein the circuit board, the first chip and the first thermal conductive element are sequentially connected along the stacking direction, and the first chip is a radio frequency chip.

7. The chip assembly as claimed in claim 6 further includes: a third thermal conductive element, wherein the third thermal conductive element, the circuit board, the first chip, and the first thermal conductive element are sequentially connected along the stacking direction.

8. The chip assembly as claimed in claim 6 further comprises: a shield, wherein the circuit board, the first chip, the first thermal conductive element and the shield are sequentially connected along the stacking direction, and the distance between the shield and the circuit board is equal to or less than 4 mm.

9. The chip assembly as claimed in claim 8, wherein the circuit board, the first chip, the first thermal conductive element, the shielding cover, and the first absorbing material are sequentially connected along the stacking direction.

10. The chip assembly as claimed in claim 8 further includes: a fourth thermal conductive element, wherein the circuit board, the first chip, the first thermal conductive element, the shield and the fourth thermal conductive element are sequentially connected along the stacking direction.

11. The chip assembly as claimed in claim 8 further comprises: a second chip; and a second thermal conductive element, wherein the circuit board, the second chip, the second thermal conductive element and the shield are sequentially connected along the stacking direction.

12. The wafer assembly as claimed in claim 11, wherein the first thermal conductive element is located on the side of the first wafer away from the second wafer.

13. The chip assembly as claimed in claim 11, wherein the circuit board, the second chip, the second thermal conductive element and the first absorbing material are sequentially connected along the stacking direction.

14. The wafer assembly as claimed in claim 11, wherein the shielding includes a main body and a recess, the circuit board, the first wafer, the first thermal conductive element and the recess are sequentially connected along the stacking direction, the circuit board, the second wafer, the second thermal conductive element and the main body are sequentially connected along the stacking direction, and the distance between the recess and the circuit board is less than the distance between the main body and the circuit board, and the thickness of the first thermal conductive element is less than the thickness of the second thermal conductive element.

15. The chip assembly as claimed in claim 1, wherein the first chip is an radio frequency chip.

16. The chip assembly as described in claim 15, wherein the first chip is a Wi-Fi system monolith.

17. A chip assembly comprising: a first chip including a first chip surface having a first chip area; a first thermal conductive member including a first heat inflow surface having a first thermally conductive area, wherein the first heat inflow surface is connected to the first chip surface, and the area ratio of the first thermally conductive area to the first chip area is greater than 0.5 and less than 0.85; and a first absorbing material connected between the first heat inflow surface and the first chip surface.

18. The chip assembly as claimed in claim 17, wherein the first thermal conductive element further includes a first heat outlet surface disposed opposite to the first heat outlet surface, and the chip assembly further includes: a shield, wherein the first heat outlet surface is connected to the shield.

19. An electronic device comprising: a chip assembly as described in either claim 1 or claim 17.

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