Directional selective fill of silicon oxide materials

Abstract

Exemplary processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. The substrate may define features. The method may include forming a plasma outflow of the silicon-containing precursor. The method may include depositing a silicon-containing material on the substrate. The method may include providing an oxygen-containing precursor to the processing region, forming a plasma outflow of the oxygen-containing precursor, and contacting the silicon-containing material with the plasma outflow of the oxygen-containing precursor to form a silicon- and oxygen-containing material. The method may include providing a fluorine-containing precursor to the processing region, forming a plasma outflow of the fluorine-containing precursor, and etching the silicon- and oxygen-containing material from the top, sidewalls, or both of the feature using the plasma outflow of the fluorine-containing precursor.

Description

Technical Field

[0001] This application claims the benefit and priority of U.S. Patent Application No. 18 / 221,240, filed on July 12, 2023, titled "DIRECTIONAL SELECTIVE FILL OF SILICON OXIDE MATERIALS", which is hereby incorporated by reference in its entirety.

[0002] This technology relates to semiconductor processing. More particularly, this technology relates to materials for deposition, oxidation, and etching in gap fill processes. Background Art

[0003] Integrated circuits have become possible through processes that create complex patterned material layers on a substrate surface. Creating patterned materials on a substrate requires controlled methods for forming and removing the exposed materials. As component sizes continue to shrink, material formation can affect subsequent operations. For example, in gap fill operations, materials can be formed or deposited to fill trenches or other features formed in a semiconductor substrate. Since features can be characterized by higher aspect ratios and smaller critical dimensions, these fill operations can be challenging. For example, since deposition can occur on top of and along the sidewalls of the features, continued deposition can pinch off the features and create voids within the features. This can affect component performance and subsequent processing operations.

[0004] Accordingly, there is a need for improved systems and methods that can be used to produce high-quality components and structures. These and other needs are addressed by this technology. Summary of the Invention

[0005] Exemplary processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be accommodated in the processing region. The substrate may define features. The processing region may be at least partially defined between a panel and a substrate support on which the substrate is disposed. The methods may include forming a plasma effluent of the silicon-containing precursor. The methods may include depositing a silicon-containing material on the substrate. The methods may include providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include forming a plasma effluent of the oxygen-containing precursor. The methods may include contacting the silicon-containing material with the plasma effluent of the oxygen-containing precursor to oxidize the silicon-containing material. The contact may form a silicon- and oxygen-containing material. The methods may include providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber. The methods may include forming a plasma effluent of the fluorine-containing precursor. The methods may include contacting the silicon- and oxygen-containing material with the plasma effluent of the fluorine-containing precursor. The contact may etch the silicon- and oxygen-containing material from the top, sidewalls, or both of the features.

[0006] In an embodiment, the features may be characterized by an aspect ratio greater than or about 1:1. The features may be characterized by a width across the feature less than or about 100 nm. The oxygen-containing precursor may be or include diatomic oxygen (O2) or nitrous oxide (N2O). The methods may include applying a bias power from a self-bias power supply to the substrate support. During deposition and etching, the plasma power supply may operate in a continuous wave mode, while the bias power supply may operate in a pulsed mode. The plasma effluent of the silicon-containing precursor may be formed from the plasma power supply at a first power level. The plasma effluent of the fluorine-containing precursor may be formed from the plasma power supply at a second power level greater than the first power level. The fluorine-containing precursor may be or include nitrogen trifluoride (NF3). The etching may remove the silicon- and oxygen-containing material at a rate less than or about 10 Å / sec. The method may repeat a second cycle. The temperature of the substrate may be maintained at a temperature less than or about 450 °C. The pressure within the semiconductor processing chamber may be maintained at a pressure greater than or about 1 Torr.

[0007] Some embodiments of the present technology may encompass semiconductor processing methods. The methods may include i) forming a plasma effluent of a silicon-containing precursor. The methods may include ii) depositing a silicon-containing material on a substrate. The substrate may define features. The substrate may be disposed on a substrate support. The methods may include iii) forming a plasma effluent of an oxygen-containing precursor. The methods may include iv) contacting the silicon-containing material with the plasma effluent of the oxygen-containing precursor to form a silicon- and oxygen-containing material. The methods may include v) forming a plasma effluent of a fluorine-containing precursor. The methods may include vi) contacting the silicon- and oxygen-containing material with the plasma effluent of the fluorine-containing precursor. The contact may etch the silicon- and oxygen-containing material from the sidewalls of the features. The methods may include repeating operations i) to vi) to iteratively fill the feature.

[0008] In an embodiment, the plasma power during operation iii) may be maintained at greater than or about 600 W. The plasma power may be pulsed during operations i) to iv). Etching may completely remove the silicon- and oxygen-containing material from the sidewalls of the feature above the base fill of the feature. The methods may include applying bias power from a bias power source during a semiconductor processing method. The bias power source may operate at a plasma power of less than or about 750 W. The temperature of the substrate may be maintained at a temperature of less than or about 450 °C.

[0009] Some embodiments of the present technology may encompass semiconductor processing methods. The methods may include providing a silicon precursor to a processing region of a semiconductor processing chamber. A substrate may be accommodated in the processing region. The substrate may define a feature. The processing region may be at least partially defined between a panel and a substrate support on which the substrate is disposed. The methods may include forming a plasma effluent of the silicon precursor. The plasma effluent of the silicon precursor may be formed from a plasma power source at a first power level. The methods may include depositing a silicon-containing material on the substrate. The methods may include providing an oxygen precursor to the processing region of the semiconductor processing chamber. The methods may include forming a plasma effluent of the oxygen precursor. The methods may include contacting the silicon-containing material with the plasma effluent of the oxygen precursor to oxidize the silicon-containing material. The contact may form a silicon- and oxygen-containing material. The methods may include providing a fluorine precursor to the processing region of the semiconductor processing chamber. The methods may include forming a plasma effluent of the fluorine precursor. The plasma effluent of the fluorine precursor may be formed from a plasma power source at a second power level greater than the first power level. The methods may include contacting the silicon- and oxygen-containing material with the plasma effluent of the fluorine precursor. Etching may etch the silicon- and oxygen-containing material from the sidewalls of the feature above the base fill of the feature.

[0010] In an embodiment, the temperature of the substrate may be maintained at a temperature of less than or about 450 °C.

[0011] Such technology may provide many benefits over conventional systems and techniques. For example, by performing sequential deposition, conversion, and etching operations in accordance with embodiments of the present technology, the sidewall coverage may be limited or controlled, which may limit the formation of seams or holes in small features. Additionally, by performing deposition, conversion, and etching operations in accordance with embodiments of the present technology, the processing temperature may be reduced and may be applied to structures with a reduced thermal budget. These and other embodiments, along with their many advantages and features, are described in more detail in conjunction with the following description and the additional figures. Brief Description of the Drawings

[0012] A further understanding of the nature and advantages of the disclosed technology can be realized by reference to the remainder of the specification and the drawings.

[0013] FIG. 1 shows a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technology.

[0014] FIG. 2 shows exemplary operations in a processing method in accordance with some embodiments of the present technology.

[0015] FIGS. 3A to 3C show schematic cross-sectional views of a substrate during processing in accordance with some embodiments of the present technology.

[0016] Several of the figures are included as schematic diagrams. It is to be understood that the figures are for illustrative purposes and are not considered to be to scale unless specifically stated to be so. Additionally, as schematic diagrams, the figures are provided to assist understanding and may not include all aspects or information compared to the actual representation and may include exaggerated material for illustrative purposes.

[0017] In the additional figures, similar components and / or features may have the same reference numerals. Additionally, various components of the same type may be distinguished by adding a letter to the reference numeral to differentiate the similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the letter. Embodiments

[0018] Silicon and oxygen containing materials can be used in semiconductor device manufacturing for many structures and processes. Some examples include using silicon and oxygen containing materials as sacrificial materials. For example, silicon and oxygen containing materials can be used as, but not limited to, dummy gate materials or trench fill materials. In a gap fill operation, some processes can utilize plasma enhanced deposition under process conditions to increase the directionality of deposition, which can allow the deposited material to better fill features on a substrate.

[0019] As feature sizes continue to shrink, plasma enhanced deposition may face challenges with narrow features, which may further feature higher aspect ratios. For example, due to deposition on the sidewalls of the feature, pinch-off in the feature may be more likely to occur, and in small feature sizes, this may further limit the flow-in and deposition into the feature, and may create seams or voids in the feature. Conventional techniques have attempted to address the formation of seams or voids by filling trenches or features with a flowable material. However, in order to convert the flowable material into an oxide material, operations such as steam annealing may be required. In many applications, the steam annealing for curing the flowable material may be far above the thermal budget. The present technology can overcome these limitations by depositing materials via cycles of deposition, conversion, and etching. The deposition can selectively deposit a silicon-containing material, such as amorphous silicon, towards the bottom portion of the trench or feature. The conversion can incorporate oxygen into the material and form a silicon- and oxygen-containing material. To prevent feature blockage or pinch-off that may form voids or seams, the etching can remove material from the sidewalls and / or upper portion of the feature. By repeating these cycles, the feature can be filled with a silicon- and oxygen-containing material without forming voids or seams.

[0020] After describing the general aspects of a chamber according to some embodiments of the present technology in which plasma processing operations as discussed below may be performed, specific methods may be discussed. It should be understood that the present technology is not intended to be limited to the specific membranes, chambers, or processes discussed, as the described techniques can be used to improve multiple film formation processes and can be applicable to various processing chambers and operations.

[0021] FIG. 1 shows a cross-sectional view of an exemplary processing chamber 100 according to some embodiments of the present technology. This figure may illustrate an overview of a system incorporating one or more aspects of the present technology, and / or a system in which one or more deposition or other processing operations may be performed according to embodiments of the present technology. Additional details of chamber 100 or the methods performed may be described further below. According to some embodiments of the present technology, chamber 100 can be used to form a film layer, but it should be understood that these methods can be similarly performed in any chamber in which film formation can occur. Processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within chamber body 102, and a lid assembly 106 coupled to chamber body 102 and surrounding substrate support 104 within a processing space 120. Substrate 103 can be provided to processing space 120 via an opening 126, which can be sealed in a conventional manner using a slit valve or door for processing. During processing, substrate 103 can be disposed on surface 105 of the substrate support. As shown by arrow 145, substrate support 104 can rotate along axis 147, where axis 144 of substrate support 104 can be located at this axis 147. Alternatively, substrate support 104 can be lifted as needed during the deposition process to rotate.

[0022] The plasma profile modulator 111 can be disposed in the processing chamber 100 to control the plasma distribution across the substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 can include a first electrode 108, which can be disposed adjacent to the chamber body 102 and can separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 can be a part of the lid assembly 106 or can be a separate sidewall electrode. The first electrode 108 can be an annular electrode. The first electrode 108 can be a continuous ring around the circumference of the processing chamber 100 surrounding the processing space 120 or, if desired, can be discontinuous at selected locations. The first electrode 108 can also be a perforated electrode (such as a perforated ring or a mesh electrode), or can be a plate electrode (such as a secondary gas distributor).

[0023] One or more insulators 110a, 110b, which can be dielectric materials (such as ceramics or metal oxides), can contact the first electrode 108 and electrically and thermally separate the first electrode 108 from the gas distributor 112 (also referred to as a panel) and from the chamber body 102. The gas distributor 112 can define pores 118 for distributing process precursors into the processing space 120. The gas distributor 112 can be coupled to a first power source 142, such as an RF generator, an RF power supply, a DC power supply, a pulsed DC power supply, a pulsed RF power supply, or any other power supply that can be coupled to the processing chamber. In some embodiments, the first power source 142 can be an RF power supply.

[0024] The gas distributor 112 can be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 can also be formed of conductive and non-conductive components. For example, the body of the gas distributor 112 can be conductive, while the panel of the gas distributor 112 can be non-conductive. The gas distributor 112 can be powered, for example, by the first power source 142 as shown in FIG. 1. Or in some embodiments, the gas distributor 112 can be coupled to ground.

[0025] The first electrode 108 can be coupled to a first tuning circuit 128, which can control the ground path of the processing chamber 100. The first tuning circuit 128 can include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 can be or include a variable capacitor or other circuit elements. The first tuning circuit 128 can be or include one or more inductors 132. The first tuning circuit 128 can be any circuit that can achieve a variable or controllable impedance under the plasma conditions present in the processing space 120 during processing. In some embodiments as depicted in the figures, the first tuning circuit 128 can include a first circuit branch and a second circuit branch coupled in parallel between ground and the first electronic sensor 130. The first circuit branch can include a first inductor 132A. The second circuit branch can include a second inductor 132B coupled in series with the first electronic controller 134. The second inductor 132B can be disposed between the first electronic controller 134 and the node connecting both the first circuit branch and the second circuit branch to the first electronic sensor 130. The first electronic sensor 130 can be a voltage or current sensor and can be coupled to the first electronic controller 134, which can provide a degree of closed-loop control over the plasma conditions within the processing space 120.

[0026] The second electrode 122 can be coupled to the substrate support 104. The second electrode 122 can be embedded within the substrate support 104 or coupled to the surface of the substrate support 104. The second electrode 122 can be a plate, a perforated plate, a grid, a mesh, or any other distributed arrangement of conductive elements. The second electrode 122 can be a tuning electrode and can be coupled to a second tuning circuit 136 via a conduit 146, such as a cable having a selected resistance (such as 50 ohms), which is disposed, for example, in the axis 144 of the substrate support 104. The second tuning circuit 136 can have a second electronic sensor 138 and a second electronic controller 140, and the second electronic controller 140 can be a second variable capacitor. The second electronic sensor 138 can be a voltage or current sensor and can be coupled to the second electronic controller 140 to provide further control over the plasma conditions in the processing space 120.

[0027] A third electrode 124, which can be a bias electrode and / or an electrostatic chuck electrode, can be coupled to the substrate support 104. The third electrode can be coupled to a second power source 150 via a filter 148, and the filter 148 can be an impedance matching circuit. The second power source 150 can be DC power, pulsed DC power, RF bias power, a pulsed RF source, or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 can be RF bias power.

[0028] The lid assembly 106 and the substrate support 104 of FIG. 1 can be used with any processing chamber for plasma or heat treatment. In operation, the processing chamber 100 can provide immediate control of plasma conditions in the processing space 120. The substrate 103 can be placed on the substrate support 104, and process gas can flow through the lid assembly 106 via the inlet 114 according to any desired flow scheme. The gas can leave the processing chamber 100 via the outlet 152. Electric power can be coupled to the gas distributor 112 to establish plasma in the processing space 120. In some embodiments, a third electrode 124 can be used to subject the substrate to an electrical bias.

[0029] When exciting the plasma in the processing space 120, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. The electronic controllers 134, 140 can then be used to adjust the flow properties of the ground paths represented by the two tuning circuits 128 and 136. Setpoints can then be sent to the first tuning circuit 128 and the second tuning circuit 136 to provide independent control of the deposition rate and plasma density uniformity from the center to the edge. In embodiments where the electronic controllers can both be variable capacitors, the electronic sensors can independently adjust the variable capacitors to maximize the deposition rate and minimize thickness non-uniformity.

[0030] Each of the tuning circuits 128, 136 can have a variable impedance, and the corresponding electronic controllers 134, 140 can be used to adjust the variable impedance. In the case where the electronic controllers 134, 140 are variable capacitors, the capacitance range of each of the variable capacitors and the inductance of the first inductor 132A and the second inductor 132B can be selected to provide an impedance range. This range can depend on the frequency and voltage characteristics of the plasma, which can have a minimum value within the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at a minimum or maximum value, the impedance of the first tuning circuit 128 can be high, resulting in a plasma shape with a minimum aerial or lateral coverage on the substrate support. When the capacitance of the first electronic controller 134 approaches the value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma can grow to a maximum value, effectively covering the entire working area of the substrate support 104. When the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape can contract from the chamber wall, and the aerial coverage of the substrate support can decrease. The second electronic controller 140 can have a similar effect, increasing and decreasing the aerial coverage of the plasma on the substrate support as the capacitance of the second electronic controller 140 can change.

[0031] The electronic sensors 130, 138 can be used to tune the corresponding circuits 128, 136 in a closed loop. Depending on the type of sensor used, a set point of current or voltage can be installed in each sensor, and the sensor can be equipped with control software that determines the adjustment to each corresponding electronic controller 134, 140 to minimize the deviation from the set point. Thus, the plasma shape can be selected and dynamically controlled during processing. It should be understood that although the foregoing discussion is based on the electronic controllers 134, 140 (which can be variable capacitors), any electronic component with adjustable characteristics can be used to provide the tuning circuits 128 and 136 with adjustable impedance.

[0032] In some embodiments of the present technology, the processing chamber 100 can be used for processing methods that can include forming or etching materials for semiconductor structures. It should be understood that the described chambers should not be considered restrictive, and any chamber that can be configured to perform the operations as described can be similarly used. FIG. 2 shows exemplary operations in a processing method 200 according to some embodiments of the present technology. The method can be performed in a variety of processing chambers and on one or more hosts or tools, including the above-described processing chamber 100. The method 200 can include a number of optional operations that may or may not be specifically associated with some embodiments of the method according to the present technology. For example, many operations are described to provide a broader scope of structure formation, but are not critical to the technology or can be performed by easily understood alternative methods. The method 200 can describe the operations schematically shown in FIGS. 3A to 3C, which will be described in conjunction with the operations of the method 200. It should be understood that the figures only show partial schematic diagrams, and the substrate can contain any number of additional materials and features with various characteristics and aspects as shown in the figures.

[0033] The method 200 can include additional operations before the listed operations begin. For example, additional processing operations can include forming structures on the substrate, which can include both forming and removing materials. For example, a transistor structure, a memory structure, or any other structure can be formed. The previous processing operations can be performed in the chamber that can execute the method 200, or before transporting the substrate to the semiconductor processing chamber or the chamber that can execute the method 200, the processing can be performed in one or more other processing chambers. In any case, the method 200 can optionally include transporting the semiconductor substrate to the processing area of the semiconductor processing chamber, such as the processing chamber 100 described above, or can include other chambers with components as described above. The substrate can be deposited on a substrate support, which can be a pedestal (such as the substrate support 104), and can reside in the processing area of the chamber, such as the above-described processing space 120.

[0034] The substrate on which several operations have been performed can be substrate 305 of structure 300, which can show a partial view of the substrate on which semiconductor processing can be performed. It should be understood that structure 300 may only show several top layers during processing to illustrate various aspects of the present technology. Substrate 305 can include materials in which one or more features 310 can be formed. Substrate 305 can be any number of types of materials used in semiconductor processing. The substrate material can be or include silicon, germanium, dielectric materials including silicon oxide or silicon nitride, metal materials, or any number of combinations of these materials, which can be substrate 305, or the materials formed in structure 300. Feature 310 can be characterized by any shape or configuration according to the present technology. In some embodiments, the feature can be or include a trench structure or pore formed within substrate 305.

[0035] Although feature 310 can be characterized by any shape or size, in some embodiments, feature 310 can be characterized by a relatively high aspect ratio, or the ratio of the depth of the feature to the width across the feature. For example, in some embodiments, feature 310 can be characterized by an aspect ratio greater than or about 1:1, and can be characterized by an aspect ratio greater than or about 2:1, greater than or about 3:1, greater than or about 5:1, greater than or about 10:1 or greater. Additionally, these features can be characterized by a narrow width or diameter across the feature (including between two sidewalls), such as a size less than or about 100 nm, and can be characterized by a width across the feature less than or about 90 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm, less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 17 nm, less than or about 15 nm, less than or about 12 nm, less than or about 10 nm, less than or about 9 nm, less than or about 8 nm, less than or about 7 nm, less than or about 6 nm, less than or about 5 nm or smaller.

[0036] In some embodiments, method 200 may include optional processing operations, such as preprocessing, which may be performed to prepare the surface of substrate 305 for deposition. Once prepared, method 200 may include providing one or more precursors to a processing region of a semiconductor processing chamber that houses structure 300 at operation 205. The precursors may include one or more silicon-containing precursors, as well as one or more diluents or carrier gases, such as an inert gas or other gas that is transported with the silicon-containing precursor. Silicon-containing precursors that may be used during deposition of silicon-containing material 315 may include, but are not limited to, silane (SiH4), disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H10), pentasilane (Si5H12), or other organosilanes including cyclohexasilane, silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl3), tetraethyl orthosilicate (TEOS), and any other silicon-containing precursor that may be used for silicon-containing film formation. In some embodiments, the silicon-containing material may be nitrogen-free, oxygen-free, and / or carbon-free.

[0037] At operation 210, a deposition plasma effluent may be formed from deposition precursors that include a silicon-containing precursor. The deposition plasma effluent may be formed within the processing region, which may allow the deposition material to deposit on the substrate. For example, in some embodiments, as described above, a capacitively coupled plasma may be formed within the processing region by applying plasma power to the panel or substrate support.

[0038] The power applied during deposition may be a low-power plasma, which may limit dissociation and may maintain the deposition rate of the silicon-containing material that does not clog feature 310. Thus, in some embodiments, the plasma power supply may deliver less than or about 500 W of plasma power to the panel or substrate support, and may deliver less than or about 450 W, less than or about 400 W, less than or about 350 W, less than or about 300 W, less than or about 250 W, less than or about 200 W, less than or about 150 W, less than or about 100 W, less than or about 50 W, or less power. When the plasma power reaching the panel or substrate support is greater than, for example, 500 W, the substrate 305 (such as the sidewalls that define feature 310) may be damaged, or the deposition rate may increase such that feature 310 may clog and pinch off.

[0039] During the deposition operation, an additional power source (bias power source) can be coupled and joined to the substrate support as described above to provide a bias to the plasma generated above the substrate 305. The bias can attract the plasma effluent to the substrate 305, which can increase the deposition at the bottom of the feature 310. The applied bias power can be relatively low to limit damage to the structure. The bias power can be delivered to the panel or the substrate support. The bias plasma power can be maintained at less than or about 1,000 W, and powers less than or about 750 W, less than or about 600 W, less than or about 500 W, less than or about 400 W, or less can be delivered. Additionally, by adjusting the applied source power and bias power, densification of the deposited silicon-containing material 315 can occur during the deposition operation. In an embodiment, both the source power and the bias power can be applied to the substrate support, such as via the second power source 150 as described above.

[0040] At operation 215, the silicon-containing material 315 can be deposited on the substrate from the plasma effluent of the silicon-containing precursor. The silicon-containing material 315 can be or include amorphous silicon. The deposited material can at least partially fill the features on the substrate to provide a bottom-up type of gap fill. As depicted in FIG. 3A, the silicon-containing material 315 can be deposited on the substrate 305, and at the bottom of the feature 310, and above and on the sidewalls of the feature 310 on the substrate 305. Although the amount of the silicon-containing material 315 deposited on the sidewalls may be relatively small or thin, continued formation may cause the feature 310 to be pinched off. If pinched off, seams or holes may form in the material as the gap fill continues. Thus, a series of depositions, conversions, and etchings as further described below can be performed to deposit a seamless silicon-containing material, such as a silicon and oxygen-containing material, in the feature 310.

[0041] During or after operation 215, a certain amount of densification of the silicon-containing material 315 can be performed. The densification can include bombarding the deposited silicon-containing material 315 with one or more diluents or carrier gases, such as an inert gas or other gases transported with the silicon-containing precursor. During densification, the bias power can be activated to densify the silicon-containing material 315 at the bottom of the feature 310 with the diluent or carrier gas. Although the silicon-containing material 315 deposited in the upper portions, such as the top of the feature 310, can also be densified, the silicon-containing material 315 deposited on the sidewalls of the feature 310 can be left undensified. Thus, the densification can selectively process the silicon-containing material 315 perpendicular to the direction in which the diluent or carrier gas is directed to the substrate 305.

[0042] After a certain amount of deposition, an etching operation can be performed that is configured to remove the silicon-containing material 315 from the sidewalls of the feature 310 and / or the upper portion of the feature 310. This operation can be performed in the same chamber as the deposition. In some embodiments, the silicon-containing precursor flow can be paused and the processing region can be purged. After purging, at operation 220, a hydrogen-containing precursor and / or a chlorine-containing precursor can be provided to the processing region of the semiconductor processing chamber. Although any hydrogen-containing precursor and / or chlorine-containing precursor can be used, in some embodiments, diatomic hydrogen (H2), hydrogen chloride (HCl), diatomic chlorine (Cl2), or other hydrogen-containing or chlorine-containing materials usable in semiconductor processing can be used as the hydrogen-containing precursor or chlorine-containing precursor together with one or more additional precursors to generate an etchant plasma. An etchant plasma can be formed at operation 225, which can also be a capacitively coupled plasma formed within the processing region, although inductively coupled plasmas can be similarly applied in some embodiments. The etchant plasma can be formed by applying plasma power to the panel or substrate support, and in some embodiments, no other power sources need to be engaged. However, it is also contemplated that a bias power can be applied to increase the directionality of the etchant plasma.

[0043] In some embodiments, the source plasma power can be less than the plasma power used during deposition. For example, the delivered plasma power can be less than or about 500 W, and can be less than or about 450 W, less than or about 400 W, less than or about 350 W, less than or about 300 W, less than or about 250 W, less than or about 200 W, less than or about 150 W, less than or about 100 W, less than or about 90 W, less than or about 80 W, less than or about 70 W, less than or about 50 W, or less power. By reducing the source plasma power during the formation of the hydrogen-containing etchant plasma, the dissociation of the hydrogen-containing precursor can be controlled, which can slow down the etching of the material. This can prevent the removal of too much material that would slow down the gap filling and can prevent damage to other materials in the structure 300. Additionally, various aspects of the bias power can also be adjusted, which can also limit damage to the underlying structure. For example, the bias power can be maintained at less than or about 1,000 W, and can be less than or about 750 W, less than or about 600 W, less than or about 500 W, less than or about 400 W, or less. Although in some operations the bias power can be higher than the plasma source power, in other operations the bias power can alternatively be maintained below the plasma power.

[0044] In operation 230, the plasma effluent may etch the silicon-containing material 315 and may remove the silicon-containing material 315 from the sidewalls of the feature 310. In an embodiment, densification of the silicon-containing material 315 after or during deposition at operation 215 may result in selective removal of the sidewall material at operation 230. In an embodiment, the plasma effluent may completely remove the silicon-containing material 315 from the sidewalls of the feature 310 above the substrate fill of the silicon-containing material 315. The substrate fill of the silicon-containing material 315 may represent the silicon-containing material 315 deposited at the bottom of the feature 310. Depending on the degree of densification, some of the silicon-containing material 315 may be removed from the bottom or the top of the feature 310.

[0045] In some embodiments of the present technology, a conversion operation configured to convert the silicon-containing material 315 to a silicon and oxygen-containing material may be performed. This operation may be performed in the same chamber as the deposition and / or etching. In some embodiments, the flow of the hydrogen-containing precursor may be paused and the processing region may be purged. After purging, at operation 235, an oxygen-containing precursor may be provided to the processing region of the semiconductor processing chamber. Although any oxygen-containing precursor may be used, in some embodiments, diatomic oxygen (O2), nitrous oxide (N2O), hydrogen peroxide (H2O2), or other oxygen-containing materials useful for semiconductor processing may be used as the oxygen-containing precursor together with one or more additional precursors to generate a conversion plasma. In an embodiment, O2 may provide better distribution and / or result in less sputtering during conversion. Without being bound by any particular theory, compared to N2O, O2 may provide better distribution and / or result in less sputtering during conversion because N2O is a heavier oxidizing gas than O2. The conversion plasma effluent may be formed at operation 240, which may also be a capacitively coupled plasma formed within the processing region, although inductively coupled plasma may be similarly applied in some embodiments. The conversion plasma effluent may be formed by applying plasma power to the panel or substrate support, and in some embodiments, no other power source may be engaged.

[0046] Compared with the power applied during deposition, the converted plasma effluent can be at a higher plasma power from the plasma source, which can oxidize the silicon-containing material 315. Thus, in an embodiment, the plasma source can deliver a plasma power greater than or about 600 W to the panel or substrate support, and can deliver greater than or about 650 W, greater than or about 700 W, greater than or about 750 W, greater than or about 800 W, greater than or about 850 W, greater than or about 950 W, greater than or about 1000 W, greater than or about 1100 W, greater than or about 1200 W, greater than or about 1300 W, greater than or about 1400 W, greater than or about 1500 W, or greater power. When the plasma power applied to the panel or substrate support is less than, for example, 600 W, the silicon- and oxygen-containing material 315 may not be fully oxidized. However, to reduce damage to the structure 300, the plasma source can deliver a plasma power less than or about 2,500 W to the panel or substrate support, and can deliver less than or about 2,250 W, less than or about 2,000 W, less than or about 1,750 W, less than or about 1,500 W or less.

[0047] Similar to the deposition operation, during the conversion operation, a bias power supply can be engaged to provide a bias to the plasma generated above the substrate. This can draw the plasma effluent to the substrate, which can bombard the film and cause the deposited silicon-containing material 315 to convert to a silicon- and oxygen-containing material. Applying a greater bias can increase the directionality of the transport perpendicular to the plane across the substrate. Thus, by reducing the supplied bias power, the amount of directionality can be reduced, which can increase the interaction of the plasma effluent within the feature. Conversely, a more directionally transported plasma effluent can penetrate the remaining silicon-containing material 315 formed at the bottom of the feature 310 and / or on the substrate 305. During operation 245, oxygen radicals and ions can easily penetrate the material formed within the feature 310 and can convert the silicon-containing material 315 to a silicon- and oxygen-containing material 320. The applied bias power can be relatively low to limit sputtering of the resulting film and to limit any potential damage to the structure. For example, the bias plasma power can be maintained at less than or about 1000 W to not damage the underlying structure, and can be maintained at less than or about 900 W, less than or about 800 W, less than or about 700 W, less than or about 600 W or less. Although in some conversion operations the source power can be higher than the bias power, in other conversion operations the source power can alternatively be maintained below the bias power.

[0048] In some embodiments of the present technology, subsequent oxidation may perform an etching operation to etch back a portion of the formed material. This operation may be performed in the same chamber as deposition and / or oxidation and may be performed in a cyclic process to fill features. In some embodiments, the flow of the oxygen-containing precursor may be paused and the processing area may be purged. After purging, at operation 250, a fluorine-containing precursor may be provided to the processing area of the semiconductor processing chamber. An etching plasma effluent may be formed at operation 255, which may also be a capacitively coupled plasma formed within the processing area, although inductively coupled plasma may be similarly applied in some embodiments. The etching plasma effluent may be formed by applying plasma power to the panel or substrate support, and in some embodiments, no other power source may be engaged.

[0049] Similar to the deposition and / or conversion operations, during the etching operation, a bias power source may be engaged to provide a bias to the plasma generated above the substrate. This may draw the plasma effluent towards the substrate, which may bombard the film and cause densification of the deposited silicon-containing material 315. Although any fluorine-containing material may be used, in some embodiments, diatomic fluorine (F2), nitrogen trifluoride (NF3) with or without H2, ammonia (NH3), octafluorocyclobutane (C4F8), carbon tetrafluoride (CF4), hexafluorobutadiene (C4F6), or other fluorocarbons may be used as the fluorine-containing precursor together with one or more additional precursors to generate the etching plasma. The applied bias power may be relatively low to limit sputtering of the resulting film and to limit any potential damage to the structure. The materials transported to form the plasma may similarly have a reduced amount of heavier materials to limit sputtering of the deposited film. Additionally, by adjusting the applied source power and bias power, an etching operation may be performed, which may reduce the sidewall coverage of the deposited material.

[0050] As described above, any fluorine-containing material can be used to generate plasma in a processing region by delivering power from a plasma source to a panel. In some embodiments, the source plasma power can be less than the plasma power used during deposition and / or conversion. For example, the delivered plasma power can be less than or about 500 W, and can be less than or about 450 W, less than or about 400 W, less than or about 350 W, less than or about 300 W, less than or about 250 W, less than or about 200 W, less than or about 150 W, less than or about 100 W, less than or about 90 W, less than or about 80 W, less than or about 70 W, less than or about 50 W, or less. By reducing the source plasma power during the formation of the etching plasma, the dissociation of the fluorine-containing precursor can be controlled, which can slow down the etching of the material. This can prevent the removal of too much material that would slow down gap filling, and can prevent damage to other materials in structure 300. Additionally, aspects of the bias power can also be adjusted, which can also limit damage to the underlying structure. For example, the bias power can be maintained at less than or about 1,000 W, and can be less than or about 750 W, less than or about 600 W, less than or about 500 W, less than or about 400 W, or less. Although in some operations the bias power can be higher than the plasma source power, in other operations the bias power can alternatively be maintained below the plasma power.

[0051] Similarly, applying a greater bias can increase the directionality of the delivery perpendicular to the plane across the substrate. Thus, by reducing the supplied bias power, the amount of directionality can be reduced, which can increase the interaction of the plasma effluent within the feature. The plasma effluent can then etch the silicon- and oxygen-containing material 320 at operation 260, and can remove the silicon- and oxygen-containing material 320 from the sidewalls of feature 310. The plasma effluent can completely remove the silicon- and oxygen-containing material 320 from the sidewalls of feature 310 above the base fill of the silicon- and oxygen-containing material 320. The base fill of the silicon- and oxygen-containing material 320 can represent the silicon- and oxygen-containing material 320 deposited at or toward the bottom of feature 310 on a previously deposited silicon- and oxygen-containing material 320. In an embodiment, densification of the silicon- and oxygen-containing material 320 can be generated at optional operation 265.

[0052] Additional adjustments can be made by adjusting one or more characteristics of the supplied plasma power or bias power to further increase the deposition of materials, the conversion of the deposited materials, or the etching of the deposited materials. For example, in some embodiments, both the plasma power supply and the bias power supply can operate in continuous wave mode. Additionally, one or both of these power supplies can operate in pulsed mode. In some embodiments, the source power can operate in continuous wave mode or pulsed mode, while the bias power operates in pulsed mode. The radio frequency (RF) frequency for the source power and / or the bias power can be greater than or about 1 MHz, and can be greater than or about 3 MHz, greater than or about 5 MHz, greater than or about 13.5 MHz, greater than or about 15 MHz, greater than or about 17.5 MHz, greater than or about 20 MHz, greater than or about 22.5 MHz, greater than or about 25 MHz, greater than or about 27 MHz, greater than or about 27.5 MHz, greater than or about 30 MHz, greater than or about 35 MHz, greater than or about 45 MHz, greater than or about 50 MHz, greater than or about 55 MHz, greater than or about 50 MHz, greater than or about 55 MHz, greater than or about 60 MHz or greater. At higher frequencies for the source power, sputtering of the deposited material can be minimized during conversion. In an embodiment, the RF frequency of the source power and / or the bias power can be less than or about 5 MHz, and can be less than or about 4 MHz, less than or about 3 MHz, less than or about 2 MHz, less than or about 1 MHz, less than or about 750 kHz, less than or about 500 kHz, less than or about 400 kHz, less than or about 350 kHz or less. Both the source power and the bias power can be capable of operating in continuous wave mode or pulsed mode, where the two powers operate in the same mode or different modes. In an embodiment, the duty cycle of the bias power can be less than or about 75%, and the bias power can operate at a duty cycle less than or about 70%, less than or about 60%, less than or about 50%, less than or about 40%, less than or about 30%, less than or about 20%, less than or about 10%, less than or about 5% or less. By applying the bias power with a reduced duty cycle for reduction, such as an on-time operation with a duty cycle less than or about 50%, a greater amount of time per cycle can perform more isotropic etching within the feature, which can better remove material from the sidewalls. Additionally, operating the bias power with a reduced duty cycle can result in less sputtering of the material deposited at the upper portion of the feature, such as an overhang. In an embodiment, the pulse frequency of the source or bias power can be less than or about 70 kHz, and can be less than or about 60 kHz, less than or about 50 kHz, less than or about 40 kHz, less than or about 30 kHz or less.

[0053] As shown in FIG. 2, in an embodiment of the present technology, the deposition and etching processes may be repeated any number of times in a cycle to fill a feature. As shown in FIG. 3C, the deposition, conversion, and etching operations may fill a feature with a silicon-containing material, such as amorphous silicon that can be converted into a silicon- and oxygen-containing material 320. For example, these processes may be repeated a second cycle, a third cycle, a fourth cycle, a fifth cycle, a sixth cycle, a seventh cycle, or any number of cycles necessary to completely fill feature 310 with the silicon- and oxygen-containing material 320.

[0054] Temperature and pressure may also affect the operation of the present technology. For example, the process may be performed at a temperature below or about 450 °C, and may be carried out at a temperature below or about 400 °C, below or about 350 °C, below or about 300 °C, below or about 250 °C, below or about 225 °C, below or about 200 °C, below or about 180 °C, below or about 160 °C, below or about 140 °C, below or about 120 °C, below or about 100 °C, below or about 80 °C, below or about 60 °C, below or about 40 °C, or lower. Throughout the method, including during processing and etching, the temperature may be maintained within any of these ranges. At higher temperatures, a material containing crystalline silicon may be formed instead of a material containing amorphous silicon. Additionally, depending on the structure, higher temperatures may be above the thermal budget.

[0055] For any of these processes, the pressure within the semiconductor processing chamber may also be kept relatively low, such as at a chamber pressure less than or about 20 Torr, and the pressure may be maintained at less than or about 18 Torr, less than or about 16 Torr, less than or about 14 Torr, less than or about 12 Torr, less than or about 10 Torr, less than or about 8 Torr, less than or about 6 Torr, less than or about 4 Torr, less than or about 2 Torr, less than or about 1 Torr, less than or about 500 mTorr, less than or about 250 mTorr, less than or about 100 mTorr, less than or about 50 mTorr, less than or about 25 mTorr, less than or about 10 mTorr, less than or about 5 mTorr, or lower. However, lower pressures may result in a slower fill rate of the feature during deposition, which can control the filling of feature 310 and prevent clogging or pinching. Additionally, higher pressures may result in reduced pattern loading and / or line bending. Further, due to increased ionization and energy of the conversion plasma effluent, a reduced pressure during the conversion operation may result in improved oxidation. Finally, a lower pressure during the etching operation of the etched material may reduce dissociation and the resulting etch rate, which can prevent the etching of materials other than the silicon- and oxygen-containing material. In an embodiment, the pressure within the semiconductor processing chamber may be maintained at greater than or about 1 Torr, greater than or about 2 Torr, and the pressure may be maintained at greater than or about 3 Torr, greater than or about 4 Torr, greater than or about 5 Torr, greater than or about 6 Torr, greater than or about 7 Torr, or greater. By performing the processes according to some embodiments of the present technology, improved filling of narrow features may be achieved using a silicon-containing material, such as a silicon- and oxygen-containing material.

[0056] In an embodiment, the refractive index of the material can demonstrate the oxidation of the material. At lower refractive index values, more complete oxidation of the deposited material can be achieved. In an embodiment, the refractive index of the material can be less than or about 1.70, and can be less than or about 1.65, less than or about 1.60, less than or about 1.58, less than or about 1.56, less than or about 1.54, less than or about 1.52, less than or about 1.50, less than or about 1.48, less than or about 1.46, less than or about 1.44, less than or about 1.42, less than or about 1.40. In an embodiment, for example, a higher duty cycle of source power and / or bias power can reduce the refractive index.

[0057] In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of the various embodiments of the technology. However, it will be apparent to those skilled in the art that some embodiments may be practiced without some of these details or with additional details.

[0058] Certain embodiments have been disclosed, and those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Additionally, many known processes and elements have not been described in order to avoid unnecessarily obscuring the technology. Therefore, the above description should not be regarded as limiting the scope of the technology. Additionally, a method or process may be described as sequential or step-by-step, but it should be understood that the operations can be performed simultaneously or in a different order than listed.

[0059] In the case where a range of values is provided, it should be understood that unless the context clearly dictates otherwise, each intermediate value between the upper and lower limits of that range is also specifically disclosed, to the smallest fraction of the lower limit unit. Any subrange within that range, between any specified value or unspecified intermediate value and any other specified value or intermediate value within the specified range. The upper and lower limits of those smaller ranges can be independently included within or excluded from the range, and each range in which either limit is included, neither limit is included, or both limits are included within the smaller range is also covered by the technology, with any specific excluded limits within the range. In the case where the specified range includes one or both of the limits, ranges excluding one or both of the limits they include are included.

[0060] As used herein and in the appended claims, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" include plural references. Thus, for example, reference to "a silicon precursor" includes plural such precursors, and reference to "the silicon-containing material" includes one or more materials known to those skilled in the art and their equivalents, and so forth.

[0061] Also, as used in this specification and the following claims, the terms "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including" are intended to specify the presence of the stated feature, integer, component, or operation, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

[0062] 100: Processing chamber 102: Chamber body 103: Substrate 104: Substrate support 105: Surface 106: Cover assembly 108: First electrode 110a: Insulator 110b: Insulator 111: Plasma profile modifier 112: Gas distributor 114: Inlet 118: Pore 120: Processing space 122: Second electrode 124: Third electrode 126: Opening 128: Tuning circuit 130: Electronic sensor 132A: First inductor 132B: Second inductor 134: Electronic controller 136: Tuning circuit 138: Electronic sensor 140: Electronic controller 142: First power source 144: Shaft 145: Arrow 146: Conduit 147: Axis 148: Filter 150: Second power source 152: Outlet 200: Method 205: Operation 210: Operation 215: Operation 220: Operation 225: Operation 230: Operation 235: Operation 240: Operation 245: Operation 250: Operation 255: Operation 260: Operation 265: Operation 300: Structure 305: Substrate 310: Feature 315: Silicon-containing material 320: Silicon- and oxygen-containing material

[0063] Domestic deposit information (Please note in the order of deposit institution, date, and number) None Foreign deposit information (Please note in the order of deposit country, institution, date, and number) None

Claims

1. A semiconductor processing method comprising the steps of: providing a silicon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is housed in the processing region, wherein the substrate defines a feature, and wherein the processing region is at least partially defined between a panel and a substrate support on which the substrate is disposed; forming a plasma effluent of the silicon-containing precursor; depositing a silicon-containing material on the substrate; providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber; forming a plasma effluent of the oxygen-containing precursor; contacting the silicon-containing material with the plasma effluent of the oxygen-containing precursor to oxidize the silicon-containing material, wherein the contact forms a silicon- and oxygen-containing material; and providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber. Forming the plasma effluent of the fluorinated precursor; and contacting the silicon- and oxygen-containing material with the plasma effluent of the fluorinated precursor, wherein the contact etches the silicon- and oxygen-containing material from a top, a sidewall, or both of the feature.

2. The semiconductor processing method as described in claim 1, wherein: The feature is characterized by a depth-to-width ratio greater than or about 1:1; and the feature is characterized by a width across the feature less than or about 100 nm.

3. The semiconductor processing method as claimed in claim 1, wherein the oxygen-containing precursor includes diatomic oxygen (O2), nitrous oxide (N2O), or hydrogen peroxide (H2O2).

4. The semiconductor processing method as described in claim 1 further includes the step of: applying a bias power from a bias power supply to the substrate support.

5. The semiconductor processing method as claimed in claim 4, wherein during the deposition and etching, a plasma power supply operates in a continuous wave mode and the bias power supply operates in a pulse mode.

6. The semiconductor processing method as described in claim 1, wherein: The plasma effluents of the silicon-containing precursor are formed at a first power level from a plasma power source; and the plasma effluents of the fluorine-containing precursor are formed at a second power level from the plasma power source that is greater than the first power level.

7. The semiconductor processing method as claimed in claim 1, wherein the fluorine-containing precursor includes diatomic fluorine (F2), nitrogen trifluoride (NF3), ammonia (NH3), octafluorocyclobutane (C4F8), carbon tetrafluoride (CF4), or hexafluorobutadiene (C4F6).

8. The semiconductor processing method as claimed in claim 1, wherein the etching removes silicon- and oxygen-containing material at a rate of less than or about 10 Å / s.

9. The semiconductor processing method as described in claim 1, wherein the method is repeated in a second cycle.

10. The semiconductor processing method as claimed in claim 1, wherein a temperature of the substrate is maintained at a temperature less than or about 450°C.

11. The semiconductor processing method as claimed in claim 1, wherein a pressure within the semiconductor processing chamber is maintained at a pressure less than or about 10 Torr.

12. A semiconductor processing method comprising the steps of: i) forming a plasma effluent containing a silicon precursor; ii) depositing a silicon-containing material on a substrate, wherein the substrate defines a feature, wherein the substrate is disposed on a substrate support; iii) forming a plasma effluent containing an oxygen precursor; iv) contacting the silicon-containing material with the plasma effluent containing the oxygen precursor to form a silicon and oxygen-containing material; v) forming a plasma effluent containing a fluorine precursor; vi) contacting the silicon and oxygen-containing material with the plasma effluent containing the fluorine precursor, wherein the contact etches the silicon and oxygen-containing material from a sidewall of the feature; and repeating operations i) to vi) to iteratively fill the feature.

13. The semiconductor processing method as claimed in claim 12, wherein a plasma power is maintained at greater than or about 600 W during operation iii).

14. The semiconductor processing method as claimed in claim 12, wherein a plasma power is pulsed during operations i) to iv).

15. The semiconductor processing method as claimed in claim 12, wherein the etching completely removes the silicon- and oxygen-containing material from the sidewalls of the feature above a substrate fill of the feature.

16. The semiconductor processing method as claimed in claim 12 further includes the step of: applying a bias power from a bias power source during the semiconductor processing method.

17. The semiconductor processing method as described in claim 16, wherein the bias power supply operates at a plasma power of less than or about 750 W.

18. The semiconductor processing method as described in claim 12, wherein a temperature of the substrate is maintained at a temperature less than or about 450°C.

19. A semiconductor processing method comprising the steps of: providing a silicon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed in the processing region, wherein the substrate defines a feature, and wherein the processing region is at least partially defined between a panel and a substrate support on which the substrate is disposed; forming a plasma effluent of the silicon-containing precursor, wherein the plasma effluent of the silicon-containing precursor is formed from a first power level of a plasma power source; depositing a silicon-containing material on the substrate; providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber; forming a plasma effluent of the oxygen-containing precursor; contacting the silicon-containing material with the plasma effluent of the oxygen-containing precursor to oxidize the silicon-containing material, wherein the contact forms a silicon- and oxygen-containing material; and providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber. The plasma effluent of the fluorinated precursor is formed at a second power level greater than the first power level from the plasma power source; and the silicon and oxygen-containing material is brought into contact with the plasma effluent of the fluorinated precursor, wherein the contact etches the silicon and oxygen-containing material from the sidewall of the feature above a substrate filler of the feature.

20. The semiconductor processing method as claimed in claim 19, wherein a temperature of the substrate is maintained at a temperature less than or about 450°C.

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