Systems, device, and methods for configurable adder circuit

Abstract

A system includes a computing circuit, a memory array operatively coupled to the computing circuit, and a controller. The controller is configured to input a plurality of input data bits to the computing circuit, determine a cumulative quantity associated with the input data bits, determine, based on the cumulative quantity, enable or disable at least one component of the computing circuit, and generate a control signal for enabling or disabling at least one component of the computing circuit based on the enable or disable determination result.

Description

System and method for configurable adder circuit none Computer artificial intelligence (AI) is based on machine learning, for example, using deep learning techniques. With machine learning, a computing system, such as a neural network, calculates the statistical likelihood of input data matching previously computed data. A neural network is a set of interconnected processing nodes that enables data analysis to compare input data with "trained" data. Trained data refers to computational analysis of the properties of known data to develop a model for comparing input data. An example application of AI and data training is object recognition, where the system analyzes the properties of many (e.g., thousands or more) images to identify patterns that can be used to perform statistical analysis to identify input objects. none The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify one embodiment of the present disclosure. Of course, these are merely examples and are not intended to be limiting. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, one embodiment of the present disclosure may reuse reference numbers and / or letters in various examples. Such repetition is for the purposes of brevity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed. Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," "top," and "bottom," may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Neural networks calculate "weights" to perform calculations on new data (an input data "word"). Neural networks use multiple layers of computational nodes, with deeper layers performing calculations based on the results of calculations performed by higher layers. Machine learning currently relies on computing dot products and absolute differences between vectors, typically through multiply-accumulate (MAC) operations on parameters, input data, and weights. Calculations in large deep neural networks often involve so many data elements that storing them in processor cache is impractical. Therefore, they are typically stored in memory. As a result, machine learning is extremely computationally intensive, calculating and comparing large numbers of different data elements. Operations within a processor are orders of magnitude faster than transferring data elements between the processor and main memory resources. Due to the memory required to store these data elements, placing all data elements closer to the processor in cache is prohibitively expensive for most practical systems. Consequently, data transfer becomes a primary bottleneck for AI computations. As datasets grow, the time and power / energy a computing system spends moving data around can ultimately be several times greater than the time and power required to perform the actual computations. To this end, computing-in-memory (CIM) circuits have been proposed to perform these MAC operations. CIM circuits perform data processing locally within appropriate memory circuits. These CIM circuits minimize the latency associated with fetching data / programs and uploading multiple output results from the corresponding memory (e.g., a memory array), thereby addressing the memory or von Neumann bottleneck of traditional computers. Another key advantage of CIM circuits is their high computational parallelism. Thanks to the specific architecture of the memory array, computations can be performed simultaneously along several current paths. CIM circuits also benefit from the high density of multiple memory arrays containing computational devices, which typically offer excellent scalability and three-dimensional integration capabilities. As a non-limiting example, CIM circuits for various machine learning applications can perform MAC operations locally in memory (i.e., without transferring data elements to the host processor), enabling higher-throughput dot product operations on neural activations and weight matrices. Compared to host processor computation, CIM circuits still offer higher performance and lower power consumption. Data elements processed by CIM circuits include various types or formats, such as integers and floating-point numbers. Floating-point numbers are typically represented by a sign portion, an exponent portion, and a significand (mantissa) portion consisting of the number of significant digits. For example, the floating-point format specified by the Institute of Electrical and Electronics Engineers (IEEE®) is 32 bits in size and includes 23 mantissa bits, 8 exponent bits, and 1 sign bit. Another floating-point format is 16 bits in size and includes 10 mantissa bits, 5 exponent bits, and 1 sign bit. In machine learning applications, CIM circuits are often used to perform dot product multiplications based on MAC operations on a large number of data elements (e.g., input word vectors and weight matrices), where each data element should be formatted as a floating-point number, and then perform the addition (or accumulation) of these dot products. This approach reduces the utilization of adder circuits configured for a fixed number of accumulations when processing different accumulations within a given neural network layer. For example, when a CIM circuit's adder circuit (or accumulator, or adder tree) is designed with 64 accumulations, processing low accumulations (e.g., 8, 16, or 32) will reduce the utilization of the CIM circuit. One embodiment of the present disclosure provides various embodiments of a CIM circuit. One embodiment of the CIM circuit includes a configurable adder circuit with a configurable accumulation count (e.g., configurable between various accumulation counts). For example, when the CIM circuit supports 64 accumulations, the CIM circuit can support two sets of 32 accumulations, four sets of 16 accumulations, and eight sets of 8 accumulations. The CIM circuit of one embodiment of the present disclosure includes features or components for detecting accumulation counts and configuring the adder circuit based on the detected accumulation counts, thereby improving CIM utilization and taking precautions to reduce computational resources / energy usage for multipliers during MAC operations. In one aspect, the CIM circuit of one embodiment of the present disclosure can input a plurality of input data bits to a computation circuit, determine accumulation counts associated with the input data bits, determine whether to enable or disable at least one component of the computation circuit based on the accumulation counts, and generate a control signal for enabling or disabling the at least one component of the computation circuit based on the enable / disable determination. In some embodiments, a CIM circuit disclosed herein includes a first component for receiving an input data bit and providing a first output in response to a control signal, a second component for receiving the first output from the first component and providing a second output in response to a control signal including a first logic value, and a multiplexer for outputting the first output in response to the control signal including the second logic value, and for outputting the second output in response to the control signal including the first logic value. FIG1 illustrates a block diagram of a data computation circuit 100 according to some embodiments of the present disclosure. In the embodiment shown in FIG1 , data computation circuit 100 may also be referred to as a (e.g., CIM) circuit or memory circuit, and includes various components that collectively perform in-memory computations (e.g., multiply-accumulate (MAC) operations) on input word vectors and weight matrices. An input word vector may include a plurality of input data elements InDE, numbering N, and a plurality of weight matrices Nd, numbering Nd, numbering weight data elements WtDE. Each input data element InDE and weight data element WtDE may include a floating-point number. As shown, data calculation circuit 100 includes a memory circuit 102, an input circuit 104, a plurality of multiplier circuits 106, a plurality of adder circuits 108, a difference circuit 110 (e.g., sometimes also referred to as a subtractor circuit 110), a shift circuit 112, an adder circuit (adder tree) 114, a first converter 116, a second converter 118, a control circuit (comparator circuit) 120, and an output multiplexer (MUX) 122. In some embodiments, the number of multiplier circuits 106 may correspond to the number of adder circuits 108 or control circuits 120. For example, data calculation circuit 100 may include N (weights / number of input data elements WtDE / InDE) multiplier circuits 106, N (weights / number of input data elements WtDE / InDE) adder circuits 108, and N (weights / number of input data elements WtDE / InDE) control circuits 120. Thanks to the simplified block diagram of the circuit shown in FIG. 1 , the data calculation circuit 100 may include any other components without departing from the scope of an embodiment of the present disclosure. Memory circuit 102 may include one or more memory arrays and one or more corresponding circuits. Each memory array is a storage device comprising a plurality of storage elements 103. Each storage element 103 comprises an electrical, electromechanical, electromagnetic, or other device for storing data elements. Each data element comprises one or more data bits represented by a logical state. In some embodiments, the logical state corresponds to the voltage level of the charge stored in some or all of the storage elements 103. In some embodiments, the logical state corresponds to the physical properties of some or all of the storage elements 103, such as resistance or magnetic orientation. In some embodiments, storage element 103 includes one or more static random-access memory (SRAM) cells. In various embodiments, the SRAM cell includes a plurality of transistors, such as a five-transistor SRAM (5T SRAM) cell, a six-transistor SRAM (6T SRAM) cell, an eight-transistor SRAM (8T SRAM) cell, a nine-transistor SRAM (9T SRAM) cell, and the like. In some embodiments, the SRAM cell includes a multi-rail SRAM cell. In some embodiments, the length of the SRAM cell is at least twice its width. In some embodiments, the storage element 103 includes one or more dynamic random-access memory (DRAM) cells, resistive random-access memory (RRAM) cells, magnetoresistive random-access memory (MRAM) cells, ferroelectric random-access memory (FeRAM) cells, NOR flash cells, NAND flash cells, conductive-bridging random-access memory (CBRAM) cells, data registers, non-volatile memory (NVM) cells, three-dimensional NVM (3D NVM) cells, or other memory cells capable of storing bit data. In addition to the memory array, memory circuit 102 may include a plurality of circuits for accessing or otherwise controlling the memory array. For example, memory circuit 102 may include a plurality of (e.g., word line) drivers operably coupled to the memory array. These drivers may apply signals (e.g., voltages) to corresponding storage elements 103 to permit access (e.g., programming, reading, etc.) to these storage elements 103. As another example, memory circuit 102 may include programming circuitry and / or read circuitry operably coupled to the memory array. The memory array of each memory circuit 102 is used to store a plurality of weight data elements WtDE. In some embodiments, the programming circuit can write the weight data elements WtDE to the storage elements 103 of the corresponding memory array respectively, and the reading circuit can read the bits written into the storage elements 103 to verify whether the weight data elements WtDE tested in other ways are correct. The driver of the memory circuit 102 may include or be operably coupled to a plurality of input activation latches, which are used to receive and temporarily store input data elements InDE. In some embodiments, such input activation latches may be part of the input circuit 104, which may further include a plurality of buffers for temporarily storing the weight data elements WtDE taken from the memory array of the memory circuit 102. Therefore, the input circuit 104 can receive the input data elements InDE and the weight data elements WtDE. In various embodiments of the present disclosure, each input data vector (including, for example, input data elements InDE) and each weight matrix (including, for example, weight data elements WtDE) used to perform a MAC operation on the data computation circuit 100 includes a plurality of floating-point numbers. Therefore, each of the input data elements InDE and the weight data elements WtDE includes a sign bit, a plurality of exponent bits, and a plurality of mantissa bits (sometimes also referred to as fraction bits). For example, each of the input data element InDE and the weight data element WtDE is in the BF16 format, which in some embodiments may also be referred to as the bfloat format or brain floating-point format. In this format, the first bit represents the sign of the floating-point number, the following 8 bits represent the exponent of the floating-point number, and the last 7 bits represent the mantissa or fraction of the floating-point number. Because the mantissa begins with a non-zero value, the last 7 bits of each stored data element represent the 8-bit mantissa with the first most significant bit (MSB) equal to 1. In some embodiments, the format of each input data element InDE and weight data element WtDE is FP16, which may also be referred to as a half-precision format. In this format, the first bit represents the sign of the floating-point number, the following five bits represent the exponent of the floating-point number, and the last ten bits represent the mantissa or fraction of the floating-point number. In this example, the last ten bits of each stored data element represent an 11-bit mantissa with the first MSB equal to 1. In some other embodiments, the floating-point format of each input data element InDE and weight data element WtDE is a format other than BF16 or FP16, such as another 16-bit format, a 32-bit, 64-bit, 128-bit, or 256-bit, or a 40-bit or 80-bit extended precision format. In data elements representing floating-point numbers, the sign and mantissa may also collectively refer to the signed mantissa of the floating-point number. The MSB of the mantissa may also be referred to as a hidden bit or a hidden MSB. Still referring to FIG. 1 , input circuit 104 is configured to output the entirety of each data element InDE and weight data element WtDE to each multiplier circuit 106 and adder circuit 108. In some embodiments, input circuit 104 is configured to output the signed mantissa of each data element to multiplier circuit 106 and the exponent of each data element to adder circuit 108, as described below. Each multiplier circuit 106 is an electronic circuit, such as an integrated circuit (IC), configured to receive, for example, a sign bit InS and a mantissa InM (collectively represented as signed mantissa InS / InM) of each of the N data elements InDE and a sign bit WtS and a mantissa WtM (collectively represented as signed mantissa WtS / WtM) of each of the N data elements WtDE from the input circuit 104. Each adder circuit 108 is an electronic circuit, such as an IC, configured to receive, for example, an exponent InE of each of the N data elements InDE and an exponent WtE of each of the N data elements WtDE from the input circuit 104. Each multiplier circuit 106 may include one or more data registers (not shown) for receiving instances of signed mantissas InS / InM and WtS / WtM. In the embodiment shown in FIG. 1 , multiplier circuit 106 is configured to receive instances of signed mantissas InS / InM and WtS / WtM, where the mantissa signs correspond to data elements InDE and WtDE. In some other embodiments, multiplier circuit 106 includes one or more data registers for receiving instances of signed mantissas InS / InM and / or WtS / WtM, where the instances include hidden MSBs. In some embodiments, multiplier circuit 106 includes one or more data registers for adding the hidden MSBs to the received instances of signed mantissas InS / InM and / or WtS / WtM. Multiplier circuit 106 may include logic circuitry (not shown) configured to reformat each instance of the signed mantissa InS / InM into a two's complement mantissa InTC, also referred to as a reformatted mantissa InTC, and to reformat each instance of the signed mantissa WtS / WtM into a two's complement mantissa WtTC during operation. The reformatted mantissa InTC may have the same number of bits as the signed mantissa InS / InM, and the reformatted mantissa WtTC may have the same number of bits as the signed mantissa WtS / WtM. The multiplier circuit 106 may include one or more logic gates M 1. Logic gate M 1 is used to multiply some or all instances of the reformatted mantissa InTC with some or all instances of the reformatted mantissa WtTC during operation, thereby generating N products, such as: P[1] to P[N]. In various embodiments, one or more logic gates M 1 includes one or more AND gates, or NOR gates, or other circuits suitable for performing some or all multiplication operations. One or more logic gates M 1 is used to generate each product P[1] to P[N] as a two's complement data element during operation, the two's complement data element including bits, the total number of which is equal to 2 times the reformatted mantissa InTC and WtTC minus 1. One or more logic gates M 1 can be considered a multiplier that multiplies some or all instances of the reformatted mantissa InTC with some or all instances of the reformatted mantissa WtTC. In some embodiments, the multiplier (e.g., one or more logic gates M1) can receive a multiplication operation of a signed mantissa InS / InM or a signed mantissa WtS / WtM. The multiplier circuit 106 is configured to generate N products P[1] to P[N] during operation. For example, the multiplier circuit 106 may generate a number N of products P[1] to P[N] equal to 16. In some embodiments, the multiplier circuit 106 may generate a number N of products P[1] to P[N] less than or greater than 16. In some embodiments, for example, when the data elements InDE and WtDE are in BF16 format, the multiplier circuit 106 generates each product P[1] to P[N] having a total of 17 bits based on each of the signed mantissas InS / InM and WtS / WtM and the reformatted mantissas InTC and WtTC, where each of the mantissas has a total of 9 bits. In some embodiments, for example, when the data elements InDE and WtDE are in FP16 format, the multiplier circuit 106 generates each product P[1] to P[N] having a total of 23 bits based on each of the signed mantissas InS / InM and WtS / WtM and the reformatted mantissas InTC and WtTC, where each of the mantissas has a total of 12 bits. In an embodiment of the multiplier circuit 106, the multiplier circuit 106 generates each product P[1] to P[N] having a total of other number of bits based on the signed mantissas InS / InM and WtS / WtM and each of the reformatted mantissas InTC and WtTC, wherein each of the mantissas has a total of other number of bits that does not exceed the scope of an embodiment of the present disclosure. The multiplier circuit 106 is configured to perform multiplication and reformat operations on the sign and mantissa bits during operation to generate two's complement products P[1] to P[N]. The multiplier circuit 106 is configured to output the products P[1] to P[N] to a shift circuit 112 (not shown) on a data bus. In various embodiments, the multiplier circuit 106 may include one or more other components to perform split multiplication (or to simplify the multiplication process). For example, the multiplier circuit 106 may include one or more multiplexers (MUXs), switches, or other types of logic components. The multiplier circuit 106 may include other types of logic components to perform functions such as selecting one of multiple inputs as an output based on a control signal. In another example, one or more logic gates M of the multiplier circuit 106 1, in addition to receiving the corresponding reformatted mantissa InTc and reformatted mantissa WtTC, can be used to receive a third input. The third input includes or corresponds to a control signal from the corresponding control circuit 120, and the value of this control signal is 0 or 1. One or more logic gates M 1 can multiply the reformatted mantissa InTc and the reformatted mantissa WtTC by the control signal. In this example, based on the control signal, one or more logic gates M 1 can output 0 (for example, the control signal is equal to 0) as the product P[n], or output the product of the reformatted mantissa InTc and the reformatted mantissa WtTC (for example, the control signal is equal to 1). Each adding circuit 108 includes one or more data registers (not shown) for receiving instances of indices InE and WtE corresponding to the number of data elements, which are the data elements InDE and WtDE of the multiplier circuit 106 discussed above. Each adding circuit 108 includes one or more logic gates A 1. Logic Gate A 1 is used to add each instance of index InE to each instance of index WtE during operation. In various embodiments, one or more logic gates A 1 includes one or more full adder gates, half adder gates, ripple carry adder circuits, carry-save adders, carry-select adders, carry-lookahead adders, or other circuits suitable for performing some or all of the addition operations. 1 is used to generate the index and S[1] to S[N] as data elements, and the total number of bits of this data element is equal to the number of bits of each index InE and WtE plus 1. Adder circuit 108 is configured to generate exponential sums S[1] to S[N] during operation, where the total number N of exponential sums and the magnitudes of the data elements correspond to the total number N and magnitudes of the data elements of the products P[1] to P[N] discussed above by multiplier circuit 106. Therefore, for a total of N combinations of data elements InDE and WtDE, each n-th combination corresponds to the n-th exponential sum S[n] in the exponential sums S[1] to S[N] and the n-th product P[n] in the products P[1] to P[N]. In some embodiments, for example, when the data elements InDE and WtDE are in BF16 format, the adder circuit 108 generates each corresponding exponent sum S[1] to S[N] having a total of 9 bits based on each of the exponents InE and WtE, where each of the exponents has a total of 8 bits. In some embodiments, for example, when the data elements InDE and WtDE are in FP16 format, the adder circuit 108 generates each corresponding sum S[0] to S[N] having a total of 6 bits based on each of the exponents InE and WtE, where each of the exponents has a total of 5 bits. The adder circuit 108 generates each corresponding sum S[1] to S[N] having a total of other numbers of bits based on each of InE and WtE, where each of the exponents has a total of other numbers of bits not exceeding the scope of one embodiment of the present disclosure. The adder circuit 108 is configured to output the exponent sums S[1] to S[N] to the difference circuit 110 on the data bus (not shown). The differential circuit 110 is an electronic circuit, such as an IC, including one or more logic gates L 1 (eg, corresponding to or serving as a selector circuit 111) and one or more logic gates B 1, each logic gate is used to receive the exponential sum S[1] to S[N] from the adding circuit 108. Sometimes one or more logic gates L 1 can refer to a selector, and sometimes one or more logic gates B 1 may refer to a subtractor. One or more logic gates L 1 is used to generate the maximum exponent and MaxExp as a data element during operation. The value of this data element is equal to the maximum value of the exponent and data elements S[1] to S[N], and the number of bits of this data element is equal to the number of data elements of the exponent and data elements S[1] to S[N]. One or more logic gates L 1 is used to output the maximum exponent and MaxExp to one or more logic gates B 1 and to converter circuit 124, discussed below. One or more logic gates B1 are used to generate differences D[1] to D[N] by subtracting the data elements of each of the exponent sums S[1] to S[N] from the maximum exponent sum MaxExp during operation. The differences D[1] to D[N] thus have a total number N and magnitude of data elements corresponding to the exponent sums S[1] to S[N] and products P[1] to P[N] discussed above. As shown in the embodiment of FIG. 1, one or more logic gates B 1 is used to output the difference D[1] to D[N] to the shift circuit 112 and the control circuit 120 on one or more data buses (not shown). In some embodiments, one or more logic gates B 1 does not output the differences D[1] to D[N] to the multiplier circuits 106, and each multiplier circuit 106 generates each instance P[n] of the product P[1] to P[N] by always performing a multiplication operation. In some other embodiments, one or more logic gates B 1 is used to output the differences D[1] to D[N] to the multiplier circuits 106 respectively, and each multiplier circuit 106 is used to selectively perform a multiplication operation based on the corresponding instance D[n] to generate each instance P[n] of the product P[1] to P[N]. Each control circuit 120 is an electronic circuit, such as an IC, configured to receive, for example, one of the corresponding differences D[1] to D[N] from the difference circuit 110 , where the corresponding difference represents the difference between at least one exponent InE or exponent WtE and a maximum exponent sum MaxExp. The control circuit 120 is configured to compare the received differences D[1] to D[N] with an exponent sum threshold (e.g., sometimes referred to as an exponent difference threshold) during operation. The exponent and threshold may be predefined or preconfigured for a specific machine learning application. The exponent and threshold may be configured based on the desired accuracy of the output of the MAC operation. In some configurations, data computation circuit 100 may set the exponent and threshold based on the precision of the mantissa InM or mantissa WtM (e.g., a portion of the input value) or the format of the input value (e.g., a data element from input circuit 104). For example, data elements InDE and WtDE may be in FP16 format, including 1 sign bit, 5 exponent bits, and 10 mantissa bits. The output of the MAC operation (e.g., the output from second converter 118) may be in the same or a different format (e.g., FP32 format, including 1 sign bit, 8 exponent bits, and 23 mantissa bits, or other formats). In this case, the precision may be set to the number of bits (e.g., precision) of the mantissa InM or WtM (e.g., 10 mantissa bits). In some configurations, data computation circuitry 100 may set the exponent and threshold based on a predetermined round-up value from the least significant bit (e.g., by configuring the exponent and threshold as a quantity that is the number of mantissa bits plus the number of extra bits). For example, in the example above, where the data elements InDE and WtDE are in FP16 format and the MAC operation output is in FP32 format, data computation circuitry 100 sets the exponent and threshold as the precision of the data element plus one or more extra bits. In some cases, the number of extra bits may be predefined. In other cases, the number of extra bits may be based on the specific structure or implementation of data computation circuitry 100 or the CIM, where six extra bits may be configured for a 64-bit MAC CIM and five extra bits may be configured for a 32-bit MAC CIM. For example, with six extra bits, data computation circuitry 100 may be configured for a 32-bit MAC CIM (e.g., 10 mantissa bits associated with the data element and six extra bits based on the specific structure). The control circuit 120 is configured to generate control signals C[1] to C[N] during operation, wherein a total number N of the control signals corresponds to at least one multiplier circuit 106, an adder circuit 108, and / or a total number N of differences D[1] to D[N]. The generated control signals C[1] to C[N] are selected based on or according to a comparison of the differences D[1] to D[N] with an index and a threshold. Each of the control circuits 120 may generate a corresponding instance C[n] of the control signals C[1] to C[N]. For example, the control circuit 120 may include one or more components capable of or suitable for performing comparison and generation operations. For example, the control circuit 120 generates a control signal C[n] based on whether the corresponding difference D[n] satisfies an exponent and a threshold (e.g., by performing a comparison). For example, satisfying the exponent and the threshold may mean that the difference D[n] is greater than or equal to the exponent and the threshold. The control signal C[n] may be 0 or 1 based on the result of the comparison. If the difference D[n] is less than the exponent and the threshold, the control circuit 120 may generate a control signal C[n] of 1. If the difference D[n] is greater than or equal to the exponent and the threshold, the control circuit 120 may generate a control signal C[n] of 0. For example, in some configurations, the control circuit 120 generates a control signal C[n] of 1 if the difference D[n] is greater than or equal to the exponent and the threshold, and generates a control signal C[n] of 0 if the difference D[n] is less than the exponent and the threshold. The control circuit 120 provides the control signal C[n] to the corresponding multiplier circuit 106 or at least one component of the multiplier circuit 106. It should be noted that variables or values, such as exponents and thresholds, input values, formats, etc., are not limited to the examples provided in one embodiment of the present disclosure, and data calculation circuit 100 or other devices or components thereof may also use other variables or values, such as different exponents and thresholds, formats, etc., to perform MAC operations on floating-point numbers while reducing computing resources. Furthermore, it should be noted that more or fewer components and / or different arrangements of one or more components may be implemented to perform the features, operations, or procedures discussed in one embodiment of the present disclosure. In various arrangements, the operations of at least one of the summing circuit 108, the differencing circuit 110, and / or the control circuit 120 may be performed before, after, or in parallel with the multiplier circuit 106. In some arrangements, the operations of a single one of the summing circuit 108, the differencing circuit 110, or the control circuit 120 may be performed sequentially or in parallel. The shift circuit 112 is an electronic circuit, such as an IC, including one or more registers and / or logic gates for performing a shift operation on each instance P[n] of the products P[1] to P[N] based on the value of the corresponding instance D[n] of the differences D[1] to D[N]. Each instance P[n] of the product P[1] to P[N] is the sign and mantissa of the corresponding combination based on the data elements InDE and WtDE, and each instance D[n] of the difference D[1] to D[N] is the sum of exponents based on the same combination. The displacement circuit 112 is used to generate the displacement product SP[1] to SP[N] during the operation by right shifting the product P[1] to each instance P[n] of P[N] by an equal number of corresponding differences D[n], wherein the symbol and mantissa bits are aligned according to the summed exponent used to generate the difference D[1] to D[N]. Based on this alignment, the displacement circuit 112 is used to generate each instance SP[n] of the displacement product SP[1] to SP[N], this displacement product SP[1] to SP[N] with the same index used for the maximum exponent and MaxExp as the baseline. To compensate for the right-shift operation, the displacement circuit may add an instance of the sign bit (0 or 1) of each of the product P[n] as the leftmost bit corresponding to the meridional-displacement product SP[n]. The number of symbol bit instances added is equal to the number of right shifts judged by the corresponding difference D[n]. In the embodiment illustrated in FIG. The displacement circuit 112 includes one or more displacers to receive the product P[1] to P[N] of the self-multiplier circuit 106 and optionally based on the respective difference D[1] to D[N] output (e.g., displacement) one or more displacement products SP[1] to SP[N] to adder circuit 114 . For example, the displacement product output to the adder circuit 114 may include SP[w] to SP[z], wherein "w" to "z" may each be one of integers from 1 to N. In one aspect of one embodiment of the present disclosure, the number sum of SP[w] to SP[z] may be equal to N . In another aspect of one embodiment of the present disclosure, the number sum of SP[w] to SP[z] may be less than N . The displacement circuit 112 (e.g., a displacer) may be controlled (e.g., enabled) by a signal based on a number (e.g.: N) generated by comparing the corresponding difference D[1] to D[N] with the difference threshold (not shown in FIG. 1). The difference threshold can be configured based on the distribution of the difference values ​​D[1] to D[N]. In examples where differences D[1] to D[N] are normal distributions, the difference threshold can be judged to be 1 standard deviation lower than the mean of the normal distribution. In another example where differences D[1] to D[N] are still normally distributed, the difference threshold can be judged to be 2 standard deviations lower than the mean of the normal distribution. In another example where differences D[1] to D[N] are still normally distributed, the difference threshold can be judged as any standard deviation lower than the mean of the normal distribution. When any difference (e.g., D[n], where n is an integer between 1 and N) is equal to or less than a difference threshold (sometimes referred to as a "small exponent difference"), the bit shift circuit 112 (e.g., a shifter) may be disabled to prevent the adder circuit 114 from receiving the corresponding shifted product SP[n] (e.g., by not shifting the corresponding product P[n] or by disconnecting the adder circuit 114). Similarly, when any difference is greater than the difference threshold (sometimes referred to as a "normal exponent difference"), the bit shift circuit 112 may be enabled to output the corresponding shifted product SP[n] to the adder circuit 114. In other words, the bit shift circuit 112 can shift any product P[1] to P[N] and output the shifted products SP[1] to SP[N] to the adder circuit 114 based on comparing the respective differences D[1] to D[N] with the difference threshold. Therefore, the sum of SP[w] to SP[z] (output by the bit shift circuit 112) can be equal to N. In some configurations, the bit shift circuit 112 can detect whether at least one product P[1] to P[N] from the multiplier circuit 106 is zero. In this case, the bit shift circuit 112 may not shift the corresponding product that is zero and / or output the product to the adder circuit 114. Therefore, the sum of SP[w] to SP[z] may be less than N. Furthermore, to generate SP[w] through SP[z], the bit shift circuit 112 may align the sign and mantissa bits according to the summed exponent by right-shifting each instance P[n] of the products P[w] through P[z] by an amount equal to the corresponding difference DA[n]. In some embodiments, the difference DA[n] may be generated (e.g., via the difference circuit 110) based on subtracting each data element of the sum S[w] through S[z] from the maximum exponent, MaxExp. The maximum exponent, MaxExp, may correspond to the maximum value of the data elements of the sum S[w] through S[z]. Based on this alignment, the bit shift circuit 112 may generate each instance SP[n] of the shifted products SP[w] through SP[z] using the same exponent as used for the maximum exponent, MaxExp, as a baseline. When any difference (e.g., D[n], where n is an integer between 1 and N) is equal to or less than a difference threshold (sometimes referred to as a "small exponential difference"), the shift circuit 112 may be disabled to prevent the adder circuit 114 from receiving the corresponding shifted product SP[n]. In some embodiments, products P[n] with such large exponential differences may be ignored. In other words, the shift circuit 112 may shift all or some of the products P[1] to P[N] and selectively output corresponding products SP[1] to SP[N] to the adder circuit 114 based on comparing the respective differences D[1] to D[N] with the difference threshold. Therefore, the sum of the number of SP[w] to SP[z] (output by the shift circuit 112) may be less than or equal to N. When one or more products P[1] to P[N] are ignored (e.g., their respective exponential differences D[n] are equal to or greater than the difference threshold), the sum is less than N; and when no products P[1] to P[N] are ignored, the sum is equal to N. In some embodiments, multiplier circuit 106 may receive differences D[1] to D[N] from difference circuit 110 to determine whether difference D[n] is greater than or equal to an exponent and a threshold (eg, sometimes referred to as an exponent difference threshold). In some embodiments, for example, when the data elements InDE and WtDE are in BF16 format, the shift circuit 112 generates each shifted product having a total of 21 bits, for example, SP[0] to SP[N], based on each product P[0] to P[N], where each of the products P[0] to P[N] has a total of 17 bits. In some embodiments, for example, when the data elements InDE and WtDE are in FP16 format, the shift circuit 112 generates each shifted product having a total of 27 bits, for example, SP[0] to SP[N], where each of the products P[0] to P[N] has a total of 23 bits. The shift circuit 112 generates each shifted product SP[0] to SP[N] having a total of other numbers of bits based on each product P[0] to P[N], where each of the products P[0] to P[N] has a total of other numbers of bits within the scope of one embodiment of the present disclosure. Based on the two's complement format of the products P[0] to P[N], the shift circuit 112 is configured to generate shifted products in two's complement format, for example, SP[0] to SP[N]. As discussed above, in the example illustrated in FIG. 1 , the shift circuit 112 is configured to output the shifted products SP[w] to SP[z] to the adder circuit (tree) 114 on the data bus (not shown). The adder tree 114 is an electronic circuit, such as an IC, including multiple layers of one or more logic gates (not shown), such as one or more logic gates A as discussed above. 1 (a logic gate of adder circuit 108). For example, adder tree 114 may include a first layer for receiving shifted products SP[w] to SP[z] and a last layer for generating sum 115 as a data element corresponding to the sum of shifted products SP[w] to SP[z]. In some embodiments, each of one or more successive layers between the first and last layers is configured to receive a first number of data elements generated by the preceding layer and to generate a second number of data elements based on the first number of data elements, where the second number is half the first number. Thus, the total number of layers includes the first and last layers and each successive layer (if any). In some embodiments, the sum PSTC (e.g., corresponding to sum 115) may refer to a partial sum PSTC or a mantissa sum PSTC, where the total number of bits in the sum PSTC corresponds to the number of bits and the number of data elements in the shifted products SP[w] to SP[z]. In some embodiments, the number of bits in the sum PSTC is equal to the number of bits in the shifted products SP[w] to SP[z] plus the number of bits that can represent the data elements in the shifted products SP[w] to SP[z]. In some embodiments, the number of bits in the sum PSTC is equal to the number of bits in the shifted products SP[w] to SP[z] plus 4 bits that can represent the 16 data elements in the shifted products SP[w] to SP[z]. In some embodiments, for example, when the data elements InDE and WtDE are in BF16 format, the adder tree 114 generates a sum PSTC having a total of 25 bits based on each of the shifted products SP[w] to SP[z], where each of the shifted products SP[w] to SP[z] has a total of 21 bits. In some embodiments, for example, when the data elements InDE and WtDE are in FP16 format, the adder tree 114 generates a sum PSTC having a total of 31 bits based on each of the shifted products SP[w] to SP[z], where each of the shifted products SP[w] to SP[z] has a total of 27 bits. The adder tree 114 generates a sum PSTC based on each of the shifted products SP[w] to SP[z], where each of the shifted products SP[w] to SP[z] has a total of other numbers of bits within the scope of one embodiment of the present disclosure. In various embodiments of the present disclosure, adder tree 114 is configured to generate a two's complement sum PSTC based on the shift products SP[w] to SP[z] being in two's complement format. Therefore, adder tree 114 is configured to output the sum PSTC to converter 116 on a data bus (not shown). In some embodiments, adder tree 114 may output the sum PSTC to circuitry external to data calculation circuit 100 (not shown). Converter 116 is an electronic circuit, such as an IC, that includes logic circuitry for receiving the sum PSTC from adder tree 114 during operation and converting the sum PSTC from a two's complement number to a sum PSSM in sign-plus-mantissa format. Converter 116 generates a sum PSSM having the same number of bits as the sum PSTC. In the embodiment shown in FIG. 1 , converter 116 further outputs the sum PSSM to converter 118 on a data bus (not shown). In some other embodiments, converter 116 may output the sum PSSM to circuitry external to data computation circuit 100 (not shown). Converter 118 is an electronic circuit, such as an IC, including logic circuitry for receiving the sum PSSM from converter 116 and the maximum exponent (MaxExp) from differencing circuit 110 during operation, and converting the sum PSSM from a sign-and-mantissa format to a sum PS. This sum PS has an output format based on the sum PSSM and MaxExp and different from the sign-and-mantissa format, such as the floating-point format discussed above. In various embodiments of the present disclosure, converter 118 can generate a sum PS compatible with circuitry external to data computation circuit 100 (not shown). For example, converter 118 can output sum PS to circuitry external to data computation circuit 100 (not shown), such as a memory array or other instance of data computation circuit 100, as part of a convolutional neural network (CNN). In some arrangements, converter 116 can be part of converter 118, and vice versa. The multiplexer 122 may be disposed between the converter 116 and the converter 118 , such that the multiplexer 122 may receive an output from the converter 116 and provide an output to the converter 118 . According to some embodiments of the present disclosure, FIG. 2 illustrates a block diagram of a portion (e.g., hereinafter referred to as "configurable circuit" 200) of a data computation circuit (e.g., data computation circuit 100). Configurable circuit 200 includes adder circuit 214, control circuit 220, and multiplexer 222, which may have similar features or be combined with features of adder circuit 114, control circuit 120, and multiplexer 122, respectively. Briefly, adder circuit 214 may receive partial sums (psums) and provide an output to multiplexer 222 via an internal output bus. Multiplexer 222 may receive the output from adder circuit 214 and output the result of a MAC operation. Control circuit 220 may provide signal 221 to adder circuit 214 and multiplexer 222 to configure adder circuit 214 and multiplexer 222. In some embodiments, adder circuit 214 may be configured differently for different accumulation quantities, as discussed in further detail below. For example, adder circuit 214 can be configured to support accumulation for point-wise convolution layers (e.g., with high accumulation counts, such as 16, 32, or 64). Adder circuit 214 can also be configured to support accumulation for depth-wise convolution layers (e.g., with low accumulation counts, such as 8). In some embodiments, multiplexer 222 can be configured to output MAC operation results for different accumulation counts (e.g., 8, 16, 32, or 64). The configurable circuit 200 shown in FIG. 2 is a non-limiting example. FIG3 illustrates a schematic diagram of an example configurable circuit 300 according to some embodiments of the present disclosure. In FIG3 , configurable circuit 300 includes an adder circuit 314 and a multiplexer 322, which may have similar features or be combined with features of adder circuit 214 and multiplexer 222, respectively. The configurable circuit 200 shown in FIG2 is a non-limiting example. As shown, adder circuit 314 can receive partial sums psum0 to psum63 and perform an addition operation on the received partial sums. Adder circuit 314 can provide the result of the addition operation to multiplexer 322, which can output the result of the MAC operation. In some embodiments, adder circuit 314 can receive signal 321 (e.g., from control circuit 220) and can be configured to support different accumulation amounts. For example, adder circuit 314 can receive signal 321 (e.g., 16A_EN) indicating an accumulation of 16 (16A) and provide four results of 16A (16A×4) without performing the next addition operation (e.g., 32A). Multiplexer 322 can receive signal 321 (e.g., 16A_EN) indicating 16A and receive the 16A×4 result from the corresponding adder (e.g., the adder performing 16A). Multiplexer 322 can output a MAC result based on the received 16A×4 result. Similarly, adder circuit 314 can receive signal 321 (e.g., 32A_EN) indicating an accumulation of 32 (32A) and provide two results of 32A (32A×2) without performing the next addition operation (e.g., 64A). Multiplexer 322 can receive signal 321 (e.g., 32A_EN) indicating 32A and the 32A×2 result received from the corresponding adder (e.g., the adder performing 32A). Multiplexer 322 can output a MAC result based on the received 32A×2 result. Similarly, adder circuit 314 can receive signal 321 (e.g., 64A_EN) indicating an accumulation of 64 (64A) and provide one result of 64A (64A×1). Multiplexer 322 may receive signal 321 indicating 64A (e.g., 64A_EN) and the 64A × 1 result received from a corresponding adder (e.g., an adder performing 64A). Multiplexer 322 may output a MAC result based on the received 64A × 1 result. This allows for configuring the accumulation amount (e.g., between various accumulation amounts), thereby improving CIM utilization and taking precautionary measures to reduce resource / energy usage for multipliers in MAC operations. In some embodiments, as shown in FIG. 3 , a configurable circuit 300 (e.g., adder circuit 314) may receive a plurality of input data bits (e.g., psums) as input. In response to receiving the input bits, the configurable circuit 300 may determine a cumulative sum associated with the received input data bits. For example, based on the input data bits (e.g., psums), the configurable circuit 300 may determine which cumulative sums can be performed. In some embodiments, based on the cumulative sums, the configurable circuit 300 may determine whether to enable or disable at least one component of the adder circuit 314. For example, if the cumulative sum is determined to be 16A×4, the configurable circuit 300 may determine to disable the circuit components that perform the 32A×2 and 64A×1 addition operations, thereby allowing the result of the 16A×4 addition operation to be provided to the multiplexer 322. Similarly, when the accumulated number is determined to be 32A×2, the configurable circuit 300 may determine to disable the circuit components performing the 64A×1 addition operation, thereby allowing the result of the 32A×2 addition operation to be provided to the multiplexer 322. When the accumulated number is determined to be 64A×1, the configurable circuit 300 may determine to enable the circuit components performing the 16A×4, 32A×2, and 64A×1 addition operations. In some embodiments, the signal 321 may include enabling or disabling at least one component of the configurable circuit 300. For example, when the accumulated number is determined to be 16A×4, the configurable circuit 300 may generate the signal 321 indicating 16A_EN and disable the components performing the 32A×2 and 64A×1 addition operations. Similarly, when the accumulated number is determined to be 32A×2, the configurable circuit 300 may generate the signal 321 indicating 32A_EN and disable the components performing the 64A×1 addition operation. Likewise, when the accumulated number is determined to be 64A×1, the configurable circuit 300 may generate a signal 321 indicating 64A_EN and enable components that perform 16A×4, 32A×2, and 64A×1 addition operations. In some embodiments, multiplexer 322 may receive signal 321 indicating an accumulated number and may be configured to output a result of a MAC operation based on the accumulated number. For example, when multiplexer 322 receives a signal indicating 16A_EN, multiplexer 322 may provide four results as the output of a 16A×4 MAC operation. Similarly, when multiplexer 322 receives a signal indicating 32A_EN, multiplexer 322 may provide two results as the output of a 32A×2 MAC operation. Similarly, when multiplexer 322 receives a signal indicating 64A_EN, multiplexer 322 may provide one result as the output of a 64A×1 MAC operation. FIG. 4A illustrates a schematic diagram of an example adder circuit 414, according to some embodiments of the present disclosure. Adder circuit 414 may have similar features to, or features that may be combined with, adder circuit 214. The adder circuit 414 shown in FIG. 4A is a non-limiting example. FIG. 4B , according to some embodiments of the present disclosure, tabulates example states of components of adder circuit 414 (e.g., an N+4-bit adder, an N+3-bit adder, etc.) at different accumulation levels (e.g., 16A, 32A, 64A, etc.). In some embodiments, when adder circuit 414 receives a signal indicating the accumulated number of 16A, at least the adders for 16A (e.g., up to N+2-bit adder 416C, including N+1-bit adder, N-bit adder, etc.) may be enabled (e.g., set to "1") via 16A_EN. However, adders for 32A and 64A (e.g., N+3-bit adder 416B and N+4-bit adder 416A) may be disabled (e.g., set to "0"). This allows the result of the addition operation (e.g., 16A×4) to be outputted by N+2-bit adder 416C (e.g., to multiplexer 222). When adder circuit 414 receives a signal indicating the accumulated number of 32A, at least the adders for 16A and 32A (e.g., up to N+3-bit adder 416B, including N+2-bit adder 416C, N+1-bit adder, N-bit adder, etc.) are enabled (e.g., set to "1") via 32A_EN and 16A_EN. However, the adders for 64A (e.g., N+4-bit adder 416A) are disabled (e.g., set to "0"). This allows the result of the addition operation (e.g., 32A×2) to be outputted at N+3-bit adder 416B (e.g., to multiplexer 222). When adder circuit 414 receives a signal indicating the accumulated number of bits 64A, it enables (e.g., sets to "1") the adders for bits 16A, 32A, and 64A (e.g., up to N+4-bit adder 416A, including N+3-bit adder 416B, N+2-bit adder 416C, N+1-bit adder, N-bit adder, etc.) via 64A_EN, 32A_EN, and 16A_EN. This allows the result of the addition operation (e.g., 64A × 1) to be outputted by N+4-bit adder 416A (e.g., to multiplexer 222). The adder circuit 414 and the states of the adding components according to various signals shown in FIG4A and FIG4B are non-limiting examples, and the number of accumulations and / or MAC outputs is not limited to 16, 32, or 64. That is, in some embodiments, a configurable circuit of an embodiment of the present disclosure can be used with any accumulation number, such that when a first number (e.g., 1) of components are disabled, the first output of the adder circuit 414 can include a first set (e.g., 2) of output bits (e.g., 32A), and when a second number (e.g., 0) of components are disabled, the second output can include a second set (e.g., 1) of output bits (e.g., 64A), where the first set is greater than the second set, and the first set is greater than the second set. Although described using 32A×2 and 64A×1 as examples, the configurable circuit of an embodiment of the present disclosure can be used with any accumulation number (e.g., 128). FIG. 5 illustrates an example diagram of signals associated with the adder circuit 414 according to some embodiments of the present disclosure. In some embodiments, the adder circuit 414 may receive signals indicating different accumulated quantities at different cycles. For example, the signal may include a first logic value at a first time and a second logic value at a second time. Referring to FIG. 5 , during a first cycle 551 (e.g., the first time), the adder circuit 414 may receive a signal indicating 64A (e.g., setting 16A, 32A, and 64A to "1" (enabled) according to FIG. 4B ). The adder circuit 414 may perform an addition operation on the psums from psum0 to psum63 and then output the result. (e.g., 64A×1). During the second cycle 552 (e.g., the second time), the adder circuit 414 may receive a signal indicating 32A (e.g., setting 16A and 32A to “1” (enabled) and setting 64A to “0” (disabled) according to FIG. 4B ). The adder circuit 414 may add the first set of psums from psum0 to psum31 and the second set of psums from psum32 to psum63, and then output the result (e.g., two MAC outputs). and (e.g., 32A×2). During the third cycle 553 (e.g., the third time), the adder circuit 414 may receive a signal indicating 16A (e.g., setting 16A to “1” (enabled) and setting 32A and 64A to “0” (disabled) according to FIG. 4B ). The adder circuit 414 may perform an addition operation on the first set of psums psum0 to psum15, the second set of psums psum16 to psum31, the third set of psums psum32 to psum47, and the fourth set of psums psum48 to psum63, and then output the result (e.g., 4 MAC outputs). 、 、 and (For example: 64A×4). FIG. 6A illustrates an example logic circuit 601 that can be coupled to configurable circuit 200, according to some embodiments of the present disclosure. In some embodiments, logic circuit 601 can receive a signal (e.g., signal 221) from a control circuit (e.g., control circuit 220). In response to the received signal, logic circuit 601 can control adder circuit 214. In some embodiments, logic circuit 601 can include a decoder 602 to read / decode the signal from the control circuit and provide a signal to enable / disable an adder (e.g., bitwise adders 416A, 416B, 416C in FIG. 4A). In some embodiments, logic circuit 601 can generate a plurality of logic values ​​and / or logic patterns, each logic value and / or logic pattern indicating a number of adders to be disabled or enabled. According to some embodiments of the present disclosure, FIG. 6B lists example patterns of cumulative numbers and corresponding control signals in a table format. In some embodiments, a control circuit (e.g., control circuit 220) may generate a control signal (e.g., signal 221) representing four patterns (e.g., pattern [1:0]). For example, when the control signal represents pattern "11," the control circuit may decode the control signal and confirm that the cumulative number is "64." In response to confirming the cumulative number, the control circuit may generate a control signal to set the adders 16A, 32A, and 64A to "1" (enabled), thereby performing an addition operation up to 64A and outputting a result of 64A x 1. Similarly, when the control signal represents pattern "10," the control circuit may decode the control signal and confirm that the cumulative number is "32." In response to confirming the cumulative number, the control circuit may generate a control signal to set the adding components of 16A and 32A to "1" (enabled) and the adding component of 64A to "0" (disabled), thereby performing an addition operation up to 32A and outputting a result of 32A × 2. Similarly, when the control signal indicates the pattern "01," the control circuit may decode the control signal and confirm that the cumulative number is "16." In response to confirming the cumulative number, the configurable circuit may generate a control signal to set the adding component of 16A to "1" (enabled) and the adding components of 32A and 64A to "0" (disabled), thereby performing an addition operation up to 16A and outputting a result of 16A × 4. Similarly, when the control signal indicates the pattern "00," the control circuit may decode the control signal and confirm that the cumulative number is "8." In response to confirming the accumulated count, the configurable circuit may generate control signals to set the adder element 16A to "1" (enabled) and the adder elements 16A, 32A, and 64A to "0" (disabled), thereby performing an addition operation up to 8A and outputting an 8A×8 result. Logic circuit 601 may include various logic components to decode signals from the control circuit and provide signals to enable / disable the adders. FIG. 6C illustrates an example logic component 651 that may be coupled to the configurable circuit, according to some embodiments of the present disclosure. For example, logic circuit 601 may include at least one of an OR gate, an AND gate, a NOR gate, a NAND gate, an XOR gate, a NOT gate, or any combination thereof. FIG. 7A illustrates a block diagram of an example configurable circuit 700, according to some embodiments of the present disclosure. FIG. 7B tabulates the control signals and outputs of the multiplexers shown in FIG. 7A, according to some embodiments of the present disclosure. In FIG. 7A, configurable circuit 700 may include adder circuit 714 and multiplexer 722, which may have similar features to, or be combined with, adder circuit 214 and multiplexer 222, respectively. The configurable circuit 700 shown in FIG. 7A is a non-limiting example. Adder circuit 714 may include different-bit adders, including a 16-bit adder 714A, a 17-bit adder 714B, an 18-bit adder 714C, a 19-bit adder 714D, a 20-bit adder 714E, and a 21-bit adder 714F. Each different-bit adder may be configured to provide an input cumulative value as an output. Adder circuit 714 may receive a partial sum (psums) (e.g., psums is 64) and perform an addition operation via at least one different-bit adder. FIG. 7C illustrates a block diagram of adder circuit 714 according to some embodiments of the present disclosure. FIG. 7A shows a non-limiting example of adder circuit 714, including bit adders 714A-714F. FIG. 7B shows adder circuit 714, which may include a plurality of adders (e.g., 731A, ..., 731N-1, 731N, etc.), where N may be any number of adders. For example, in FIG. 7A , adder 731A may be a 16-bit adder 714A, and in FIG. 7A , adder 731N may be a 21-bit adder 714F. Each adder, for example, 731N-1, may receive inputs An-1 and Bn-1 and output an addition result in accordance with a control signal. When the adder circuit 714 receives a control signal including a first logic value (e.g., "1" or an enable signal) associated with a next adder, for example, 731N, the adder 731N-1 may provide the addition result as an input (carry bit, "CI") to the next adder, for example, 731N. When the adder circuit 714 receives a control signal including a second logic value (e.g., "0" or a disable signal) associated with the next adder, for example, 731N, the adder 731N-1 may provide the addition result (Sn-1) to the multiplexer 722. FIG7D shows a table of example bit widths for various adders in FIG7A according to some embodiments of the present disclosure. In some embodiments, as shown, the input bit width of the 16-bit adder 714A may be 16 (and the accumulation number), and the output bit width may be 17. Similarly, the 17-bit adder 714B may have an input bit width of 17 (and the accumulated number), and an output bit width of 18; the 18-bit adder 714C may have an input bit width of 18 (and the accumulated number), and an output bit width of 19; the 19-bit adder 714D may have an input bit width of 19 (and the accumulated number), and an output bit width of 20; the 20-bit adder 714E may have an input bit width of 20 (and the accumulated number), and an output bit width of 21; and the 21-bit adder 714F may have an input bit width of 21 (and the accumulated number), and an output bit width of 22. Referring to FIG. 7A , in some embodiments, a first component (including a 19-bit adder 714D) may be configured to receive a plurality of input data bits (e.g., psums from an 18-bit adder 714C) and provide a first output (e.g., 20b (16A_out1-3)). When adder circuit 714 receives a control signal associated with a second component or subsequent adder (e.g., 20-bit adder 714E) comprising a first logic value (e.g., "1" and / or an enable signal; for example, 32A_EN or 64A_EN for enabling 32A), the second component may receive the first output from the first component and provide a second output (e.g., 21b (32A_out0-1)). When adder circuit 714 receives a control signal associated with a second component or next adder (e.g., a 20-bit adder) comprising a second logic value (e.g., "0," for example, 16A_EN to disable 32A), the second component may be disabled, and the first output from the first component may be provided to multiplexer 722. Thus, multiplexer 722 may be configured to output a first output in response to a control signal comprising the second logic value (associated with 20-bit adder 714E), and to output a second output in response to a control signal comprising the first logic value (associated with 20-bit adder 714E). Similarly, the second component (including the 20-bit adder 714E) can be configured to receive a plurality of input data bits (e.g., psums from the 19-bit adder) and provide a second output (e.g., 21b (32A_out0-1)). When the adder circuit 714 receives a control signal associated with a third component or a subsequent adder (e.g., a 21-bit adder) and including a first logic value (e.g., "1" and / or an enable signal; for example, 64A_EN to enable 64A), the third component can receive the second output from the second component and provide a third output (e.g., 22b (64A_out0)). When the adder circuit 714 receives a control signal associated with the third component or the subsequent adder (e.g., a 21-bit adder) and including a second logic value (e.g., "0"; for example, 32A_EN to disable 64A), the third component can be disabled, and the second output from the second component can be provided to the multiplexer 722. Therefore, the multiplexer 722 can be configured to output a second output in response to a control signal including a second logic value (associated with the 21-bit adder), and can be configured to output a third output in response to a control signal including a first logic value (associated with the 21-bit adder). In some embodiments, multiplexer 722 can be configured to receive different sets of bits (e.g., 20b×4, 21b×2, 22b×1, etc.) from different sets of adders (e.g., 19-bit adder 714D, 20-bit adder 714E, 21-bit adder 714F, etc.). In response to receiving bits from the adders, multiplexer 722 can be configured to output MAC operation results corresponding to the received bits. For example, when multiplexer 722 receives 20b×4 from 19-bit adder 714D and a signal indicating a corresponding accumulated amount (e.g., 16A), multiplexer 722 can provide MAC operation outputs, 16A_out0, 16A_out1, 16A_out2, and 16A_out3. When multiplexer 722 receives 21b×2 from 20-bit adder 714E and a signal indicating a corresponding accumulated number (e.g., 32A), multiplexer 722 provides MAC operation outputs, 32A_out0 and 32A_out1. When multiplexer 722 receives 22b×1 from 21-bit adder 714F and a signal indicating a corresponding accumulated number (e.g., 64A), multiplexer 722 provides MAC operation output, 64A_out0. In some embodiments, when the number of bits from the adder is less than the number of output bits of the multiplexer, multiplexer 722 may be configured to set at least one of the output bits to a logic state (e.g., "0"). For example, when the multiplexer 722 is configured to output 80 bits (as shown in 80 b ) and receives bits from the 20-bit adder 714E (e.g., two 21-bit bits), the multiplexer 722 can provide an 80-bit output including 42 bits (32A_out0, 32A_out1) from the 20-bit adder 714E and 38 bits of "0." Similarly, when the multiplexer 722 is configured to output 80 bits (as shown in 80 b ) and receives bits from the 21-bit adder 714E (e.g., one 22-bit bit), the multiplexer 722 can provide an 80-bit output including 22 bits (64A_out0) and 58 bits of "0." FIG8 illustrates an example selection circuit 800 coupled to configurable circuit 200 , according to some embodiments of the present disclosure. In some embodiments, selection circuit 800 may be coupled to multiplexer 222 to receive the addition result from adder circuit 214 and provide the result to multiplexer 222 . In some embodiments, selection circuit 800 may include a first circuit 801 for receiving and outputting a first set of bits (e.g., 64A×1) in response to enabling the corresponding adder (e.g., 16A, 32A, 64A). In response to disabling at least one adder (e.g., 64A), selection circuit 800 may include a second circuit 802 for receiving and outputting a second set of bits (e.g., 32A×2). As shown, in some examples, selection circuit 800 may include a plurality of circuit components (e.g., switches, transistors, etc.) to receive a set of bits from adder circuit 214 and output them to multiplexer 222. For example, selection circuit 800 may receive control signals (e.g., signal 221 from control circuit 220), such as 32A_EN and 32_ENB, and select either the first circuit or the second circuit to provide the received bits to multiplexer 222. Although described and illustrated for addition operations of 32A and 64A, respectively, selection circuit 800 may be used for any accumulation number (e.g., 8A, 16A, 32A, 64A, etc.). According to some embodiments of the present disclosure, FIG. 9A illustrates an example circuit 901 coupled to configurable circuit 200. In some embodiments, circuit 901 may include a D-type flip-flop (DFF) 905 and an adder 914. Adder 914 may have similar features to or be combined with adder circuit 214 or an adder therein. For example, adder 914 may be any of the 16-bit adder, 17-bit adder, 18-bit adder, 19-bit adder, 20-bit adder, 21-bit adder, or a combination thereof, in adder circuit 714. DFF 905 may be used to store binary data while adder 914 performs an addition operation. In some embodiments, DFF 905 may synchronize and store intermediate results as data propagates through adder 914 during the addition operation. The output of adder 914 can be fed back to DFF 905 via first path 930 as an input to DFF 905 and added to the previously stored data in DFF 905 via adder 914. Circuit 901 can be configured to repeat (e.g., N cycles) the addition operation via first path 930 until a predetermined condition (e.g., a cycle requirement) is met. When the cycle condition is met, adder 914 can provide an output via second path 940. FIG. 9B illustrates an example signal diagram associated with circuit 901 according to some embodiments of the present disclosure. In some embodiments, N accumulations require N cycles. For example, 8 accumulations require 8 cycles, 16 accumulations require 16 cycles, 32 accumulations require 32 cycles, and 64 accumulations require 64 cycles. That is, for example, when adder 914 performs 8 accumulations, adder 914 and DFF 905 can be used to perform 8-cycle additions via first route 930 and then output the result of the addition via second route 940, thereby calculating P0+P1+P2+P3+P4+P5+P6+P7. Similarly, when adder 914 performs 16 accumulations, adder 914 and DFF 905 can be used to perform 16-cycle additions via first route 930 and then output the result of the addition via second route 940, thereby calculating P0+…+P14+P15. Likewise, when the adder 914 performs 64 accumulation addition operations, the adder 914 and the DFF 905 can be used to perform 64 cycles of addition operations via the first path 930 and then output the addition result via the second path 940, thereby calculating P0+...+P62+P63. FIG. 10 illustrates a flow chart of an example method 1000 for operating a configurable circuit, according to various embodiments. Example method 1000 may be performed using circuit 200 or one or more components of circuit 200. Therefore, the following embodiments of method 1000 may be described in conjunction with, but not limited to, at least one of FIG. 1 through FIG. 9B. The illustrated embodiments of method 1000 are provided as examples and do not limit the scope of one embodiment of the present disclosure. Therefore, it is understood that various operations of method 1000 may be omitted, reordered, and / or added without departing from the scope of one embodiment of the present disclosure. In brief overview, method 1000 may begin at step 1010 by receiving a plurality of input data bits into a computing circuit. Method 1000 may proceed to step 1020 by determining a cumulative number associated with the data bits. Method 1000 may proceed to step 1030 by determining whether to enable or disable at least one component of the computing circuit based on the cumulative number. Method 1000 may proceed to step 1040 by generating a control signal to enable or disable at least one component of the computing circuit based on the enable or disable determination. In step 1010, a computing circuit (e.g., configurable circuit 200) may receive a plurality of input data bits (e.g., psums shown in FIG. 2). For example, the first component of the computing circuit (e.g., 19-bit adder 714D) may receive 64 psums. At step 1020, the computation circuitry may determine a summation number (e.g., 8A, 16A, 32A, 64A, etc.) associated with a plurality of input data bits. In some embodiments, the computation circuitry may determine an addition operation to be performed (e.g., 8A, 16A, 32A, 64A, etc.) based on the received input data bits (e.g., psums). In some embodiments, the computation circuitry may be configured to determine whether to perform an addition operation on a point-by-point convolutional layer (e.g., with a high summation number (e.g., 16, 32, 64, etc.) or a channel-by-channel convolutional layer (e.g., with a low summation number (e.g., 8, etc.)). During step 1030, the computing circuit may determine whether to enable or disable at least one component of the computing circuit (e.g., at least one of the N+2-bit adder 416C, the N+3-bit adder 416B, the N+4-bit adder 416A, etc.). At step 1040, based on the enable / disable determination, the computing circuit may generate a control signal (e.g., signal 221) to enable or disable the at least one component of the computing circuit. For example, when the control signal indicates a first cumulative number (e.g., 16A), the computing circuit may disable the at least one component (e.g., the N+3-bit adder 416B and the N+4-bit adder 416A in FIG. 4A ). For example, when the control signal indicates a second cumulative number (e.g., 32A), the computing circuit may disable the at least one component (e.g., the N+4-bit adder 416A in FIG. 4A ). For example, when the control signal indicates the third cumulative number (e.g., 64A), the calculation circuit may enable at least one component (e.g., N+2-bit adder 416C, N+3-bit adder 416B, and N+4-bit adder 416A in FIG. 4A ). FIG. 11 illustrates a flow chart of an example method 1100 for operating a configurable circuit, according to various embodiments. Example method 1100 may be performed using circuit 200 or one or more components of circuit 200. Therefore, embodiments of method 1100 described below may be combined with, but not limited to, at least one of FIG. 1 through FIG. 9B. The illustrated embodiments of method 1100 are provided as examples and do not limit the scope of one embodiment of the present disclosure. Therefore, it is understood that various operations of method 1100 may be omitted, reordered, and / or added without departing from the scope of one embodiment of the present disclosure. In brief overview, method 1100 may begin at step 1110 by receiving 64 psums. Method 1100 may proceed to step 1120 to determine a cumulative number associated with the received psums and determine a pattern in the cumulative number. Method 1100 may proceed to step 1130 to sum the received psums. Method 1100 may proceed to step 1140 to generate a MAC operation output based on the sum of the psums. At step 1110, an adder circuit (e.g., adder circuit 214) may receive 64 psums. At step 1120, a control circuit (e.g., control circuit 220) may determine the cumulative number associated with the 64 received psums (e.g., 8A, 16A, 32A, 64A, etc.). In some embodiments, the control circuit may generate control signals representing four modes (e.g., as shown in FIG. 6B ), each control signal indicating whether to enable or disable an adder. For example, when the control signal indicates 64A, adders for 16A, 32A, and 64A may be enabled (e.g., by setting 16A_EN, 32A_EN, and 64A_EN to "1"). When the control signal indicates 32A, adders for 16A and 32A may be enabled (e.g., by setting 16A_EN and 32A_EN to "1"), and adder for 64A may be disabled (set to "0"). When the control signal indicates 16A, the adder for 16A may be enabled (eg, by setting 16A_EN to "1") and the adders for 32A and 64A may be disabled (set to "0"). In steps 1130A to 1130C, the psums may be summed according to the control signal indicating the cumulative number. When the control signal indicates 64A, all 64 psums may be summed, thereby generating one MAC operation output in step 1140A. When the control signal indicates 32A, two groups of 32 psums may be summed, thereby generating two MAC operation outputs in step 1140B. When the control signal indicates 16A, four groups of 16 psums may be summed, thereby generating four MAC operation outputs in step 1140C. Although not shown, when the control signal indicates 8A, eight groups of eight psums may be summed, thereby generating eight MAC operation outputs. In one aspect of one embodiment of the present disclosure, a circuit is disclosed. The system includes a computing circuit, a memory array operatively coupled to the computing circuit, and a controller configured to input a plurality of input data bits to the computing circuit, determine a cumulative number associated with the input data bits, determine whether to enable or disable at least one component of the computing circuit based on the cumulative number, and generate a control signal for enabling or disabling the at least one component of the computing circuit based on the enable / disable determination result. In one aspect of one embodiment of the present disclosure, a device is disclosed. The device includes a computing circuit operatively coupled to a memory array, the computing circuit including a first component for receiving a plurality of input data bits in response to a control signal and providing a first output, a second component for receiving the first output from the first component in response to a control signal having a first logic value and providing a second output, and a multiplexer for outputting the first output in response to the control signal having the second logic value and for outputting the second output in response to the control signal having the first logic value. In another aspect of an embodiment of the present disclosure, a method is disclosed. The method includes receiving a plurality of input data bits to a computing circuit, determining a cumulative number associated with the input data bits, determining whether to enable or disable at least one component of the computing circuit, and generating a control signal for enabling or disabling the at least one component of the computing circuit based on the enabling or disabling determination. As used herein, the terms "about" and "substantially" generally refer to a value of a given quantity that may vary depending on the particular technology node associated with the subject semiconductor. Based on the particular technology node, the term "about" may refer to a value of a given quantity that varies within a range of 10-30% of that value (e.g., +10%, ±20%, or ±30% of that value). The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of one embodiment of the present disclosure. Those skilled in the art will appreciate that they can readily use one embodiment of the present disclosure as a basis for designing or modifying other processes and structures for achieving the same objectives and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of one embodiment of the present disclosure, and that they may make various changes, substitutions, and replacements herein without departing from the spirit and scope of one embodiment of the present disclosure. 100: Data calculation circuit 102: Memory circuit 103: Storage element 104: Input circuit 106: Multiplier circuit 108: Adder circuit 110: Differential circuit 111: Selector circuit 112: Shift circuit 114: Adder circuit / Adder tree 115: Sum 116: First converter 118: Second converter 120: Control circuit / Comparator circuit 122: Output multiplexer A 1: Logic Gate B 1: Logic Gate M 1: Logic gate L 1: Logic Gate InDE: Input Data Element InS: Signed Bit InM: Mantissa InTc: Mantissa InE: Exponent WtDE: Weighted Data Element WtS: Signed Bit WtM: Mantissa WtTc: Mantissa WtE: Exponent MaxExp: Maximum Exponent Sum PSTC: Sum PSSM: Sum PS: Sum C[1]: Control Signal C[N]: Control Signal D[1]: Difference D[N]: Difference P[1]: Product P[N]: Product S[1]: Exponential Sum S[N]: Exponential Sum SP[w]: Shift Product SP[z]: Shift Product SP[,]-SP[N]: shift product 200: configurable circuit 214: adder circuit 220: control circuit 221: signal 222: multiplexer MAC: multiplication-accumulation operation psums: partial sum psum: partial sum N: quantity 300: configurable circuit 314: adder circuit 321: signal 322: multiplexer 16A_EN: signal 32A_EN: signal 64A_EN: signal psum0: partial sum psum1: partial sum psum2: partial sum psum3: partial sum psum4: partial sum psum5: partial sum psum60: partial sum psum61: partial sum psum62: partial sum psum63: partial sum 414: adder circuit 416A: N+4-bit adder 416B: N+3-bit adder 416C : N+2 bit adder 16A: Indicates accumulation 32A: Indicates accumulation 64A: Indicates accumulation 551: First cycle 552: Second cycle 553: Third cycle psum0_cyc1: First cycle and psum1_cyc1: First cycle and psum62_cyc1: First cycle and psum63_cyc1: First cycle and psum0_cyc2: Second cycle and psum1_cyc2: Second cycle and psum62_cyc2: Second cycle and psum63_cyc2: Second cycle and psum0_cyc3: Third cycle and psum1_cyc3: Third cycle and psum62_cyc3: Third cycle and psum63_cyc3: Third cycle and 601: Logic circuit 602: Decoder bit Adder: Bit adder Disable: Disable Enable: Enable 651: Logic component mode[0]: Mode mode[1]: Mode 700: Configurable circuit 714: Adder circuit 714A: 16-bit adder 714B: 17-bit adder 714C: 18-bit adder 714D: 19-bit adder 714E: 20-bit adder 714F: 21-bit adder 721: Signal 722: Multiplexer 20b: A group of bits 21b: A group of bits 22b: A group of bits 80b: A group of bits 16A_out1: Output 16A_out2: Output 16A_out3: Output 32A_out0: Output 32A_out1: Output 64A_out0: Output 38'b000000…0: 38-bit 0 58'b000000…0: 58-bit 0 731A: Adder 731N: Adder 731N-1: Adder FA: Adder A, n :Enter A n-1 :Input A0:Input B n :Enter B n-1 : Input B0: Input S n : Operation result S n-1 : Operation result S0: Operation result CI: Carry CO: Carry output 800: Selection circuit 801: First circuit 802: Second circuit 32A_ENB: Signal 32 accu: 32 accumulations 901: Circuit 905: D-type flip-flop 914: Adder 930: First route 940: Second route P0~P63: Partial sum 1000: Method 1010: Step 1020: Step 1030: Step 1040: Step 1100: Method 1110: Step 1120: Step 1130A: Step 1130B: Step 1130C: Step 1140A: Step 1140B: Step 1140C: Step The various aspects of one embodiment of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is important to note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. FIG1 is a block diagram of a data calculation circuit according to some embodiments of the present disclosure; FIG2 is a block diagram of an example data calculation circuit (hereinafter referred to as a "configurable circuit") according to some embodiments of the present disclosure; FIG3 is a schematic diagram of an example configurable circuit according to some embodiments of the present disclosure; FIG4A is a schematic diagram of an example adder circuit according to some embodiments of the present disclosure; FIG4B is a table showing example states of components of the adder circuit shown in FIG4A at different accumulation numbers according to some embodiments of the present disclosure; FIG5 is an example diagram of signals associated with the adder circuit shown in FIG4A according to some embodiments of the present disclosure; FIG6A is an example logic circuit that can be coupled to the configurable circuit shown in FIG2 according to some embodiments of the present disclosure; FIG6B is a table showing example patterns of accumulation numbers and corresponding control signals according to some embodiments of the present disclosure; FIG6C is an example logic component that can be coupled to the configurable circuit shown in FIG2 according to some embodiments of the present disclosure; FIG7A is a block diagram of an example configurable circuit according to some embodiments of the present disclosure; Figure 7B is a table listing the example control signals and corresponding outputs of the multiplexer shown in Figure 7A according to some embodiments of the present disclosure; Figure 7C is a block diagram of the adder circuit shown in Figure 7A according to some embodiments of the present disclosure; Figure 7D is a table listing the example bit numbers of different adders shown in Figure 7A according to some embodiments of the present disclosure; Figure 8 is an example selection circuit that can be coupled to the configurable circuit shown in Figure 2 according to some embodiments of the present disclosure; Figure 9A is an example circuit that can be coupled to the configurable circuit shown in Figure 2 according to some embodiments of the present disclosure; Figure 9B is an example diagram of signals associated with the circuit shown in Figure 9A according to some embodiments of the present disclosure; Figure 10 is a flowchart of an example method of operating a configurable circuit according to various embodiments; and Figure 11 is a flowchart of an example method of operating a configurable circuit according to various embodiments. Domestic deposit information (please note in the order of deposit organization, date, and number) None Foreign deposit information (please note in the order of deposit country, organization, date, and number) None 100: Data calculation circuit 102:Memory Circuit 103: Storage element 104: Input circuit 106:Multiplier circuit 108: Adding circuit 110: Differential Circuit 111: Selector circuit 112: Displacement Circuit 114: Adder Circuit / Adder Tree 115: and 116: First converter 118: Second converter 120: Control circuit / comparator circuit 122: Output multiplexer A 1: Logic Gate B 1: Logic Gate M 1: Logic Gate L 1: Logic Gate InDE: Input Data Element InS: Signed bit InM: tail number InTc: tail number InE: Index WtDE: Weighted Data Element WtS: Signed bit WtM: tail number WtTc: tail number WtE: Index MaxExp: Maximum exponential sum PSTC: and PSSM: and PS: and C[1]: control signal C[N]: control signal D[1]: Difference D[N]: Poor P[1]: product P[N]: Product S[1]: exponential sum S[N]: exponential sum SP[w]: displacement product SP[z]: displacement product SP[,]-SP[N]: displacement product

Claims

1. A system with a configurable adder circuit, comprising: A computing circuit; A memory array is operatively coupled to the computing circuit; A controller is configured to: input a plurality of input data bits to the computing circuit; determine a cumulative quantity associated with the input data bits; determine, based on the cumulative quantity, whether to enable or disable at least one component of the computing circuit; and generate a control signal for enabling or disabling the at least one component of the computing circuit based on an enable or disable determination result; and a multiplexer is configured to: receive a plurality of bits from a plurality of components of the computing circuit, the components including the at least one component; and configure a plurality of output bits based on the cumulative quantity and the bits, wherein when a number of bits from the components is less than a number of output bits, the controller is configured to set at least one bit of the output bits to a logic state.

2. The system as described in claim 1, further comprising: A first circuit for outputting a first set of bits in response to the at least one component activating the computing circuit; And a second circuit for outputting a second set of bits in response to disabling the computing circuitry at least one component.

3. The system as described in claim 1, further comprising: At least one logic circuit component associated with a plurality of logic values, each of which indicates a number of the at least one component that is disabled in the computing circuit.

4. An apparatus for configuring an adder circuit, comprising: A memory array; A controller used to generate a control signal; A computing circuit operatively coupled to the memory array includes: a first component for receiving a plurality of input data bits and providing a first output in response to a control signal; a second component for receiving the first output from the first component and providing a second output in response to a control signal including a first logic value; and a multiplexer for outputting the first output in response to a control signal including a second logic value and for outputting the second output in response to the control signal including the first logic value, wherein when the number of bits of the first output is less than the number of bits of the second output, the controller is configured to set at least one bit of the second output to a logic state.

5. The apparatus as claimed in claim 4, wherein the second component is disabled in response to a control signal including the second logic value.

6. The apparatus as claimed in claim 4, wherein the control signal includes a first signal including the first logic value at a first time and a second signal including the second logic value at a second time.

7. A method for configuring an adder circuit, comprising: Receive a plurality of input data bits through a computing circuit; determine a cumulative quantity associated with these input data bits; Based on the accumulated quantity, determine whether to enable or disable at least one component of the computing circuit; based on the enable or disable determination result, generate a control signal to enable or disable the at least one component of the computing circuit; receive a plurality of bits from a plurality of components of the computing circuit, including the at least one component, through a multiplexer; and configure a plurality of output bits through the multiplexer based on the accumulated quantity and the bits, wherein when a number of bits from the components is less than a number of output bits, a controller sets at least one bit of the output bits to a logic state.

8. The method as described in claim 7, wherein the computing circuit includes an addition component, and wherein the method further includes enabling or activating the addition component.

9. The method as described in claim 7, further comprising: In response to enabling the computing circuit, the at least one component outputs a first set of bits of the output bits; And a second set of bits that outputs the output bits in response to disabling the computing circuitry.

10. The method as described in claim 7, wherein the control signal is a first control signal provided at a first time to disable a first number of the components of the computing circuit, the method further comprising: A second control signal is generated at a second time to disable a second number of components of the computing circuit, the second number being different from the first number.

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