Semiconductor memory devices

Abstract

This invention provides a semiconductor memory device that reduces the number of sensing operations. One embodiment of the semiconductor memory device includes a memory cell, a word line WLsel connected to the memory cell, a bit line connected to the memory cell, and a sensing amplifier. The sensing amplifier includes a first node SEN connected to the bit line, which senses a first voltage at the first node when charge charged to the first node is discharged to the bit line. A write operation performed on the memory cell includes a programming operation and a verification operation. During the verification operation, while a verification voltage VH is applied to the word line, the sensing amplifier performs a first sensing operation at a first voltage level VM as the first sensing operation. Based on the result of the first sensing operation, it performs a second sensing operation at a second voltage level VH or a third sensing operation at a third voltage level VL as the second sensing operation.

Description

Semiconductor memory devices The embodiments of the present invention relate to a semiconductor memory device. As a semiconductor memory device, NAND (Not And) type flash memory is known. In NAND type flash memory, a programming operation is performed that raises the threshold voltage when data is written to the transistor of the memory cell, and a verification operation is performed to confirm the threshold voltage. A semiconductor memory device is provided that can reduce the number of sensing operations. A semiconductor memory device according to an embodiment includes: a first memory cell configured to a first threshold voltage; a second memory cell configured to a second threshold voltage; a word line commonly connected to the first memory cell and the second memory cell; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sensing amplifier including a first node connected to the first bit line, determining the first threshold voltage of the first memory cell based on a first voltage of the first node when a charge charged to the first node is discharged to the first bit line; and a second sensing amplifier including a second node connected to the second bit line, determining the second threshold voltage of the second memory cell based on a second voltage of the second node when a charge charged to the second node is discharged to the second bit line; and the semiconductor memory device is capable of... The first memory cell and the second memory cell perform a write operation that includes programming and verification operations. During the first period of the verification operation, the first sensing amplifier performs a first sensing operation to determine whether the first threshold voltage of the first memory cell is above a first voltage level, and the second sensing amplifier performs a second sensing operation to determine whether the second threshold voltage of the second memory cell is above the first voltage level. During the second period of the verification operation, which is later than the first period, the first sensing amplifier performs a third sensing operation to determine whether the first threshold voltage of the first memory cell is above a second voltage level that is higher than the first voltage level, and the second sensing amplifier performs a fourth sensing operation to determine whether the second threshold voltage of the second memory cell is above a third voltage level that is lower than the first voltage level. The embodiments will now be described with reference to the drawings. The dimensions and scale of the drawings may not be the same as those in reality. Furthermore, in the following description, constituent elements with substantially the same function and structure are labeled with the same symbols. When it is necessary to distinguish between constituent elements with the same structure, different text or numbers will be added to the end of the same symbol. 1. The first embodiment describes the semiconductor memory device of the first embodiment. 1.1 Configuration 1.1.1 Configuration of the memory system The configuration of the memory system including the semiconductor memory device of the first embodiment will be described using FIG1. ​​FIG1 is a block diagram showing an example of the configuration of the memory system including the semiconductor memory device of the first embodiment. Memory system 1 is a device that stores data. Memory system 1 can be, for example, an SSD (solid-state drive), a UFS (Universal Flash Storage) device, a USB (Universal Serial Bus) memory, an MMC (Multi-Media Card), or an SD card. TM The memory system 1 can be connected to the host 2 via a host bus. The memory system 1 processes data based on request signals received from the host 2 or on its own processing requests. Request signals are requests for various actions, such as write, read, and erase operations. Host 2 is a device that controls memory system 1. Host 2 can be, for example, a personal computer, server system, mobile device, vehicle device, or digital camera. Next, the internal structure of the memory system 1 will be described. As shown in Figure 1, the memory system 1 includes a memory controller 10 and a semiconductor memory device 30. The semiconductor memory device 30 is, for example, a non-volatile memory such as NAND flash memory. Hereinafter, the semiconductor memory device 30 will be referred to as NAND flash memory 30. The memory controller 10 is a device that controls the NAND flash memory 30. The memory controller 10 is, for example, a System-on-a-Chip (SoC). The memory controller 10 is connected to the host 2 via the host bus. The memory controller 10 receives request signals from the host 2 via the host bus. Furthermore, the memory controller 10 sends information to the host 2 via the host bus. The type of host bus depends on the application running in memory system 1. When memory system 1 is an SSD, the host bus could be, for example, SAS (Serial Attached SCSI), SATA (Serial ATA), or PCIe. TMThe interface is based on the Peripheral Component Interconnect Express (PMI) standard. When memory system 1 is a UFS device, the M-PHY standard interface can be used as the host bus. When memory system 1 is USB memory, the USB standard interface can be used as the host bus. When memory system 1 is MMC, the eMMC (Embedded Multi Media Card) standard interface can be used as the host bus. When memory system 1 is an SD card... TM In the case of a card, an SD card can be used as the host bus. TM Specifications and interfaces. The memory controller 10 controls the NAND flash memory 30 via the NAND bus based on request signals received from the host 2 or spontaneous processing requests. For example, the memory controller 10 performs data transmission and reception, as well as instruction and address transmission, with the NAND flash memory 30. The NAND bus performs signal transmission and reception compliant with the NAND interface. NAND flash memory 30 is a data storage device. NAND flash memory 30 includes a plurality of memory cell transistors. Each of the plurality of memory cell transistors stores data non-volatilely. NAND flash memory 30 performs write, read, and erase operations based on instructions and addresses received from memory controller 10. During a write operation, NAND flash memory 30 non-volatilely stores the data received from memory controller 10 into the plurality of memory cell transistors. During a read operation, NAND flash memory 30 outputs the data read from the plurality of memory cell transistors to memory controller 10. Next, the internal structure of the memory controller 10 will be described. The memory controller 10 includes a host interface (I / F) circuit 11, a processor (CPU: Central Processing Unit) 12, a buffer memory 13, an ECC (Error Checking and Correcting) circuit 14, a ROM (Read Only Memory) 15, a RAM (Random Access Memory) 16, and a NAND interface (I / F) circuit 17. The host interface circuit 11 is responsible for communication between the memory controller 10 and the host 2. The host interface circuit 11 is connected to the host 2 via the host bus. Processor 12 is the control circuit for memory controller 10. Processor 12 controls the operation of memory controller 10 by executing programs (firmware) stored in ROM 15. For example, once processor 12 receives a write request from host 2, it controls the write operation accordingly. The same applies to read and erase operations. Buffer memory 13 is a memory that temporarily stores data. Buffer memory 13 is, for example, SRAM (Static Random Access Memory). Buffer memory 13 temporarily stores data written to and data read from. Data written to refers to data written to NAND flash memory 30. Data read from refers to data read from NAND flash memory 30. ECC circuit 14 is a circuit that performs data error correction processing. Specifically, during a data write operation, ECC circuit 14 generates an error correction code based on the written data. Then, during a data read operation, ECC circuit 14 generates a corrector based on the error correction code in a predetermined unit to detect and correct errors. ROM15 is non-volatile memory. For example, ROM15 could be an EEPROM. TM (Electrically Erasable Programmable Read-Only Memory). ROM15 memory firmware and other programs. RAM16 is a volatile memory. RAM16 is, for example, SRAM. RAM16 is used as the operating area of ​​processor 12. RAM16 stores the firmware and various management information of NAND flash memory 30. The NAND interface circuit 17 is responsible for communication between the memory controller 10 and the NAND flash memory 30. The NAND interface circuit 17 is connected to the NAND flash memory 30 via the NAND bus. For example, the NAND interface circuit 17 controls the transmission of data, instructions, and addresses between the memory controller 10 and the NAND flash memory 30. 1.1.2 Configuration of NAND Flash Memory The configuration of NAND flash memory 30 will be explained using Figure 2. Figure 2 is a block diagram showing an example of the configuration of NAND flash memory 30. Figure 2 also shows the memory controller 10. As shown in Figure 2, the NAND flash memory 30 includes an input / output circuit 31, a logic control circuit 32, a ready / busy circuit 33, a temporary register 34, a sequencer 35, a memory cell array 36, a voltage generation circuit 37, a column decoder module 38, a sense amplifier 39, and a data bus circuit 40. The input / output circuit 31 is a circuit that transmits and receives signals and information with the memory controller 10. The input / output circuit 31 transmits and receives input / output signals DQ (e.g., 8-bit signals DQ0 to DQ7) and data strobe signals DQS and DQSn (inverted signals of signal DQS) with the memory controller 10. Signal DQ is the physical data transmitted and received between the NAND flash memory 30 and the memory controller 10. Signal DQ may include, for example, instructions (CMD), addresses (ADD), status information (STS), and data (DAT). Signals DQS and DQSn are signals used to control the transmission and reception timing of signal DQ. For example, during data writing, the signal DQ containing the data being written, along with signals DQS and DQSn, are sent from the memory controller 10 to the NAND flash memory 30. The NAND flash memory 30 synchronously receives the signal DQ containing the data being written, along with signals DQS and DQSn. Similarly, during data reading, the signal DQ containing the data being read, along with signals DQS and DQSn, are sent from the NAND flash memory 30 to the memory controller 10. The memory controller 10 synchronously receives the signal DQ containing the data being read, along with signals DQS and DQSn. Furthermore, the input / output circuit 31 can also receive signals DQS and DQSn from the memory controller 10 via the logic control circuit 32. Furthermore, input / output circuit 31 sends the instruction CMD within signal DQ to instruction register 34A. Input / output circuit 31 sends the address ADD within signal DQ to address register 34B. Input / output circuit 31 receives status information STS from status register 34C. Input / output circuit 31 and data bus circuit 40 transmit and receive data DAT within signal DQ. The logic control circuit 32 controls the input / output circuit 31 and the sequencer 35 based on control signals. The logic control circuit 32 receives the chip enable signal CEn, the instruction latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the read enable signal REn from the memory controller 10. Signal CEn is used to enable the NAND flash memory 30. Signal CLE indicates that the signal DQ received by the NAND flash memory 30 is the instruction CMD signal. Signal ALE indicates that the signal DQ received by the NAND flash memory 30 is the address ADD signal. Signal WEn commands the NAND flash memory 30 to input the signal DQ. Signal REn commands the NAND flash memory 30 to output the signal DQ. Based on signal REn, the NAND flash memory 30 generates signals DQS and DQSn. The NAND flash memory 30 outputs signal DQ to the memory controller 10 based on the generated signals DQS and DQSn. The logic control circuit 32 controls the input / output circuit 31 and the sequencer 35 based on the received control signals. The ready / busy circuit 33 informs the memory controller 10 of the operating status of the sequencer 35. Based on the operating status of the sequencer 35, the ready / busy circuit 33 sends a ready / busy signal RBn to the memory controller 10. The signal RBn indicates whether the NAND flash memory 30 is in a ready or busy state. For example, when the NAND flash memory 30 is in a busy state, the signal RBn is at a "low" level. The ready state is the state in which the NAND flash memory 30 can receive instructions from the memory controller 10. The busy state is the state in which the NAND flash memory 30 cannot receive instructions from the memory controller 10. Register 34 is a circuit that temporarily stores information. Register 34 includes instruction register 34A, address register 34B, and status register 34C. Instruction register 34A is a circuit that stores instruction CMD. Instruction CMD may include commands that cause sequencer 35 to perform read, write, and erase operations. Address register 34B is a circuit that stores addresses ADD. Address ADD includes, for example, column address RA (including block address and page address) and row address CA. The block address, page address, and row address CA are used, for example, to select block BLK, word line, and bit line, respectively. For example, address register 34B transmits column address RA to column decoder module 38. Address register 34B transmits row address CA to sense amplifier 39. The status register 34C is, for example, a circuit for temporarily storing status information STS during read, write, and erase operations. The status information STS is used to notify the memory controller 10 whether the operation has been completed normally. The sequencer 35 is a circuit that controls the operation of other circuits according to a pre-determined program. The sequencer 35 controls the operation of the entire NAND flash memory 30. For example, based on the instruction CMD stored in the instruction register 34A, the sequencer 35 controls the ready / busy circuit 33, the voltage generation circuit 37, the column decoder module 38, the sense amplifier 39, and the data bus circuit 40. For example, the sequencer 35 performs read operations, write operations, and erase operations. The memory cell array 36 comprises a plurality of blocks BLK0 to BLKn (n being an integer greater than or equal to 1). Hereinafter, unless it is necessary to distinguish between blocks BLK0 to BLKn, they will be simply referred to as blocks BLK. A block BLK is, for example, a collection of a plurality of memory cell transistors whose data is erased in one operation. For example, a block BLK is used as a unit for data erasure operations. The memory cell array 36 is provided with a plurality of bit lines and a plurality of word lines. A memory cell transistor is associated with, for example, one bit line and one word line. Details regarding the memory cell array 36 will be described below. The voltage generation circuit 37 is a circuit that generates the voltage used in various operations. The voltage generation circuit 37 supplies the generated voltage to, for example, the column decoder module 38 and the sensing amplifier 39. The column decoder module 38 is a circuit that selects one block BLK within the memory cell array 36 based on the column address RA. The column decoder module 38 transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line within the selected block BLK. The sense amplifier 39 is a circuit that determines the data stored in the memory cell transistor. During the read operation, the sense amplifier 39 determines the data stored in the memory cell transistor based on the voltage of the bit line. The sense amplifier 39 transmits the determination result as read data DAT to the data bus circuit 40. Furthermore, during the write operation, the sense amplifier 39 applies a voltage to the bit line based on the write data DAT received from the input / output circuit 31 via the data bus circuit 40. The data bus circuit 40 is a circuit that transmits data between the input / output circuit 31 and the sensing amplifier 39. Furthermore, as shown in FIG2, the NAND flash memory 30 includes an array chip 100 and a circuit chip 200. In this embodiment, the NAND flash memory 30 has a structure in which the array chip 100 and the circuit chip 200 are bonded together (hereinafter referred to as "bonding structure"). The array chip 100 is a chip equipped with a memory cell array 36. The circuit chip 200 is a chip equipped with an input / output circuit 31, a logic control circuit 32, a ready / busy circuit 33, a temporary register 34, a sequencer 35, a voltage generation circuit 37, a column decoder module 38, a sense amplifier 39, and a data bus circuit 40. Furthermore, multiple array chips 100 can be provided. In this case, multiple array chips 100 can be laminated onto the circuit chip 200 in a multilayer manner. 1.1.3 Circuit Configuration of Memory Cell Array The circuit configuration of memory cell array 36 will be explained using Figure 3. Figure 3 is a circuit diagram showing an example of the circuit configuration of memory cell array 36. Figure 3 shows the circuit configuration of block BLK included in memory cell array 36 as an example of the circuit configuration of memory cell array 36. Other blocks BLK also have the same configuration as shown in Figure 3. As shown in Figure 3, a block BLK, for example, contains four string components SU0 to SU3. Hereinafter, unless it is necessary to distinguish between string components SU0 to SU3, they will be simply referred to as string component SU. A string component SU is, for example, a collection of multiple NAND strings NS selected at once during a write or read operation. A string component SU contains multiple NAND strings NS associated with bit lines BL0 to BLm (m being an integer greater than or equal to 1). Hereinafter, unless it is necessary to distinguish between bit lines BL0 to BLm, they will be simply referred to as bit lines BL. NAND strings NS are collections of multiple memory cell transistors connected in series. Each NAND string NS, for example, contains memory cell transistors MC0 to MC7, and select transistors ST1 and ST2. Hereinafter, unless it is necessary to distinguish between memory cell transistors MC0 to MC7, they will be simply referred to as memory cell transistor MC. Memory cell transistor MC non-volatilely stores data. Memory cell transistor MC includes a control gate and a charge storage layer. Select transistors ST1 and ST2 are switching elements. Select transistors ST1 and ST2 are used to select the string assembly SU during various operations. In the NAND string NS, memory cell transistors MC0 to MC7 are connected in series. The drain of selector ST1 is connected to its associated bit line BL. The source of selector ST1 is connected to one end of the series-connected memory cell transistors MC0 to MC7. The drain of selector ST2 is connected to the other end of the series-connected memory cell transistors MC0 to MC7. The source of selector ST2 is connected to the source line SL. Within the same block BLK, the control gates of memory cell transistors MC0 to MC7 are all connected to word lines WL0 to WL7. Hereinafter, unless there is a need to distinguish between word lines WL0 to WL7, they will be abbreviated as word lines WL. The gates of each select transistor ST1 within serial modules SU0 to SU3 are all connected to select gate lines SGD0 to SGD3. Hereinafter, unless there is a need to distinguish between select gate lines SGD0 to SGD3, they will be abbreviated as select gate lines SGD. The gates of select transistors ST2 contained within the same block BLK are all connected to select gate line SGS. In the circuit configuration of the memory cell array 36 described above, the bit line BL is shared, for example, by a plurality of NAND strings NS that are assigned the same row address CA in a plurality of string components SU. The source line SL is shared, for example, among a plurality of blocks BLK. A collection of multiple memory cell transistors (MCs) connected to a common word line (WL) within a serial component (SU) is called a memory cell component (CU). A block (BLK) contains multiple memory cell components (CUs). The data stored in a memory cell component (CU), which contains multiple memory cell transistors (MCs) that each store 1 bit of data based on a threshold voltage, is equivalent to one page of data. Based on the number of bits of data stored by the memory cell transistors (MCs), a memory cell component (CU) can store more than two pages of data. The following will explain the case where the memory cell transistors (MCs) are TLCs (Triple Level Cells) that store 3 bits of data. Furthermore, the circuit configuration of the memory cell array 36 is not limited to the configuration described above. For example, the number of string components SU contained in the block BLK, the number of memory cell transistors MC contained in the NAND string NS, and the number of select transistors ST1 and ST2 can all be arbitrary. Hereinafter, the memory cell transistor MC will sometimes be referred to as memory cell MC. 1.1.4 Bonding Structure of NAND Flash Memory Figure 4 illustrates the outline of the bonding structure of the NAND flash memory 30. Figure 4 is a perspective view showing the outline of the bonding structure of the NAND flash memory 30. As shown in Figure 4, the array chip 100 is bonded to the circuit chip 200, for example, with its first surface P1. The array chip 100 and the circuit chip 200 each include a plurality of bonding pads BP disposed on opposite surfaces. In the bonding configuration, the bonding pads BP of the array chip 100 and the bonding pads BP of the circuit chip 200 are bonded together to form one bonding pad BP. In other words, the bonding pad BP is formed by bonding the electrodes (conductors) of the bonding pad BP disposed on the array chip 100 with the electrodes (conductors) of the bonding pad BP disposed on the circuit chip 200. Hereinafter, the surface on which the array chip 100 and the circuit chip 200 are bonded (hereinafter referred to as the "bonding surface") is designated as the XY plane. The bonding surface is, for example, the first surface P1 of the array chip 100. Directions orthogonal to each other on the XY plane are designated as the X direction and the Y direction. Furthermore, the direction approximately perpendicular to the XY plane and extending from the array chip 100 toward the circuit chip 200 is designated as the Z1 direction. The direction approximately perpendicular to the XY plane and extending from the circuit chip 200 toward the array chip 100 is designated as the Z2 direction. If it is not necessary to specify which direction, Z1 or Z2, it is designated as the Z direction. 1.1.5 Layout of the Array Chip Figure 5 illustrates the planar layout of the array chip 100. Figure 5 is a top view showing an example of the planar layout of the array chip 100. As shown in Figure 5, the array chip 100 includes a memory cell region MA and two word line connection regions WHUA. The memory cell region MA is used to house the memory cell array 36. The word line connection regions WHUA are used to connect the word lines WL to the column decoder module 38. The two word line connection regions WHUA are arranged, for example, along the X direction. The memory cell region MA is, for example, disposed between the two word line connection regions WHUA. 1.1.6 Circuit Chip Layout Figure 6 illustrates the planar layout of the circuit chip 200. Figure 6 is a top view showing an example of the planar layout of the circuit chip 200. As shown in Figure 6, the circuit chip 200 includes a sense amplifier region SAA, two peripheral circuit regions PCA, and two column decoder regions RDA. The sense amplifier region SAA is for housing the sense amplifier 39. The peripheral circuit regions PCA are for housing peripheral circuits such as the voltage generation circuit 37 and the data bus circuit 40. The two peripheral circuit regions PCA are arranged, for example, along the Y direction. The sense amplifier region SAA is, for example, positioned between the two peripheral circuit regions PCA. The sense amplifier region SAA and the two peripheral circuit regions PCA correspond to the memory cell region MA of the array chip 100. The column decoder regions RDA are for housing the column decoder module 38. The two column decoder regions RDA are, for example, arranged along the X direction. The sense amplifier region SAA and the two peripheral circuit regions PCA are, for example, positioned between the two column decoder regions RDA. The column decoder regions RDA correspond to the word line connection region WHUA of the array chip 100. 1.1.7 Cross-sectional structure of NAND flash memory The cross-sectional structure of NAND flash memory 30 is described below. Figure 7 is an example of a cross-sectional structure of a NAND flash memory 30, a cross-sectional view along line II of Figures 5 and 6. Figure 7 shows the structure in which the array chip 100 and the circuit chip 200 are bonded together. First, the array chip 100 will be described. As shown in Figure 7, the array chip 100 includes a plurality of wiring layers 101, an insulating layer 102, wiring layers 103, insulating layers 104 and 105, a passivation layer 121, a plurality of contact plugs CV, CT, CP1 and CP2, wiring layers 106, 107, 109 and 110, bonding pads 108 and 111, and a plurality of memory pillars MP. In the memory cell region MA, a plurality of (10) wiring layers 101 are stacked at intervals along the Z direction. The wiring layers 101 function as word lines (WL) and select gate lines (SGD and SGS). An insulating layer 102 is disposed between each wiring layer 101. An insulating layer 102 is disposed above the uppermost wiring layer 101. An insulating layer 102 is disposed below the lowermost wiring layer 101. The wiring layers 101 are made of conductive materials, such as metals, p-type semiconductors, or n-type semiconductors. The insulating layers 102 are made of insulating materials, such as silicon oxide (SiO). A wiring layer 103 is disposed on the uppermost insulating layer 102. The wiring layer 103 is formed, for example, in the form of a plate extending along the XY plane, and functions as a source line SL. The wiring layer 103 is made of a conductive material, such as phosphorus-doped silicon, tungsten silicate, or titanium nitride. An insulating layer 104 is provided above the wiring layer 103. The insulating layer 104 is made of an insulating material, such as silicon oxide. An insulating layer 105 is provided on top of the insulating layer 104. The insulating layer 105 is made of an insulating material, such as silicon oxide. A passivation layer 121 is provided on the insulating layer 105. The passivation layer 121 may contain, for example, polyimide. A plurality of memory pillars MP extend along the Z-direction, penetrating a plurality of wiring layers 101 and insulating layers 102. The Z2-direction end of the memory pillar MP is connected to wiring layer 103. The memory pillar MP includes, for example, a semiconductor film and an insulating film. The semiconductor film is connected to wiring layer 103. One memory pillar MP corresponds to one NAND string NS. Details about the memory pillar MP will be described below. The Z1-direction end of the memory pillar MP is connected to wiring layer 106 via a contact plug CV. The wiring layer 106, electrically connected to the memory pillar MP, functions as a bit line BL. The contact plug CV is made of a conductive material, such as a metal, p-type semiconductor, or n-type semiconductor. The wiring layer 106 is made of a conductive material, such as a metal, p-type semiconductor, or n-type semiconductor. Wiring layer 106 is electrically connected to bonding pad 108, for example, via contact plug CP1, wiring layer 107, and contact plug CP2. Bonding pad 108 is used for connection to circuit chip 200. Contact plugs CP1 and CP2 are made of conductive material, such as metal, p-type semiconductor, or n-type semiconductor. Wiring layer 107 is made of conductive material, such as metal, p-type semiconductor, or n-type semiconductor. Bonding pad 108 is made of conductive material, such as metal. Bonding pad 108 may contain, for example, copper (Cu). In the character line wiring area WHUA, a plurality of stepped portions of wiring layers 101 are arranged in a stepped manner. In the Z1 direction, contact plugs CT are disposed on the stepped portions of each of the plurality of wiring layers 101. In the Z1 direction, the contact plugs CT are connected to wiring layers 109. Wiring layers 109 are electrically connected to bonding pads 111, for example, via contact plugs CP1, wiring layers 110, and contact plugs CP2. Bonding pads 111 are used for connection to the circuit chip 200. Contact plugs CT are made of conductive materials, such as metal, p-type semiconductor, or n-type semiconductor. Wiring layers 109 and 110 are made of conductive materials, such as metal, p-type semiconductor, or n-type semiconductor. Bonding pads 111 are made of conductive materials, such as metal. Bonding pads 111 may contain copper, for example. Figure 8 is a cross-sectional view of the memory cylinder MP and its vicinity in the memory cell region MA of the array chip 100. Furthermore, the contact plugs CP1 and CP2, the wiring layer 107, and the bonding pad 108 are omitted in Figure 8. The portion where the memory column MP intersects with wiring layer 101 (select gate line SGS) functions as the select transistor ST2. The portion where the memory column MP intersects with one of the plurality of wiring layers 101 (word lines WL0 to WL7) functions as one memory cell transistor MC. The portion where the memory column MP intersects with wiring layer 101 (select gate line SGD) functions as the select transistor ST1. The memory column MP may include, for example, a core film 181, a semiconductor film 182, and a multilayer film 183. The core film 181 extends along the Z direction. For example, in the Z2 direction, the lower end of the core film 181 is located below the lowest wiring layer 101, and the upper end of the core film 181 is located below the wiring layer 103. The core film 181 is made of an insulating material, such as silicon oxide. Semiconductor film 182 covers the periphery of core film 181. At the upper end of the memory column MP in the Z2 direction, a portion of semiconductor film 182 is in contact with wiring layer 103. Semiconductor film 182 functions as a channel for memory cell transistor MC and select transistors ST1 and ST2 respectively. Semiconductor film 182 may contain silicon, for example. The stacked film 183 covers the sides and bottom of the semiconductor film 182, except for the portion where the semiconductor film 182 contacts the wiring layer 103. The stacked film 183 is, for example, a stacked film formed by sequentially stacking a first insulating layer 183a, a second insulating layer 183b, and a third insulating layer 183c. Figure 9 is an example of the cross-sectional structure of the memory column MP, a cross-sectional view along line SS in Figure 8. Specifically, Figure 9 shows the cross-sectional structure of the memory column MP in a layer parallel to the XY plane and containing wiring layer 101. The first insulating layer 183a covers the area surrounding the semiconductor film 182. The first insulating layer 183a functions as a tunnel insulating film for the memory cell transistor MC. The first insulating layer 183a is made of an insulating material, such as silicon oxide or silicon oxynitride. The second insulating layer 183b covers the area surrounding the first insulating layer 183a. The second insulating layer 183b functions as a charge storage layer for the memory cell transistor MC. The second insulating layer 183b is made of an insulating material, such as silicon nitride. The third insulating layer 183c covers the area surrounding the second insulating layer 183b. The third insulating layer 183c functions as a barrier insulating film for the memory cell transistor MC. The third insulating layer 183c is made of an insulating material, such as silicon oxide or aluminum oxide. The wiring layer 101 covers the area surrounding the third insulating layer 183c. Next, the circuit chip 200 will be described. As shown in Figure 7, the circuit chip 200 includes a semiconductor substrate 201, an insulating layer 202, wiring layers GC, 203-205 and 207-209, contact plugs CS and C0-C3, and bonding pads 206 and 210. Figure 7 also shows the transistors of the sense amplifier 39 disposed in the sense amplifier region SAA and the column decoder module 38 disposed in the column decoder region RDA. Semiconductor substrate 201 is used to form circuit chip 200, and may contain, for example, P-type impurities. Furthermore, semiconductor substrate 201 includes a plurality of well regions (not shown in the figure). Transistors are formed in each of the plurality of well regions, for example. Moreover, the plurality of well regions are separated, for example, by STI (Shallow Trench Isolation). An insulating layer 202 is disposed on semiconductor substrate 201. Insulating layer 202 is made of an insulating material, for example, silicon oxide. In the sense amplifier region SAA, a wiring layer GC is provided on the semiconductor substrate 201, separated by a gate insulating film. The wiring layer GC in the sense amplifier region SAA is used, for example, as the gate electrode of the transistor TR1 included in the sense amplifier 39. Corresponding to the gate of the transistor TR1, a contact plug C0 is provided on the wiring layer GC, and corresponding to the source and drain of the transistor TR1, two contact plugs CS are provided on the semiconductor substrate 201. For example, the upper surface of the contact plug CS is aligned with the upper surface of the contact plug C0. Furthermore, in the sense amplifier region SAA, one wiring layer 203 is provided on each of the contact plugs CS and C0. A contact plug C1 is provided on wiring layer 203. A wiring layer 204 is provided on contact plug C1. A contact plug C2 is provided on wiring layer 204. A wiring layer 205 is provided on contact plug C2. Wiring layer 205 functions as the wiring BLI included in the sense amplifier 39. A contact plug C3 is provided on wiring layer 205. A bonding pad 206 is provided on contact plug C3. The bonding pad 206 is used for connection with the array chip 100. The bonding pad 206 is bonded to the bonding pad 108 of the array chip 100. The sense amplifier region SAA includes a plurality of transistors having the same structure as the transistor TR1 of the sense amplifier 39 shown in FIG. 7, but the relevant illustrations are omitted. Wiring layers 203-205 are made of conductive material, such as metal, p-type semiconductor, or n-type semiconductor. Contact plugs CS and C0-C3 are made of conductive material, such as metal, p-type semiconductor, or n-type semiconductor. Adhesive pad 206 is made of conductive material, such as metal. Adhesive pad 206 may contain, for example, copper. In the column decoder region RDA, a wiring layer GC is disposed on the semiconductor substrate 201, separated by a gate insulating film. The wiring layer GC in the column decoder region RDA is used, for example, as the gate electrode of a transistor included in the column decoder module 38. Corresponding to the gate of the transistor, a contact plug C0 is disposed on the wiring layer GC, and corresponding to the source and drain of the transistor TR, two contact plugs CS are disposed on the semiconductor substrate 201. Furthermore, in the column decoder region RDA, one wiring layer 207 is provided on each of the contact plugs CS and C0. A contact plug C1 is provided on wiring layer 207. A wiring layer 208 is provided on contact plug C1. A contact plug C2 is provided on wiring layer 208. A wiring layer 209 is provided on contact plug C2. A contact plug C3 is provided on wiring layer 209. A bonding pad 210 is provided on contact plug C3. The bonding pad 210 is used for connection with the array chip 100. The bonding pad 210 is bonded to the bonding pad 111 of the array chip 100. The column decoder region RDA includes a plurality of transistors having the same structure as the transistors of the column decoder module 38 shown in FIG. 7, but the relevant illustrations are omitted. Wiring layers 207-209 are made of conductive material, such as metal, p-type semiconductor, or n-type semiconductor. The bonding pad 210 is made of a conductive material, such as a metal. The bonding pad 210 may contain copper, for example. 1.1.8 Configuration of the Sensing Amplifier The configuration of the sensing amplifier 39 will be explained using Figure 10. Figure 10 is a block diagram showing an example of the configuration of the sensing amplifier 39. Figure 10 also shows the data bus circuit 40. As shown in Figure 10, the sensing amplifier 39 includes sensing amplifier components SAU0 to SAUm and latching circuits XDL0 to XDLm. The sensing amplifier components SAU0 to SAUm and the latching circuits XDL0 to XDLm are associated with bit lines BL0 to BLm, respectively. Hereinafter, unless it is necessary to distinguish between the sensing amplifier components SAU0 to SAUm, they will be simply referred to as the sensing amplifier component SAU. Unless it is necessary to distinguish between the latching circuits XDL0 to XDLm, they will be simply referred to as the latching circuits XDL. The sensing amplifier component SAU is, for example, a current sensing amplifier component that senses the current flowing in the bit line BL. The latch circuit XDL is a circuit that temporarily stores read and write data. The latch circuit XDL is used to input and output data between the sense amplifier component SAU and the input / output circuit 31. The latch circuit XDL is connected to the corresponding sense amplifier component SAU via the bus DBUS. Furthermore, multiple sense amplifier components SAU can be connected to one latch circuit XDL. Also, the latch circuit XDL is connected to the data bus circuit 40 via the corresponding data lines IO. Next, the internal structure of the sense amplifier assembly (SAU) will be described. The sense amplifier assembly (SAU) includes, for example, a sense circuit (SAC) and latch circuits (SDL, ADL, BDL, CDL, DDL, EDL, and FDL). The sense circuit (SAC) and the latch circuits (SDL, ADL, BDL, CDL, DDL, EDL, and FDL) are commonly connected to the bus (LBUS). During a read operation, the sensing circuit SAC senses the data read from the corresponding bit line BL and determines whether the read data is "0" or "1". During a write operation, the sensing circuit SAC applies a voltage to the bit line BL based on the data stored in the latch circuits DDL, EDL, FDL, and SDL. The latch circuits SDL, ADL, BDL, and CDL are circuits that temporarily store read and write data. For example, during a read operation, data can be transferred from the self-sensing circuit SAC to any one of the latch circuits SDL, ADL, BDL, and CDL. Similarly, during a write operation, data can be transferred from the latch circuit XDL to any one of the latch circuits SDL, ADL, BDL, and CDL. The latch circuit DDL temporarily stores the result of the first sensing described below. The latch circuit EDL temporarily stores the result of the second sensing described below. The latch circuit FDL temporarily stores the result of the operation between the value stored in latch circuit DDL and the value stored in latch circuit EDL. The latch circuit SDL can also be used as a circuit to temporarily store the result of the operation between the value stored in latch circuit DDL and the value stored in latch circuit EDL. Furthermore, the configuration of the sense amplifier assembly (SAU) is not limited to this and can be modified in various ways. For example, the number of latching circuits in the sense amplifier assembly (SAU) can be designed based on the number of bits of data stored in one memory cell (MC). Next, the circuit configuration of the sense amplifier 39 will be described using FIG11. FIG11 is a circuit diagram showing an example of the circuit configuration of the sense amplifier 39. FIG11 shows one sense amplifier component SAU included in the sense amplifier 39. Other sense amplifier components also have the same configuration as FIG11. In the following description, unless it is not necessary to define the source and drain of the transistor, either the source or drain of the transistor will be referred to as "one end of the transistor", and the other one of the source or drain of the transistor will be referred to as "the other end of the transistor". As shown in Figure 11, in addition to the configuration shown in Figure 10, the sense amplifier 39 further includes a high-voltage n-channel MOS (Metal Oxide Semiconductor) transistor TR1 corresponding to each sense amplifier component SAU. In other words, a transistor TR1 is provided for each sense amplifier component SAU within the sense amplifier 39. One end of transistor TR1 is connected to the corresponding bit line BL. The other end of transistor TR1 is connected to wiring BLI. A control signal BLS is input to the gate of transistor TR1. The control signal BLS is generated, for example, by sequencer 35. Transistor TR1 is used, for example, to prevent the supply of high voltage to the sense amplifier assembly SAU. The sense amplifier assembly (SAU) includes a sense circuit (SAC), a precharge circuit (LBP), a bus switch (BSW), and seven latch circuits: SDL, ADL, BDL, CDL, DDL, EDL, and FDL. First, the circuit configuration of the sensing circuit SAC will be explained. The sensing circuit SAC includes n-channel MOS transistors TR2, TR3, TR5, TR7, TR9 to TR11 and TR13 to TR17, p-channel MOS transistors TR4, TR6, TR8 and TR12, and capacitor elements C21 and C22. One end of transistor TR2 is connected to wiring BLI. The other end of transistor TR2 is connected to node SCOM. A control signal BLC is input to the gate of transistor TR2. The control signal BLC is generated, for example, by sequencer 35. Transistor TR2 is used, for example, to clamp the corresponding bit line BL to a voltage corresponding to the control signal BLC. One end of transistor TR3 is connected to node SCOM. The other end of transistor TR3 is connected to one end of transistor TR4. A control signal BLX is input to the gate of transistor TR3. The control signal BLX is generated, for example, by sequencer 35. Apply a voltage VHSA to the other end of transistor TR4. Voltage VHSA is, for example, the power supply voltage VCC. The gate of transistor TR4 is connected to the node INV_S below. One end of transistor TR5 is connected to one end of transistor TR4. A voltage SRCGND is applied to the other end of transistor TR5. The voltage SRCGND is, for example, the ground voltage VSS. The gate of transistor TR5 is connected to node INV_S. One end of transistor TR6 is connected to node SCOM. The other end of transistor TR6 is connected to one end of transistor TR7. A control signal BLP is input to the gate of transistor TR6. The control signal BLP is generated, for example, by sequencer 35. Apply a voltage SRCGND to the other end of transistor TR7. The gate of transistor TR7 is connected to the following node INV_F. One end of transistor TR8 is connected to one end of transistor TR7. A voltage VHSA is applied to the other end of transistor TR8. The gate of transistor TR8 is connected to node INV_F. One end of transistor TR9 is connected to node SCOM. The other end of transistor TR9 is connected to node SEN. A control signal XXL is input to the gate of transistor TR9. The control signal XXL is generated, for example, by sequencer 35. Transistor TR9 is used to control the period during which data is sensed in memory cell MC. Node SEN functions as a sensing node, which senses the data in memory cell MC during data readout. More specifically, during readout, depending on the on or off state of memory cell MC, the charge in node SEN contained in sense amplifier 39 is discharged to bit line BL. Data is read out by sense amplifier 39 sensing the voltage VSEN of node SEN at this time. One electrode of capacitor C21 is connected to node SEN. A clock signal CLKSA is input to the other electrode of capacitor C21. One end of transistor TR10 is connected to node SEN. A voltage VHLB is applied to the other end of transistor TR10. Voltage VHLB is, for example, the power supply voltage VCC. A control signal SPC is input to the gate of transistor TR10. The control signal SPC is generated, for example, by sequencer 35. One end of transistor TR11 is connected to node SEN. The other end of transistor TR11 is connected to node ND1. The gate of transistor TR11 is connected to node INV_D. One end of transistor TR12 is connected to node ND1. The other end of transistor TR12 is connected to node SEN. The gate of transistor TR12 is connected to node LAT_D. One electrode of capacitor C22 is connected to node ND1. A clock signal CLKSA is input to the other electrode of capacitor C22. Transistors TR11 and TR12 can connect capacitor C21 and capacitor C22 in parallel, serving as a circuit to switch the connection and disconnection of capacitor C21 and capacitor C22. A voltage VLOP is applied to one end of transistor TR13. Voltage VLOP is, for example, the ground voltage VSS. The other end of transistor TR13 is connected to one end of transistor TR14. The gate of transistor TR13 is connected to node SEN. The other end of transistor TR14 is connected to bus LBUS. A control signal STB is input to the gate of transistor TR14. The control signal STB is generated, for example, by sequencer 35. One end of transistor TR15 is connected to node SEN. The other end of transistor TR15 is connected to bus LBUS. A control signal BLQ is input to the gate of transistor TR15. The control signal BLQ is generated, for example, by sequencer 35. A voltage VLOP is applied to one end of transistor TR16. The other end of transistor TR16 is connected to one end of transistor TR17. The gate of transistor TR16 is connected to bus LBUS. The other end of transistor TR17 is connected to node SEN. A control signal LSL is input to the gate of transistor TR17. The control signal LSL is generated, for example, by sequencer 35. Next, the circuit configuration of the pre-charge circuit LBP will be explained. The pre-charge circuit LBP is a circuit for pre-charging the bus LBUS. The pre-charge circuit LBP includes an n-channel MOS transistor TR18. One end of transistor TR18 is connected to bus LBUS. A voltage VDDSA is applied to the other end of transistor TR18. Voltage VDDSA is, for example, the power supply voltage VCC. A control signal LPC is input to the gate of transistor TR18. The control signal LPC is generated, for example, by sequencer 35. When transistor TR18 is in the ON state, voltage VDDSA is applied to bus LBUS. This charges bus LBUS. Next, the circuit configuration of the bus switch (BSW) will be explained. The bus switch (BSW) is a switch used to connect the bus (LBUS) and the bus (DBUS). The bus switch (BSW) includes an n-channel MOS transistor (TR19). One end of transistor TR19 is connected to bus LBUS. The other end of transistor TR19 is connected to bus DBUS. A control signal DSW is input to the gate of transistor TR19. The control signal DSW is generated, for example, by sequencer 35. Next, the circuit configurations of the latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL will be explained. The latch circuit SDL includes n-channel MOS transistors TR21 and TR22, as well as inverter circuits IV21 and IV22. One end of transistor TR21 is connected to bus LBUS. The other end of transistor TR21 is connected to node INV_S. A control signal STI is input to the gate of transistor TR21. The control signal STI is generated, for example, by sequencer 35. One end of transistor TR22 is connected to bus LBUS. The other end of transistor TR22 is connected to node LAT_S. A control signal STL is input to the gate of transistor TR22. The control signal STL is generated, for example, by sequencer 35. The input terminal of inverter circuit IV21 is connected to node LAT_S. The output terminal of inverter circuit IV21 is connected to node INV_S. The input terminal of inverter circuit IV22 is connected to node INV_S. The output terminal of inverter circuit IV22 is connected to node LAT_S. The latch circuits ADL, BDL, and CDL have the same configuration as the latch circuit SDL. The latch circuit DDL includes n-channel MOS transistors TR31 and TR32, as well as inverter circuits IV31 and IV32. One end of transistor TR31 is connected to bus LBUS. The other end of transistor TR31 is connected to node INV_D. A control signal DTI is input to the gate of transistor TR31. The control signal DTI is generated, for example, by sequencer 35. One end of transistor TR32 is connected to bus LBUS. The other end of transistor TR32 is connected to node LAT_D. A control signal DTL is input to the gate of transistor TR32. The control signal DTL is generated, for example, by sequencer 35. The input terminal of inverter circuit IV31 is connected to node LAT_D. The output terminal of inverter circuit IV31 is connected to node INV_D. The input terminals of inverter circuit IV32 are connected to node INV_D. The output terminals of inverter circuit IV32 are connected to node LAT_D. The latch circuit EDL includes n-channel MOS transistors TR41 and TR42, and inverter circuits IV41 and IV42. One end of transistor TR41 is connected to bus LBUS. The other end of transistor TR41 is connected to node INV_E. A control signal ETI is input to the gate of transistor TR41. The control signal ETI is generated, for example, by sequencer 35. One end of transistor TR42 is connected to bus LBUS. The other end of transistor TR42 is connected to node LAT_E. A control signal ETL is input to the gate of transistor TR42. The control signal ETL is generated, for example, by sequencer 35. The input terminal of inverter circuit IV41 is connected to node LAT_E. The output terminal of inverter circuit IV41 is connected to node INV_E. The input terminals of inverter circuit IV42 are connected to node INV_E. The output terminals of inverter circuit IV42 are connected to node LAT_E. The latch circuit FDL includes n-channel MOS transistors TR51 and TR52, and inverter circuits IV51 and IV52. One end of transistor TR51 is connected to bus LBUS. The other end of transistor TR51 is connected to node INV_F. A control signal FTI is input to the gate of transistor TR51. The control signal FTI is generated, for example, by sequencer 35. One end of the transistor TR52 is connected to the bus LBUS. The other end of the transistor TR52 is connected to node LAT_F. A control signal FTL is input to the gate of the transistor TR52. The control signal FTL is generated, for example, by the sequencer 35. The input terminals of inverter circuit IV51 are connected to node LAT_F. The output terminals of inverter circuit IV51 are connected to node INV_F. The input terminals of inverter circuit IV52 are connected to node INV_F. The output terminals of inverter circuit IV52 are connected to node LAT_F. Thus, in the sense amplifier assembly SAU, the sense circuit SAC, and the latch circuits SDL, ADL, BDL, CDL, DDL, EDL and FDL are connected to the bus LBUS in a manner that enables them to send and receive data with each other. Furthermore, the latch circuit XDL also has the same structure as the latch circuit SDL. 1.2 Data Memory Method Figure 12 illustrates an example of a data memory method. Figure 12 is a conceptual diagram representing an example of a data memory method. Figure 12 shows an example of the threshold voltage distribution of the memory cell transistor MC, data allocation, and the voltage used for data readout. In the threshold voltage distribution diagram referred to below, the vertical axis “NMCs” represents the number of memory cell transistors MC, and the horizontal axis voltage represents the voltage applied to the gate of the memory cell transistor MC. As shown in Figure 12, in the case of a TLC that stores 3 bits of data using a single memory cell transistor MC, the threshold voltage distribution formed by the plurality of memory cell transistors MC contained in the memory cell assembly CU can have 8 states. Hereinafter, these 8 states are denoted as "S0", "S1", "S2", "S3", "S4", "S5", "S6" and "S7" in order of threshold voltage from low to high. When the memory cell transistor MC is in the erase state, the threshold voltage of the memory cell transistor MC is included in the "S0" state. When data is written to the memory cell transistor MC, the threshold voltage of the memory cell transistor MC is included in any of the "S0" to "S7" states. Three bits of data are allocated to each of the "S0" to "S7" states. It is preferable that the data allocation for two adjacent states differs by only one bit. An example of data allocation for the eight states will be listed below. State "S0": "111 (highest bit / middle bit / lowest bit)" data; State "S1": "110" data; State "S2": "100" data; State "S3": "000" data; State "S4": "010" data; State "S5": "011" data; State "S6": "001" data; State "S7": "101" data. Between adjacent states, a verification voltage is set for confirming the data write operation, and a read voltage is set for the data read operation. Specifically, verification voltage V1 and read voltage R1 are set between states "S0" and "S1". Verification voltage V2 and read voltage R2 are set between states "S1" and "S2". Verification voltage V3 and read voltage R3 are set between states "S2" and "S3". Verification voltage V4 and read voltage R4 are set between states "S3" and "S4". Set the verification voltage V5 and readout voltage R5 between states "S4" and "S5". Set the verification voltage V6 and readout voltage R6 between states "S5" and "S6". Set the verification voltage V7 and readout voltage R7 between states "S6" and "S7". The verification voltages V1 to V7 are preferably set to be higher than the readout voltages R1 to R7, respectively. Verification voltages V1 to V7 are associated with states “S1” to “S7”, respectively. During the write operation, the NAND flash memory 30 uses a read operation with verification voltages (hereinafter referred to as “verification operation”) to confirm whether the threshold voltage of the memory cell transistor MC, which is to store certain data, exceeds the verification voltage associated with that data. Then, once the sequencer 35 detects that the threshold voltage of the memory cell transistor MC exceeds the verification voltage associated with that data, it completes the data write operation on the memory cell transistor MC. The read voltage R1 distinguishes between states "S0" and "S1" and above. The read voltage R2 distinguishes between states "below S1" and "S2" and above. The read voltage R3 distinguishes between states "below S2" and "S3" and above. The read voltage R4 distinguishes between states "below S3" and "S4" and above. The read voltage R5 distinguishes between states "below S4" and "S5" and above. The read voltage R6 distinguishes between states "below S5" and "S6" and above. The read voltage R7 distinguishes between states "below S6" and "S7" and above. Furthermore, the read path voltage VREAD is set to a higher voltage than the highest state. The memory cell transistor MC with the read path voltage VREAD applied to its gate becomes in the ON state regardless of the data stored. During a read operation, the NAND flash memory 30 uses at least one read voltage to determine the state of the memory cell transistor MC distribution. For example, the set of lower-level bit data, i.e., the lower-level page data, is determined by read operations using read voltages R1 and R5. The set of middle-level bit data, i.e., the middle-level page data, is determined by read operations using read voltages R2, R4, and R6. The set of upper-level bit data, i.e., the upper-level page data, is determined by read operations using read voltages R3 and R7. In page read operations using multiple read voltages, appropriate computational processing is performed. Furthermore, when the NAND flash memory 30 uses a TLC (Telematics-Limited) transistor MC (hereinafter referred to as "TLC mode"), other data allocation methods can also be employed. Moreover, the NAND flash memory 30 can also employ memory methods other than TLC mode, and can use all data allocation methods. For example, one transistor MC can store 2 bits of data or more than 4 bits of data. The execution of the operations described in this specification is not limited by the data storage method or the type of data allocation. 1.3 Write Operation Next, the write operation will be explained. In the following explanation, the word line WL selected in the write operation will be referred to as "word line WLsel". The memory cell transistor MC connected to the word line WLsel will be referred to as "memory cell transistor MCsel". 1.3.1 Overview of Write Operation First, the overview of the write operation will be explained using Figure 13. Figure 13 is a timing diagram showing the overview of the write operation. As shown in Figure 13, the NAND flash memory 30 repeatedly executes a programming loop during the write operation. Figure 13 shows the number of times the programming loop is executed during the write operation (hereinafter referred to as the "loop number") and the voltage change of the word line WLsel (WLsel voltage). Each programming loop includes a programming action (Program) and a verification action (Verify). That is, during the write operation, the programming loop, which includes the programming action and the verification action, is repeated i times (i is an integer greater than or equal to 2). Programming raises the threshold voltage of the memory cell transistors (MCsels). During programming, multiple memory cell transistors (MCsels) connected to the word line WLsel are set as program-targets or program-inhibits based on the write data stored in the associated sense amplifier assembly (SAU). Specifically, memory cell transistors (MCsels) that have not reached the threshold voltage of the write target state (hereinafter referred to as the "write state") are set as program-targets. Memory cell transistors (MCsels) that have reached the threshold voltage of the write state are set as program-inhibits. During the programming operation, a programming voltage VPGM is applied to the word line WLsel. The programming voltage VPGM is a high voltage that raises the threshold voltage of the memory cell transistor MCsel. The programming voltage VPGM increases, for example, with the repetition of the programming cycle. That is, the programming voltage VPGM increases according to the number of programming cycles executed. The increase magnitude VPGM can be set to any value. When the programming voltage VPGM is applied to the word line WLsel, the threshold voltage of the memory cell transistor MCsel connected to the word line WLsel and to the bit line BL that is being programmed rises. The rise in the threshold voltage of the memory cell transistor MCsel connected to the word line WLsel and to the bit line BL that is not programmed is suppressed by a boost converter technique, etc. Hereinafter, during the programming operation, the action that raises the threshold voltage will be denoted as "0" write, or simply "write". The action that maintains the threshold voltage will be denoted as "1" write or "no write". The bit line corresponding to writing "0" is denoted as BL("0"), and the bit line corresponding to writing "1" is denoted as BL("1"). That is, bit line BL("0") is connected to the bit line BL of the memory cell transistor MC that is being written to. Bit line BL("1") is connected to the bit line BL of the memory cell transistor MC that is not being written to. After the sequencer 35 finishes the programming operation, it will perform a verification operation. The verification action is a read operation that confirms whether the threshold voltage of the memory cell transistor MCsel has reached the threshold voltage for the write state. Within the same programming cycle, the sequencer 35 sets the memory cell transistor MCsel, which is set as the programming object and whose write state is consistent with that of the verification object, as the object and performs the verification action. During the verification process, the sense amplifier unit (SAU) determines whether the threshold voltage of the memory cell transistor (MCsel) exceeds the verification voltage applied to the word line (WLsel) based on the voltage of the bit line (BL). The verification voltage is applied sequentially, for example, within the programming cycle, starting with the verification voltage associated with the state with the highest threshold voltage among the states being verified. Each sense amplifier unit (SAU) determines a memory cell transistor (MCsel) whose threshold voltage exceeds the verification voltage (i.e., reaches the threshold voltage for the write state) as "verified successfully." Conversely, each sense amplifier unit (SAU) determines a memory cell transistor (MCsel) whose threshold voltage is below the verification voltage (i.e., does not reach the threshold voltage for the write state) as "verified unsuccessfully." Each sense amplifier unit (SAU) stores the verification results of the write states described above into any internal latch circuit. After the verification process is completed, the sequencer (35), based on the verification results of the current programming cycle, sets each memory cell transistor (MCsel) as a programming target or disables programming, and begins processing for the next programming cycle. Furthermore, the NAND flash memory 30 can perform a detection operation (“Detection”) after each programming cycle. During the detection operation, the number of memory cell transistors (MCsels) whose verification operations were successful is counted for each write state. Then, the sequencer 35 determines whether the write operation for each write state has been completed based on the count value. During the repetition of the programming cycle, the sequencer 35 will terminate the write operation, for example, once it detects that the number of memory cell transistors (MCsels) whose verification operations failed in states “S1” to “S7” is lower than a predetermined number. 1.3.2 Specific Example of a Programming Loop Next, Figure 14 illustrates a specific example of a programming loop. Figure 14 is a table showing an example of the settings for a programming loop in a write operation. The table in Figure 14 shows the relationship between the loop number and the write state assigned to that loop as the verification object, with white circles marking the portions where verification actions are set. As shown in Figure 14, the types and number of write states that are the objects of verification change as the programming loop progresses. In this example, the sequencer 35 executes a maximum of 19 programming loops. Moreover, in each of the 19 programming loops, the sequencer 35 performs a verification action with at least one state as the object. Specifically, state "S1" is set as the verification object in programming loops 1-6. State "S2" is set as the verification object in programming loops 2-8. State "S3" is set as the verification object in programming loops 4-10. State "S4" is set as the verification object in programming loops 6-12. State "S5" is set as the verification object in programming loops 8-14. State "S6" is set as the verification object in programming loops 10-16. State "S7" is set as the verification object in programming loops 12-19. In the first programming cycle, the verification voltage V1 associated with state "S1" is applied. In the second and third programming cycles, the verification voltage V2 associated with state "S2" and the verification voltage V1 associated with state "S1" are applied sequentially. Similarly, in the fourth and fifth programming cycles, the verification voltages V3, V2, and V1 are applied sequentially. In the sixth programming cycle, the verification voltages V4, V3, V2, and V1 are applied sequentially. In the seventh programming cycle, the verification voltages V4, V3, and V2 are applied sequentially. In the eighth programming cycle, the verification voltages V5, V4, V3, and V2 are applied sequentially. In the ninth programming cycle, the verification voltages V5, V4, and V3 are applied sequentially. In the 10th programming cycle, verification voltages V6, V5, V4, and V3 are applied sequentially. In the 11th programming cycle, verification voltages V6, V5, and V4 are applied sequentially. In the 12th programming cycle, verification voltages V7, V6, V5, and V4 are applied sequentially. In programming cycles 13 and 14, verification voltages V7, V6, and V5 are applied sequentially. In programming cycles 15 and 16, verification voltages V7 and V6 are applied sequentially. In programming cycles 17 through 19, verification voltage V7 is applied. Furthermore, the number of programming loops that the NAND flash memory 30 can execute in a single write operation can be any number of times. Even if the write operation is not completed in all write states, the sequencer 35 will terminate the write operation as soon as the prescribed number of programming loops has been executed. The write state that is used as the verification object and is associated with the number of loops can also be set to other values. The sequencer 35 can also omit the programming and verification actions for that write state in subsequent programming loops based on the result of the detection action. 1.3.3 Details of the Write Action Next, the details of the write action will be explained. Figure 15 illustrates the relationship between the three verification voltages and threshold voltage distributions available for each write state during a write operation. In the example shown in Figure 15, all memory cell transistors (MCsel) are written from the "S0" state to the "S1" state. As shown in Figure 15, in this embodiment, verification voltages VL, VM, and VH are set for each write state for verification operations. Verification operations include VL sensing, VM sensing, and VH sensing. The VL sensing operation determines whether the threshold voltage of the memory cell transistor MCsel is above the verification voltage VL. The VM sensing operation determines whether the threshold voltage of the memory cell transistor MCsel is above the verification voltage VM. The VM sensing operation determines whether the threshold voltage of the memory cell transistor MCsel is above the verification voltage VH. The verification voltage VH is the verification voltage described with reference to Figure 12. In the example shown in Figure 15, VH = V1. The verification voltages VL, VM, and VH have a relationship of VL < VM < VH. That is, the VM sensing operation is the sensing operation of the voltage level VM. The VH sensing operation is the sensing operation of the voltage level VH, which is higher than the voltage level VM. The VL sensing operation is the sensing operation of the voltage level VL, which is lower than the voltage level VM. In the threshold voltage distribution shown in Figure 15, the region where the threshold voltage does not reach voltage VL is denoted as "Threshold Region A1"; the region where the threshold voltage is above voltage VL but below voltage VM is denoted as "Threshold Region A2"; the region where the threshold voltage is above voltage VM but below voltage VH is denoted as "Threshold Region A3"; and the region where the threshold voltage is above voltage VH is denoted as "Threshold Region A4". The threshold voltage of the memory cell transistor MCsel contained in Threshold Region A1 is denoted as "Threshold Voltage Vth1". The threshold voltage of the memory cell transistor MCsel contained in Threshold Region A2 is denoted as "Threshold Voltage Vth2". The threshold voltage of the memory cell transistor MCsel contained in Threshold Region A3 is denoted as "Threshold Voltage Vth3". The threshold voltage of the memory cell transistor MCsel contained in Threshold Region A4 is denoted as "Threshold Voltage Vth4". The threshold voltages Vth1, Vth2, Vth3, and Vth4 have the relationship Vth1 < Vth2 < Vth3 < Vth4. If the VL sensing operation fails, the memory cell transistor MCsel is set as the programming object in the next programming cycle because the threshold voltage does not reach the threshold voltage VH of the write state. In this case, a programming operation (hereinafter referred to as "the first programming operation") is performed that applies a programming condition (hereinafter referred to as "the first programming condition") with a relatively large change in the threshold voltage of the memory cell transistor MC. A memory cell transistor (MCsel) that successfully completes the VL sensing action but fails the VM sensing action is set as the programming target in the next programming cycle because its threshold voltage has not reached the write state threshold voltage VH. In this case, performing the first programming action on the memory cell transistor MCsel may result in overwriting. Therefore, a programming action (hereinafter referred to as the "second programming action") is performed that applies a programming condition where the change in the threshold voltage of the memory cell transistor MC is smaller than that of the first programming condition. A memory cell transistor (MCsel) that successfully senses VM but fails to sense VH is set as the programming target in the next programming cycle because its threshold voltage has not reached the write state threshold voltage VH. In this case, performing the first or second programming operation on the memory cell transistor MCsel may result in overwriting. Therefore, a programming operation (hereinafter referred to as the "third programming operation") is performed where the change in the threshold voltage of the memory cell transistor MC is smaller than that of the second programming condition. The memory cell transistor MCsel that successfully completes the VH sensing action is set to be unprogrammable in the next programming cycle because its threshold voltage has reached the write state threshold voltage VH. In this case, a non-write programming action is performed (hereinafter referred to as "programming action 4"). With this configuration, the threshold voltage distribution has a smaller dispersion compared to the case where no more than two verification voltages are used to perform verification for each write state. Figure 16 illustrates the change in voltage VSEN of node SEN during the verification process, when the voltage of word line WLsel is fixed (e.g., the verification voltage VH corresponding to the write state) and the charge charged to node SEN is discharged to bit line BL. Figure 16 shows the change in voltage VSEN when the threshold voltage of the memory cell transistor MCsel connected to node SEN is Vth1 to Vth4. In Figure 16, the vertical axis represents voltage VSEN, and the horizontal axis represents the elapsed time after the start of discharge. The capacitance of node SEN is assumed to be the first capacitance value. The threshold voltage of transistor TR13, whose gate is connected to node SEN, can be a value within the range of voltage Vt13a to voltage Vt13b. As shown in Figure 16, the lower the threshold voltage of the memory cell transistor MCsel, the greater the decrease in voltage VSEN after a fixed time following the start of discharge. Therefore, in the verification process, data from the memory cell transistor MCsel can be sensed, for example, as described below. During the period from time t1 to time t2, data from the memory cell transistor MCsel is sensed. This allows determination of whether the memory cell transistor MCsel is located within threshold region A1 or threshold regions A2-A4. That is, VL sensing is performed. When the threshold voltage of the memory cell transistor MCsel is below voltage VL, the memory cell transistor MCsel becomes on (hereinafter referred to as "on-cell"), and current flows from the corresponding bit line BL to the source line SL. Therefore, the voltage VSEN at node SEN decreases by a relatively large margin. Consequently, transistor TR13 is turned off. In this case, the memory cell transistor MCsel is determined to be located within threshold region A1. When the threshold voltage of the memory cell transistor MCsel is above voltage VL, the memory cell transistor MCsel becomes off (hereinafter referred to as "off-cell"), and current flows almost no further from the corresponding bit line BL to the source line SL. Therefore, the voltage VSEN at node SEN decreases by a relatively small amount. This causes transistor TR13 to turn on. In this case, the threshold voltage of the memory cell transistor MCsel is determined to be contained within the threshold regions A2 to A4. During the period from time t3 to time t4, data from the memory cell transistor MCsel is sensed. This allows determination of whether the memory cell transistor MCsel falls within threshold regions A1-A2 or A3-A4. In other words, VM sensing is performed. When the threshold voltage of the memory cell transistor MCsel is below voltage VM, the MCsel becomes a conducting unit, and the voltage VSEN at node SEN decreases by a relatively large amount. Transistor TR13 then turns off. In this case, the memory cell transistor MCsel is determined to be within threshold regions A1-A2. When the threshold voltage of the memory cell transistor MCsel is above voltage VM, the MCsel becomes a de-conducting unit, and the voltage VSEN at node SEN decreases by a relatively small amount. Transistor TR13 then turns on. In this case, the memory cell transistor MCsel is determined to be within threshold regions A3-A4. During the period from time t5 to time t6, data from the memory cell transistor MCsel is sensed. This allows determination of whether the memory cell transistor MCsel falls within threshold regions A1-A3 or threshold region A4. That is, a VH sensing operation can be performed. When the threshold voltage of the memory cell transistor MCsel is below voltage VH, the memory cell transistor MCsel becomes a conducting unit, and the voltage VSEN at node SEN decreases by a relatively large amount. In this case, transistor TR13 is turned off. In this situation, the memory cell transistor MCsel is determined to be within threshold regions A1-A3. When the threshold voltage of the memory cell transistor MCsel is above voltage VH, the memory cell transistor MCsel becomes a de-conducting unit, and the voltage VSEN at node SEN decreases by a relatively small amount. In this case, transistor TR13 is turned on. In this situation, the memory cell transistor MCsel is determined to be within threshold region A4. When the voltage of the character line WLsel is fixed, and the VL sensing operation is performed during time t1 to time t2, the VM sensing operation is performed during time t3 to time t4, and the VH sensing operation is performed during time t5 to time t6, three sensing operations will be performed. In this case, compared with the case where no more than two verification voltages are used to perform verification operations for each write state, the number of sensing operations increases, and the verification operation time increases. Furthermore, when three verification voltages are provided for each write state, the sensing range becomes narrower compared to when two or fewer verification voltages are used to perform verification actions for each write state. Therefore, in this embodiment, during the verification operation, after setting the voltage of the character line Wsel to the verification voltage VH corresponding to the write state, the following operations are performed. First, a VM sensing operation is performed. Second, based on the result of the VM sensing operation, both a VH sensing operation and a VL sensing operation are performed simultaneously. By performing VM sensing, it is possible to determine whether the memory cell transistor MCsel is contained in the threshold regions A1-A2 or A3-A4. Furthermore, in order to perform VH sensing and VL sensing actions simultaneously, the discharge time of the node SEN connected to the memory cell transistor MCsel that is determined to be included in the threshold regions A1 to A2 during VM sensing must be consistent with the discharge time of the node SEN connected to the memory cell transistor MCsel that is determined to be included in the threshold regions A3 to A4 during VM sensing. For example, consider a scenario where the capacitance of node SEN is set to a larger value than that in the example of Figure 16 (the first capacitance value). In this case, the discharge time of the charge in node SEN is longer than in the example of Figure 16. That is, the time for voltage VSEN to drop to voltages Vt13a and Vt13b is later than in the example of Figure 16. Therefore, the capacitance of node SEN connected to the memory cell transistors MCsel determined to be included in threshold regions A1-A2 will be greater than the capacitance of node SEN connected to the memory cell transistors MCsel determined to be included in threshold regions A3-A4. In this way, the discharge time of the former node SEN can be made consistent with the discharge time of the latter node SEN. Figure 43 is a diagram showing the memory cell transistor MC and its general electrical characteristics. In Figure 43, the left diagram shows the memory cell transistor MC, and the right diagram shows the general electrical characteristics of the memory cell transistor MC. In the right diagram, the vertical axis represents the drain current Ids of the memory cell transistor MC, and the horizontal axis represents the gate-source voltage Vgs of the memory cell transistor MC. As shown in the right figure of Figure 43, if a voltage is applied to the gate of the memory cell transistor MC, such that the gate-source voltage Vgs exceeds the threshold voltage Vth of the memory cell transistor MC, the drain current Ids increases sharply. Therefore, for example, when a voltage Vgs1 higher than the threshold voltage Vth4 is applied as the voltage Vgs, the drain currents Ids1, Ids2, Ids3, and Ids4 of the memory cell transistor MC with threshold voltage Vth1, Vth2, Vth3, and Vth4 are in the following order: Ids1 > Ids2 > Ids3 > Ids4. Figure 17 illustrates the change in voltage VSEN of node SEN when the charge is discharged from node SEN during the verification process, with the voltage of word line WLsel fixed. Figure 17 shows the case where the discharge time of node SEN connected to the memory cell transistors MCsels contained in threshold regions A1-A2 is consistent with the discharge time of node SEN connected to the memory cell transistors MCsels contained in threshold regions A3-A4. The solid line represents the change in voltage VSEN of node SEN connected to the memory cell transistors MCsels contained in threshold regions A1-A4 when the capacitance of node SEN is the first capacitance value. The dashed line represents the change in voltage VSEN of node SEN connected to the memory cell transistors MCsels contained in threshold region A1 when the capacitance of node SEN is the second capacitance value, which is larger than the first capacitance value, and is labeled Vth1'. A single link line represents the change in voltage VSEN of node SEN when the capacitance of node SEN is the second capacitance value, which is connected to the memory cell transistor MCsel contained in the threshold region A2. It is labeled as Vth2'. As shown in Figure 17, the discharge time of node SEN is consistent in both the case where the threshold voltage of the memory cell transistor MCsel connected to node SEN is Vth1' and the case where the threshold voltage of the memory cell transistor MCsel connected to node SEN is Vth3. Similarly, the discharge time of node SEN is consistent in both the case where the threshold voltage of the memory cell transistor MCsel connected to node SEN is Vth2' and the case where the threshold voltage of the memory cell transistor MCsel connected to node SEN is Vth4. Therefore, for example, during the period from time t5 to time t6, VH sensing and VL sensing operations can be performed. When the VM sensing action determines that the memory cell transistor MCsel is included in the threshold regions A3 to A4, the capacitance of the SEN node connected to the memory cell transistor MCsel is set to the first capacitance value. In this case, the sensing action performed during the period from time t5 to time t6 becomes the VH sensing action. Based on the VH sensing action, when the memory cell transistor MCsel is an off cell, transistor TR13 is turned on, and the memory cell transistor MCsel is determined to be included in the threshold region A4. When the memory cell transistor MCsel is a turned-on cell, transistor TR13 is turned off, and the memory cell transistor MCsel is determined to be included in the threshold region A3. When the VM sensing action determines that the memory cell transistor MCsel is included in the threshold regions A1 to A2, the capacitance of the SEN node connected to the memory cell transistor MCsel is set to the second capacitance value. In this case, the sensing action performed between time t5 and time t6 becomes the VL sensing action. Through the VL sensing action, when the memory cell transistor MCsel is an off cell, transistor TR13 is turned on, and the memory cell transistor MCsel is determined to be included in the threshold region A2. When the memory cell transistor MCsel is a turned-on cell, transistor TR13 is turned off, and the memory cell transistor MCsel is determined to be included in the threshold region A1. Thus, in this embodiment, during the verification process, the capacitance of node SEN is changed based on the result of the VM sensing action. For example, when the ratio of the drain current Ids1 of the memory cell transistor MCsel with a threshold voltage of Vth1 to the drain current Ids2 of the memory cell transistor MCsel with a threshold voltage of Vth2, and the ratio of the drain current Ids3 of the memory cell transistor MCsel with a threshold voltage of Vth3 to the drain current Ids4 of the memory cell transistor MCsel with a threshold voltage of Vth4, the capacitance values ​​of capacitors C21 and C22 are appropriately adjusted. This ensures that the drain current Ids1' of the memory cell transistor MCsel with a threshold voltage of Vth1' is approximately the same as the drain current Ids3 of the memory cell transistor MCsel with a threshold voltage of Vth3, and that the drain current Ids2' of the memory cell transistor MCsel with a threshold voltage of Vth2' is approximately the same as the drain current Ids4 of the memory cell transistor MCsel with a threshold voltage of Vth4. In other words, the memory cell transistor MCsel, which is the object of the VL sensing operation, and the memory cell transistor MCsel, which is the object of the VH sensing operation, can be configured to have corresponding sensing ranges. In this way, the VL sensing operation and the VH sensing operation, which follow the VM sensing operation, can be executed simultaneously. Furthermore, in this embodiment, the above-mentioned two sensing operations are performed for each write state during the programming loop. If a verification action (two sensing operations) is performed for all write states, then based on the determination result of the verification action, any one of the first to fourth programming actions is performed in the next programming loop. 1.3.4 Verification Operation Next, the verification operation will be explained focusing on the operation of the sensing amplifier 39. The following will describe the application of verification voltage V2 to the word line WLsel during the verification operation of the second programming loop. Figure 18 is a timing diagram showing an example of the voltage of various wiring and signals during the verification operation. First, during the period when the verification voltage V2 is applied to the character line WLsel, the sensing amplifier 39 performs a VM sensing operation as the first sensing. Figure 19 is a diagram illustrating the operation of the sensing amplifier 39 during the VM sensing operation. As shown in Figure 18, at time t11, the voltage of the word line WLsel is set to voltage VSS. The voltage of node SEN, VSEN, is set to voltage VSS. The control signals SPC, XXL, and STB are set to the "low" level (L level). The clock signal CLKSA is set to the L level. The node INV_D of the latch circuit DDL is set to the L level ("0"). That is, the node LAT_D of the latch circuit DDL is set to the "high" level (H (High) level ("1")). The node INV_E of the latch circuit EDL is set to the L level ("0"). That is, the node LAT_E of the latch circuit EDL is set to the H level ("1"). By setting node INV_D to the L level, as shown in Figure 19, transistors TR11 and TR12 become off. That is, the capacitance of node SEN becomes equal to the capacitance of capacitor element C21. Furthermore, as shown in Figure 18, at time t11, the column decoder module 38 applies a verification voltage VH (V2) to the character line WLsel. Thus, the voltage of the character line WLsel becomes voltage V2. Next, at time t12, the control signal SPC is set to level H. As shown in Figure 19, transistor TR10 is turned on, thus applying voltage VHLB to node SEN. That is, as indicated by the solid arrow in Figure 19, charging of node SEN begins. Then, as shown in Figure 18, at time t13, the control signal SPC is set to the L level. This ends the charging of node SEN. Also, at time t13, the clock signal CLKSA is set to the H level. This charges capacitor C21, and the voltage VSEN at node SEN becomes higher than voltage VHLB due to capacitive coupling. Next, at time t14, control signal XXL is set to level H. Although the diagram is omitted, control signals BLS and BLC are also set to level H. As shown in Figure 19, transistors TR9, TR2, and TR1 are turned on. Therefore, as indicated by the dashed arrow in Figure 19, the charge at node SEN begins to discharge onto bit line BL. As shown in Figure 18, when the memory cell transistor MCsel connected to bit line BL is a conducting cell, the voltage VSEN at node SEN decreases by a relatively large amount. Conversely, when the memory cell transistor MCsel connected to bit line BL is a disconnected cell, the voltage VSEN at node SEN decreases by a relatively small amount. Next, at time t15, the control signal XXL is set to level L, and the control signals BLS and BLC are also set to level L. This ends the discharge of bit line BL. Also, at time t15, the clock signal CLKSA is set to level L. Therefore, when the memory cell transistor MCsel connected to bit line BL is in the ON position, the voltage VSEN at node SEN becomes VSS. When the memory cell transistor MCsel connected to bit line BL is in the OFF position, the voltage VSEN at node SEN decreases. Subsequently, at time t16, the control signal STB is set to level H. Although the diagram is omitted, the control signal DTI is also set to level H. This turns transistors TR14 and TR31 on, thus data from node SEN begins to be transmitted to node INV_D. When the memory cell transistor MCsel connected to bit line BL is on, transistor TR13 is off. Therefore, at time t17, node INV_D becomes "1". Conversely, when the memory cell transistor MCsel connected to bit line BL is off, transistor TR13 is on. Therefore, at time t17, node INV_D becomes "0". Next, at time t18, the control signal STB is set to level L, and the control signal DTI is also set to level L. This concludes the data transmission from node SEN to node INV_D. That is, the sensing amplifier 39 stores the result of the first sensing in the latch circuit DDL. Then, at time t19, the voltage VSEN of node SEN is set to voltage VSS. This completes the VM sensing operation. Figure 20 illustrates the result of the first sensing operation performed using VM sensing. As shown in Figure 20, when the memory cell transistor MCsel connected to bit line BL is a conducting cell, the node LAT_D of the latch circuit DDL becomes "0". That is, the memory cell transistor MCsel connected to bit line BL is determined to be included in the threshold regions A1 to A2. When the memory cell transistor MCsel connected to bit line BL is a de-conducting cell, the node LAT_D of the latch circuit DDL becomes "1". That is, the memory cell transistor MCsel connected to bit line BL is determined to be included in the threshold regions A3 to A4. Secondly, during the period when the verification voltage V2 is applied to the character line WLsel, the sensing amplifier 39 stores the result of the first sensing in the latch circuit DDL, and then performs either the VH sensing operation or the VL sensing operation as the second sensing. Figure 21 is a diagram illustrating the operation of the sensing amplifier 39 during the VH sensing operation. Figure 23 is a diagram illustrating the operation of the sensing amplifier 39 during the VL sensing operation. After the VM sensing operation, when the memory cell transistor MCsel is in the off state, the sensing amplifier 39 performs a VH sensing operation as a second sensing. As shown in Figure 18, at time t20, node INV_D is at level L ("0"). Node INV_E is at level L ("0"). By setting node INV_D to level L, as shown in Figure 21, transistors TR11 and TR12 become off. That is, the capacitance of node SEN becomes equal to the capacitance of capacitor element C21. Also, as shown in Figure 18, at time t20, the control signal SPC is set to level H. Therefore, as shown in Figure 21, transistor TR10 becomes on, and a voltage VHLB is applied to node SEN. That is, as shown by the solid arrow in Figure 21, charging of node SEN begins. Then, as shown in Figure 18, at time t21, the control signal SPC is set to the L level. This ends the charging of node SEN. Also, at time t21, the clock signal CLKSA is set to the H level. This makes the voltage VSEN of node SEN higher than the voltage VHLB. Next, at time t22, control signal XXL is set to level H, and control signals BLS and BLC are also set to level H. As shown in Figure 21, transistors TR9, TR2, and TR1 are turned on. Therefore, as indicated by the dashed arrow in Figure 21, the charge at node SEN begins to discharge onto bit line BL. As shown in Figure 18, when the memory cell transistor MCsel connected to bit line BL is a conducting cell, as shown by the solid line, the voltage VSEN at node SEN decreases by a relatively large amount. Conversely, when the memory cell transistor MCsel connected to bit line BL is a disconnected cell, as shown by the solid line, the voltage VSEN at node SEN decreases by a relatively small amount. Next, at time t23, the control signal XXL is set to level L, and control signals BLS and BLC are also set to level L. This ends the discharge of bit line BL. The discharge time, i.e., the time it takes for the control signal XXL to reach level H, is set to, for example, a longer time than the discharge time for VM sensing operation. Also, at time t23, the clock signal CLKSA is set to level L. Therefore, when the memory cell transistor MCsel connected to bit line BL is in the ON position, as shown by the solid line, the voltage VSEN at node SEN becomes VSS. When the memory cell transistor MCsel connected to bit line BL is in the OFF position, as shown by the solid line, the voltage VSEN at node SEN decreases. Subsequently, at time t24, the control signal STB is set to level H. Although related illustrations are omitted, the control signal ETI is also set to level H. This turns transistors TR14 and TR41 on, thus data from node SEN begins to be transmitted to node INV_E. When the memory cell transistor MCsel connected to bit line BL is on, transistor TR13 is off. Therefore, at time t25, as shown by the solid line, node INV_E becomes "1". Conversely, when the memory cell transistor MCsel connected to bit line BL is off, transistor TR13 is on. Therefore, at time t25, as shown by the solid line, node INV_E becomes "0". Next, at time t26, the control signal STB is set to level L, and the control signal ETI is also set to level L. This concludes the data transmission from node SEN to node INV_E. That is, the sensing amplifier 39 stores the result of the second sensing in the latch circuit EDL. Subsequently, at time t27, the voltage VSEN of node SEN is set to voltage VSS. Also at time t27, the column decoder module 38 applies voltage VSS to the character line WLsel. Thus, the voltage of character line WLsel becomes voltage VSS. At this point, the VH sensing operation ends. Figure 22 illustrates the results of performing a VM sensing operation as the first sensing and a VH sensing operation as the second sensing. As shown in Figure 22, when the memory cell transistor MCsel connected to bit line BL is a conducting cell, node LAT_E of the latch circuit EDL becomes "0". Since node LAT_D of the latch circuit DDL is "1", the memory cell transistor MCsel connected to bit line BL is determined to be included in the threshold region A3. When the memory cell transistor MCsel connected to bit line BL is a de-conducting cell, node LAT_E of the latch circuit EDL becomes "1". Since node LAT_D of the latch circuit DDL is "1", the memory cell transistor MCsel connected to bit line BL is determined to be included in the threshold region A4. On the other hand, after the VM sensing operation, when the memory cell transistor MCsel is in the conducting state, the sensing amplifier 39 performs a VL sensing operation as a second sensing. As shown in Figure 18, at time t20, node INV_D is at level H ("1"). Node INV_E is at level L ("0"). By setting node INV_D to level H, as shown in Figure 23, transistors TR11 and TR12 become in the conducting state. That is, the capacitance of node SEN becomes equal to the combined capacitance of capacitor elements C21 and C22. Since capacitor elements C21 and C22 are connected in parallel, the capacitance of node SEN becomes a larger capacitance than that of capacitor element C21 (for example, when the capacitance of capacitor element C21 equals the capacitance of capacitor element C22, it is twice the capacitance of capacitor element C21). Also, as shown in Figure 18, at time t20, the control signal SPC is set to level H. Therefore, as shown in Figure 23, transistor TR10 becomes conductive, thus applying voltage VHLB to node SEN. That is, as indicated by the solid arrow in Figure 23, charging of node SEN begins. Then, as shown in Figure 18, at time t21, the control signal SPC is set to the L level. This ends the charging of node SEN. Also, at time t21, the clock signal CLKSA is set to the H level. This charges capacitors C21 and C22, and the voltage VSEN at node SEN becomes higher than the voltage VHLB due to capacitive coupling. Next, at time t22, control signal XXL is set to level H, and control signals BLS and BLC are also set to level H. As shown in Figure 23, transistors TR9, TR2, and TR1 are turned on. Therefore, as indicated by the dashed arrow in Figure 23, the charge at node SEN begins to discharge onto bit line BL. As shown in Figure 18, when the memory cell transistor MCsel connected to bit line BL is a conducting cell, as indicated by the dashed line, the voltage VSEN at node SEN decreases by a relatively large amount. Conversely, when the memory cell transistor MCsel connected to bit line BL is a de-conducting cell, as indicated by the dashed line, the voltage VSEN at node SEN decreases by a relatively small amount. Next, at time t23, the control signal XXL is set to level L, and the control signals BLS and BLC are also set to level L. This ends the discharge of bit line BL. The discharge time, i.e., the time it takes for the control signal XXL to reach level H, is set to, for example, a longer time than the discharge time for the VM sensing operation. Also, at time t23, the clock signal CLKSA is set to level L. This means that when the memory cell transistor MCsel connected to bit line BL is in the ON position, as shown by the dashed line, the voltage VSEN at node SEN becomes VSS. When the memory cell transistor MCsel connected to bit line BL is in the OFF position, as shown by the dashed line, the voltage VSEN at node SEN decreases. Subsequently, at time t24, control signal STB and control signal ETI are both set to H level. This turns transistors TR14 and TR41 on, allowing data from node SEN to begin transmitting to node INV_E. When the memory cell transistor MCsel connected to bit line BL is on, transistor TR13 is off. Therefore, at time t25, as shown by the dashed line, node INV_E becomes "1". Conversely, when the memory cell transistor MCsel connected to bit line BL is off, transistor TR13 is on. Therefore, at time t25, as shown by the dashed line, node INV_E becomes "0". Next, at time t26, the control signal STB is set to level L, and the control signal ETI is also set to level L. This concludes the data transmission from node SEN to node INV_E. That is, the sensing amplifier 39 stores the result of the second sensing in the latch circuit EDL. Subsequently, at time t27, the voltage VSEN of node SEN is set to voltage VSS. Also at time t27, the column decoder module 38 applies voltage VSS to the character line WLsel. Thus, the voltage of character line WLsel becomes voltage VSS. At this point, the VL sensing operation ends. Figure 24 illustrates the results of performing a VM sensing operation as the first sensing and a VL sensing operation as the second sensing. As shown in Figure 24, when the memory cell transistor MCsel connected to bit line BL is a conducting cell, the node LAT_E of the latch circuit EDL becomes "0". Since the node LAT_D of the latch circuit DDL is "0", the memory cell transistor MCsel connected to bit line BL is determined to be included in the threshold region A1. When the memory cell transistor MCsel connected to bit line BL is a de-conducting cell, the node LAT_E of the latch circuit EDL becomes "1". Since the node LAT_D of the latch circuit DDL is "0", the memory cell transistor MCsel connected to bit line BL is determined to be included in the threshold region A2. During the verification operation of the second programming cycle, after the two sensing operations described above are completed, the same two sensing operations are performed again during the period when the verification voltage V1 is applied to the character line WLsel. This completes the verification operation of the second programming cycle. 1.3.5 Programming Actions Next, the programming actions will be explained focusing on the operation of the sensing amplifier 39. The following will describe the execution of the first to fourth programming actions in the (k+1)th programming loop (k being an integer greater than or equal to 1). (4th Programming Action) After the verification action of the k-th programming cycle, if the node INV_D of the latch circuit DDL is at level L ("0") and the node INV_E of the latch circuit EDL is at level L ("0"), the 4th programming action is executed in the (k+1)-th programming cycle. This is equivalent to determining, after the 1st and 2nd sensing in the verification action of the k-th programming cycle, that the threshold voltage of the memory cell transistor MCsel is above the voltage level VH. Figure 25 is a timing diagram showing an example of the voltage of various wiring and signals during the fourth programming operation. Figure 26 is a diagram illustrating the operation of the sensing amplifier 39 during the fourth programming operation. As shown in Figure 25, at time t31, the voltage of the word line WLsel is set to voltage VSS. The voltage of the bit line BL (“1”) is set to voltage VSS. Control signals BLS, BLC, and BLX are set to level L (voltage VSS). Control signal BLP is set to level H (voltage VSS). The sensing amplifier 39 stores the value of the latch circuit DDL into the latch circuit FDL. That is, the node INV_F of the latch circuit FDL is set to the value of node INV_D (level L (“0”)). Furthermore, the sensing amplifier 39 stores the value of the latch circuit DDL into the latch circuit SDL. That is, the node INV_S of the latch circuit SDL is set to the value of node INV_D (level L (“0”)). Hereby, transistors TR4 and TR8 become on. Transistors TR1-TR3 and TR5-TR7 become off. Next, at time t32, the control signal BLS is set to level H (voltage VBLS). The control signal BLC is set to level H (voltage VBLC). The control signal BLX is set to level H (voltage VBLX). The control signal BLP is set to level L (voltage VBLP). Here, VBLX - Vt3 < VBLP + Vt6. Vt3 is the threshold voltage of transistor TR3. Vt6 is the threshold voltage of transistor TR6. Thus, as shown in Figure 26, transistors TR1, TR2, and TR6 are in the on state. Transistor TR3 is in the off state. Therefore, the sense amplifier 39 applies voltage VHSA to bit line BL (“1”) via transistors TR8, TR6, TR2, and TR1. Then, as shown in Figure 25, at time t33, the column decoder module 38 applies a voltage VPASS to the word line WLsel. The voltage VPASS is the voltage that will cause the memory cell transistor MC to be in the on state, regardless of the threshold voltage of the memory cell transistor MC. Thus, the voltage of the word line WLsel becomes the voltage VPASS. Next, at time t34, the sensing amplifier 39 performs an AND operation on the values ​​of latch circuits DDL and EDL, and stores the result of the AND operation in latch circuit FDL. That is, the node INV_F of latch circuit FDL is set to level L (“0”). Then, the sensing amplifier 39 performs an OR operation on the values ​​of latch circuits DDL and EDL, and stores the result of the OR operation in latch circuit SDL. That is, the node INV_S of latch circuit SDL is set to level L (“0”). Thus, transistors TR1, TR2, TR4, TR6, and TR8 remain on. Transistors TR3, TR5, and TR7 remain off. Therefore, the voltage VHSA applied to bit line BL (“1”) can be maintained. Thus, the sensing amplifier 39 adjusts the voltage applied to the bit line (“1”) based on the values ​​of the latch circuit FDL and the latch circuit SDL. Next, at time t35, the column decoder module 38 applies a voltage VPGM to the word line WLsel. Thus, the voltage of the word line WLsel becomes the voltage VPGM. As a result, as described above, the rise in the threshold voltage of the memory cell transistor MCsel is suppressed. Subsequently, at time t36, the column decoder module 38 applies voltage VSS to the word line WLsel. Thus, the voltage of the word line WLsel becomes voltage VSS. Control signals BLS, BLC, and BLX are set to level L. Control signal BLP is set to level H. This completes the fourth write operation. (First Programming Action) After the verification action of the k-th programming cycle, if node INV_D of the latch circuit DDL is at level H ("1") and node INV_E of the latch circuit EDL is at level H ("1"), the first programming action is executed in the (k+1)-th programming cycle. This is equivalent to determining, after the first and second sensing in the verification action of the k-th programming cycle, that the threshold voltage of the memory cell transistor MCsel has not reached the voltage level VL. Figure 27 is a timing diagram showing an example of the voltage of various wiring and signals during the first programming operation. Figure 28 is a diagram illustrating the operation of the sensing amplifier 39 during the first programming operation. As shown in Figure 27, at time t31, the voltage of the word line WLsel is set to voltage VSS. The voltage of the bit line BL (“0”) is set to voltage VSS. Control signals BLS, BLC, and BLX are set to level L. Control signal BLP is set to level H. The sense amplifier 39 sets the value of the latch circuit DDL to the latch circuit FDL. That is, the node INV_F of the latch circuit FDL is set to the value of node INV_D (level H (“1”)). Also, the sense amplifier 39 sets the value of the latch circuit DDL to the latch circuit SDL. That is, the node INV_S of the latch circuit SDL is set to the value of node INV_D (level H (“1”)). Hereby, transistors TR5 and TR7 become on. Transistors TR1-TR4, TR6, and TR8 become off. Next, at time t32, control signals BLS, BLC, and BLX are set to the H level. Control signal BLP is set to the L level. As shown in Figure 28, transistors TR1 to TR3 are turned on, and transistor TR6 is turned off. Therefore, the sense amplifier 39 applies voltage SRCGND to the bit line BL (“0”) via transistors TR5, TR3, TR2, and TR1. Then, as shown in Figure 27, at time t33, the column decoder module 38 applies voltage VPASS to the character line WLsel. Next, at time t34, the sensing amplifier 39 sets the result of the AND operation between the values ​​of latch circuit DDL and latch circuit EDL to latch circuit FDL. That is, it sets the node INV_F of latch circuit FDL to level H ("1"). Furthermore, the sensing amplifier 39 sets the result of the OR operation between the values ​​of latch circuit DDL and latch circuit EDL to latch circuit SDL. That is, it sets the node INV_S of latch circuit SDL to level H ("1"). As a result, transistors TR1-TR3, TR5, and TR7 remain in the ON state. Transistors TR4, TR6, and TR8 remain in the OFF state. Therefore, the voltage SRCGND applied to bit line BL ("0") can be maintained. Thus, the sensing amplifier 39 adjusts the voltage applied to the bit line (“0”) based on the values ​​of the latch circuit FDL and the latch circuit SDL. Next, at time t35, the column decoder module 38 applies voltage VPGM to the word line WLsel. As a result, as described above, the threshold voltage of the memory cell transistor MCsel increases. Due to the application of the first programming condition, the change in the threshold voltage of the memory cell transistor MC is relatively large. Subsequently, at time t36, the column decoder module 38 applies voltage VSS to the word line WLsel. Control signals BLS, BLC, and BLX are set to level L. Control signal BLP is set to level H. This completes the first write operation. (Second Programming Action) After the verification action of the k-th programming cycle, if the node INV_D of the latch circuit DDL is at level H ("1") and the node INV_E of the latch circuit EDL is at level L ("0"), the second programming action is executed in the (k+1)-th programming cycle. This is equivalent to determining, after the first and second sensing in the verification action of the k-th programming cycle, that the threshold voltage of the memory cell transistor MCsel is above voltage level VL but below voltage level VM. Figure 29 is a timing diagram showing an example of the voltage of various wiring and signals during the second programming operation. Figure 30 is a diagram illustrating the operation of the sensing amplifier 39 during the second programming operation. As shown in Figure 29, at time t31, the voltage of the word line WLsel is set to voltage VSS. The voltage of the bit line BL (“0”) is set to voltage VSS. Control signals BLS, BLC, and BLX are set to level L. Control signal BLP is set to level H. The sense amplifier 39 sets the value of the latch circuit DDL to the latch circuit FDL. That is, the node INV_F of the latch circuit FDL is set to the value of node INV_D (level H (“1”)). Also, the sense amplifier 39 sets the value of the latch circuit DDL to the latch circuit SDL. That is, the node INV_S of the latch circuit SDL is set to the value of node INV_D (level H (“1”)). Thus, similar to the first programming operation, transistors TR5 and TR7 are turned on, and transistors TR1-TR4, TR6, and TR8 are turned off. Next, at time t32, control signals BLS, BLC, and BLX are set to the H level. Control signal BLP is set to the L level. Consequently, similar to the first programming operation, transistors TR1 to TR3 are turned on, and transistor TR6 is turned off. Therefore, the sense amplifier 39 applies a voltage SRCGND to the bit line BL (“0”). Then, as shown in Figure 29, at time t33, the column decoder module 38 applies voltage VPASS to the character line WLsel. Next, at time t34, the sensing amplifier 39 sets the result of the AND operation between the values ​​of latch circuits DDL and EDL to latch circuit FDL. That is, it sets the node INV_F of latch circuit FDL to level H ("1"). Furthermore, the sensing amplifier 39 sets the result of the OR operation between the values ​​of latch circuits DDL and EDL to latch circuit SDL. That is, it sets the node INV_S of latch circuit SDL to level L ("0"). As a result, transistor TR4 becomes on. Transistor TR5 becomes off. Transistors TR1-TR3 and TR7 remain on. Transistors TR6 and TR8 remain off. Therefore, the sensing amplifier 39 applies a voltage VQPWL to bit line BL ("0"). Voltage VQPWL is higher than voltage VSS and lower than voltage VHSA. Thus, the sensing amplifier 39 adjusts the voltage applied to the bit line (“0”) based on the values ​​of the latch circuit FDL and the latch circuit SDL. Next, at time t35, the column decoder module 38 applies voltage VPGM to the word line WLsel. As a result, as described above, the threshold voltage of the memory cell transistor MCsel increases. Due to the application of the second programming condition, the change in the threshold voltage of the memory cell transistor MC is smaller than that under the first programming condition. Subsequently, at time t36, the column decoder module 38 applies voltage VSS to the word line WLsel. Control signals BLS, BLC, and BLX are set to level L. Control signal BLP is set to level H. This completes the second write operation. (Third Programming Action) After the verification action of the k-th programming cycle, if the node INV_D of the latch circuit DDL is at level L ("0") and the node INV_E of the latch circuit EDL is at level H ("1"), the third programming action is executed in the (k+1)-th programming cycle. This is equivalent to determining, after the first and second sensing in the verification action of the k-th programming cycle, that the threshold voltage of the memory cell transistor MCsel is above voltage level VM but below voltage level VH. Figure 31 is a timing diagram showing an example of the voltage of various wiring and signals during the third programming operation. Figure 32 is a diagram illustrating the operation of the sensing amplifier 39 during the third programming operation. As shown in Figure 31, at time t31, the voltage of the word line WLsel is set to voltage VSS. The voltage of the bit line BL (“0”) is set to voltage VSS. Control signals BLS, BLC, and BLX are set to level L. Control signal BLP is set to level H. The sense amplifier 39 sets the value of the latch circuit DDL to the latch circuit FDL. That is, the node INV_F of the latch circuit FDL is set to the value of node INV_D (level L (“0”)). Also, the sense amplifier 39 sets the value of the latch circuit DDL to the latch circuit SDL. That is, the node INV_S of the latch circuit SDL is set to the value of node INV_D (level L (“0”)). Thus, similar to the fourth programming operation, transistors TR4 and TR8 are turned on, and transistors TR1-TR3 and TR5-TR7 are turned off. Next, at time t32, control signals BLS, BLC, and BLX are set to the H level. Control signal BLP is set to the L level. Consequently, similar to the fourth programming operation, transistors TR1, TR2, and TR6 are turned on, and transistor TR3 is turned off. Therefore, the sense amplifier 39 applies a voltage VHSA to the bit line BL (“0”). Then, as shown in Figure 31, at time t33, the column decoder module 38 applies voltage VPASS to the character line WLsel. Next, at time t34, the sensing amplifier 39 sets the result of the AND operation between the values ​​of latch circuits DDL and EDL to latch circuit FDL. That is, it sets the node INV_F of latch circuit FDL to level H ("1"). Furthermore, the sensing amplifier 39 sets the result of the OR operation between the values ​​of latch circuits DDL and EDL to latch circuit SDL. That is, it sets the node INV_S of latch circuit SDL to level L ("0"). Hereby, transistor TR7 becomes on. Transistor TR8 becomes off. Transistors TR1, TR2, and TR4 remain on. Transistor TR5 remains off. Since VBLX - Vt3 < VBLP + Vt6, transistor TR6 becomes on, and transistor TR3 becomes off. Therefore, the sensing amplifier 39 applies a voltage VQPWH to bit line BL ("0"). The voltage VQPWH is higher than the voltage VQPWL but lower than the voltage VHSA. Thus, the sensing amplifier 39 adjusts the voltage applied to the bit line (“0”) based on the values ​​of the latch circuit FDL and the latch circuit SDL. Next, at time t35, the column decoder module 38 applies voltage VPGM to the word line WLsel. As a result, as described above, the threshold voltage of the memory cell transistor MCsel increases. Due to the application of the third programming condition, the change in the threshold voltage of the memory cell transistor MC is smaller than that under the second programming condition. Subsequently, at time t36, the column decoder module 38 applies voltage VSS to the word line WLsel. Control signals BLS, BLC, and BLX are set to level L. Control signal BLP is set to level H. This completes the third write operation. Furthermore, in the first programming cycle, when the memory cell transistor MCsel is set as the programming target, the sense amplifier 39 sets the node INV_D of the latch circuit DDL to level H ("1") and the node INV_E of the latch circuit EDL to level H ("1"), and then performs the first programming operation as described above. When the memory cell transistor MCsel is set to be unprogrammable, the sense amplifier 39 sets the node INV_D of the latch circuit DDL to level L ("0") and the node INV_E of the latch circuit EDL to level L ("0"), and then performs the fourth programming operation as described above. 1.4 Effects of this embodiment In this embodiment, during the verification operation, the sensing amplifier 39 performs a VM sensing operation as the first sensing during the period when a verification voltage VH corresponding to the write state is applied to the character line Wsel. Based on the result of the first sensing, a VH sensing operation or a VL sensing operation is performed as the second sensing. Specifically, the sensing amplifier 39 changes the capacitance value of node SEN based on the result of the VM sensing action. For example, the sensing amplifier 39 sets the capacitance value of node SEN to a first capacitance value or a second capacitance value that is larger than the first capacitance value. If, after the first sensing, the threshold voltage of the memory cell transistor MCsel is above the voltage level VM, the sensing amplifier 39 sets the capacitance value of node SEN to the first capacitance value. If, after the first sensing, the threshold voltage of the memory cell transistor MCsel is below the voltage level VM, the sensing amplifier 39 sets the capacitance value of node SEN to the second capacitance value. By changing the capacitance of node SEN, the discharge time of node SEN connected to the memory cell transistors (MCsels) contained in threshold regions A1-A2 can be made consistent with the discharge time of node SEN connected to the memory cell transistors (MCsels) contained in threshold regions A3-A4. That is, the discharge time of the charge of node SEN during VH sensing operation can be made the same as the discharge time of the charge of node SEN during VL sensing operation. This allows for a second sensing operation (VH or VL sensing) based on the result of the VM sensing operation, following the VM sensing operation. In other words, both VH and VL sensing operations can be performed simultaneously after the VM sensing operation. Therefore, through these two sensing operations, it is possible to determine which of the four threshold regions A1 to A4 the memory cell transistor MCsel is located in. Thus, according to this embodiment, compared to the case where three sensing operations are performed using the verification voltage VL, VM, and VL, the number of sensing operations can be reduced. Therefore, the increase in verification operation time can be suppressed. Furthermore, the narrowing of the sensing range can be suppressed. 2. The second embodiment will describe the NAND flash memory of the second embodiment. In the NAND flash memory 30A of the second embodiment, the circuit configuration of the sense amplifier 39A is different from that of the first embodiment. The differences from the first embodiment will be described below. 2.1 Circuit Configuration of Sensing Amplifier The circuit configuration of sensing amplifier 39A will be explained using Figure 33. Figure 33 is a circuit diagram showing an example of the circuit configuration of sensing amplifier 39A. As shown in Figure 33, in the sensing amplifier 39A, capacitors C21 and C22, the n-channel MOS transistor TR11, and the p-channel MOS transistor TR12 are removed from the sensing circuit SAC shown in Figure 11 of the first embodiment. Furthermore, in the sensing amplifier 39A, capacitors C61 and C62, the n-channel MOS transistor TR61, and the p-channel MOS transistor TR62 are added to the sensing circuit SAC. One electrode of capacitor element C61 is connected to node SEN. The other electrode of capacitor element C61 is connected to node ND2. One end of transistor TR61 is connected to node ND2. The other end of transistor TR61 is connected to node ND3. The gate of transistor TR61 is connected to node LAT_D. One end of transistor TR62 is connected to node ND2. A clock signal CLKSA is input to the other end of transistor TR62. The gate of transistor TR62 is connected to node LAT_D. One electrode of capacitor C62 is connected to node ND3. A clock signal CLKSA is input to the other electrode of capacitor C62. Transistors TR61 and TR62 can connect capacitor C61 and capacitor C62 in series, serving as a circuit to switch the connection and disconnection of capacitor C61 and capacitor C62. 2.2 Verification Operation The verification operation will be explained focusing on the operation of the sensing amplifier 39A. The following will describe the application of verification voltage V2 to the word line WLsel during the verification operation of the second programming loop. The timing diagram for the verification action in this embodiment is the same as the timing diagram in Figure 18 shown in the first embodiment. First, during the period when the verification voltage V2 is applied to the character line WLsel, the sensing amplifier 39A performs a VM sensing operation as the first sensing. Figure 34 is a diagram illustrating the operation of the sensing amplifier 39A during the VM sensing operation. As shown in Figure 18, at time t11, the voltage of the character line WLsel is set to voltage VSS. The voltage of node SEN, VSEN, is set to voltage VSS. The control signals SPC, XXL, and STB are set to level L. The clock signal CLKSA is set to level L. The node INV_D of the latch circuit DDL is set to level L ("0"). The node INV_E of the latch circuit EDL is set to level L ("0"). By setting node INV_D to level L, as shown in Figure 34, transistor TR61 becomes the on state. Transistor TR62 becomes the off state. That is, the capacitance of node SEN becomes equal to the combined capacitance of capacitor element C61 and capacitor element C62. Since capacitor C61 and capacitor C62 are connected in series, the capacitance at node SEN is smaller than the capacitance of capacitor C61 (for example, when the capacitance of capacitor C61 is equal to the capacitance of capacitor C62, it is 1 / 2 times the capacitance of capacitor C61). As shown in Figure 18, at time t12, the control signal SPC is set to level H. Consequently, as shown in Figure 34, transistor TR10 becomes on, thus applying voltage VHLB to node SEN. That is, as indicated by the solid arrow in Figure 34, node SEN is charged. As shown in Figure 18, at time t14, control signal XXL is set to level H, and control signals BLS and BLC are also set to level H. Consequently, as shown in Figure 34, transistors TR9, TR2, and TR1 are turned on. Therefore, as indicated by the dashed arrow in Figure 34, the charge charged to node SEN is discharged to bit line BL. After the VM sensing operation is completed, during the period when the verification voltage V2 is applied to the character line WLsel, the sensing amplifier 39A stores the result of the first sensing in the latch circuit DDL, and then performs either the VH sensing operation or the VL sensing operation as the second sensing. Figure 35 is a diagram illustrating the operation of the sensing amplifier 39A during the VH sensing operation. Figure 36 is a diagram illustrating the operation of the sensing amplifier 39A during the VL sensing operation. After the VM sensing operation, when the memory cell transistor MCsel is in the off state, the sensing amplifier 39A performs a VH sensing operation as a second sensing. As shown in Figure 18, at time t20, node INV_D is at level L ("0"). Node INV_E is at level L ("0"). By setting node INV_D to level L, as shown in Figure 35, transistor TR61 becomes on. Transistor TR62 becomes off. That is, the capacitance of node SEN becomes equal to the combined capacitance of capacitor elements C61 and C62. Also, as shown in Figure 18, at time t20, the control signal SPC is set to level H. Therefore, as shown in Figure 35, transistor TR10 becomes on, thus applying voltage VHLB to node SEN. That is, as shown by the solid arrow in Figure 35, node SEN is charged. As shown in Figure 18, at time t22, control signal XXL is set to level H, and control signals BLS and BLC are also set to level H. Consequently, as shown in Figure 35, transistors TR9, TR2, and TR1 are turned on. Therefore, as indicated by the dashed arrow in Figure 35, the charge charged to node SEN is discharged to bit line BL. After the VM sensing operation, when the memory cell transistor MCsel is in the conducting state, the sensing amplifier 39A performs a VL sensing operation as a second sensing. As shown in Figure 18, at time t20, node INV_D is at level H ("1"). Node INV_E is at level L ("0"). By setting node INV_D to level H, as shown in Figure 36, transistor TR61 becomes off. Transistor TR62 becomes on. That is, the capacitance of node SEN becomes equal to the capacitance of capacitor element C61. Also, as shown in Figure 18, at time t20, the control signal SPC is set to level H. Therefore, as shown in Figure 36, transistor TR10 becomes on, and a voltage VHLB is applied to node SEN. That is, as shown by the solid arrow in Figure 36, node SEN is charged. As shown in Figure 18, at time t22, control signal XXL is set to level H, and control signals BLS and BLC are also set to level H. Consequently, as shown in Figure 36, transistors TR9, TR2, and TR1 are turned on. Therefore, as indicated by the dashed arrow in Figure 36, the charge charged to node SEN is discharged to bit line BL. 2.3 Effects of this embodiment According to the second embodiment, the same effects as the first embodiment can be achieved. 3. The third embodiment will describe the NAND flash memory of the third embodiment. In the NAND flash memory 30B of the third embodiment, the circuit configuration of the sense amplifier 39B is different from that of the first embodiment. The differences from the first embodiment will be described below. 3.1 Circuit Configuration of Sensing Amplifier The circuit configuration of sensing amplifier 39B will be explained using Figure 37. Figure 37 is a circuit diagram showing an example of the circuit configuration of sensing amplifier 39B. As shown in Figure 37, in the sensing amplifier 39B, capacitors C21 and C22, the n-channel MOS transistor TR11, and the p-channel MOS transistor TR12 are removed from the sensing circuit SAC shown in Figure 11 of the first embodiment. Furthermore, in the sensing amplifier 39B, capacitors C71 and C72, and the n-channel MOS transistor TR71 are added to the sensing circuit SAC. One electrode of capacitor C71 is connected to node SEN. A clock signal CLKSA is input to the other electrode of capacitor C71. One end of transistor TR71 is connected to node SEN. The other end of transistor TR71 is connected to node ND4. The gate of transistor TR71 is connected to node INV_D. Capacitor C72 is, for example, a parasitic capacitance of the bus LBUS. One electrode of capacitor C72 is connected to the bus LBUS. A clock signal CLKSA is input to the other electrode of capacitor C72. Transistors TR71 and TR15 can connect capacitor C71 and capacitor C72 in parallel, serving as a circuit to switch the connection and disconnection of capacitor C71 and capacitor C72. 3.2 Verification Operation The verification operation will be explained focusing on the operation of the sensing amplifier 39B. The following will describe the application of verification voltage V2 to the word line WLsel during the verification operation of the second programming loop. Figure 38 is a timing diagram showing an example of the voltage of various wiring and signals during the verification operation. First, during the period when the verification voltage V2 is applied to the character line WLsel, the sensing amplifier 39B performs a VM sensing operation as the first sensing. Figure 39 is a diagram illustrating the operation of the sensing amplifier 39B during the VM sensing operation. As shown in Figure 38, at time t11, the voltage of the word line WLsel is set to voltage VSS. The voltage of node SEN, VSEN, is set to voltage VSS. The control signals SPC, XXL, STB, LPC, and BLQ are set to level L. The clock signal CLKSA is set to level L. The node INV_D of the latch circuit DDL is set to level L ("0"). The node INV_E of the latch circuit EDL is set to level L ("0"). By setting node INV_D to level L, as shown in Figure 39, transistor TR71 becomes off. That is, the capacitance of node SEN becomes equal to the capacitance of capacitor element C71. As shown in Figure 38, at time t12, the control signal SPC is set to level H. Consequently, as shown in Figure 39, transistor TR10 becomes on, thus applying voltage VHLB to node SEN. That is, as indicated by the solid arrow in Figure 39, node SEN is charged. As shown in Figure 38, at time t14, control signal XXL is set to level H, and control signals BLS and BLC are also set to level H. Consequently, as shown in Figure 39, transistors TR9, TR2, and TR1 are turned on. Therefore, as indicated by the dashed arrow in Figure 39, the charge charged to node SEN is discharged to bit line BL. After the VM sensing operation is completed, during the period when the verification voltage V2 is applied to the word line WLsel, the sensing amplifier 39B stores the result of the first sensing in the latch circuit DDL, and then performs either the VH sensing operation or the VL sensing operation as the second sensing. Figure 40 is a diagram illustrating the operation of the sensing amplifier 39B during the VH sensing operation. Figure 41 is a diagram illustrating the operation of the sensing amplifier 39B during the VL sensing operation. After the VM sensing operation, when the memory cell transistor MCsel is in the off state, the sensing amplifier 39B performs a VH sensing operation as a second sensing. As shown in Figure 38, at time t19a, node INV_D is at level L ("0"). Node INV_E is at level L ("0"). By setting node INV_D to level L, as shown in Figure 40, transistor TR71 becomes off. That is, the capacitance of node SEN becomes equal to the capacitance of capacitor element C71. Also, as shown in Figure 38, at time t19a, the control signal LPC is set to level L. At time t20, the control signal SPC is set to level H. Therefore, as shown in Figure 40, transistor TR10 becomes on, thus applying voltage VHLB to node SEN. That is, as shown by the solid arrow in Figure 40, node SEN is charged. As shown in Figure 38, at time t22, control signal XXL is set to level H, control signals BLS and BLC are also set to level H, and control signal BLQ is set to level L. Consequently, as shown in Figure 40, transistors TR9, TR2, and TR1 are turned on. Therefore, as indicated by the dashed arrow in Figure 40, the charge charged to node SEN is discharged to bit line BL. After the VM sensing operation, when the memory cell transistor MCsel is in the conducting state, the sensing amplifier 39B performs a VL sensing operation as a second sensing. As shown in Figure 38, at time t19a, node INV_D is at level H ("1"). Node INV_E is at level L ("0"). By setting node INV_D to level H, as shown in Figure 41, transistor TR71 becomes in the conducting state. Also, as shown in Figure 38, at time t19a, the control signal LPC is set to level H. Therefore, as shown in Figure 41, transistor TR18 becomes in the conducting state, thus applying voltage VDDSA to bus LBUS. That is, as shown by the solid arrow in Figure 41, charging of bus LBUS begins. As shown in Figure 38, at time t19b, the control signal LPC is set to the L level. This ends the charging of the bus LBUS. At time t20, the control signal SPC is set to level H. As shown in Figure 41, transistor TR10 is turned on, thus applying voltage VHLB to node SEN. That is, node SEN is charged, as indicated by the solid arrow in Figure 41. As shown in Figure 38, at time t22, control signals XXL and BLQ are set to H level, and control signals BLS and BLC are also set to H level. Consequently, as shown in Figure 41, transistors TR15, TR9, TR2, and TR1 are turned on. At this time, the capacitance of node SEN becomes equal to the combined capacitance of capacitors C71 and C72. Since capacitors C71 and C72 are connected in parallel, the capacitance of node SEN becomes larger than the capacitance of capacitor C71 (for example, when the capacitance of capacitor C71 equals the capacitance of capacitor C72, it is twice the capacitance of capacitor C71). Therefore, as shown by the dashed arrow in Figure 41, the charge charged to node SEN and bus LBUS begins to discharge to bit line BL. As shown in Figure 38, at time t23, control signals XXL and BLQ are set to the L level, and control signals BLS and BLC are also set to the L level. This ends the discharge of bit line BL. The operation of the sensing amplifier 39, other than the above-described operation, is the same as the timing diagram in FIG18 shown in the first embodiment. 3.3 Effects of this embodiment According to the third embodiment, the same effects as the first embodiment can be achieved. Furthermore, in this embodiment, the parasitic capacitance (capacitor element C72) of the bus LBUS is used as the capacitor element for the VL sensing operation. Therefore, according to this embodiment, no new capacitor element needs to be added to the sensing circuit SAC as the capacitor element for the sensing operation, thus reducing the number of components. 3.4 Variations A variation of the NAND flash memory according to the third embodiment will be described. In the NAND flash memory 30C of the variation of the third embodiment, the circuit configuration of the sense amplifier 39C differs from that of the third embodiment. The differences from the third embodiment will be explained below. 3.4.1 Circuit Configuration of Sensing Amplifier The circuit configuration of sensing amplifier 39C will be explained using Figure 42. Figure 42 is a circuit diagram showing an example of the circuit configuration of sensing amplifier 39C. As shown in Figure 33, an n-channel MOS transistor TR72 is added to the sensing circuit SAC of Figure 37 shown in the third embodiment in the sensing amplifier 39C. One end of transistor TR72 is connected to node SEN. The other end of transistor TR72 is connected to node ND4. A control signal / QPW is input to the gate of transistor TR72. The control signal / QPW is generated, for example, by sequencer 35. Transistor TR72 is in an off state during the aforementioned two sensing write operations in the verification operation, and in an on state during other operations. That is, when one of transistors TR71 and TR72 is in an on state, the other is in an off state. 3.4.2 Effects of this variation: According to this variation, the same effects as in the third embodiment can be achieved. Furthermore, in this variation, a transistor TR72 is provided in the sensing circuit SAC for operations other than the write operation of the two sensing operations described above during the verification process. Therefore, according to this variation, the write operation of the two sensing operations described above during the verification process and other operations can be used separately. 4. Variations, etc. As described above, the semiconductor memory device (30) of the embodiment includes: a memory cell (MC) for storing data; a word line (WLsel) connected to the memory cell; a bit line (BL) connectable to the memory cell; and a sense amplifier (39) including a first node (SEN) connectable to the bit line, which senses the first voltage (VSEN) of the first node when a charge charged to the first node is discharged to the bit line. The write operation performed on the memory cell (MC) includes a programming operation and a verification operation. During the verification operation, the sensing amplifier (39) performs a first sensing operation at the first voltage level (VM) as the first sensing during the period when a verification voltage (VH) is applied to the character line (WLsel). Based on the result of the first sensing, it performs a second sensing operation at the second voltage level (VH) with a voltage higher than the first voltage level, or a third sensing operation at the third voltage level (VL) with a voltage lower than the first voltage level, as the second sensing. Furthermore, the implementation method is not limited to the method described above, but can be varied in various ways. Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included within the scope of the invention equivalents described in the claims. [Related Applications] This application claims priority to Japanese Patent Application No. 2024-028620 (filed on February 28, 2024). This application incorporates the entire contents of that basic application by reference. 1: Memory System 2: Host 10: Memory Controller 11: Host Interface Circuit 12: Processor 13: Buffer Memory 14: ECC Circuit 15: ROM 16: RAM 17: NAND Interface Circuit 30, 30A, 30B, 30C: Semiconductor Memory Device 31: Input / Output Circuit 32: Logic Control Circuit 33: Ready / Busy Circuit 34: Register 34A: Instruction Register 34B: Address Register 34C: Status Register 35: Sequencer 36: Memory Cell Array 37: Voltage Generation Circuit 38: Column Decoder Module 39, 39A, 39B, 39C: Sensing Amplifier 40: Data Bus Circuit 100: Array Chip 101, 103, 106, 107, 109, 110: Wiring Layer 102, 104, 105: Insulating Layer 108, 111: Bonding pad; 121: Passivation layer; 181: Core film; 182: Semiconductor film; 183: Multilayer film; 183a: First insulating layer; 183b: Second insulating layer; 183c: Third insulating layer; 200: Circuit chip; 201: Semiconductor substrate; 202: Insulating layer; 203-205, 207-209: Wiring layer; 206, 210: Fitting Pad CLKSA: Clock Signal INV_D: Node INV_E: Node SEN: Node SPC: Control Signal STB: Control Signal t11: Time t12: Time t13: Time t14: Time t15: Time t16: Time t17: Time t18: Time t19: Time t20: Time t21: Time t22: Time t23: Time t24: Time t25: Time t26: Time t27: Time V2: Voltage VH: Verification Voltage VHLB: Voltage VL: Verification Voltage VM: Verification Voltage VSS: Voltage WLsel: Character Line XXL: Control Signal Figure 1 is a block diagram showing an example of the configuration of a memory system including the semiconductor memory device of the first embodiment. Figure 2 is a block diagram showing an example of the configuration of the semiconductor memory device of the first embodiment. Figure 3 is a circuit diagram showing an example of the circuit configuration of the memory cell array included in the semiconductor memory device of the first embodiment. Figure 4 is a perspective view showing the outline of the bonding structure of the semiconductor memory device of the first embodiment. Figure 5 is a top view showing an example of the planar layout of the array chip in the semiconductor memory device of the first embodiment. Figure 6 is a top view showing an example of the planar layout of the circuit chip in the semiconductor memory device of the first embodiment. Figure 7 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device of the first embodiment. Figure 8 is a cross-sectional view of the memory pillar and its vicinity in the memory cell region of the array chip in the semiconductor memory device of the first embodiment. Figure 9 is a cross-sectional view showing an example of the cross-sectional structure of the memory pillar included in the semiconductor memory device of the first embodiment. Figure 10 is a block diagram showing an example of the configuration of the sense amplifier included in the semiconductor memory device of the first embodiment. Figure 11 is a circuit diagram showing an example of the circuit configuration of the sense amplifier included in the semiconductor memory device of the first embodiment. Figure 12 is a conceptual diagram showing an example of the data storage method of the semiconductor memory device of the first embodiment. Figure 13 is a timing diagram showing an overview of the write operation of the semiconductor memory device of the first embodiment. Figure 14 is a table showing an example of the programming loop setting in the write operation of the semiconductor memory device of the first embodiment. Figure 15 is a graph illustrating the relationship between the three verification voltages and threshold voltage distributions that can be used in each write state in the write operation of the semiconductor memory device of the first embodiment. Figure 16 is a graph showing the voltage change of the sense node when the charge of the sense node is discharged while the voltage of the word line is fixed during the verification operation. Figure 17 is a graph showing the voltage change of the sense node when the charge of the sense node is discharged while the voltage of the word line is fixed during the verification operation. Figure 18 is a timing diagram showing an example of the voltages of various wiring and signals during the verification operation of the semiconductor memory device of the first embodiment. Figure 19 illustrates the operation of the sensing amplifier during the VM sensing operation of the semiconductor memory device according to the first embodiment. Figure 20 illustrates the result of the first sensing obtained by the semiconductor memory device of the first embodiment performing the VM sensing operation. Figure 21 illustrates the operation of the sensing amplifier during the VH sensing operation of the semiconductor memory device of the first embodiment. Figure 22 illustrates the result of the second sensing obtained by the semiconductor memory device of the first embodiment performing the VH sensing operation. Figure 23 illustrates the operation of the sensing amplifier during the VL sensing operation of the semiconductor memory device of the first embodiment. Figure 24 illustrates the result of the second sensing obtained by the semiconductor memory device of the first embodiment performing the VL sensing operation.Figure 25 is a timing diagram showing an example of the voltages of various wirings and signals during the fourth programming operation of the semiconductor memory device of the first embodiment. Figure 26 is a diagram illustrating the operation of the sense amplifier during the fourth programming operation of the semiconductor memory device of the first embodiment. Figure 27 is a timing diagram showing an example of the voltages of various wirings and signals during the first programming operation of the semiconductor memory device of the first embodiment. Figure 28 is a diagram illustrating the operation of the sense amplifier during the first programming operation of the semiconductor memory device of the first embodiment. Figure 29 is a timing diagram showing an example of the voltages of various wirings and signals during the second programming operation of the semiconductor memory device of the first embodiment. Figure 30 is a diagram illustrating the operation of the sense amplifier during the second programming operation of the semiconductor memory device of the first embodiment. Figure 31 is a timing diagram showing an example of the voltages of various wirings and signals during the third programming operation of the semiconductor memory device of the first embodiment. Figure 32 is a diagram illustrating the operation of the sense amplifier during the third programming operation of the semiconductor memory device of the first embodiment. Figure 33 is a circuit diagram illustrating an example of the circuit configuration of the sense amplifier included in the semiconductor memory device of the second embodiment. Figure 34 is a diagram illustrating the operation of the sense amplifier when the VM sensing operation of the semiconductor memory device of the second embodiment is activated. Figure 35 is a diagram illustrating the operation of the sense amplifier when the VH sensing operation of the semiconductor memory device of the second embodiment is activated. Figure 36 is a diagram illustrating the operation of the sense amplifier when the VL sensing operation of the semiconductor memory device of the second embodiment is activated. Figure 37 is a circuit diagram illustrating an example of the circuit configuration of the sense amplifier included in the semiconductor memory device of the third embodiment. Figure 38 is a timing diagram illustrating an example of the voltage of various wirings and signals during the verification operation of the semiconductor memory device of the third embodiment. Figure 39 is a diagram illustrating the operation of the sense amplifier when the VM sensing operation of the semiconductor memory device of the third embodiment is activated. Figure 40 is a diagram illustrating the operation of the sense amplifier when the VH sensing operation of the semiconductor memory device of the third embodiment is activated. Figure 41 is a diagram illustrating the operation of the sense amplifier when the VL sensing operation of the semiconductor memory device of the third embodiment is activated. Figure 42 is a circuit diagram showing an example of the circuit configuration of the sense amplifier included in the semiconductor memory device according to a variation of the third embodiment. Figure 43 is a diagram showing the memory cell transistor included in the semiconductor memory device according to the first embodiment and its general electrical characteristics. CLKSA: Clock signal INV_D: Node INV_E: Node SEN: node SPC: Control Signal STB: Control Signal t11: Time t12: Time t13: Time t14: Time t15: Time t16: Time t17: Time t18: Time t19: Time t20: Time t21: Time t22: Time t23: Time t24: Time t25: Time t26: Time t27: Time V2: Voltage VH: Verification voltage VHLB: Voltage VL: Verification voltage VM: Verification Voltage VSS: Voltage WLsel: Character Line XXL: Control signal

Claims

1. A semiconductor memory device comprising: a first memory cell configured to a first threshold voltage; a second memory cell configured to a second threshold voltage; a word line commonly connected to the first memory cell and the second memory cell; a first bit line connected to the first memory cell; and a second bit line connected to the second memory cell. A first sensing amplifier, comprising a first node and connectable to the first bit line, determines the first threshold voltage of the first memory cell based on a first voltage of the first node when the charge charged to the first node is discharged to the first bit line; and a second sensing amplifier, comprising a second node and connectable to the second bit line, determines the second threshold voltage of the second memory cell based on a second voltage of the second node when the charge charged to the second node is discharged to the second bit line; and the semiconductor memory device performs a write operation including a programming operation and a verification operation on the first memory cell and the second memory cell; during the first period of the verification operation, the first sensing amplifier performs a first sensing operation to determine whether the first threshold voltage of the first memory cell is above a first voltage level, and the second sensing amplifier performs a second sensing operation to determine whether the second threshold voltage of the second memory cell is above the first voltage level. During the second period following the first period of the verification operation, the first sensing amplifier performs a third sensing operation to determine whether the first threshold voltage of the first memory cell is above a second voltage level that is higher than the first voltage level, and the second sensing amplifier performs a fourth sensing operation to determine whether the second threshold voltage of the second memory cell is above a third voltage level that is lower than the first voltage level. When the first sensing amplifier determines that the first threshold voltage of the first memory cell is above the first voltage level through the first sensing operation, it performs the third sensing operation. When the second sensing amplifier determines that the second threshold voltage of the second memory cell does not reach the first voltage level through the second sensing operation, it performs the fourth sensing operation.

2. The semiconductor memory device of claim 1, wherein the charge discharge time of the first node in the third sensing operation is the same as the charge discharge time of the second node in the fourth sensing operation.

3. The semiconductor memory device of claim 1, wherein the first sensing amplifier sets the capacitance value of the first node to a first capacitance value in the first sensing operation and the third sensing operation, the second sensing amplifier sets the capacitance value of the second node to the first capacitance value in the second sensing operation, and sets the capacitance value of the second node to a second capacitance value that is larger than the first capacitance value in the fourth sensing operation.

4. The semiconductor memory device of claim 3, wherein when the first threshold voltage of the first memory cell is above the first voltage level, the first sensing amplifier sets the capacitance value of the first node in the third sensing operation to the first capacitance value; and when the second threshold voltage of the second memory cell does not reach the first voltage level, the second sensing amplifier sets the capacitance value of the second node in the fourth sensing operation to the second capacitance value.

5. The semiconductor memory device of claim 1, wherein in the programming operation following the verification operation, when the first threshold voltage of the first memory cell does not reach the third voltage level, the first sensing amplifier applies the second voltage to the first bit line; when the first threshold voltage of the first memory cell is above the third voltage level but below the first voltage level, the first sensing amplifier applies a third voltage higher than the second voltage to the first bit line; when the second threshold voltage of the second memory cell is above the first voltage level but below the second voltage level, the second sensing amplifier applies a fourth voltage higher than the third voltage to the second bit line; and when the second threshold voltage of the second memory cell is above the second voltage level, the second sensing amplifier applies a fifth voltage higher than the fourth voltage to the second bit line.

6. A semiconductor memory device comprising: a non-volatile first memory cell configured to a first threshold voltage; a first bit line connected to the first memory cell; and a first sense amplifier; the first sense amplifier comprising: a first node connected to the first bit line; a first capacitor connected to the first node; a second capacitor; a first circuit capable of switching the connection and disconnection of the second capacitor to the first node; and a first latch circuit; wherein the first sense amplifier is capable of performing a sensing operation, the sensing operation referring to: storing in the first latch circuit a value of a first voltage of the first node based on the discharge of charge charged to the first node to the bit line; and the first circuit switching the connection and disconnection of the second capacitor to the first node based on the value of the first latch circuit.

7. The semiconductor memory device of claim 6, wherein the first circuit can connect the first capacitor element and the second capacitor element in parallel.

8. The semiconductor memory device of claim 6, wherein the first circuit can connect the first capacitor element and the second capacitor element in series.

9. The semiconductor memory device of claim 6 further includes a first word line connected to the first memory cell and is capable of performing a write operation including a programming operation and a verification operation on the first memory cell. During the first period of the verification operation, the first sensing amplifier performs a first sensing operation to determine whether the first threshold voltage of the first memory cell is above a first voltage level, and stores the result of the first sensing operation in the first latch circuit.

10. The semiconductor memory device of claim 9, wherein the first sensing amplifier performs a second sensing operation to determine whether the first threshold voltage of the first memory cell is above a second voltage level higher than the first voltage level, or a third sensing operation to determine whether the first threshold voltage of the first memory cell is above a third voltage level lower than the first voltage level, during a second period after the first period of the verification operation.

11. The semiconductor memory device of claim 10, wherein the charge discharge time of the first node in the second sensing operation is the same as the charge discharge time of the first node in the third sensing operation.

12. The semiconductor memory device of claim 10, wherein the first sensing amplifier further includes a second latch circuit, and the first sensing amplifier stores the result of the second sensing action or the third sensing action in the second latch circuit.

13. The semiconductor memory device of claim 12, wherein the first sense amplifier further comprises: a third latch circuit; and a fourth latch circuit, and in the programming operation, the first sense amplifier, after storing the value of the first latch circuit to the third latch circuit and the fourth latch circuit, performs an AND operation between the value of the first latch circuit and the value of the second latch circuit, and stores the result of the AND operation to the third latch circuit, performs an OR operation between the value of the first latch circuit and the value of the second latch circuit, and stores the result of the OR operation to the fourth latch circuit.

14. The semiconductor memory device of claim 13, wherein the first sensing amplifier adjusts the voltage applied to the first bit line during the programming operation based on the value of the third latch circuit and the value of the fourth latch circuit.

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