Semiconductor device and fabricating method thereof

Abstract

A semiconductor device and a method for manufacturing the semiconductor device are disclosed. The semiconductor device includes first and second redundant epitaxial layers disposed in first and second base structures, first and second active epitaxial layers disposed on the first and second redundant epitaxial layers, a first active nanostructure layer disposed adjacent to and in contact with the first active epitaxial layer, a second active nanostructure layer disposed adjacent to and in contact with the second active epitaxial layer, a redundant nanostructure layer disposed adjacent to and in contact with the second redundant epitaxial layer, a first gate structure surrounding the first active nanostructure layer, and a second gate structure surrounding the second active nanostructure layer and the redundant nanostructure layer.

Description

Semiconductor devices and manufacturing methods thereof This disclosure relates to a semiconductor device, particularly a semiconductor device with a gate-all-around field-effect transistor having different drive current characteristics on the same substrate. With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher efficiency, and lower costs continues to grow. To meet these demands, the semiconductor industry continues to miniaturize semiconductor devices, such as metal oxide semiconductor field-effect transistors (MOSFETs), including planar MOSFETs, fin field-effect transistors (finFETs), and gate-all-around field-effect transistors (GAAFETs). This miniaturization increases the complexity of the semiconductor manufacturing process. This disclosure provides a semiconductor device. The semiconductor device includes a first base structure and a second base structure, a first redundancy layer and a second redundancy layer, a first active epitaxial layer and a second active epitaxial layer, a first active nanostructure layer, a second active nanostructure layer, a redundancy nanostructure layer, a first gate structure, and a second gate structure. The first redundancy layer and the second redundancy layer are individually disposed in the first base structure and the second base structure. The height of the second redundancy layer is greater than the height of the first redundancy layer. The first active epitaxial layer and the second active epitaxial layer are individually disposed on the first redundancy layer and the second redundancy layer. The height of the first active epitaxial layer is greater than the height of the second active epitaxial layer. The first active nanostructure layer is disposed adjacent to and in contact with the first active epitaxial layer. The second active nanostructure layer is disposed adjacent to and in contact with the second active epitaxial layer. The redundancy nanostructure layer is disposed adjacent to and in contact with the second redundancy layer. The first gate structure surrounds the first active nanostructure layer. The second gate structure surrounds the second active nanostructure layer and the redundancy nanostructure layer. This disclosure provides a semiconductor device. The semiconductor device includes a base structure, a redundant nanostructure layer, an active nanostructure layer, a first source / drain region, a second source / drain region, an isolation layer, a first contact structure, a second contact structure, and a gate structure. The redundant nanostructure layer is disposed on the base structure layer. The active nanostructure layer is disposed on the redundant nanostructure layer. The first source / drain region is disposed adjacent to a first end of the active nanostructure layer. The second source / drain region is disposed adjacent to a second end of the active nanostructure layer. The isolation layer is disposed on the back side of the first source / drain region. The first contact structure is disposed on the front side of the first source / drain region. The second contact structure is disposed on the back side of the second source / drain region. The gate structure surrounds the active nanostructure layer and the redundant nanostructure layer. This disclosure provides a method for manufacturing a semiconductor device. The method includes forming a superlattice structure on a substrate, the superlattice structure including a first nanostructure layer, a sacrificial nanostructure layer on the first nanostructure layer, and a second nanostructure layer on the sacrificial nanostructure layer; forming a polycrystalline silicon layer on the superlattice structure; forming a first opening and a second opening in the superlattice structure; epitaxially growing a first semiconductor layer and a second semiconductor layer in the first opening and the second opening, wherein the first semiconductor layer and the second semiconductor layer contact a plurality of sidewalls of the first nanostructure layer; epitaxially growing a third semiconductor layer and a fourth semiconductor layer on the first semiconductor layer and the second semiconductor layer, wherein the third semiconductor layer and the fourth semiconductor layer contact the second nanostructure layer and the sacrificial nanostructure layer; replacing the polycrystalline silicon layer and the sacrificial nanostructure layer with a gate structure; and replacing the first semiconductor layer with a contact structure on the back side of the third semiconductor layer. This disclosure provides many different embodiments or examples to implement the different features of this invention. The following disclosure describes specific embodiments of the various components and their arrangements for simplification. Of course, these specific examples are not intended to be limiting. For example, if this disclosure describes a first feature formed on or above a second feature, it means that it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features may not be in direct contact. As used herein, forming a first feature on a second feature means that the first feature is formed in direct contact with the second feature. Furthermore, the same reference numerals and / or designations may be repeated in the different embodiments of this disclosure below. These repetitions are for simplification and clarity and are not intended to limit the specific relationship between the different embodiments and / or structures discussed. Spatial terms, such as “below,” “lower,” “above,” “higher,” and similar terms, are used to facilitate the description of the relationship between one element or feature and another element(s) in the illustration. In addition to the orientation shown in the illustration, these spatial terms are intended to encompass different orientations of the device in use or operation. Furthermore, the device may be rotated to different orientations (90 degrees or other orientations), and the spatial terms used here can be interpreted in the same way. It is worth noting that references to "an embodiment," "an exemplary embodiment," "an example," etc., in the specification indicate that the described embodiment may include specific features, structures, or characteristics, but not every embodiment necessarily includes specific features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such features, structures, or characteristics in conjunction with other embodiments will be within the knowledge of those skilled in the art. It should be understood that the terms or expressions used herein are for descriptive and not limiting purposes, and that the terms or expressions used herein shall be interpreted by one of ordinary skill in the art based on the teachings herein. In some embodiments, the terms "about" and "approximately" may refer to a value of a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10~15%, ±15~20%). These values ​​are merely examples and not limiting. The terms "about" and "approximately" may refer to a percentage of a value as interpreted by one of ordinary skill in the art based on the teachings herein. Gate-all-around (GAA) transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more lithography processes, including dual-patterning or multi-patterning processes. Dual-patterning or multi-patterning processes combine lithography and self-alignment processes, allowing the creation of patterns with a smaller pitch than that achievable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure. A Gaussian Analog FET (GAA FET) may include a base structure (also called a "sheet base" or "fin base") disposed on a substrate, source / drain (S / D) regions disposed on the substrate, nanostructured layers disposed on the base structure and between the S / D regions, and a gate structure surrounding each nanostructured layer. The nanostructured layers between the S / D regions serve as the channel regions of the GAA FET, and the drive current characteristics (e.g., drive current value) of the GAA FET may depend on the number of nanostructured layers between the S / D regions. This disclosure provides exemplary structures of GAA FETs with different drive current characteristics on the same substrate of a semiconductor device, and also provides exemplary methods for manufacturing these GAA FETs. In some embodiments, a first GAA FET may have a first nanostructure layer between a first pair of S / D regions, and a second GAA FET may have a second nanostructure layer between a second pair of S / D regions. The number of first nanostructure layers may be greater than the number of second nanostructure layers to achieve a higher drive current in the first GAA FET than in the second GAA FET. The semiconductor device may have GAA FETs with different drive current values ​​to optimize the overall power consumption of the semiconductor device. In some embodiments, the number of first and second nanostructure layers in contact with the first and second pairs of S / D regions may be controlled by using first and second electrically inactive (“redundant”) epitaxial layers disposed beneath the first and second pairs of S / D regions. In some embodiments, the first and second redundant epitaxial layers may also be used to form self-aligned back-side contact structures on the back-side surfaces of the first and second pairs of S / D regions. In some embodiments, the first redundant epitaxial layer and the second redundant epitaxial layer can be replaced by a back isolation layer to reduce current leakage from the first pair of S / D regions and the second pair of S / D regions to the substrate. Figure 1 shows a schematic diagram of a semiconductor device 100 having GAA FETs 102A and 102B according to some embodiments. In some embodiments, GAA FETs 102A and 102B may both be P-type GAA FETs or N-type GAA FETs, or may be one of each conductivity type of GAA FET. Figures 2A through 6A show different cross-sectional views of GAA FET 102A along line segment AA of Figure 1 according to some embodiments. Figures 2B through 6B show different cross-sectional views of GAA FET 102B along line segment BB of Figure 1 according to some embodiments. Figures 2A through 6A and 2B through 6B show cross-sectional views with additional structures, which are not shown in Figure 1 for simplicity. Unless otherwise stated, the discussion of elements with the same annotations in Figures 1, 2A through 6A, and 2B through 6B applies to each other. Semiconductor device 100 may be formed on substrate 104, wherein GAA FETs 102A and 102B are formed on different regions of substrate 104. Other GAA FETs and / or structures (e.g., isolation structures) between GAA FETs 102A and 102B formed on substrate 104 may be present. In some embodiments, substrate 104 may be a semiconductor material, such as silicon, germanium (Ge), silicon-germanium (SiGe), silicon-on-insulator (SOI) structures, and combinations thereof. Furthermore, substrate 104 may be doped with p-type dopant (e.g., boron, indium, aluminum, or gallium) or n-type dopant (e.g., phosphorus or arsenic). Semiconductor device 100 may further include a shallow trench isolation (STI) region 105 disposed on substrate 104. STI region 105 may include an insulating material, such as silicon oxide (SiO2). 2) Silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbide (SiCN), silicon oxycarbide (SiOCN), and germanium silicon oxide (SiGeO) x ). Referring to Figures 1 and 2A, in some embodiments, the GAA FET 102A may include (i) a fin-like base structure 106A (also referred to as "sheet base 106A" or "fin sheet base 106A") disposed on a substrate 104, (ii) an active nanostructure layer 208A disposed on the base structure 106A, (iii) an S / D region 110A disposed adjacent to the active nanostructure layer 208A, (iv) a gate structure 112A surrounding the active nanostructure layer 208A, (v) an external gate spacer 114A, (vi) an internal gate spacer 216A, (vii) a back-side (BS) etch stop layer (ESL) 118A (also referred to as "capping layer 118A" or "seed layer 118A"), (viii) a redundant epitaxial layer 120A, and (ix) a front-side (FS) ESL. 122A, (x) interlayer dielectric (ILD) layer 124A, and (xi) FS junction structure 226A. Similarly, referring to Figures 1 and 2B, in some embodiments, the GAA FET 102B may include (i) a fin-like base structure 106B (also referred to as "sheet base 106B" or "fin sheet base 106B") disposed on a substrate 104, (ii) a redundant nanostructure layer 208C disposed on the base structure 106B, (iii) an active nanostructure layer 208B disposed on the redundant nanostructure layer 208C, (iv) an S / D region 110B disposed adjacent to the active nanostructure layer 208B, (v) a gate structure 112B surrounding the active nanostructure layer 208B and the redundant nanostructure layer 208C, (vi) an external gate spacer 114B, (vii) an internal gate spacer 216B, (viii) a BS ESL 118B (also referred to as "capping layer 118B" or "seed layer 118B"), (ix) a redundant epitaxial layer 120B, and (x) a FS. ESL 122B, (xi)ILD layer 124B, and (xii)FS contact structure 226B. In some embodiments, base structures 106A and 106B may comprise a material similar to substrate 104. Base structures 106A and 106B may have elongated sides extending along the X-axis. Referring to Figures 2A and 2B, in some embodiments, the active nanostructure layers 208A and 208B and the redundant nanostructure layer 208C may be in the form of nanosheets, nanowires, nanorods, nanotubes, or other suitable nanostructure shapes. As used herein, the term "nanostructure" defines a structure, layer, and / or region as having a horizontal dimension (e.g., along the X-axis and / or Y-axis) and / or a vertical dimension (e.g., along the Z-axis) of less than about 100 nm, such as about 90 nm, about 50 nm, about 10 nm, or other values ​​less than about 100 nm. In some embodiments, the active nanostructure layers 208A and 208B and the redundant nanostructure layer 208C may comprise semiconductor materials similar to or different from the substrate 104. In some embodiments, the active nanostructure layers 208A and 208B and the redundant nanostructure layer 208C may include Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon phosphide carbon (SiCP), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), group III-V semiconductor compounds or other suitable semiconductor materials. In some embodiments, each of the active nanostructure layers 208A and 208B and the redundant nanostructure layer 208C may have a thickness of about 3 nm to about 15 nm along the Z-axis. Although a rectangular cross-section of the active nanostructure layers 208A and 208B and the redundant nanostructure layer 208C is shown, the active nanostructure layers 208A and 208B and the redundant nanostructure layer 208C may have cross-sections of other geometries (e.g., circular, elliptical, triangular, or polygonal). In some embodiments, the active nanostructure layers 208A and 208B and the redundant nanostructure layer 208C may be similar to each other in structure and composition, but may differ from each other in function. Since the active nanostructure layer 208A is disposed between and in contact with the S / D regions 110A, the active nanostructure layer 208A may be electrically active and can be used as a channel region for the GAA FET 102A. Similarly, since the active nanostructure layer 208B is disposed between and in contact with the S / D regions 110B, the active nanostructure layer 208B may be electrically active and can be used as a channel region for the GAA FET 102B. On the other hand, since the redundant nanostructure layer 208C does not contact the S / D regions 110B, the redundant nanostructure layer 208C may be electrically inactive and not used as a channel region for the GAA FET 102B. Therefore, even though both GAA FETs 102A and 102B have the same number of nanostructure layers between adjacent S / D regions, GAA FET 102A can have a greater number of active nanostructure layers (also known as "nanostructure channel regions") than GAA FET 102B. Since the number of active nanostructure layers 208A between adjacent S / D regions 110A is greater than the number of active nanostructure layers 208B between adjacent S / D regions 110B, GAA FET 102A can have a higher drive current than GAA FET 102B. Although three active nanostructure layers 208A are displayed between adjacent S / D regions 110A and two active nanostructure layers 208B are displayed between adjacent S / D regions 110B, GAA FETs 102A and 102B may have any number of active nanostructure layers 208A and 208B, except that (i) the number of active nanostructure layers 208A between adjacent S / D regions 110A is greater than the number of active nanostructure layers 208B between adjacent S / D regions 110B, and (ii) the total number of active nanostructure layers 208A between adjacent S / D regions 110A is equal to the sum of active nanostructure layers 208B and redundant nanostructure layers 208C between adjacent S / D regions 110B. Referring to Figures 1, 2A, and 2B, in some embodiments, S / D regions 110A and 110B (also referred to as "active epitaxial layers 110A and 110B") may include epitaxially grown semiconductor material (e.g., Si) and N-type dopants (e.g., phosphorus, arsenic, and other suitable N-type dopants for N-type GAA FETs 102A and / or 102B). In some embodiments, the N-type dopants may have approximately 5 x 10⁻⁶ Ω·cm². 19 cm -3 Approximately 5x10 21 cm -3 The concentration of the S / D regions 110A and 110B may include epitaxially grown semiconductor materials (e.g., Si and SiGe) and P-type dopants (e.g., boron and other suitable P-type dopants for P-type GAA FETs 102A and / or 102B). In some embodiments, the P-type dopants may have a concentration of approximately 5 x 10⁻⁶. 19 cm -3 Approximately 5x10 21 cm -3 The concentration. Each of the S / D regions 110A and 110B can individually or collectively refer to the source or drain, depending on the context. Referring to Figures 2A and 2B, in some embodiments, each of gate structures 112A and 112B may have an outer gate portion 113A and an inner gate portion 113B. In some embodiments, the outer gate portion 113A may be individually disposed on and physically contacting the topmost active nanostructure layers 208A and 208B. In some embodiments, the inner gate portion 113B of gate structure 112A may be disposed between adjacent active nanostructure layers 208A and between adjacent inner gate spacers 216A. Similarly, in some embodiments, the inner gate portion 113B of gate structure 112B may be disposed between adjacent active nanostructure layers 208B and between adjacent inner gate spacers 216B. Each of the gate structures 112A and 11BN can be a multilayer structure and may include (i) an interfacial oxide (IL) layer (not shown), (ii) a high-k (HK) gate dielectric layer 228, and (iii) a conductive layer 230. In some embodiments, the IL layer may be directly disposed on the topmost active nanostructure layers 208A and 208B. In some embodiments, the IL layer may include SiO2. 2. SiGeO x or germanium oxide (GeO) x The gate dielectric layer 228 can have a thickness of about 1 nm to about 20 nm. In some embodiments, the HK gate dielectric layer 228 can be directly disposed on the IL layer and can include a high-k dielectric material, such as hafnium oxide (HfO). 2) Titanium oxide (TiO2) 2) Hafnium zirconium oxide (HfZrO) and tantalum oxide (Ta) 2O 3) Hafnium silicate (HfSiO) 4) Zirconia (ZrO) 2) and zirconium silicate (ZrSiO2) 2). In some embodiments, the sidewalls of the IL layer and the HK gate dielectric layer 228 may contact the sidewalls of the external gate spacers 114A and 114B. In some embodiments, the conductive layer 230 may be disposed on the HK gate dielectric layer 228 and may be a multilayer structure. For simplicity, the different layers of the conductive layer 230 are not shown. In some embodiments, the conductive layer 230 may include a work function metal (WFM) layer disposed on the HK gate dielectric layer 228 and a gate metal filling layer disposed on the WFM layer. In some embodiments, the WFM layer may include a Ti-based or Ta-based nitride or alloy that is substantially free of Al (e.g., without Al), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, and tantalum copper (Ta-Cu). In some embodiments, the WFM layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or other suitable Al-based materials. In some embodiments, the gate metal filling layer may include a suitable conductive material, such as tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof. Referring to Figures 2A and 2B, external gate spacers 114A and 114B electrically isolate the external gate portion 113A from the adjacent S / D regions 110A and 110B, and form adjacent FS contact structures 226A and 226B. In some embodiments, external gate spacers 114A and 114B may be individually disposed directly on the topmost active nanostructure layers 208A and 208B. In some embodiments, external gate spacers 114A and 114B may comprise a dielectric material, such as SiO2. 2. SiN, SiON, SiCN, SiOC, and SiOCN, and any other suitable dielectric material. Internal gate spacers 216A and 216B electrically isolate the internal gate portion 113B from the adjacent S / D regions 110A and 110B, and may include a dielectric material such as SiO2. 2. SiN, SiON, SiCN, SiOC and SiOCN, and any other suitable dielectric material. Referring to Figures 1, 2A, and 2B, in some embodiments, BS ESLs 118A and 118B may be individually disposed below and in contact with the BS surfaces of S / D regions 110A and 110B. The sidewalls of BS ESL 118A may contact the bottom inner gate spacer 216A and the base structure 106A. The sidewalls of BS ESL 118B may contact the sidewalls of the redundant nanostructure layer 208C and the bottom inner gate spacer 216B. In some embodiments, BS ESLs 118A and 118B may each comprise the same semiconductor material (e.g., Si or SiGe) as S / D regions 110A and 110B, and may be used as seed layers for epitaxial growth of S / D regions 110A and 110B. In some embodiments, BS ESL 118A and 118B may comprise dielectric materials, such as SiN, SiON, SiCN, SiOC, and SiOCN, rather than semiconductor materials, and may be used as barrier layers to prevent current leakage from the S / D region 110A. In some embodiments, BS ESL 118A and 118B may have thicknesses T1 and T2 of about 1 nm to about 10 nm to be used effectively as seed layers or barrier layers. In some embodiments, redundant epitaxial layers 120A and 120B may be electrically inactive and may comprise undoped SiGe or boron-doped SiGe. In some embodiments, the doped or undoped SiGe may have a Ge concentration of about 10 atomic% to about 50 atomic%. In some embodiments, redundant epitaxial layers 120A and 120B may be individually disposed below and in contact with the BS surfaces of BS ESLs 118A and 118B. Redundant epitaxial layers 120A and 120B can be used to control the height of S / D regions 110A and 110B. Controlling the height of S / D regions 110A and 110B can control the number of nanostructure layers contacting S / D regions 110A and 110B to form active nanostructure layers 208A and 208B. In the GAA FET 102B, a redundant epitaxial layer 120B, together with the BS ESL 118B, prevents the S / D region 110B from contacting the bottommost nanostructure layer, resulting in a redundant nanostructure layer 208C. In some embodiments, the redundant epitaxial layer 120A may have a height H1 smaller than the height H2 of the redundant epitaxial layer 120B, to form an S / D region 110A with a height greater than that of the S / D region 110B. As a result, there are more nanostructure layers contacting the S / D region 110A than contacting the S / D region 110B, thus forming a greater number of active nanostructure layers 208A than the active nanostructure layer 208B. In some embodiments, heights H1 and H2 may be from about 5 nm to about 70 nm. In some embodiments, for the N-type doped S / D regions 110A and / or 110B, the redundant epitaxial layer 120A and / or 120B may comprise undoped SiGe or doped SiGe. In some embodiments, FS ESLs 122A and 122B (visible in Figure 1; not visible in Figures 2A and 2B) can be directly disposed on the FS surfaces of S / D regions 110A and 110B. In some embodiments, FS ESLs 122A and 122B can have a dielectric constant of about 4 to about 7 and can comprise dielectric materials such as lanthanum oxide (LaO) and aluminum oxide (Al). 2O 3) Yttrium oxide (Y) 2O 3) Tantalum carbide (TaCN), zirconium silicate (ZrSi), SiOCN, SiOC, SiCN, zirconium nitride (ZrN), aluminum zirconium oxide (ZrAlO), TiO 2. Ta 2O 3. ZrO 2. HfO2, SiN, Hafnium silicate (HfSi), Aluminum oxynitride (AlON), SiO 2. SiC, SiN, and zinc oxide (ZnO). In some embodiments, ILD layers 124A and 124B (visible in Figure 1; not visible in Figures 2A and 2B) can be directly disposed on FS ESL 122A and 122B. In some embodiments, ILD layers 124A and 124B may include an insulating material, such as SiO2. 2. SiN, SiON, SiCN, SiOC and SiOCN. In some embodiments, each of the FS contact structures 226A and 226B may include (i) a silica layer 232, (ii) a contact plug 234 disposed on the silica layer 232, and (iii) a dielectric pad 236 surrounding the contact plug 234. In some embodiments, the silica layer 232 in the N-type GAA FETs 102A and 102B may include titanium silicate (Ti). x Si y ), Tantalum silicate (Ta x Si y ), beryllium silicate (Mo) x Si y Zirconium silicate (Zr) x Si y Hafnium silicate (Hf) x Si y Scandium silicide (Sc) x Si y ), Yttrium silicate (Y x Si y ), lithium silicate (Tb x Siy, Lutium silicate (Lu x Si y ), Erbium silicate (Er) x Si y ), Ytterbium silicate (Yb x Si y Europium silicate (Eu) x Si y ), Thorium silicate (Th) x Si y Other suitable metal silicate materials or combinations thereof. In some embodiments, the silicate layer 232 in the P-type GAA FETs 102A and 102B may include nickel silicate (Ni). x Si y ), cobalt silicate (Co) x Si y ), manganese silicate (Mn) x Si y ), Tungsten Silicate (W x Si y ), iron silicide (Fe) x Si y Rhodium silicate (Rh) x Si y ), Palladium silicide (Pd) x Si y Ruthenium silicate (Ru) x Si y Platinum silicate (Pt) x Si y ), Iridium silicate (Ir) x Si y Os(silicon) x Si yOther suitable metal silicate materials or combinations thereof. In some embodiments, the contact plug 234 may include a conductive material, such as Co, W, Ru, Al, Mo, Ir, Ni, osmium (Os), rhodium (Rh), other suitable conductive materials, and combinations thereof. In some embodiments, the dielectric pad 236 may include a dielectric material, such as SiN, SiON, SiCN, SiOC, and SiOCN. Referring to Figures 3A and 3B, in some embodiments, GAA FETs 102A and 102B may have BS contact structures 338A and 338B disposed on the BS surface of one or more of the S / D regions 110A and 110B, instead of BS ESLs 118A and 118B. BS contact structures 338A and 338B can electrically connect the S / D regions 110A and 110B to BS power rails (not shown) disposed on the BS contact structures 338A and 338B. The BS power rails may include metal wires (not shown) for supplying power to the S / D regions 110A and 110B through the BS contact structures 338A and 338B. By using BS power rails, the device area required for placing interconnects between the S / D regions 110A and 110B and the power supply can be reduced, thereby reducing power consumption compared to other GAA FETs without BS power rails. In some embodiments, each of the BS contact structures 338A and 338B may include (i) a silicate layer 340, (ii) a contact plug 342 disposed on the silicate layer 340, and (iii) a dielectric pad 344 surrounding the contact plug 342. In some embodiments, the silicate layer 340 may include Ti x Si y Ta x Si y Mo x Si y Zr x Si y Hf x Si y ,Sc x Si y Y x Si y 、(Tb x Siy, Lu x Si y Er x Si y Yb x Si y Chromium silicon (Cr) x Si y ), Ho2Si (Ho) x Si y ), Gd x Si y ), Dysprosium silicate (Dy x Si y Other suitable metal silicate materials or combinations thereof. In some embodiments, the silicate layer 340 may have a thickness of about 1 nm to about 10 nm to minimize the contact resistance between the S / D region 110A and the contact plug 342 of the BS contact structure 338A, and the contact resistance between the S / D region 110B and the contact plug 342 of the BS contact structure 338A. In some embodiments, the contact plug 342 may include a conductive material, such as Co, W, Ru, Mo, Ir, Cu, other suitable conductive materials, and combinations thereof. In some embodiments, the contact plug 342 of the BS contact structure 338A may have a height H3 of about 5 nm to about 70 nm, and the contact plug 342 of the BS contact structure 338B may have a height H4 of about 5 nm to about 70 nm. In some embodiments, the height H3 is less than the height H4. Since the BS contact structures 338A and 338B are individually formed by replacing redundant epitaxial layers 120A and 120B (described in detail below), the relative relationship between the heights H1 and H2 of the redundant epitaxial layers 120A and 120B applies to the relative relationship between the heights H3 and H4. In some embodiments, the contact plug 342 of the BS contact structure 338A may have a top surface width W1 of about 5 nm to about 50 nm and a bottom surface width W2 of about 5 nm to about 40 nm, which may be equal to or less than the width W1. Similarly, the contact plug 342 of the BS contact structure 338B may have a top surface width W3 of about 5 nm to about 50 nm and a bottom surface width W4 of about 5 nm to about 40 nm, which may be equal to or less than the width W3. In some embodiments, the dielectric pad 344 may include a dielectric material, such as SiN, SiON, SiCN, SiOC, and SiOCN, and may have a thickness of about 0.5 nm to about 5 nm. Referring to Figures 4A and 4B, in some embodiments, GAA FETs 102A and 102B may have BS contact structures 438A and 438B instead of the BS contact structures 338A and 338B of Figures 3A and 3B. Unless otherwise stated, the discussion of BS contact structures 338A and 338B applies to BS contact structures 438A and 438B. In some embodiments, each of BS contact structures 438A and 438B may include (i) a silicate layer 340, (ii) a barrier layer 446 disposed on the silicate layer 340, (iii) contact plugs 342 disposed on the inner sidewalls and bottom surface of the barrier layer, and (iv) a dielectric pad 344 disposed on the outer sidewall of the barrier layer 446. In some embodiments, the barrier layer 446 may prevent oxidation of the metal of the contact plug 342 and may include Ti, TiN, TaN, W, or Ru. In some embodiments, the barrier layer 446 may have a thickness of about 0.1 nm to about 2 nm to adequately prevent oxidation of the metal of the contact plug 342. Referring to Figure 5A, in some embodiments, the GAA FET 102A may have a BS contact structure 338A and a BS isolation layer 548A disposed on the BS surface of the S / D region 110A, instead of the BS ESL 118A and redundant epitaxial layer 120A of Figure 2A. Similarly, referring to Figure 5B, the GAA FET 102B may have a BS contact structure 338B and a BS isolation layer 548B disposed on the BS surface of the S / D region 110B, instead of the BS ESL 118B and redundant epitaxial layer 120B of Figure 2B. In some embodiments, the BS isolation layers 548A and 548B may electrically isolate the S / D regions 110A and 110B from the base structures 106A and 106B and / or from other BS structures (e.g., BS power rails; not shown) disposed on the BS surface of the base structure. Furthermore, the BS isolation layer 548B and dielectric pad 344 of the BS contact structure 338B can prevent the S / D region 110B from contacting the redundant nanostructure layer 208C. In some embodiments, BS isolation layers 548A and 548B may include dielectric materials such as LaO and Al. 2O 3. Y 2O 3. TaCN, SiOCN, SiOC, SiCN, TiO 2. Ta 2O 3. ZrO 2. ZrAlO, HfO 2. AlON, SiO 2. SiN and ZnO. In some embodiments, BS isolation layers 548A and 548B may have heights H5 and H6 of about 5 nm to about 70 nm. In some embodiments, height H5 is less than height H6. Since BS isolation layers 548A and 548B are individually formed by replacing redundant epitaxial layers 120A and 120B (described in detail below), the relative relationship between the heights H1 and H2 of redundant epitaxial layers 120A and 120B applies to the relative relationship between heights H5 and H6. In some embodiments, BS isolation layers 548A and 548B may have top surface widths W5 and W7 of about 5 nm to about 50 nm and bottom surface widths W6 and W8 of about 5 nm to about 50 nm, which may be equal to or less than widths W5 and W7. Referring to Figure 6A, in some embodiments, the GAA FET 102A may have a BS contact structure 438A and a BS isolation layer 548A disposed on the BS surface of the S / D region 110A, instead of the BS ESL 118A and redundant epitaxial layer 120A as shown in Figure 2A. Similarly, referring to Figure 6B, the GAA FET 102B may have a BS contact structure 438B and a BS isolation layer 548B disposed on the BS surface of the S / D region 110B, instead of the BS ESL 118B and redundant epitaxial layer 120B as shown in Figure 2B. Figure 7 is a flowchart of an exemplary method 700 for manufacturing a semiconductor device 100 having cross-sectional views as shown in Figures 2A to 6A and Figures 2B to 6B, according to some embodiments. For illustrative purposes, the operations shown in Figure 7 will be described with reference to an exemplary manufacturing process for manufacturing the semiconductor device 100 as shown in Figures 8A to 28A and Figures 8B to 28B. Figures 8A to 28A are cross-sectional views of the semiconductor device 100 at various sites in the process of the semiconductor device 100 along line segment AA of Figure 1, according to some embodiments, and Figures 8B to 28B are cross-sectional views of the semiconductor device 100 at various sites in the process of the semiconductor device 100 along line segment BB of Figure 1, according to some embodiments. Depending on the specific application, the operations may be performed in a different order or not at all. It is worth noting that method 700 may not produce a completed semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 700, and some other processes may need to be described here. Unless otherwise stated, the discussion of elements with the same annotations in Figures 1, 2A to 6A, 2B to 6B, 8A to 28A, and 8B to 28B applies to each other. Referring to Figure 7, in operation 705, a first superlattice structure and a second superlattice structure having a nanostructure layer and a nanostructure sacrificial layer are formed on a base structure. For example, as described with reference to Figures 8A and 8B, superlattice structures 807A and 807B (also referred to as "nanosheet stacks 807A and 807B") are individually formed on base structures 106A and 106B, which are formed on substrate 104. Each of the superlattice structures 807A and 807B may include a nanostructure layer 208 and a nanostructure sacrificial layer 808 configured in an alternating configuration. In some embodiments, the nanostructure layer 208 may include Si, and the nanostructure sacrificial layer 808 may include SiGe. Referring to Figure 7, in operation 710, polycrystalline silicon structures are formed on the first superlattice structure and the second superlattice structure. For example, as described with reference to Figures 8A and 8B, polycrystalline silicon structures 812A and 812B are individually formed on superlattice structures 807A and 807B. In some embodiments, SiO may be formed on superlattice structures 807A and 807B prior to the formation of polycrystalline silicon structures 812A and 812B. Two layers of 850. During subsequent processes, polycrystalline silicon structures 812A and 812B, SiO2... The two-layer 850 and the nanostructure sacrificial layer 808 can be replaced with gate structures 112A and 112B in the gate replacement process. In some embodiments, external gate spacers 114A and 114B can be formed after forming the polycrystalline silicon structures 812A and 812B, as shown in Figures 8A and 8B. Referring to Figure 7, in operation 715, a first S / D opening and a second S / D opening are formed in a first superlattice structure and a second superlattice structure. For example, as described with reference to Figures 9A and 9B, a first S / D opening 910A is formed in superlattice structure 807A, and a second S / D opening 910B is formed in superlattice structure 807B. S / D openings 910A and 910B can be formed by etching portions of superlattice structures 807A and 807B that are not covered by polycrystalline silicon structures 812A and 812B. In some embodiments, etching of superlattice structures 807A and 807B may include using a mixed gas (e.g., hydrogen (H2O)). 2) Oxygen (O 2) Nitrogen (N 2) Etching gases such as argon (Ar) and carbon tetrafluoride (CF2) 4) Sulfur dioxide (SO₂) 2) Hexafluoroethane (C 2F 6) Chlorine (Cl) 2) Nitrogen trifluoride (NF) 3) Sulfur hexafluoride (SF6) 6) and a plasma-based dry etching process using hydrogen bromide (HBr). Etching can be performed at a temperature of approximately 25°C to approximately 200°C and a pressure of approximately 5 mTorr to approximately 50 mTorr. The flow rate of the etching gas can range from approximately 5 standard cubic centimeters per minute (sccm) to approximately 100 sccm. The electrical power ranges from approximately 50 W to approximately 200 W, with a bias voltage ranging from approximately 30 V to approximately 200 V. In some embodiments, internal gate spacers 216A and 216B can be formed after the formation of S / D openings 910A and 910B, as shown in Figures 9A and 9B. Referring to Figure 7, in operation 720, a first redundant epitaxial layer, a first BS ESL, and a first S / D region are formed in the first S / D opening. For example, as described with reference to Figures 10A to 13A and 10B to 13B, a redundant epitaxial layer 120A, a BS ESL 118A, and an S / D region 110A are formed in the S / D opening 910A. The redundant epitaxial layer 120A, the BS ESL... The formation of 118A and S / D region 110A may include the following sequential operations: (i) depositing a hard mask layer 1052 (e.g., a SiN layer) on the structures of Figures 9A and 9B to form the structures of Figures 10A and 10B; (ii) removing (e.g., by etching) portions of the hard mask layer 1052 on the structure of Figure 10A, without removing portions of the hard mask layer 1052 on the structure of Figure 10B, to form the structures of Figures 11A and 11B; (iii) epitaxially growing a semiconductor material (e.g., doped or undoped SiGe) of redundant epitaxial layer 120A to a height H1 in S / D opening 910A, as shown in Figure 12A, without growing the semiconductor material of redundant epitaxial layer 120A in S / D opening 910B, as shown in Figure 12B; and (iv) epitaxially growing or depositing a BS ESL with a thickness Tl on redundant epitaxial layer 120A. 118A, as shown in Figure 12A, but without growing BS ESL 118A in S / D opening 910B, as shown in Figure 12B; (v) epitaxially growing semiconductor material (e.g., doped Si or doped SiGe) of S / D region 110A on BS ESL 118A, as shown in Figure 12A, but without growing semiconductor material of S / D region 110A in S / D opening 910B, as shown in Figure 12B; and (vi) removing hard mask layer 1052 from the structure of Figure 12B without etching S / D region 110A to form the structures of Figures 13A and 13B. The dielectric material of hard mask layer 1052 on the structure of Figure 12B prevents redundant epitaxial layer 120A, BS ESL 118A, and S / D region 110A from growing in S / D opening 910B, as shown in Figure 12B. In some embodiments, if the BS ESL 118A is formed of a semiconductor material, the BS ESL 118A is epitaxially grown or deposited on the redundant epitaxial layer 120A. In some embodiments, if the BS ESL 118A is formed of a dielectric material, the BS ESL 118A is deposited on the redundant epitaxial layer 120A. Referring to Figure 7, in operation 725, a second redundant epitaxial layer, a second BS ESL, and a second S / D region are formed in the second S / D opening. For example, as described with reference to Figures 14A to 16A and 14B to 16B, a redundant epitaxial layer 120B, a BS ESL 118B, and an S / D region 110B are formed in the S / D opening 910B. The redundant epitaxial layer 120B, the BS ESL... The formation of 118B and S / D region 110B may include the following sequential operations: (i) depositing a hard mask layer 1452 (e.g., a SiN layer) on the structures of Figures 13A and 13B to form the structures of Figures 14A and 14B; (ii) removing (e.g., by etching) portions of the hard mask layer 1452 on the structure of Figure 14A, without removing portions of the hard mask layer 1452 on the structure of Figure 14B, to form the structures of Figures 15A and 15B; (iii) epitaxially growing a semiconductor material (e.g., doped or undoped SiGe) of redundant epitaxial layer 120B to a height H2 in S / D opening 910B, as shown in Figure 16B, without growing the semiconductor material of redundant epitaxial layer 120B in S / D opening 910A, as shown in Figure 16A; and (iv) epitaxially growing or depositing a BS ESL having a thickness T2 on redundant epitaxial layer 120B. 118B, as shown in Figure 16B, but without growing the BS ESL 118B in the S / D opening 910A, as shown in Figure 16A; (v) epitaxially growing the semiconductor material (e.g., doped Si or doped SiGe) of the S / D region 110B on the BS ESL 118B, as shown in Figure 16B, but without growing the semiconductor material of the S / D region 110B in the S / D opening 910A, as shown in Figure 16A; and (vi) removing the hard mask layer 1452 from the structure of Figure 16A without etching the S / D region 110B. In some embodiments, if the BS ESL 118B is formed of a semiconductor material, the BS ESL 118B is epitaxially grown or deposited on the redundant epitaxial layer 120B. In some embodiments, if the BS ESL 118B is formed of a dielectric material, the BS ESL 118B is deposited on the redundant epitaxial layer 120B. The redundant epitaxial layer 120B, grown to height H2, and the BS ESL 118B, having a thickness T2, prevent the S / D region 110B from forming as the bottommost nanostructure layer 208 adjacent to and in contact with the bottommost nanostructure layer 208 of the superlattice structure 807B. As a result, the bottommost nanostructure layer 208 of the superlattice structure 807B forms a redundant nanostructure layer 208C, and the nanostructure layer 208 of the superlattice structure 807B, adjacent to and in contact with the S / D region 110B, forms an active nanostructure layer 208B, as shown in Figure 16B. The dielectric material of the hard mask layer 1452 on the structure in Figure 16A prevents the redundant epitaxial layer 120B, BS ESL 118B, and S / D region 110B from growing on the S / D region 110A. After the formation of S / D region 110B, FS ESL 122A and 122B and ILD layers 124A and 124B can be formed, as shown in Figures 17A and 17B. Referring to Figure 7, in operation 730, the polycrystalline silicon structure and the nanostructure sacrificial layer are replaced with gate structures. For example, as described with reference to Figures 18A and 18B, the polycrystalline silicon structures 812A and 812B and the nanostructure sacrificial layer 808 are replaced by gate structures 112A and 112B. The formation of gate structures 112A and 112B may include (i) removing the polycrystalline silicon structures 812A and 812B and the SiO2 from the structures in Figures 17A and 17B. (ii) A two-layer structure 850 and a nanostructure sacrificial layer 808 are used to form a gate opening (not shown), and gate structures 112A and 112B are formed in the gate opening, as shown in Figures 18A and 18B. In some embodiments, after the formation of gate structures 112A and 112B, an FS contact structure 226A may be formed on the S / D region 110A and an FS contact structure 226B may be formed on the S / D region 110B, as shown in Figures 18A and 18B. Referring to Figure 7, in operation 735, a BS contact structure is formed on one of the first S / D regions and one of the second S / D regions. For example, as described with reference to Figures 19A to 25A and 19B to 25B, a BS contact structure 338A is formed on the BS surface of one of the S / D regions 110A, and a BS contact structure 338B is formed on the BS surface of one of the S / D regions 110A. The formation of BS contact structures 338A and 338B may include the following sequential operations: (i) removing substrate 104 to expose the back surfaces of base structures 106A and 106B and redundant epitaxial layers 120A and 120B, as shown in Figures 19A and 19B; and (ii) depositing a hard mask layer 2054 (e.g., a SiN layer) on the back surfaces of base structures 106A and 106B and redundant epitaxial layers 120A and 120B. As shown in Figures 20A and 20B, (iii) openings 2138A and 2138B are formed in the hard mask layer 2054 using a photolithography patterning process and an etching process, as shown in Figures 21A and 21B; (iv) redundant epitaxial layers 120A and 120B are individually etched through openings 2138A and 2138B, as shown in Figures 22A and 22B; and (v) BS ESL is individually etched through openings 2138A and 2138B. 118A and 118B are used to form contact openings 2238A and 2238B, as shown in Figures 22A and 22B. (vi) A dielectric layer 2344 with a dielectric pad 344 is deposited on the hard mask layer 2054 and in the openings 2238A and 2238B, as shown in Figures 23A and 23B. (vii) The horizontal portion of the dielectric layer 2344 is removed (e.g., by etching) without removing the vertical portion of the dielectric layer 2344. (viii) Forming a dielectric layer 2344*, as shown in Figures 24A and 24B; (ix) Depositing a conductive layer 2442 of material having contact plugs 342 to fill openings 2238A and 2238B, as shown in Figures 24A and 24B; and (x) Performing a chemical mechanical polishing (CMP) process on the structures in Figures 24A and 24B to make the back surfaces of the base structures 106A and 106B, contact plugs 342, dielectric pads 344, and redundant epitaxial layers 120A and 120B coplanar, as shown in Figures 25A and 25B. By using redundant epitaxial layers 120A and 120B, self-aligned BS contact structures 338A and 338B of different heights can be formed simultaneously in GAA FETs 102A and 102B, as shown in Figures 25A and 25B. In some embodiments, the barrier layer 446 can be formed after the formation of the silicon layer 340 and before the deposition of the conductive layer 2442. Referring to Figure 7, in operation 740, a BS isolation layer is formed on the other of the first S / D region and the other of the second S / D region. For example, as described with reference to Figures 26A to 28A and 26B to 28B, a BS isolation layer 548A is formed on the BS surface of the other S / D region 110A, and a BS isolation layer 548B is formed on the BS surface of the other S / D region 110A. The formation of BS isolation layers 548A and 548B may include the following sequential operations: (i) etching redundant epitaxial layers 120A and 120B and BS ESL 118A and 118B from the structures in Figures 25A and 25B to form isolation openings 2648A and 2648B, as shown in Figures 26A and 26B; (ii) depositing a dielectric layer 2748 of material having BS isolation layers 548A and 548B to fill openings 2648A and 2648B, as shown in Figures 27A and 27B; and (iii) performing a CMP process on dielectric layer 2748 to make the back surfaces of base structures 106A and 106B, contact plug 342, dielectric pad 344, and BS isolation layers 548A and 548B coplanar, as shown in Figures 28A and 28B. By using redundant epitaxial layers 120A and 120B, self-aligned BS isolation layers 548A and 548B of different heights can be formed simultaneously in GAA FETs 102A and 102B, as shown in Figures 28A and 28B. This disclosure provides exemplary structures of GAA FETs (e.g., GAA FETs 102A and 102B) with different drive current characteristics on the same substrate (e.g., substrate 104) of a semiconductor device (e.g., semiconductor device 100), and also provides exemplary methods (e.g., method 700) for manufacturing these GAA FETs. In some embodiments, a first GAA FET (e.g., GAA FET 102A) may have a first nanostructure layer (e.g., nanostructured layer 208A) between a first pair of S / D regions (e.g., S / D region 110A), and a second GAA FET (e.g., GAA FET 102B) may have a second nanostructure layer (e.g., nanostructured layer 208B) between a second pair of S / D regions (e.g., S / D region 110B). The number of first nanostructure layers may be greater than the number of second nanostructure layers to achieve a higher drive current in the first GAA FET than in the second GAA FET. Semiconductor devices can utilize GAA FETs with different drive current values ​​to optimize overall power consumption. In some embodiments, the number of first and second nanostructure layers in contact with the first and second pairs of S / D regions can be controlled by using first and second electrically inactive (“redundant”) epitaxial layers (e.g., redundant epitaxial layers 120A and 120B) disposed beneath the first and second pairs of S / D regions. In some embodiments, the first and second redundant epitaxial layers can also be used to form self-aligned back-side contact structures (e.g., BS contact structures 338A and 338B) on the back-side surfaces of the first and second pairs of S / D regions. In some embodiments, the first and second redundant epitaxial layers can be replaced with back-side isolation layers (e.g., BS isolation layers 548A and 548B) to reduce current leakage from the first and second pairs of S / D regions to the substrate. In some embodiments, the semiconductor device includes a first base structure and a second base structure, a first redundant epitaxial layer and a second redundant epitaxial layer individually disposed in the first base structure and the second base structure, a first active epitaxial layer and a second active epitaxial layer individually disposed on the first redundant epitaxial layer and the second redundant epitaxial layer, a first active nanostructure layer disposed adjacent to and in contact with the first active epitaxial layer, a second active nanostructure layer disposed adjacent to and in contact with the second active epitaxial layer, a redundant nanostructure layer disposed adjacent to and on the second redundant layer, a first gate structure surrounding the first active nanostructure layer, and a second gate structure surrounding the second active nanostructure layer and the redundant nanostructure layer. The height of the second redundant layer is greater than the height of the first redundant layer. The height of the first active epitaxial layer is greater than the height of the second active epitaxial layer. In some embodiments, the semiconductor device further includes a semiconductor layer disposed between the first active epitaxial layer and the first redundant layer. In some embodiments, the semiconductor device further includes a dielectric layer disposed between the first active epitaxial layer and the first redundant layer. In some embodiments, the semiconductor device further includes a semiconductor layer disposed between the second active epitaxial layer and the second redundant layer, and in contact with the redundant nanostructure layer. In some embodiments, the semiconductor device further includes a dielectric layer disposed between the second active epitaxial layer and the second redundant layer, and in contact with the redundant nanostructure layer. In some embodiments, the semiconductor device further includes a first conductive structure disposed in a first base structure and a second conductive structure disposed in a second base structure. The height of the second conductive structure is greater than the height of the first conductive structure. In some embodiments, the semiconductor device further includes a conductive structure disposed in a second base structure, wherein a redundant nanostructure layer is disposed between the conductive structure and the second redundant layer. In some embodiments, the semiconductor device further includes a third active epitaxial layer and a fourth active epitaxial layer. A first active nanostructure layer is disposed between the first active epitaxial layer and the third active epitaxial layer, and contacts the first active epitaxial layer and the third active epitaxial layer. A second active nanostructure layer is disposed between the second active epitaxial layer and the fourth active epitaxial layer, and contacts the second active epitaxial layer and the fourth active epitaxial layer. In some embodiments, the material of the first redundant layer is different from the material of the first active epitaxial layer. In some embodiments, the second active nanostructure layer and the redundant nanostructure layer comprise the same semiconductor material. In some embodiments, the semiconductor device includes a base structure, a redundant nanostructure layer disposed on the base structure, an active nanostructure layer disposed on the redundant nanostructure layer, a first source / drain region disposed adjacent to a first end of the active nanostructure layer, a second source / drain region disposed adjacent to a second end of the active nanostructure layer, an isolation layer disposed on the back side of the first source / drain region, a first contact structure disposed on the front side of the first source / drain region, a second contact structure disposed on the back side of the second source / drain region, and a gate structure surrounding the active nanostructure layer and the redundant nanostructure layer. In some embodiments, the isolation layer includes a dielectric layer. In some embodiments, a redundant nanostructure layer is disposed between the isolation layer and the second contact structure, and contacts the isolation layer and the second contact structure. In some embodiments, the active nanostructure layer contacts the first source / drain region and the second source / drain region. In some embodiments, the semiconductor device further includes an internal gate spacer that contacts the isolation layer. In some embodiments, the semiconductor device further includes an internal gate spacer that contacts the second contact structure. In some embodiments, a method of manufacturing a semiconductor device includes forming a superlattice structure on a substrate, the superlattice structure including a first nanostructure layer, a sacrificial nanostructure layer on the first nanostructure layer, and a second nanostructure layer on the sacrificial nanostructure layer; forming a polycrystalline silicon layer on the superlattice structure; forming a first opening and a second opening in the superlattice structure; epitaxially growing a first semiconductor layer and a second semiconductor layer in the first opening and the second opening; epitaxially growing a third semiconductor layer and a fourth semiconductor layer on the first semiconductor layer and the second semiconductor layer; replacing the polycrystalline silicon layer and the sacrificial nanostructure layer with a gate structure; and replacing the first semiconductor layer with a contact structure on the back side of the third semiconductor layer. The first semiconductor layer and the second semiconductor layer contact a plurality of sidewalls of the first nanostructure layer. The third semiconductor layer and the fourth semiconductor layer contact the second nanostructure layer and the sacrificial nanostructure layer. In some embodiments, the method of forming a semiconductor device further includes replacing the second semiconductor layer with a dielectric layer on the back side of the fourth semiconductor layer. In some embodiments, the method of forming a semiconductor device further includes removing a substrate before replacing the first semiconductor layer. In some embodiments, the method of forming a semiconductor device further includes depositing a first dielectric layer and a second dielectric layer separately on the first semiconductor layer and the second semiconductor layer before epitaxially growing the third semiconductor layer and the fourth semiconductor layer. The foregoing outlines features of numerous embodiments, enabling those skilled in the art to better understand this disclosure from various perspectives. Those skilled in the art will understand that other processes and structures can be easily designed or modified based on this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive spirit and scope of this disclosure. Various changes, substitutions, or modifications can be made to this disclosure without departing from its inventive spirit and scope. 100: Semiconductor device; 102A, 102B: All-around gate field-effect transistor; 104: Substrate; 105: Shallow trench isolation region; 106A: Basic structure, wafer base, fin base; 106B: Basic structure, wafer base, fin base; 110A: Source / drain region; 110B: Source / drain region; 112A: Gate structure; 112B: Gate structure; 114A: External gate spacer; 114B: External gate spacer; 118A: Backside etch stop layer, capping layer, seed layer; 11 8B: Backside etch stop layer, capping layer, seed layer; 120A: Redundant epitaxial layer; 120B: Redundant epitaxial layer; 122A: Frontside etch stop layer; 122B: Frontside etch stop layer; 124A: Interlayer dielectric layer; 124B: Interlayer dielectric layer; AA: Line segment; BB: Line segment; 113A: External gate portion; 113B: Internal gate portion; 208A: Active nanostructure layer; 208B: Active nanostructure layer; 208C: Redundant nanostructure layer; 216A: Internal gate spacer; 216B: Internal... Gate spacer 226A: Front contact structure 226B: Front contact structure 228: High-k gate dielectric layer 230: Conductive layer 232: Silicone layer 234: Contact plug 236: Dielectric pad T1: Thickness T2: Thickness H1: Height H2: Height 338A: Back contact structure 338B: Back contact structure 340: Silicone layer 342: Contact plug 344: Dielectric pad H3: Height H4: Height W1: Top surface width W2: Bottom surface width W3: Top surface width Width W4: Bottom surface width 438A: Back surface contact structure 438B: Back surface contact structure 446: Barrier layer 548A: Back surface isolation layer 548B: Back surface isolation layer H5: Height H6: Height W5: Top surface width W6: Bottom surface width W7: Top surface width W8: Bottom surface width 208: Nanostructure layer 807A: Superlattice structure 807B: Superlattice structure 808: Nanostructure sacrificial layer 812A: Polycrystalline silicon structure 812B: Polycrystalline silicon structure 850: SiO 2 layers 910A: First source / drain opening, source / drain opening 910B: Second source / drain opening, source / drain opening 1052: Hard mask layer 1452: Hard mask layer 2054: Hard mask layer 2138A, 2138B: Opening 2238A, 2238B: Contact opening, opening 2344: Dielectric layer 2344*: Dielectric layer 2442: Conductive layer 2648A, 2648B: Isolation opening, opening 2748: Dielectric layer This disclosure of embodiments can be understood in more detail by reading the following detailed description and examples in conjunction with the corresponding drawings. Figure 1 shows a schematic diagram of a semiconductor device according to some embodiments. Figures 2A, 3A, 4A, 5A, 6A and 2B, 3B, 4B, 5B, and 6B show different cross-sectional views of semiconductor devices with transistors having different drive current characteristics according to some embodiments. Figure 7 is a flowchart of a method for manufacturing a semiconductor device with transistors having different drive current characteristics according to some embodiments. Figures 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28A and Figures 8B, 9B, 10B, 11B Figures 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B, 23B, 24B, 25B, 26B, 27B, and 28B show cross-sectional views of semiconductor devices with transistors having different drive current characteristics at various stations in their fabrication process, according to some embodiments. Illustrative embodiments will now be described with reference to the figures. In the figures, similar reference numerals generally denote the same, functionally similar, and / or structurally similar elements. The discussion of elements with the same annotations applies to each other unless otherwise stated. 104:Substrate 106B: Basic structure, plate foundation, fin foundation 110B: Source / Drain Region 112B: Gate structure 114B: External gate spacer 118B: Backside etching stop layer, cover layer, seed layer 120B: Redundant epitaxial layer 113A: External gate section 113B: Internal gate section 208B: Active Nanostructure Layer 208C: Redundant Nanostructure Layer 216B: Internal gate spacer 226B: Front contact structure 228: High-k gate dielectric layer 230: Conductive layer 232: Silicone layer 234: Contact plug 236: Dielectric Pad T2: Thickness H2: Height

Claims

1. A semiconductor device, comprising: A first base structure and a second base structure; a first redundancy layer and a second redundancy layer, individually disposed in the first base structure and the second base structure, wherein a height of the second redundancy layer is greater than a height of the first redundancy layer; a first active epitaxial layer and a second active epitaxial layer, individually disposed on the first redundancy layer and the second redundancy layer, wherein a height of the first active epitaxial layer is greater than a height of the second active epitaxial layer; a first active nanostructure layer disposed adjacent to and in contact with the first active epitaxial layer; a second active nanostructure layer disposed adjacent to and in contact with the second active epitaxial layer; a redundancy nanostructure layer disposed adjacent to the second redundancy layer, wherein the second redundancy layer includes a dielectric layer and is in contact with the redundancy nanostructure layer; a first gate structure surrounding the first active nanostructure layer; and a second gate structure surrounding the second active nanostructure layer and the redundancy nanostructure layer.

2. The semiconductor device as claimed in claim 1 further includes a dielectric layer disposed between the first active epitaxial layer and the first redundant layer.

3. The semiconductor device as claimed in claim 1 further includes a semiconductor layer disposed between the second active epitaxial layer and the second redundant layer, and in contact with the redundant nanostructure layer.

4. The semiconductor device as claimed in claim 1 further includes a dielectric layer disposed between the second active epitaxial layer and the second redundant layer, and in contact with the redundant nanostructure layer.

5. The semiconductor device as described in claim 1, further comprising: A first conductive structure is disposed in the aforementioned first basic structure; And a second conductive structure is disposed in the second basic structure, wherein the height of the second conductive structure is greater than the height of the first conductive structure.

6. The semiconductor device as claimed in claim 1 further includes a conductive structure disposed in the second basic structure, wherein the redundant nanostructure layer is disposed between the conductive structure and the second redundant layer.

7. A semiconductor device, comprising: A basic structure; A redundant nanostructure layer is disposed on the aforementioned base structure layer; an active nanostructure layer is disposed on the aforementioned redundant nanostructure layer; a first source / drain region is disposed adjacent to a first end of the aforementioned active nanostructure layer; a second source / drain region is disposed adjacent to a second end of the aforementioned active nanostructure layer; an isolation layer is disposed on a back side of the aforementioned first source / drain region, wherein the isolation layer includes a dielectric layer and is contacted with the aforementioned redundant nanostructure layer; a first contact structure is disposed on a front side of the aforementioned first source / drain region; a second contact structure is disposed on a back side of the aforementioned second source / drain region; and a gate structure surrounds the aforementioned active nanostructure layer and the aforementioned redundant nanostructure layer.

8. The semiconductor device as claimed in claim 7, wherein the redundant nanostructure layer is disposed between the isolation layer and the second contact structure, and contacts the isolation layer and the second contact structure.

9. The semiconductor device as claimed in claim 7 further includes an internal gate spacer that contacts the aforementioned isolation layer.

10. A method for manufacturing a semiconductor device, comprising: A superlattice structure is formed on a substrate, the superlattice structure including a first nanostructure layer, a nanostructure sacrificial layer on the first nanostructure layer, and a second nanostructure layer on the sacrificial layer; a polycrystalline silicon layer is formed on the superlattice structure; a first opening and a second opening are formed in the superlattice structure; a first semiconductor layer and a second semiconductor layer are epitaxially grown in the first opening and the second opening, wherein the first semiconductor layer and the second semiconductor layer contact the plurality of sidewalls of the first nanostructure layer; a third semiconductor layer and a fourth semiconductor layer are epitaxially grown in the first semiconductor layer and the second semiconductor layer, wherein the third semiconductor layer and the fourth semiconductor layer contact the second nanostructure layer and the sacrificial layer; a gate structure replaces the polycrystalline silicon layer and the sacrificial layer. The first semiconductor layer is replaced by a contact structure on a back side of the third semiconductor layer; and the second semiconductor layer is replaced by a dielectric layer, wherein the dielectric layer is adjacent to the first nanostructure layer.

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