Semiconductor device and an attribute matching method thereof

Abstract

A semiconductor device and a method for matching the properties of the same are disclosed. The semiconductor device includes a frequency-variable element, a matching control unit, and a matching adjustment circuit. The matching control unit is connected to the frequency-variable element and is used to detect the noise voltage of the frequency-variable element. The matching adjustment circuit is connected to the frequency-variable element and the matching control unit. The matching control unit dynamically adjusts the properties of the matching adjustment circuit based on the noise voltage of the frequency-variable element, thereby correspondingly changing the properties of the semiconductor device.

Description

[Technical Field]

[0001] This application relates to a semiconductor device, and more particularly to a semiconductor device packaged using an advanced packaging process and a method for matching its attributes. [Previous Technology]

[0002] Current chip devices are typically packaged using the conventional IC (Integrated Circuit) standard packaging process. This involves processes such as die bonding, wire bonding, and molding to package the bare die into the existing chip device. The chip device is mounted on a circuit board to operate in conjunction with other electronic devices through the circuit board's wiring. Generally, to ensure the stability of the overall circuit, chip devices and circuit boards with matched zeros and poles are selected. However, due to the influence of the manufacturing process and / or the operating state of the chip device, the zeros and poles of the chip device and the circuit board cannot be perfectly matched. Furthermore, the zeros and poles of the chip device may shift with different operating states, resulting in excessive zero-pole differences between the chip device and the circuit board, leading to poor stability of the overall circuit.

[0003] In recent years, in order to improve the performance of chip devices without increasing their size, advanced packaging processes that integrate bare dies of different processes and properties have been proposed. Among them, the CoWoS (Chip-on-Wafer-on-Substrate) process is one of the most popular advanced packaging processes. The CoWoS process is a packaging process that stacks bare dies and then packages them on a substrate. Multiple bare dies are arranged or stacked on the substrate, and electrical connections can be established between the multiple bare dies through an interposer or silicon through-holes in the bare dies. In this way, the size of the chip device can be significantly reduced, and it has the advantages of reducing power consumption and cost.

[0004] Therefore, how to optimize the zero-pole matching between the bare die and its substrate based on the CoWoS process is one of the problems that urgently need to be solved in this field. [Summary of the Invention]

[0005] In order to solve the above-mentioned technical problems, this application proposes a semiconductor device and a method for matching its properties. By adjusting the properties of the semiconductor device in real time, the semiconductor device can dynamically match the zeros and poles of the frequency-variable element according to the operating state of the frequency-variable element, thereby achieving the effect of making the semiconductor device have better circuit stability.

[0006] To achieve the above objectives, this application provides a semiconductor device including a frequency-variable element, a matching control unit, and a matching adjustment circuit. The matching control unit is connected to the frequency-variable element and is used to detect a noise voltage of the frequency-variable element. The matching adjustment circuit is connected to both the frequency-variable element and the matching control unit. The matching control unit dynamically adjusts the matching adjustment circuit based on the noise voltage of the frequency-variable element to change the properties of the semiconductor device.

[0007] In order to achieve the above objectives, this application proposes a method for matching the properties of a semiconductor device, applicable to the semiconductor device described above, the steps of which include: obtaining the noise voltage; and dynamically adjusting the matching adjustment circuit based on the noise voltage.

[0008] Based on the above, the semiconductor device and its attribute matching method of this application can monitor the noise voltage of the frequency variable element in real time by means of the matching control unit, and decide whether to adjust the matching adjustment circuit based on the noise voltage to change the attribute of the semiconductor device, so that the zero and pole of the semiconductor device can be dynamically matched with the zero and pole of the frequency variable element according to the operating state of the frequency variable element, thereby achieving the effect of making the semiconductor device have better circuit stability.

Implementation Method

[0016] Please refer to Figure 1, which is a schematic diagram of an embodiment of the semiconductor device of this application. The semiconductor device 100 has an electronic component layer 110 and a carrier layer 120. The electronic component layer 110 includes a plurality of electronic components and is disposed on the carrier layer 120. The carrier layer 120 is electrically connected to the electronic component layer 110. In this embodiment, the semiconductor device 100 is a semiconductor device packaged using a CoWoS (Chip-on-Wafer-Substrate Stacking) process, meaning that the electronic component layer 110 and the carrier layer 120 can be implemented through a semiconductor process and stacked before being packaged. In one embodiment, the electronic components are, for example, die components that implement a system on a chip (SoC) or a high-bandwidth memory (HBM), and this application is not limited thereto. In one embodiment, the carrier layer 120 includes a silicon interposer layer, a bridge die layer, a local silicon interconnect (LSI) layer, a redistribution layer (RDL), a semiconductor layer, a packaging layer, a board-connect layer, and / or a bonding layer. The carrier layer 120 can be electrically connected to the electronic component layer 110 directly or indirectly. For example, in an embodiment where the carrier layer 120 is a redistribution layer, a silicon interposer layer, a bridge die layer, and / or a local silicon interconnect layer may be provided between the carrier layer 120 and the electronic component layer 110. The carrier layer 120 can be electrically connected to the electronic component layer 110 through the silicon interposer layer, the bridge die layer, and / or the local silicon interconnect layer, and this application is not limited thereto.

[0017] Figure 2 is a schematic diagram of the circuit architecture of the semiconductor device 100 of this application. Figure 3 is a schematic diagram of the configuration of the frequency variable element. The semiconductor device 100 includes a frequency variable element 111, a matching control unit 130, and a matching adjustment circuit 121.

[0018] The frequency-variable element 111 is disposed on the electronic component layer 110, and its frequency changes with different operating states. For example, the frequency-variable element 111 can operate in different operating states, such as overclocking, high frequency, or low frequency, and this application is not limited thereto. In one embodiment, the frequency-variable element 111 is, for example, an arithmetic element (microprocessor element, microcontroller element, digital signal processor element, etc.), a power processing circuit element (voltage drop converter, filter element, rectifier circuit element, etc.), a signal transmitting element (transceiver), a switching element, or other element that forms a frequency phenomenon. The frequency phenomenon can be, for example, a fixed frequency, a non-fixed frequency, a variable frequency, an adjustable frequency, or any electrical frequency phenomenon, and this application is not limited thereto. The frequency-variable element 111 is disposed on a substrate 112, which is used to support the frequency-variable element 111. The substrate 112 is connected to the frequency-variable element 111.

[0019] The matching adjustment circuit 121 is connected to the frequency variable element 111 and the matching control unit 130. The matching adjustment circuit 121 has variable properties. In this embodiment, the properties are inductance or capacitance. In this embodiment, the matching adjustment circuit 121 is disposed in the substrate 112, and the matching adjustment circuit 121 is disposed in the electronic component layer 110 or the carrier layer 120. In this embodiment, the substrate 112 includes the electronic component layer 110 or the carrier layer 120 containing the matching adjustment circuit 121. For example, when the matching adjustment circuit 121 is disposed in the electronic component layer 110, the substrate 112 includes one or more layers in the electronic component layer 110 that have the matching adjustment circuit 121 and carry the frequency variable element 111. That is, the substrate 112 may include one or more layers between the frequency variable element 111 and the matching adjustment circuit 121, and the layer that has the matching adjustment circuit 121. For example, when the matching adjustment circuit 121 is disposed in the carrier layer 120, the substrate 112 includes a layer in the carrier layer 120 in which the matching adjustment circuit 121 is disposed, and one or more layers in the carrier layer 120 and the electronic component layer 110 in which the frequency variable element 111 is carried.

[0020] The matching control unit 130 is connected to the frequency variable element 111 and the matching adjustment circuit 121 . The matching control unit 130 is used to instantly detect the noise voltage of the frequency variable element 111 , and based on the noise voltage of the frequency variable element 111 determines whether to generate a control signal to adjust the properties of the matching adjustment circuit 121 through the control signal so that the zero pole of the substrate 112 matches the zero pole of the frequency variable element 111 . In this embodiment, the matching control unit 130 may be implemented at least by an existing noise detection circuit, a microcontroller element, or a microcontroller element and is not limited by this application. In this embodiment, the matching control unit 130 may be disposed in the electronic component layer 110 , the bearing layer 120 , or other intermediary layer electrically connected to the electronic component layer 110 and the bearing layer 120 , and is not limited by this application. In one embodiment, the matching control unit 130 may also be implemented by the frequency variable element 111 and is not limited by this application.

[0021] Since the frequency variable element 111 operates in different operating states, causing the zero pole of the frequency variable element 111 to change with the operating state, the zero pole of the frequency variable element 111 and the substrate 112 cannot be maintained in a matching state. The greater the difference between the zero pole of the substrate 112 and the zero pole of the frequency variable element 111 , the noise voltage of the frequency variable element 111 increases accordingly. For example, the aliasing voltage of the bump (bump) connected to the substrate 112 of the frequency variable element 111 increases. Therefore, the zero-pole matching state between the substrate 112 and the frequency variable element 111 can be quickly and easily confirmed by the means of detecting aliasing voltage in this application. Meanwhile, based on the operating state of the frequency variable element 111 , the matching control unit 130 may be adjusted by changing the matching adjustment circuit 121 when the difference between the zero pole of the substrate 112 and the zero pole of the frequency variable element 111 is too large attribute (capacitance value or inductance value), which accordingly changes the overall zero pole of the substrate 112 , reducing the noise voltage of the frequency variable element 111 , so that the zero pole of the substrate 112 matches the zero pole of the frequency variable element 111 .

[0022] In one embodiment, the matching control unit 130 can determine whether the zeros and poles of the substrate 112 match the zeros and poles of the frequency variable element 111 by judging whether the noise voltage of the detected frequency variable element 111 is equal to or less than a threshold value. In one embodiment, since the zeros and poles of the frequency variable element 111 are different when operating in different operating states, the matching control unit 130 can determine its threshold value by judging the operating state of the detected frequency variable element 111, and the threshold value is the same or different for different zeros and poles. In another embodiment, the matching control unit 130 can dynamically adjust the properties of the matching adjustment circuit 121 and record the changes in noise voltage in real time until the minimum noise voltage is found, and then stop adjusting the properties of the matching adjustment circuit 121. In this embodiment, the minimum noise voltage represents that the zeros and poles of the substrate 112 as a whole are the zeros and poles that best match the frequency variable element 111. In one embodiment, the matching control unit 130 can determine whether to detect noise voltage by judging whether the operating state of the detected frequency variable element 111 changes. For example, when the matching control unit 130 determines that the frequency variable element 111 has changed from a high frequency state to a low frequency state, the matching control unit 130 then detects the noise voltage. In this way, the matching control unit 130 can avoid maintaining the noise voltage detection state for a long time, effectively reducing the overall power consumption of the semiconductor device 100.

[0023] Please refer to Figure 4, which is a schematic diagram of the matching adjustment circuit 121 of this application. The matching adjustment circuit 121 includes a plurality of inductor elements 122 (122a~122n) connected in series with each other. Each inductor element 122 individually receives a control signal LCS (LCSa~LCSn) from the matching control unit 130. Each inductor element 122 determines whether to connect to the frequency variable element 111 according to the received control signal LCS. One end of one of the inductor elements 122 is connected to terminal N1. Each inductor element 122 includes a switching unit LSW and an inductor unit L. The switching unit LSW and the inductor unit L are connected in series. The switching unit LSW determines to establish a connection with terminal N2 or another inductor unit L according to the received control signal LCS. For example, the switching unit LSW of inductor element 122a determines to establish a connection with terminal N2 or the inductor unit L of inductor element 122b according to the control signal LCSa. In this embodiment, terminal N1 is electrically connected to the frequency variable element 111, and terminal N2 is grounded. In this embodiment, the switching unit LSW and the inductor unit L are semiconductor switching units and semiconductor inductor units formed in the carrier layer 120 through a semiconductor process. Thereby, the matching control unit 130 can determine the number of inductor elements 122 connected in series by the control signal LCS, thereby increasing or decreasing the inductance value of the matching adjustment circuit 121.

[0024] Please refer to Figure 5, which is another schematic diagram of the matching adjustment circuit 121 of this application. The matching adjustment circuit 121 includes a plurality of capacitor elements 123 (123a~123n) connected in parallel with each other. Each capacitor element 123 individually receives a control signal CCS (CCSa~CCSn) from the matching control unit 130. Each capacitor element 123 determines whether to connect to the frequency variable element 111 according to the received control signal CCS. One end of each capacitor element 123 is connected to terminal N1, and the other end is connected to terminal N2. Each capacitor element 123 includes a switching unit CSW and a capacitor unit C. The switching unit CSW and the capacitor unit C are connected in series. The switching unit CSW determines whether to establish a connection with the capacitor unit C according to the received control signal CCS. For example, the switching unit CSW of capacitor element 123a determines whether to establish a connection with the capacitor unit C of capacitor element 123a according to the control signal CCSa. In this embodiment, terminal N1 is electrically connected to the frequency variable element 111, and terminal N2 is grounded. In this embodiment, the switching unit CSW and the capacitor unit L are semiconductor switching units and semiconductor capacitor units formed in the carrier layer 120 through a semiconductor process. Therefore, the matching control unit 130 can determine the number of parallel capacitor elements 123 by using the control signal CCS, thereby increasing or decreasing the capacitance value of the matching adjustment circuit 121.

[0025] Please refer to Figure 6, which is another schematic diagram of the matching adjustment circuit 121 of this application. The matching adjustment circuit 121 includes a plurality of capacitor elements 123 (123a~123n) connected in parallel with each other. Each capacitor element 123 individually receives a bias control signal CVS (CVSa~CVSn) from the matching control unit 130. Each capacitor element 123 determines its capacitance value according to the received bias control signal CVS. One end of each capacitor element 123 is connected to terminal N1, and the other end is connected to terminal N2. In this embodiment, the capacitor element 123 is a metal-oxide-semiconductor capacitor (MOS Capacitor, MOSCAP). Thereby, the matching control unit 130 can determine the capacitance value of the parallel capacitor elements 123 by means of the bias control signal CVS, thereby increasing or decreasing the capacitance value of the matching adjustment circuit 121.

[0026] Please refer to Figure 7, which shows the attribute matching method of this application. It can be implemented by the aforementioned semiconductor device 100, and its steps include S100~S400.

[0027] Step S100: Obtain noise voltage. In this step, the matching control unit 130 detects the noise voltage of the frequency variable element 111 to confirm the current noise voltage of the frequency variable element 111. In one embodiment, the matching control unit 130 may further read the operating frequency of the frequency variable element 111.

[0028] Step S200: Determine whether to adjust the properties of the matching adjustment circuit based on the noise voltage. In this step, the matching control unit 130 determines whether to adjust the inductance or capacitance value of the matching adjustment circuit 121 based on the noise voltage. In one embodiment, when the matching control unit 130 determines that the noise voltage is greater than a threshold value, the matching control unit 130 adjusts the properties of the matching adjustment circuit 121. In one embodiment, the matching control unit 130 can dynamically adjust the properties of the matching adjustment circuit 121 and record the changes in the noise voltage in real time until the minimum noise voltage is found, at which point the adjustment of the properties of the matching adjustment circuit 121 stops. In one embodiment, the matching control unit 130 can determine whether to detect the noise voltage by judging whether the operating state of the frequency variable element 111 changes. For example, when the matching control unit 130 determines that the frequency variable element 111 changes from a high-frequency state to a low-frequency state, the matching control unit 130 then detects the noise voltage. If step S200 determines "yes", then in step S300, the matching control unit 130 adjusts the inductance or capacitance value of the matching adjustment circuit 121; otherwise, in step S400, the matching control unit 130 does not adjust the inductance or capacitance value of the matching adjustment circuit 121, keeping the inductance or capacitance value of the matching adjustment circuit 121 unchanged. After steps S300 and S400, the process returns to step S100.

[0029] Accordingly, the attribute matching method of this application obtains the desired noise voltage by adjusting the attributes of the matching adjustment circuit 121, thereby matching the zeros and poles of the substrate 112 with the frequency variable element 111, so as to achieve the effect of making the semiconductor device have better circuit stability.

[0030] In summary, the semiconductor device and its attribute matching method of this application, by applying advanced process technology, enable the matching adjustment circuit to be set in the substrate before packaging through advanced process technology. This application also uses a matching control unit to adjust the attributes of the matching adjustment circuit, so that the attributes of the substrate can be dynamically adjusted, so that the zeros and poles of the substrate can be matched with the zeros and poles of the frequency variable element in accordance with the operating state of the frequency variable element, thereby achieving the effect of making the semiconductor device have better circuit stability. [Simplified Explanation of the Diagram]

[0009] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of this application.

[0010] Figure 2 is a schematic diagram of the circuit architecture of a semiconductor device according to an embodiment of the present application.

[0011] Figure 3 is a schematic diagram of the configuration of a frequency-variable element according to an embodiment of this application.

[0012] Figure 4 is a schematic diagram of the architecture of the matching adjustment circuit according to an embodiment of this application.

[0013] Figure 5 is a schematic diagram of another architecture of the matching adjustment circuit according to an embodiment of this application.

[0014] Figure 6 is a schematic diagram of another architecture of the matching adjustment circuit according to an embodiment of this application.

[0015] Figure 7 is a schematic diagram of the steps of the attribute matching method according to an embodiment of this application.

Claims

1. A semiconductor device comprising: A frequency-variable element; A matching control unit is connected to the frequency variable element to detect a noise voltage of the frequency variable element; A matching adjustment circuit is connected to the frequency variable element and the matching control unit; wherein the matching control unit dynamically adjusts the properties of the matching adjustment circuit based on the noise voltage of the frequency variable element to change the properties of the semiconductor device.

2. The semiconductor device as claimed in claim 1, wherein, This property of the semiconductor device is an inductance value or a capacitance value.

3. The semiconductor device as claimed in claim 1, wherein, The matching adjustment circuit includes multiple inductors connected in series with each other. Each inductor individually receives a control signal from the matching control unit, and the inductors determine whether to connect to the frequency variable element based on the received control signal.

4. The semiconductor device as claimed in claim 1, wherein, The matching adjustment circuit includes multiple capacitor elements connected in parallel with each other. Each capacitor element individually receives a control signal from the matching control unit, and the capacitor elements determine whether to connect to the frequency variable element based on the received control signal.

5. The semiconductor device as claimed in claim 4, wherein, The capacitor is a metal-oxide-semiconductor capacitor.

6. The semiconductor device as claimed in claim 4, wherein, The capacitor element includes a switching unit and a capacitor unit, the switching unit being connected in series with the capacitor unit, and the switching unit receiving the control signal from the matching control unit.

7. The semiconductor device as claimed in claim 1, wherein, The semiconductor device includes an electronic component layer and a carrier layer, the electronic component layer being disposed on the carrier layer, and the matching adjustment circuit being disposed on the electronic component layer or the carrier layer.

8. The semiconductor device as claimed in claim 1, wherein, The semiconductor device is packaged using a wafer-based substrate stacking packaging technology.

9. A method for matching the attributes of a semiconductor device, applicable to the semiconductor device as described in claim 1, comprising the steps of: Obtain the noise voltage; And the matching adjustment circuit is dynamically adjusted based on the noise voltage.

10. The attribute matching method as described in request item 9, wherein, Adjusting the inductance or capacitance value of the matching adjustment circuit increases or decreases the inductance or capacitance value of the semiconductor device.

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