Thin film transistor substrate and display device using the same

Abstract

The present invention provides a thin-film transistor substrate and a display device using the thin-film transistor substrate. The thin-film transistor substrate includes: a substrate; a buffer layer having a buffer groove disposed on the substrate, wherein the buffer groove includes: an inclined surface; an active layer disposed on the buffer layer; and a gate electrode disposed on the active layer, wherein the active layer is disposed in a stepped manner on the buffer groove, and one end of the gate electrode overlaps with the inclined surface of the buffer groove.

Description

Technical Field

[0001] The present invention relates to a thin film transistor substrate and a display device using the thin film transistor substrate. Prior Art

[0002] Since thin film transistors can be manufactured on glass or plastic substrates, they are widely used as switching elements or driving elements in display devices such as liquid crystal display devices or organic light-emitting devices.

[0003] Various types of thin film transistors can be used in display panels to drive organic light-emitting devices (OLEDs), such as: driving thin film transistors for making each pixel emit light, switching thin film transistors for adjusting the amount of voltage applied to the driving thin film transistors, logic-GIP thin film transistors for controlling thin film transistors set in the display area, and buffer-GIP thin film transistors for controlling the overall power supply.

[0004] To achieve high-mobility devices, thin-film transistors with a top-gate structure can use a gate electrode as a mask to make the oxide semiconductor layer conductive. However, this process can result in excessive penetration into the desired conductive region, making the channel region smaller than the intended region, shortening the channel length, and shifting the threshold voltage (Vth) in the negative direction. In particular, a larger width of the oxide semiconductor layer can increase the degree of penetration into the desired conductive region, further shortening the channel length.

[0005] When the threshold voltage (Vth) shifts in the negative direction, leakage current may occur in the initial image. As a result, the display panel containing thin film transistors may not drive properly due to the leakage current, and the power consumption of the panel may increase. Summary of the Invention

[0006] The present invention has been proposed in view of the above-mentioned problems, and its purpose is to provide a thin film transistor substrate and a display device including the thin film transistor substrate, wherein an active layer is arranged on a buffer groove provided in a buffer layer, thereby preventing oxygen vacancies diffused through the conductive process from penetrating deeply into the channel of the active layer, thereby preventing a negative shift in the threshold voltage (Vth) of the thin film transistor.

[0007] To achieve these and other advantages and in accordance with the purposes of the present invention, as embodied and broadly described herein, a thin film transistor substrate includes: a substrate; a buffer layer having a buffer trench disposed on the substrate, wherein the buffer trench includes: an inclined surface; an active layer disposed on the buffer layer; and a gate electrode disposed on the active layer, wherein the active layer is disposed in a stepped manner on the buffer trench, and one end of the gate electrode overlaps the inclined surface of the buffer trench.

[0008] In some embodiments, one end of the gate electrode may overlap with a portion of the active layer disposed on the inclined surface of the buffer trench.

[0009] In some embodiments, the thin film transistor substrate may further include: a gate insulation layer disposed between the active layer and the gate electrode, wherein the gate insulation layer overlaps with the buffer groove, and one end of the gate insulation layer corresponds to one end of the gate electrode.

[0010] In some embodiments, the thin film transistor substrate may further include: a gate insulation layer disposed between the active layer and the gate electrode, wherein the gate insulation layer overlaps with the buffer groove, and one end of the gate insulation layer is disposed between one end of the active layer and one end of the gate electrode.

[0011] In some embodiments, the gate insulating layer may have a first width, the gate electrode may have a second width, the active layer may have a first length, and the first width of the gate insulating layer may be greater than the second width of the gate electrode and less than the first length of the active layer.

[0012] In some embodiments, the active layer may include: a channel portion; a connecting portion disposed on one side of the channel portion; and a diffusion portion disposed between the channel portion and the connecting portion, and the channel portion may include: a first area in contact with the bottom surface of the buffer groove; and a second area in contact with the inclined surface of the buffer groove.

[0013] In some embodiments, one end of the second region of the channel portion may be disposed in the inclined surface.

[0014] In some embodiments, one end of the second region of the channel portion may correspond to one end of the gate electrode.

[0015] In some embodiments, one end of the diffusion portion may be disposed on an inclined surface of the buffer groove.

[0016] In some embodiments, the other end of the diffusion portion may correspond to one end of the gate electrode.

[0017] In some embodiments, the other end of the diffusion portion may be disposed between one end of the gate electrode and one end of the active layer.

[0018] In some embodiments, the active layer may include: a channel portion; a connecting portion, which is arranged on one side of the channel portion; and a diffusion portion, which is arranged between the channel portion and the connecting portion, wherein one end of the channel portion may be arranged on the bottom surface of the buffer groove, and one end of the diffusion portion is arranged on the inclined surface of the buffer groove, and one end of the channel portion and one end of the diffusion portion may contact each other at the boundary between the bottom surface of the buffer groove and the inclined surface of the buffer groove.

[0019] In some embodiments, the buffer tank may further include a bottom surface connected to the inclined surface, and an angle formed between the bottom surface and the inclined surface may be equal to or greater than 30 degrees and equal to or less than 45 degrees.

[0020] In some embodiments, the buffer groove may further include a bottom surface connected to the inclined surface, and a depth of the bottom surface of the buffer groove may be equal to or greater than 1.41 μm and equal to or less than 2 μm.

[0021] In another aspect of the present invention, a thin film transistor substrate includes: a substrate; a buffer layer having a buffer groove disposed on the substrate; an active layer disposed on the buffer layer; and a gate electrode disposed on the active layer, wherein the buffer groove includes a bottom surface and an inclined surface connected to the bottom surface, and the active layer includes: a channel portion; a connecting portion disposed on one side of the channel portion; and a diffusion portion disposed between the channel portion and the connecting portion, and the channel portion overlaps with the bottom surface and the inclined surface, and one end of the channel portion is disposed on the inclined surface of the buffer groove.

[0022] In some embodiments, the width of the bottom surface of the buffer trench may be smaller than the width of the gate electrode, and the width of the entire bottom surface and inclined surface of the buffer trench may be greater than the width of the gate electrode.

[0023] In some embodiments, the thin film transistor substrate may further include: a gate insulating layer disposed between the active layer and the gate electrode, wherein the entire area of the diffusion portion may overlap with the gate insulating layer.

[0024] In some embodiments, a portion of the diffusion portion may not overlap with the gate electrode.

[0025] In some embodiments, one end of the channel portion may correspond to one end of the gate electrode.

[0026] In yet another aspect of the present invention, a display device including a thin film transistor substrate comprises: a substrate; a buffer layer disposed on the substrate and having a buffer groove; an active layer disposed on the buffer layer; and a gate electrode disposed on the active layer, wherein the active layer is disposed in a stepped manner on the buffer groove, and one end of the gate electrode overlaps with an inclined surface disposed in the buffer groove.

[0027] It should be understood that both the foregoing general description and the following detailed description of the present invention are by way of illustration and are intended to provide further explanation of the present invention. Simple diagram description

[0028] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention. FIG. 1 is a plan view of a thin film transistor substrate according to an embodiment of the present invention. FIG2A is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present invention; in this case, FIG2A corresponds to the cross-sectional view II' of FIG1. FIG2B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention; in this case, FIG2B corresponds to the cross-sectional view II' of FIG1. 3A and 3B are schematic cross-sectional views respectively showing a thin film transistor substrate according to an embodiment of the present invention and a thin film transistor substrate according to a comparative example. 3C is a graph showing carrier concentrations according to distances from diffusion portions of the thin film transistor substrate according to the embodiment of the present invention and the thin film transistor substrate according to the comparative example. 4A to 4E are cross-sectional views of a process for manufacturing a thin film transistor substrate according to an embodiment of the present invention. FIG5 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention; in this case, FIG5 corresponds to the cross-sectional view II' of FIG1. 6A to 6F are cross-sectional views showing a process of manufacturing a thin film transistor substrate according to another embodiment of the present invention. FIG. 7 is a cross-sectional view of a display device including a thin film transistor substrate according to an embodiment of the present invention. FIG. 8 is a schematic diagram of a display device according to an embodiment of the present invention. FIG. 9 is a circuit diagram of a pixel included in a display device according to an embodiment of the present invention. Implementation Method

[0029] The advantages, features, and implementation methods of the present invention are illustrated by the following embodiments described with reference to the accompanying drawings. The present invention may be embodied in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the scope of the present invention to those skilled in the art. Furthermore, the present invention is defined solely by the scope of the claims.

[0030] The shapes, sizes, proportions, angles, and quantities shown in the drawings used to describe the embodiments of the present invention are merely examples, and the present invention is not limited to the details shown. Identical reference numerals generally denote identical components. In the following description, detailed descriptions of known functions or configurations will be omitted if they unnecessarily obscure the key points of the present invention.

[0031] When "include," "have," and "comprise" are used in this specification, other parts may also be present unless "only" is used. Terms in the singular form may include plural forms unless otherwise mentioned.

[0032] When explaining an element, although there is no explicit description, the element is interpreted as including an error area.

[0033] When describing positional relationships, for example, when the position sequence is described as "on", "above", "below", "under", and "beside", unless "immediately" or "directly" is used, the situation where there is no contact between them can be included.

[0034] If a first element is stated to be "above" a second element, this does not necessarily mean that the first element is actually above the second element in the drawings. The top and bottom parts of an object can vary depending on the orientation of the object. Therefore, a first element being "above" a second element includes both cases where the first element is "below" the second element and cases where the first element is "above" the second element in the drawings or in actual configuration.

[0035] When describing temporal relationships, for example, when describing time sequence as "after", "followed", "next" and "before", discontinuities may be included unless "immediately" or "directly" is used.

[0036] It should be understood that although terms such as "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0037] It should be understood that the term "at least one" includes all combinations related to any one element. For example, "at least one of a first element, a second element, and a third element" includes all combinations of two or more elements selected from the first, second, and third elements, as well as each of the first, second, and third elements.

[0038] The features of the various embodiments of the present invention may be partially or entirely connected or combined with each other, and may be mutually operable and technically driven in various ways. The embodiments of the present invention may be implemented independently of each other, or may be implemented together in an interrelated manner.

[0039] In the drawings, the same reference numerals are used to represent the same or similar elements even though they are depicted in different drawings.

[0040] In the embodiments of the present invention, source electrodes and drain electrodes are distinguished from each other for ease of description. However, the terms source electrode and drain electrode can be used interchangeably. Thus, a source electrode can be a drain electrode, and a drain electrode can be a source electrode. Furthermore, a source electrode in any embodiment of the present invention can be a drain electrode in another embodiment of the present invention, and a drain electrode in any embodiment of the present invention can be a source electrode in another embodiment of the present invention.

[0041] In one or more embodiments of the present invention, for ease of description, the source region is distinguished from the source electrode, and the drain region is distinguished from the drain electrode. However, embodiments of the present invention are not limited to this structure. For example, the source region can be the source electrode, and the drain region can be the drain electrode. Alternatively, the source region can be the drain electrode, and the drain region can be the source electrode.

[0042] FIG. 1 is a plan view of a thin film transistor substrate according to an embodiment of the present invention.

[0043] As shown in FIG. 1 , a thin film transistor substrate according to an embodiment of the present invention may include: a buffer layer 110 ; an active layer 120 ; a gate electrode 140 ; a source electrode 161 ; and a drain electrode 162 .

[0044] The active layer 120 may extend in a first direction, for example, in a horizontal direction. The source electrode 161 may be disposed on one side of the active layer 120, for example, on the left side, and the drain electrode 162 may be disposed on the other side of the active layer 120, for example, on the right side.

[0045] The gate electrode 140 may extend in a second direction, for example, in a vertical direction. In this case, the second direction may correspond to a direction perpendicular to the first direction. The gate electrode 140 overlaps the active layer 120.

[0046] The source electrode 161 may be electrically connected to one side of the active layer 120 through the first contact hole CH1, and the drain electrode 162 may be electrically connected to the other side of the active layer 120 through the second contact hole CH2.

[0047] According to an embodiment of the present invention, the buffer layer 110 can be formed on the entire surface of the thin film transistor substrate according to an embodiment of the present invention so as to overlap with the active layer 120, the gate electrode 140, the source electrode 161, and the drain electrode 162. In this case, since the buffer trench BG is provided in the buffer layer 110, the length of the channel portion provided in the active layer 120 can be prevented from being excessively shortened, which will be described in detail below with reference to FIG. 2A.

[0048] The buffer trench BG may overlap the active layer 120 and the gate electrode 140 in a region where the active layer 120 and the gate electrode 140 overlap each other. In this case, the buffer trench BG may have a first width W BG in the horizontal direction, the gate electrode 140 may have a second width W GE in the horizontal direction, and the active layer 120 may have a first length L ACT in the horizontal direction.

[0049] According to an embodiment of the present invention, the first width W BG of the buffer trench BG may be formed to be larger than the second width W GE of the gate electrode 140 , and the first width W BG of the buffer trench BG may be formed to be smaller than the first length L ACT of the active layer 120 .

[0050] FIG2A is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present invention. In this case, FIG2A corresponds to the cross-sectional view II' of FIG1.

[0051] As shown in FIG. 2A , a thin film transistor substrate according to an embodiment of the present invention may include: a substrate 100 ; a buffer layer 110 ; an active layer 120 ; a gate insulating layer 130 ; a gate electrode 140 ; an interlayer insulating layer 150 ; a source electrode 161 ; and a drain electrode 162 .

[0052] Substrate 100 can be made of glass or plastic. Specifically, substrate 100 can be made of a flexible, transparent plastic, such as polyimide. When using polyimide as substrate 100, considering that a high-temperature deposition process will be performed on substrate 100, a heat-resistant polyimide that can withstand high temperatures can be used.

[0053] The buffer layer 110 may be formed on the substrate 100. The buffer layer 110 may protect the active layer 120 by blocking air and moisture. The buffer layer 110 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or metal oxide, but is not limited thereto and may be made of an organic insulating material.

[0054] According to an embodiment of the present invention, the buffer layer 110 may be provided with a buffer groove BG formed by being recessed from the upper surface US of the buffer layer 110. The buffer groove BG is formed by removing a portion of the upper surface US of the buffer layer 110.

[0055] The buffer groove BG includes a bottom surface BS disposed at a deepest portion from the upper surface US of the buffer layer 110 , and an inclined surface IS connected to the bottom surface BS and forming a first angle θ1 therewith.

[0056] A first angle θ1 formed by the bottom surface BS and the inclined surface IS of the buffer trench BG may be equal to or greater than 30 degrees and equal to or less than 45 degrees. When the first angle θ1 formed by the bottom surface BS and the inclined surface IS is less than 30 degrees, the length of the channel portion 121 may be excessively shortened due to oxygen vacancies diffused from the first connection portion 122a or the second connection portion 122b. Furthermore, when the first angle θ1 formed by the bottom surface BS and the inclined surface IS exceeds 45 degrees, the thickness of the active layer 120 deposited on the inclined surface IS and the thickness of the active layer 120 deposited on the bottom surface BS and the upper surface US may become different from each other, thereby causing a problem of unstable device characteristics.

[0057] The first angle θ1 of the inclined surface IS can be controlled by adjusting the first height H1 of the bottom surface BS of the buffer groove BG and the second height H2 of the upper surface US of the buffer layer 110. In this case, the first height H1 and the second height H2 can each be defined as the distance from the lower surface of the buffer layer 110 to the bottom surface BS of the buffer groove BG, or the distance from the lower surface of the buffer layer 110 to the upper surface US of the buffer layer 110.

[0058] According to an embodiment of the present invention, the depth H2-H1 of the bottom surface BS of the buffer trench BG may be equal to or greater than 1.41 μm and equal to or less than 2 μm. When the depth H2-H1 of the bottom surface BS of the buffer trench BG is less than 1.41 μm, the length of the channel portion 121 may be excessively shortened due to oxygen vacancies diffused from the first connection portion 122a or the second connection portion 122b. Furthermore, when the depth H2-H1 of the bottom surface BS of the buffer trench BG exceeds 2 μm, the thickness of the active layer 120 deposited on the inclined surface IS and the thickness of the active layer 120 deposited on the bottom surface BS and the upper surface US may become different from each other, thereby causing a problem of unstable device characteristics.

[0059] The active layer 120 may be disposed on the buffer layer 110 so as to overlap the buffer groove BG. Specifically, the active layer 120 may be disposed on a portion of the upper surface US of the buffer layer 110, the inclined surface IS of the buffer groove BG, and the bottom surface BS of the buffer groove BG. The active layer 120 may be disposed on the buffer groove BG in a stepped manner. In this case, the active layer 120 may have a first horizontal length L ACT .

[0060] The active layer 120 may include a semiconductor material, such as an oxide semiconductor material. The oxide semiconductor material may include, for example, at least one of the following: an indium zinc oxide (IZO, InZnO)-based oxide semiconductor material, an indium gallium oxide (IGO, InGaO)-based oxide semiconductor material, an indium tin oxide (ITO, InSnO)-based oxide semiconductor material, an indium gallium zinc oxide (IGZO, InGaZnO)-based oxide semiconductor material, an indium gallium zinc tin oxide (IGZTO, InGaZnSnO)-based oxide semiconductor material, a gallium zinc tin oxide (GZTO, GaZnSnO)-based oxide semiconductor material, a gallium zinc oxide (GZO, GaZnO)-based oxide semiconductor material, an indium tin zinc oxide (ITZO, InSnZnO)-based oxide semiconductor material, and an iron indium zinc oxide (FIZO, FeInZnO)-based oxide semiconductor material.

[0061] The active layer 120 may include: a channel portion 121; a first connecting portion 122a; a second connecting portion 122b; a first diffusing portion 123a; and a second diffusing portion 123b. In this case, the first connecting portion 122a is disposed on one side of the channel portion 121, for example, the left side, and the second connecting portion 122b is disposed on the other side of the channel portion 121, for example, the right side. The first diffusing portion 123a is disposed between the channel portion 121 and the first connecting portion 122a, and the second diffusing portion 123b may be disposed between the channel portion 121 and the second connecting portion 122b.

[0062] The channel portion 121 is disposed inside the buffer tank BG. Specifically, a central portion of the channel portion 121 may be disposed on the bottom surface BS of the buffer tank BG, and one end and the other end of the channel portion 121 may be disposed on the inclined surface IS of the buffer tank BG.

[0063] Channel portion 121 includes a first region connected to bottom surface BS and a second region connected to the first region and in contact with inclined surface IS. In this case, the first region and the second region may form a first angle θ1 like bottom surface BS and inclined surface IS of buffer groove BG.

[0064] Channel portion 121 overlaps gate electrode 140. According to an embodiment of the present invention, one end of channel portion 121, for example, the left end, corresponds to one end of gate electrode 140, for example, the left end; and the other end of channel portion 121, for example, the right end, may correspond to the other end of gate electrode 140. However, the present invention is not limited thereto.

[0065] The first connection portion 122a and the second connection portion 122b can be made conductive, for example, by performing a plasma treatment on a semiconductor material using the gate electrode 140 as a mask. For example, in the first connection portion 122a and the second connection portion 122b, portions of the active layer 120 can be made conductive during the patterning of the gate insulation layer 130 disposed on the active layer 120. The gate insulation layer 130 can be formed over the entire surface of the active layer 120 and then etched using plasma to form a pattern. In this case, during the patterning of the gate insulation layer 130, when portions of the gate insulation layer 130 formed over the entire surface are etched, portions of the active layer 120 exposed can be made conductive, thereby forming the first connection portion 122a and the second connection portion 122b.

[0066] A conductive process can be defined as a process that imparts conductive properties to an oxide semiconductor material. The oxide semiconductor material that has undergone the conductive process may have conductive properties. The conductive process may include, for example, a plasma process, in which plasma is applied to create a conductor, but is not limited thereto. More specifically, when plasma is applied to the oxide semiconductor material, oxygen contained in the oxide semiconductor is released, forming oxygen vacancies, and electrons migrate through the oxygen vacancies. Therefore, the oxide semiconductor material has conductive properties due to the oxygen vacancies. When plasma is used for the conductive process, the plasma may contain, for example, fluorine (F). Specifically, the fluorine-containing plasma may include, for example, sulfur hexafluoride (SF6) and nitrogen trifluoride (NF3). However, the plasma used to render the first and second connection portions 122a and 122b conductive is not limited thereto and may include various materials known in the art.

[0067] Through the conductive process, portions of the active layer 120, such as the first and second connection portions 122a and 122b, can be made conductive to have conductive properties. Therefore, the first and second connection portions 122a and 122b can have better conductivity than the channel portion 121, and each can function as a conductive line or a source / drain electrode.

[0068] During the formation of the first connecting portion 122a or the second connecting portion 122b, the first diffusion portion 123a and the second diffusion portion 123b may be formed, respectively. Specifically, oxygen vacancies formed in the first connecting portion 122a or the second connecting portion 122b may diffuse toward the center of the channel portion 121 through the conductive process. The oxygen vacancies diffused toward the center of the channel portion 121 form the first diffusion portion 123a and the second diffusion portion 123b.

[0069] For example, the first diffusion portion 123a may be formed when oxygen vacancies formed in the first connection portion 122a diffuse in the direction of the channel portion 121. Likewise, the second diffusion portion 123b may be formed when oxygen vacancies formed in the second connection portion 122b diffuse.

[0070] Since the first diffusion portion 123a and the second diffusion portion 123b are conductive through oxygen vacancies diffused from the first connection portion 122a and the second connection portion 122b, the conductive properties are relatively lower than the first connection portion 122a and the second connection portion 122b, but relatively higher than the channel portion 121.

[0071] According to an embodiment of the present invention, the first diffusion portion 123a and the second diffusion portion 123b can be disposed within the inclined surface IS of the buffer trench BG. Specifically, either one end of the first diffusion portion 123a or the other end of the second diffusion portion 123b can be disposed within the inclined surface IS. This formation ensures that the designed length of the channel portion 121 is maintained even if oxygen vacancies diffuse from the first connection portion 122a or the second connection portion 122b. Because the designed length of the channel portion 121 is maintained, a thin-film transistor substrate with a short channel can be achieved without shifting the threshold voltage (Vth) in the negative direction.

[0072] According to an embodiment of the present invention, one end of the first diffusion portion 123a, for example, the left end, corresponds to one end of the gate insulating layer 130 and one end of the gate electrode 140, while the other end of the first diffusion portion 123a, for example, the right end, is located within the inclined surface IS of the buffer trench BG. Similarly, one end of the second diffusion portion 123b, for example, the right end, corresponds to the other end of the gate insulating layer 130 and the other end of the gate electrode 140, while the other end of the second diffusion portion 123b, for example, the left end, is located within the inclined surface IS of the buffer trench BG. In this specification, the term "corresponding" means being located on a straight line or any plane.

[0073] The gate insulating layer 130 is disposed on the active layer 120. In this case, the top surface of the gate insulating layer 130 may have a third width WGIa in the horizontal direction, and the third width WGIa may be smaller than the first length LACT of the active layer 120.

[0074] The gate insulating layer 130 is etched using the gate electrode 140 as a mask, and thus the gate insulating layer 130 may be formed to have the same size as the gate electrode 140. However, the present invention is not limited thereto.

[0075] One end of the gate insulating layer 130, for example, the left end, may correspond to one end of the gate electrode 140, and the other end of the gate insulating layer 130, for example, the right end, may correspond to the other end of the gate electrode 140. Therefore, the third width W GIa of the gate insulating layer 130 may be equal to the second width W GE of the gate electrode 140.

[0076] The gate insulating layer 130 may be disposed in a stepped manner on the buffer trench BG. Specifically, the height of the central portion of the gate insulating layer 130 may be lower than the height of the edge portion.

[0077] The gate insulating layer 130 may include a silicon nitride layer SiN x or a silicon oxide layer SiO x, but is not limited thereto. The gate insulating layer 130 may be formed of a single layer or multiple layers including an inorganic insulating material and / or an organic insulating material.

[0078] The gate electrode 140 is disposed on the gate insulating layer 130. The horizontal width of the gate electrode 140 is set to be longer than the horizontal width of the bottom surface BS of the buffer trench BG and set to be smaller than the width of the entire buffer trench BG.

[0079] The gate electrode 140 overlaps the buffer trench BG. Specifically, one end and the other end of the gate electrode 140 are formed to overlap the inclined surface IS of the buffer trench BG.

[0080] According to an embodiment of the present invention, one end and the other end of the gate electrode 140 overlap the inclined surface IS of the buffer trench BG, respectively, allowing the channel portion 121 of the active layer 120 to be disposed within the buffer trench BG. In other words, the channel portion 121 is formed into a short channel, thereby enhancing the on-current characteristics of the thin-film transistor substrate according to an embodiment of the present invention and further preventing the channel portion 121 from becoming too short, thereby preventing the threshold voltage (Vth) of the thin-film transistor substrate according to an embodiment of the present invention from shifting in the negative (-) direction.

[0081] The gate electrode 140 can be arranged in a stepped manner on the buffer trench BG. Specifically, the height of the center portion of the gate electrode 140 can be lower than the height of the edge portion. In this case, the height of the gate electrode 140 can be defined as the height from the upper surface of the substrate 100 to the upper surface of the center portion of the gate electrode 140, or from the upper surface of the substrate 100 to the upper surface of the edge portion of the gate electrode 140.

[0082] The gate electrode 140 may include at least one of the following materials: aluminum-based metals, such as aluminum (Al) or aluminum alloys; silver-based metals, such as silver (Ag) or silver alloys; copper-based metals, such as copper (Cu) or copper alloys; molybdenum-based metals, such as molybdenum (Mo) or molybdenum alloys; chromium (Cr); tantalum (Ta); neodymium (Nd); or titanium (Ti). The gate electrode 140 may have a structure comprising a single metal layer or a multilayer structure comprising at least two metal layers, each with different physical properties.

[0083] The interlayer insulating layer 150 insulates the gate electrode 140 from the source electrode 161 and further insulates the gate electrode 140 from the drain electrode 162. The interlayer insulating layer 150 may be formed of a single layer or multiple layers including an inorganic insulating material and / or an organic insulating material.

[0084] The first contact hole CH1 and the second contact hole CH2 may be provided in the interlayer insulating layer 150. Therefore, a portion of the upper surface of the first connection portion 122a of the active layer 120 may be exposed through the first contact hole CH1, and further, a portion of the upper surface of the second connection portion 122b of the active layer 120 may be exposed through the second contact hole CH2.

[0085] The source electrode 161 and the drain electrode 162 may be disposed on the interlayer insulating layer 150 .

[0086] The source electrode 161 may be electrically connected to the first connection portion 122a of the active layer 120 through the first contact hole CH1, and the drain electrode 162 may be electrically connected to the second connection portion 122b of the active layer 120 through the second contact hole CH2.

[0087] The source electrode 161 and the drain electrode 162 may be formed of the same material as the gate electrode 140, but are not limited thereto and may be formed of materials known in the art.

[0088] FIG2B is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present invention. FIG2B corresponds to FIG1 , along the line II'. The embodiment of FIG2B is identical to FIG2A except for the configuration of the channel and diffusion sections. Therefore, the following description will primarily focus on the differences.

[0089] As shown in FIG2B , a thin film transistor substrate according to another embodiment of the present invention may include: a substrate 100; a buffer layer 110; an active layer 120; a gate insulating layer 130; a gate electrode 140; an interlayer insulating layer 150; a source electrode 161; and a drain electrode 162. Meanwhile, in the embodiment of FIG2B , the first height H1 of the bottom surface BS of the buffer trench BG is the same as that of the embodiment of FIG2A . However, unlike the embodiment of FIG2A , the upper surface US of the buffer layer 110 is at a third height H3 from the bottom surface BS of the buffer layer 110. Therefore, the inclined surface IS of the buffer trench BG may be formed at a second angle θ2 different from the first angle θ1.

[0090] According to another embodiment of the present invention, the channel portion 121 of the active layer 120 may not be disposed on the inclined surface IS of the buffer groove BG, but may be formed only on the bottom surface BS of the buffer groove BG. Specifically, one end and the other end of the channel portion 121, for example, the left end and the right end, may be disposed on the bottom surface BS of the buffer groove BG, while one end and the other end of the channel portion 121 may not be disposed on the inclined surface IS of the buffer groove BG.

[0091] Furthermore, the first diffusion portion 123a and the second diffusion portion 123b may be formed to cover the inclined surface IS of the buffer tank BG. In this case, the first diffusion portion 123a and the second diffusion portion 123b may contact the channel portion 121 at the boundary between the bottom surface BS of the buffer tank BG and the inclined surface IS of the buffer tank BG. Specifically, one end of the first diffusion portion 123a, for example, the right end, may contact one end of the channel portion 121, for example, at the boundary between the bottom surface BS and the inclined surface IS. Similarly, one end of the second diffusion portion 123b, for example, the left end, may contact the other end of the channel portion 121, for example, at the boundary between the bottom surface BS and the inclined surface IS.

[0092] According to another embodiment of the present invention, since oxygen vacancies diffused from first connection portion 122a and second connection portion 122b do not reach the portion of active layer 120 disposed on bottom surface BS of buffer trench BG, the length of channel portion 121 disposed on bottom surface BS of buffer trench BG can be prevented from being excessively shortened. Furthermore, since the length of channel portion 121 is not excessively shortened, a thin film transistor substrate with a short channel can be realized without shifting the threshold voltage (Vth) in the negative direction.

[0093] Figures 3A and 3B are schematic cross-sectional views of a thin film transistor substrate according to an embodiment of the present invention and a thin film transistor substrate according to a comparative example, respectively. Figures 3A and 3B are cross-sectional views showing only the substrate, buffer layer, active layer, gate insulating layer, and gate electrode for ease of description of the thin film transistor substrate according to the embodiment of Figure 2A or the thin film transistor substrate according to the comparative example.

[0094] First, since the thin film transistor substrate of FIG. 3A is identical to the thin film transistor substrate of FIG. 2A , a repeated description thereof will be omitted. Furthermore, since the thin film transistor substrate according to the comparative example of FIG. 3B has the same configuration as that of the present invention except for the configuration of the buffer tank, the remaining configuration will be described using the same reference numerals, and a repeated description thereof will be omitted.

[0095] As shown in FIG3B , the thin film transistor substrate according to the comparative example includes: a substrate 100; a buffer layer 110; an active layer 120; a gate insulating layer 130; and a gate electrode 140. However, a separate buffer trench is not provided in the buffer layer 110 of the thin film transistor substrate according to the comparative example.

[0096] Figure 3C is a graph showing carrier concentration as a function of distance from the diffusion portion of a thin-film transistor substrate according to an embodiment of the present invention and a comparative example. In this case, Figure 3C shows carrier concentration as a function of distance from the thin-film transistor substrate according to the embodiment of Figure 3A and the comparative example of Figure 3B . Each embodiment includes an active layer 120 having a length of 20 μm and a width of 20 μm (20 μm × 10 μm). Furthermore, this distance is measured from one end of the first connection portion 122a along the active layer 120 toward the channel portion 121.

[0097] Point a in FIG3C is about the carrier concentration at one end, for example, the left end, of the thin film transistor substrate according to the embodiment of FIG3A and the comparative example of FIG3B , while point b in FIG3C is about the carrier concentration at the other end, for example, the right end, of the thin film transistor substrate according to the embodiment of FIG3A and the comparative example of FIG3B .

[0098] As shown in Figure 3C, at point a, the carrier concentration is relatively high because one end of first diffusion portion 123a is in contact with first connecting portion 122a. On the other hand, at point b, the other end of first diffusion portion 123a is spaced apart from first connecting portion 122a. In this case, it can be seen that the carrier concentration gradually decreases from point a toward point b. Furthermore, it can be seen that the carrier concentration at point b differs by approximately 0.28 times that of point a. Therefore, since the diffusion of oxygen vacancies begins to decrease significantly at a point approximately 1 μm away from first connecting portion 122a, such as point b, and the carrier concentration is relatively low, it can function as channel portion 121 starting from point b.

[0099] 3A , since first diffusion portion 123a is disposed on inclined surface IS, oxygen vacancies from first connection portion 122a diffuse only from point a to point b. In this case, since one end of first diffusion portion 123a, for example, its right end, diffuses only to the point (point b) corresponding to gate electrode 140, the designed length of channel portion 121 can be ensured to be not too short.

[0100] On the other hand, referring to FIG3B , since the comparative example of FIG3B does not include a separate buffer trench BG, the first diffusion portion 123a is disposed on a flat surface. Therefore, unlike the case of FIG3A , when oxygen vacancies diffuse from the first connection portion 122a from point a to point b, one end of the first diffusion portion 123a, for example, the right end, is located within the gate electrode 140. Consequently, the horizontal width of the channel portion 121 is formed to be shorter than the horizontal width of the gate electrode 140. Therefore, according to the comparative example of FIG3B , a channel portion 121 is obtained that is shorter than the designed length.

[0101] Therefore, as shown in the embodiment of Figure 3A, when the buffer layer 110 is provided with a buffer groove BG and the active layer 120 is provided on the buffer groove BG, the first diffusion portion 123a and the second diffusion portion 123b are provided on the inclined surface IS of the buffer groove BG, thereby ensuring that the length of the channel portion 121 is as designed.

[0102] Meanwhile, in FIG. 3A to FIG. 3C , the carrier concentration varying according to the distance is described, focusing on the case where the active layer 120 has a length of 20 μm and a width of 10 μm. However, the length and width of the active layer 120 are not limited thereto and can be formed in various sizes according to the knowledge in this technical field.

[0103] 4A to 4E are cross-sectional views illustrating a process for manufacturing a thin film transistor substrate according to an embodiment of the present invention. The process cross-sectional views of FIG. 4A to 4E relate to the process for manufacturing the embodiment of FIG. 2A , and like reference numerals are assigned to like elements, and repeated descriptions will be omitted.

[0104] 4A , a substrate 100 is prepared and a buffer layer 110 is formed on the substrate 100. Next, a buffer groove BG is formed in the buffer layer 110. In this case, the buffer groove BG is formed such that a bottom surface BS and an inclined surface IS of the buffer groove BG form a first angle θ1.

[0105] Next, as shown in FIG4B , an active layer 120 is formed on the buffer layer 110. In this case, the active layer 120 may be formed to cover the entire buffer trench BG. Therefore, the active layer 120 may cover the bottom surface BS and the inclined surface IS of the buffer trench BG, as well as a portion of the upper surface US of the buffer layer 110.

[0106] Since the active layer 120 is formed to cover the buffer groove BG and a portion of the upper surface US of the buffer layer 110 , the active layer 120 may be disposed on the buffer layer 110 in a stepped manner.

[0107] 4C , a gate insulating film layer 130 a is formed on the buffer layer 110 and the active layer 120 , and a gate electrode 140 is patterned on the gate insulating film layer 130 a . In this case, the gate insulating film layer 130 a may be formed on the entire surface of the substrate 100 .

[0108] Since the gate insulating film layer 130 a and the gate electrode 140 are formed to overlap with the buffer trench BG, the gate insulating film layer 130 a and the gate electrode 140 are formed such that the height of the central portion is lower than that of the edge portion in a step-like manner.

[0109] Regarding the gate electrode 140, although not shown in detail, a metal material layer for forming the gate electrode 140 is deposited on the entire surface of the substrate 100, and then the metal material layer is patterned according to a design to form the gate electrode 140. However, the present invention is not limited thereto.

[0110] Next, as shown in FIG4D , the gate insulating film layer 130a can be patterned using the gate electrode 140 as a mask to form the gate insulating layer 130. In this case, dry etching can be used to pattern the gate insulating layer 130. However, the present invention is not limited thereto, and various methods widely known in the art can be used according to the level of skill of one of ordinary skill in the art.

[0111] Furthermore, during the process of forming the gate insulating layer 130, a portion of the active layer 120, such as the portion covered by the gate insulating film layer 130a and then exposed during etching, may be exposed to the plasma applied during the etching process. In this case, since a portion of the active layer 120 is made of an oxide semiconductor material, oxygen vacancies are generated and provide conductive properties. Therefore, the portion of the active layer 120 covered by the gate insulating film layer 130a and then exposed during etching becomes the first connecting portion 122a and the second connecting portion 122b.

[0112] Furthermore, when oxygen vacancies formed in the first connecting portion 122a and / or the second connecting portion 122b diffuse toward the channel portion 121, the other portion of the active layer 120 covered by the gate insulating layer 130 can become conductive. This other portion of the conductive active layer 120 becomes the first diffusion portion 123a and the second diffusion portion 123b.

[0113] Finally, as shown in FIG4E , an interlayer insulating layer 150 is formed to cover the buffer layer 110, the active layer 120, the gate insulating layer 130, and the gate electrode 140. In this case, a first contact hole CH1 and a second contact hole CH2 are provided in the interlayer insulating layer 150 to expose portions of the upper surface of the first connection portion 122 a and the upper surface of the second connection portion 122 b, respectively. When the source electrode 161 and the drain electrode 162 are formed on the interlayer insulating layer 150, the source electrode 161 is electrically connected to the first connection portion 122 a through the first contact hole CH1, and the drain electrode 162 is electrically connected to the second connection portion 122 b through the second contact hole CH2.

[0114] FIG5 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. FIG5 corresponds to FIG1 's cross-sectional view. The embodiment of FIG5 is identical to the embodiment of FIG2A except for the configuration of the gate insulating layer, and therefore, a repeated description thereof will be omitted.

[0115] As shown in FIG5 , a thin film transistor substrate according to another embodiment of the present invention includes: a substrate 100 ; a buffer layer 110 ; an active layer 120 ; a gate insulating layer 130 ; a gate electrode 140 ; an interlayer insulating layer 150 ; a source electrode 161 ; and a drain electrode 162 .

[0116] According to another embodiment of the present invention, the gate insulating layer 130 is formed to have a larger size than the gate electrode 140. Specifically, the upper surface of the gate insulating layer 130 may have a fourth width W GIb in the horizontal direction. The fourth width W GIb of the gate insulating layer 130 may be shorter than the first length L ACT of the active layer 120 and greater than the second width W GE of the gate electrode 140. Therefore, one end and the other end of the gate insulating layer 130 are disposed outside the gate electrode 140, and do not correspond to the one end and the other end of the gate electrode 140.

[0117] Since the gate insulating layer 130 is formed to be larger than the gate electrode 140, a portion of the upper surface of the gate insulating layer 130 may be exposed to the outside without being covered by the gate electrode 140.

[0118] The gate insulating layer 130 overlaps a portion of the upper surface US of the buffer trench BG and the buffer layer 110. The gate insulating layer 130 may be disposed on the buffer trench BG, with one end, such as the left end, and the other end, such as the right end, respectively disposed on the upper surface US of the buffer layer 110.

[0119] In this case, one end of the gate insulating layer 130 may be disposed between one end of the gate electrode 140 and one end of the active layer 120 , and the other end of the gate insulating layer 130 may be disposed between the other end of the gate electrode 140 and the other end of the active layer 120 .

[0120] According to another embodiment of the present invention, the first diffusion portion 123a and the second diffusion portion 123b may be disposed below the gate insulating layer 130. Specifically, the first diffusion portion 123a and the second diffusion portion 123b may be disposed below a portion of the gate insulating layer 130 not covered by the gate electrode 140.

[0121] Furthermore, the first diffusion portion 123a and the second diffusion portion 123b may be formed over a region extending from the upper surface US of the buffer layer 110 to the inclined surface IS of the buffer groove BG. Thus, one end, for example, the left end, of the first diffusion portion 123a and one end, for example, the right end, of the second diffusion portion 123b are disposed on the upper surface US of the buffer layer 110, and the other end, for example, the right end, of the first diffusion portion 123a and the other end, for example, the left end, of the second diffusion portion 123b are disposed on the inclined surface IS of the buffer groove BG.

[0122] By forming the channel 121 in this manner, the length increases from the first and second connection portions 122a and 122b toward the channel 121. Therefore, even if oxygen vacancies diffuse from the first or second connection portions 122a and 122b toward the channel 121, the length of the channel 121 can be maintained as designed. Therefore, since the length of the channel 121 can be maintained as designed, a thin film transistor substrate with a short channel can be realized without shifting the threshold voltage (Vth) in the negative direction.

[0123] Meanwhile, although not specifically shown in FIG. 5 , in another embodiment of the present invention, the gate insulating layer 130 is formed to be larger than the gate electrode 140, such that a portion of the upper surface of the gate insulating layer 130 is exposed to the outside and not covered by the gate electrode 140. Furthermore, as in the embodiment of FIG. 2B , oxygen vacancies diffused from the first and second connecting portions 122 a and 122 b reach the inclined surface IS of the buffer trench BG, so that the first and second diffusion portions 123 a and 123 b are formed to cover the entire inclined surface IS of the buffer trench BG, and the channel portion 121 can be provided only on the bottom surface BS of the buffer trench BG.

[0124] Figures 6A to 6F are cross-sectional views illustrating a process for manufacturing a thin-film transistor substrate according to another embodiment of the present invention. The process cross-sectional views of Figures 6A to 6F relate to the manufacturing process of the embodiment of Figure 5 , and like reference numerals are assigned to like elements, omitting any repetitive descriptions.

[0125] 6A , a substrate 100 is prepared, and a buffer layer 110 is formed on the substrate 100, and then a buffer groove BG is formed in the buffer layer 110. Meanwhile, since the manufacturing process of FIG. 6A is the same as that of FIG. 4A , a repeated description thereof will be omitted.

[0126] 6B, an active layer 120 is formed on the buffer layer 110. Meanwhile, since the manufacturing process of FIG6B is the same as that of FIG4B, a repeated description thereof will be omitted.

[0127] 6C , a gate insulating film layer 130 a is formed on the buffer layer 110 and the active layer 120 , and a gate electrode 140 is patterned on the gate insulating film layer 130 a . In this case, the gate insulating film layer 130 a may be formed on the entire surface of the substrate 100 .

[0128] A resist pattern 200 for patterning the gate electrode 140 is formed on the gate electrode 140. The gate electrode 140 is patterned using the resist pattern 200 as a mask.

[0129] The resist pattern 200 may be formed to have a width in the first direction wider than that of the gate electrode 140. In addition, the resist pattern 200 may be formed to have a width in the first direction wider than that of the buffer groove BG.

[0130] Since the gate insulating film layer 130 a and the gate electrode 140 are formed to overlap with the buffer trench BG, the gate insulating film layer 130 a and the gate electrode 140 are formed such that the height of the central portion is lower than that of the edge portion in a step-like manner.

[0131] Next, as shown in FIG6D , the gate insulating film layer 130a can be patterned using the resist pattern 200 as a mask to form the gate insulating layer 130. In this case, dry etching can be used to pattern the gate insulating layer 130. However, the present invention is not limited thereto, and various methods widely known in the art can be used according to the level of skill of one of ordinary skill in the art to which the present invention pertains.

[0132] According to another embodiment of the present invention, since the gate insulating layer 130 is formed using the resist pattern 200 as a mask, the gate insulating layer 130 can be formed to have a greater width than the gate electrode 140. Therefore, one end and the other end of the gate insulating layer 130 are disposed outside the gate electrode 140 and formed on the upper surface US of the buffer layer 110.

[0133] During the formation of the gate insulating layer 130, a portion of the active layer 120, such as the portion covered by the gate insulating film layer 130a and exposed during etching, may be exposed to the plasma applied during the etching process. In this case, since a portion of the active layer 120 is made of an oxide semiconductor material, oxygen vacancies are generated and provide conductive properties. Therefore, the portion of the active layer 120 covered by the gate insulating film layer 130a and exposed during etching becomes the first connecting portion 122a and the second connecting portion 122b.

[0134] Furthermore, when oxygen vacancies formed in the first connecting portion 122a and / or the second connecting portion 122b diffuse toward the channel portion 121, the other portion of the active layer 120 covered by the gate insulating layer 130 can become conductive. This other portion of the conductive active layer 120 becomes the first diffusion portion 123a and the second diffusion portion 123b.

[0135] According to another embodiment of the present invention, since the gate insulating layer 130 is disposed on the upper surface US of the buffer layer 110, the first diffusion portion 123a and the second diffusion portion 123b can also be disposed on the upper surface US of the buffer layer 110. This formation method increases the distance between the first connecting portion 122a or the second connecting portion 122b and the channel portion 121, thereby ensuring that the length of the channel portion 121 remains as designed.

[0136] Next, as shown in FIG. 6E , the resist pattern 200 may be removed through a stripping process.

[0137] 6F, an interlayer insulating layer 150, a source electrode 161, and a drain electrode 162 are formed. Since the manufacturing process of FIG. 6F is the same as that of FIG. 4E, a repeated description thereof will be omitted.

[0138] FIG. 7 is a cross-sectional view of a display device including a thin film transistor substrate according to an embodiment of the present invention.

[0139] As shown in FIG7 , a display device according to another embodiment of the present invention may include: a substrate 100; a buffer layer 110; an active layer 120; a gate insulating layer 130; a gate electrode 140; an interlayer insulating layer 150; a source electrode 161; a drain electrode 162; a planarization layer 170; a first electrode 300; a bank layer 310; a light-emitting layer 320; and a second electrode 330.

[0140] Since the substrate 100, the buffer layer 110, the active layer 120, the gate insulating layer 130, the gate electrode 140, the interlayer insulating layer 150, the source electrode 161, and the drain electrode 162 are the same as those described in the above embodiments, only the different configurations are described below.

[0141] A planarization layer 170 is provided on the source electrode 161 and the drain electrode 162. A third contact hole CH3 is provided in the planarization layer 170, and the drain electrode 162 is exposed by the third contact hole CH3. However, in some cases, the source electrode 161 may be exposed by the third contact hole CH3.

[0142] The first electrode 300 is formed on the planarization layer 170 and is connected to the source electrode 161 or the drain electrode 162 through the third contact hole CH3. The first electrode 300 may function as an anode.

[0143] The bank layer 310 may be provided to cover the edge of the first electrode 300 to define a light emitting region. Thus, the upper surface area of the first electrode 300 that is not covered by the bank layer 310 and is exposed becomes a light emitting region.

[0144] The light-emitting layer 320 may be disposed on the first electrode 300. The light-emitting layer 320 may include red, green, and blue light-emitting layers patterned for each pixel, or may be formed from a white light-emitting layer connected from all pixels. When the light-emitting layer 320 is formed from a white light-emitting layer, the light-emitting layer 320 may include, for example, a first stack including a blue light-emitting layer, a second stack including a yellow-green light-emitting layer, and a charge generation layer disposed between the first and second stacks, but is not limited thereto.

[0145] The second electrode 330 may be disposed on the light emitting layer 320. The second electrode 330 may function as a cathode.

[0146] Although not shown, an encapsulation layer for preventing moisture or oxygen from penetrating may be additionally formed on the second electrode 330 .

[0147] FIG. 8 is a schematic diagram of a display device according to an embodiment of the present invention.

[0148] As shown in FIG. 8 , a display device according to an embodiment of the present invention may include: a display panel 410 ; a gate driver 420 ; a data driver 430 ; and a controller 440 .

[0149] The display panel 410 includes gate lines GL and data lines DL, and pixels P are arranged at corresponding intersections of the gate lines GL and the data lines DL. Images are displayed by driving the pixels P. The gate lines GL, the data lines DL, and the pixels P can be arranged on the substrate 100.

[0150] Controller 440 controls gate driver 420 and data driver 430. Controller 440 outputs a gate control signal GCS for controlling gate driver 420 and a data control signal DCS for controlling data driver 430 using a signal supplied from an external system (not shown). Controller 440 also samples input video data from the external system, reshapes the sampled input video data, and then supplies the reshaped digital video data RGB to data driver 430.

[0151] The gate control signal GCS includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), a start signal (Vst), and a gate clock (GCLK). Furthermore, the control signal for controlling the shift register may be included in the gate control signal GCS.

[0152] The data control signal DCS includes: a source start pulse (SSP); a source shift clock signal (SSC); a source output enable signal (SOE); and a polarity control signal (POL).

[0153] The data driver 430 supplies data voltages to the data lines DL of the display panel 410. Specifically, the data driver 430 converts the video data RGB input from the controller 440 into analog data voltages and supplies the data voltages to the data lines DL.

[0154] The gate driver 420 can be mounted on the display panel 410. As described above, the structure in which the gate driver 420 is directly mounted on the display panel 410 is called a gate-in-panel (GIP) structure. Specifically, in the GIP structure, the gate driver 420 can be disposed on the substrate 100.

[0155] The gate driver 420 may include a shift register 450 .

[0156] The shift register 450 sequentially supplies gate pulses to the gate lines GL during a frame period using an enable signal and a gate clock transmitted from the controller 440. Herein, a frame refers to a period in which the display panel 410 outputs one image. The gate pulses have a turn-on voltage capable of turning on the switching devices (thin-film transistors) provided in the pixels P.

[0157] In addition, during the remaining period of a frame, during which no gate pulse is supplied, the shift register 450 supplies a gate-off signal capable of turning off the switching device to the gate line GL. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as the scan signal GS.

[0158] FIG. 9 is a circuit diagram of a pixel included in a display device according to an embodiment of the present invention.

[0159] As shown in FIG9 , the display device according to the embodiment of the present invention may include: a first thin film transistor T1; a second thin film transistor T2; and a capacitor Cst.

[0160] The first thin film transistor T1 is a driving thin film transistor, and the second thin film transistor T2 is a switching thin film transistor. At least one of the first thin film transistor T1 and the second thin film transistor T2 can be formed by any of the above-mentioned thin film transistors.

[0161] The first thin film transistor T1 is switched according to the data voltage Vdata supplied from the second thin film transistor T2, generates a data current from the driving voltage Vdd supplied from the power line PL, and supplies the data current to the organic light emitting diode OLED.

[0162] The second thin film transistor T2 is switched according to the gate signal GS supplied to the gate line GL, and supplies the data voltage Vdata supplied from the data line DL to the first thin film transistor T1.

[0163] According to an embodiment of the present invention, the thin film transistor substrate according to the above-described embodiment may be used as a thin film transistor substrate including any one of the first thin film transistor T1 and the second thin film transistor T2.

[0164] The capacitor Cst is used to maintain the data voltage Vdata supplied to the first thin film transistor T1 in one frame, and is disposed between the gate electrode and the source electrode of the first thin film transistor T1.

[0165] The organic light emitting diode OLED emits predetermined light according to the data current supplied from the first thin film transistor T1.

[0166] Therefore, the present invention can have the following advantages.

[0167] According to an embodiment of the present invention, both ends of the gate electrode overlap with the inclined surface of the buffer groove provided in the buffer layer, and the channel portion of the active layer is provided inside the buffer groove. That is, the channel portion is formed to have a short length, thereby improving the on-current characteristics of the thin film transistor substrate according to the embodiment of the present invention.

[0168] Furthermore, according to an embodiment of the present invention, by providing an active layer on the inclined surface of the buffer groove, the length of the channel portion during the conductive process is not too short, and thus the threshold voltage (Vth) of the thin film transistor substrate according to the embodiment of the present invention is not shifted in the negative (-) direction.

[0169] It is obvious to those skilled in the art that various substitutions, modifications, and variations can be made within the scope of the present invention without departing from the spirit or scope of the present invention. Therefore, the scope of the present invention includes the appended claims, and all changes or modifications derived from the meaning, scope, and equivalents of the claims should be construed as being included within the scope of the present invention.

[0170] This application claims priority to Korean Patent Application No. 10-2023-0191622, filed on December 26, 2023, the entire contents of which are incorporated herein by reference.

[0171] 100:Substrate 110: buffer layer 120: Active layer 121: Channel part 122a: first connecting portion 122b: Second connecting portion 123a: first diffusion part 123b: Second diffusion part 130: Gate insulation layer 130a: gate insulating film layer 140: Gate electrode 150: Interlayer insulation layer 161: Source electrode 162: Drain electrode 170: planarization layer 200: resist pattern 300: first electrode 310: embankment layer 320: Luminous layer 330: second electrode 410: Display panel 420: Gate driver 430:Data Drive 440:Controller 450: Shift register BG: Buffer Tank BS: bottom surface CH1: first contact hole CH2: second contact hole CH3: third contact hole Cst: capacitor DCS: Data Control Signal DL: Data Line GCS: Gate Control Signal GL: Gate Line GS: Scan signal, gate signal H1: First Height H2: Second height H3: The third height IS: Inclined surface L ACT: first length OLED: Organic Light-Emitting Diode P: Pixel PL: Power cord RGB: digital video data T1: First Thin Film Transistor T2: Second thin film transistor US: Upper surface Vdata: data voltage Vdd: driving voltage W BG: first width W GE: Second width W GIa: Third width W GIb: fourth width θ 1: first angle θ 2: Second angle a,b:point

Claims

1. A thin-film transistor substrate, comprising: One substrate; A buffer layer having a buffer groove disposed on the substrate, wherein the buffer groove includes an inclined surface; An active layer is disposed on the buffer layer; and a gate electrode is disposed on the active layer, wherein the active layer is disposed in a stepped manner on the buffer groove, wherein one end of the gate electrode overlaps with the inclined surface of the buffer groove, and wherein one end of a channel portion of the active layer is disposed on the inclined surface or at the boundary between the inclined surface and a bottom surface of the buffer groove.

2. The thin-film transistor substrate as claimed in claim 1, wherein, One end of the gate electrode overlaps with a portion of the active layer disposed on the inclined surface of the buffer groove.

3. The thin-film transistor substrate as claimed in claim 1, further comprising: A gate insulating layer is disposed between the active layer and the gate electrode, wherein the gate insulating layer overlaps with the buffer groove, and one end of the gate insulating layer corresponds to one end of the gate electrode.

4. The thin-film transistor substrate as claimed in claim 1, further comprising: A gate insulating layer is disposed between the active layer and the gate electrode, wherein the gate insulating layer overlaps with the buffer groove, and one end of the gate insulating layer is disposed between one end of the active layer and one end of the gate electrode.

5. The thin-film transistor substrate as claimed in claim 4, wherein, The gate insulating layer has a first width, the gate electrode has a second width, the active layer has a first length, and the first width of the gate insulating layer is greater than the second width of the gate electrode and less than the first length of the active layer.

6. The thin-film transistor substrate as claimed in claim 1, wherein, The active layer includes: the channel portion; a connecting portion disposed on one side of the channel portion; and a diffusion portion disposed between the channel portion and the connecting portion; and the channel portion includes: a first region in contact with the bottom surface of the buffer groove; and a second region in contact with the inclined surface of the buffer groove.

7. The thin-film transistor substrate as claimed in claim 6, wherein, One end of the second region of the channel portion is disposed in the inclined surface.

8. The thin-film transistor substrate as claimed in claim 6, wherein, One end of the second region of the channel portion corresponds to one end of the gate electrode.

9. The thin-film transistor substrate as claimed in claim 6, wherein, One end of the diffusion section is disposed on the inclined surface of the buffer groove.

10. The thin-film transistor substrate as claimed in claim 9, wherein, The other end of the diffusion portion corresponds to that end of the gate electrode.

11. The thin-film transistor substrate as claimed in claim 9, wherein, The other end of the diffusion portion is disposed between one end of the gate electrode and one end of the active layer.

12. The thin-film transistor substrate as claimed in claim 1, wherein, The active layer includes: the channel portion; a connecting portion disposed on one side of the channel portion; and a diffusion portion disposed between the channel portion and the connecting portion; wherein one end of the channel portion is disposed on the bottom surface of the buffer groove, and one end of the diffusion portion is disposed on the inclined surface of the buffer groove, and the one end of the channel portion and the one end of the diffusion portion are in contact with each other at the boundary between the bottom surface of the buffer groove and the inclined surface of the buffer groove.

13. The thin-film transistor substrate as claimed in claim 1, wherein, The buffer groove further includes a bottom surface connected to the inclined surface, and the angle formed between the bottom surface and the inclined surface is equal to or greater than 30 degrees and equal to or less than 45 degrees.

14. The thin-film transistor substrate as claimed in claim 1, wherein, The buffer groove further includes a bottom surface connected to the inclined surface, and the depth of the bottom surface of the buffer groove is equal to or greater than 1.41 μm and equal to or less than 2 μm.

15. A thin-film transistor substrate, comprising: One substrate; A buffer layer having a buffer groove disposed on the substrate; An active layer is set on this buffer layer; A gate electrode is disposed on the active layer. The buffer groove includes a bottom surface and an inclined surface connected to the bottom surface. The active layer includes: a channel portion; a connecting portion disposed on one side of the channel portion; and a diffusion portion disposed between the channel portion and the connecting portion. The channel portion overlaps with the bottom surface and the inclined surface, and one end of the channel portion is disposed on the inclined surface of the buffer groove.

16. The thin-film transistor substrate as claimed in claim 15, wherein, The width of the bottom surface of the buffer groove is less than the width of the gate electrode, and the width of the entire bottom surface and the inclined surface of the buffer groove is greater than the width of the gate electrode.

17. The thin-film transistor substrate as claimed in claim 15, further comprising: A gate insulating layer is disposed between the active layer and the gate electrode, wherein the entire area of ​​the diffusion portion overlaps with the gate insulating layer.

18. The thin-film transistor substrate as claimed in claim 15, wherein, A portion of the diffusion section does not overlap with the gate electrode.

19. The thin-film transistor substrate as claimed in claim 15, wherein, One end of the channel corresponds to one end of the gate electrode.

20. A display device comprising a thin-film transistor substrate, comprising: One substrate; A buffer layer is disposed on the substrate and has a buffer groove; An active layer is set on this buffer layer; A gate electrode is disposed on the active layer, wherein the active layer is disposed in a stepped manner on the buffer groove, wherein one end of the gate electrode overlaps with an inclined surface disposed in the buffer groove, and wherein one end of a channel portion of the active layer is disposed on the inclined surface or at the boundary between the inclined surface and a bottom surface of the buffer groove.

Images