Integrated circuit structure and computing device with backside metals

Abstract

An apparatus includes a circuit structure including a first side and an opposing second side, the first side including a device layer comprising a plurality of devices; a conductive contact coupled to one of the plurality of devices on the first side; and a conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method includes forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming a conductive contact from the first side to one of the source and the drain; and forming an interconnect on the second side of the device, wherein the interconnect is coupled to the contact.

Description

Technical Field

[0001] Semiconductor devices include devices having electrical connections from the back side of the device. Prior Art

[0002] For the past few decades, the shrinking of features in integrated circuits has been the driving force behind the continued growth of the semiconductor industry. Scaling to ever-smaller features has enabled an increase in the density of functional units within the limited area of ​​semiconductor chips. For example, shrinking transistor size has allowed for the integration of an increasing number of memory devices on a chip, resulting in the manufacture of products with increased capacity. However, the need for greater capacity is not without its challenges. The need to optimize the performance of each device has become increasingly prominent.

[0003] Future circuit devices, such as central processing unit devices, will desire both high performance devices and low capacitance low power devices integrated into a single die or chip. Simple diagram description

[0004] 100:Structure 110:Substrate 120: Any buffer layer 125: Gate 127: Gate dielectric layer 128: Opening 130: Fin 140A: Source 140B: Drain 145A: Open 145B: Open 150: spacer 155: Dielectric materials 155A: Dielectric material 155B: Dielectric material 155C: Dielectric material 160A:Interconnect 160B:Interconnect 165A:Contact 1651A: Prominent 1652A: Prominent 165B:Contact 170:Interconnect 175:Contact 180:Carrier 181: Dielectric materials 182A: Opening 182B: Opening 190A:Contact 190B:Contact 195A:Interconnect 200: Aggregate 210: Grain 2100B: Second side 215: Device Level 2150A: First side 2150B: Second side 220:Interconnect 230:Interconnect 240:Carrier substrate 250:Contact 290: Encapsulation 300:Procedure 400: Intermediary layer 402: first substrate 404: Second substrate 406:Ball Grid Array 408:Metal interconnect 410: Perforation 412:Through silicon via 414:Embedded device 500: computing device 502: integrated circuit die 504: Central Processing Unit 506: On-die memory 508: Communication chip 510: Volatile memory 512: Non-volatile memory 514: Graphics Processing Unit 516: Digital Signal Processor 520: Chipset 522: Antenna 524: Touch screen display 526:Touch screen controller 528:Battery 530: Compass 532: Motion sensor 534: Speaker 536: Camera 538: User input device 540: Mass Storage Device 542:Encryption Processor 544:GPS device

[0005] FIG. 1 shows a top perspective view of a portion of a three-dimensional transistor device on a substrate, such as a portion of an integrated circuit die or chip on a wafer. FIG. 2 shows the structure of FIG. 1 after forming contact openings or through-holes to the transistor device. 3A-3C show cross-sectional side views through the structure of FIG. 2 . FIG. 4 shows the structure of FIG. 2 after forming contacts and interconnects to the three-dimensional transistor device structure. 5A-5C show cross-sectional side views through the structure of FIG. 4 . Figures 6A-6C show the structure of Figures 5A-5C after inverting or flipping the structure and attaching the structure to a support. 7A-7C show the structure of FIGs. 6A-6C after removing or thinning the substrate to expose the second or back side of the device's fin. 8A-8C show the structure of FIG. 7A-7C after depositing dielectric material on the back side of the transistor device. 9A-9C show the structure of FIG. 8A-8C after patterning the dielectric material on the back side of the transistor device. 10A-10C show the structure of FIG. 9A-9C after filling the through-hole opening in the dielectric material with a conductive contact material and showing the interconnect connected to the source contact as part of the first backside interconnect or metal layer. FIG. 11 shows various examples of cross-sections through a source region of a three-dimensional transistor device having contacts extending from a first side of the device level to a second side of the device level on only one side of a fin in the source region. FIG. 12 shows a schematic cross-sectional side view of one embodiment of an assembly including an integrated circuit chip or die connected to a package substrate. FIG. 13 is a flow chart of a process for forming wraparound contacts to the source and drain of a three-dimensional transistor device connected to backside metallization. FIG. 14 illustrates an interposer implementing one or more embodiments. FIG15 shows an embodiment of a computing device. Summary of the Invention [Summary of the invention and implementation methods]

[0006] Embodiments described herein are directed to semiconductor devices including non-planar semiconductor devices (e.g., three-dimensional devices) having interconnects or wiring beneath or on the backside of the device. Such embodiments are achieved by using backside exposure and backside processing. The embodiments include an apparatus comprising: a circuit structure comprising a first side and an opposing second side, the first side comprising a device layer comprising a plurality of devices; a conductive contact coupled to one of the plurality of devices on the first side; and a conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. Embodiments for forming such a device are also described. Backside exposure processing allows for flexibility in the types of connections that can be made.

[0007] FIG. 1-10C describes a method or process for forming a three-dimensional or non-planar semiconductor device including electrical connections on a non-device side or backside of the structure. In one embodiment, the device is a three-dimensional metal oxide semiconductor field effect transistor (MOSFET) and is either an isolated device or one of a plurality of nested devices. As will be understood, for a typical integrated circuit, both N- and P-channel transistors can be fabricated on a single substrate to form a complementary metal oxide semiconductor (CMOS) integrated circuit. Furthermore, additional interconnects can be fabricated to facilitate integration of the device into the integrated circuit.

[0008] In the fabrication of non-planar transistors, such as multi-gate transistors and FinFETs, non-planar semiconductor bodies can be used to form transistors that are generally capable of being fully depleted with relatively small gate lengths (e.g., less than approximately 30 nm). These semiconductor bodies are typically fin-shaped and are therefore commonly referred to as transistor "fins." For example, in a tri-gate transistor, the transistor fin has a top surface and two opposing sidewalls formed on a bulk semiconductor substrate or a silicon-on-insulator substrate. A gate dielectric layer can be formed on the top or upper surface and sidewalls of the semiconductor body, and a gate electrode can be formed above the gate dielectric layer on the top or upper surface of the semiconductor body and adjacent to the gate dielectric layer on the sidewalls of the semiconductor body. Because the gate dielectric layer and the gate electrode are adjacent to three surfaces of the semiconductor body, three separate channels and gates are formed. Because three separate channels are formed, the semiconductor body can be fully depleted when the transistor is turned on. With a finFET transistor, the gate material and the electrode contact the sidewalls of the semiconductor body so that two separate channels are formed.

[0009] FIG1 shows a top perspective view of a portion of a semiconductor or semiconductor-on-insulator (SOI) substrate, such as a portion of an integrated circuit die or chip on a wafer. Specifically, FIG1 shows a structure 100 comprising a silicon or SOI substrate 110. Overlying substrate 110 is an optional buffer layer 120. In one embodiment, the buffer layer is a silicon germanium buffer layer introduced onto substrate 110 by a growth technique. Typically, buffer layer 120 has a thickness of several hundred nanometers (nm).

[0010] Disposed on the surface (as seen on the upper surface) of the substrate 110 and any buffer layer 120 in the embodiment shown in FIG. 1 is a portion of a transistor device, such as an N-type transistor device or a P-type transistor device. Common to both the N-type and P-type transistor devices in this embodiment is a body or fin 130 disposed on the surface of the buffer layer 120. In one embodiment, the fin 130 is formed from a semiconductor material, such as silicon, silicon germanium, or a Group III-V or Group IV-V semiconductor material. In one embodiment, the material of the fin 130 is formed using conventional processing techniques used to form three-dimensional integrated circuit devices. Typically, the semiconductor material is epitaxially grown on the substrate and then formed into the fin 130 (e.g., by a masking and etching process).

[0011] In one embodiment, fin 130 has a length dimension L that is greater than its height dimension H. A representative length range is approximately 10 nanometers (nm) to 1 millimeter (mm), and a representative height range is approximately 5 nm to 200 nm. Fin 130 also has a width W, typically approximately 4-10 nm. As shown, fin 130 is a three-dimensional body extending from or onto the surface of substrate 110 (or optionally from or onto buffer layer 120). As shown in FIG. 1 , this three-dimensional body is a rectangular body having opposing sides (first and second sides), as seen protruding from the surface of buffer layer 120. It is understood that in processing such bodies, a true rectangular form is not achievable with available tools, and other shapes may be produced. Representative shapes include, but are not limited to, trapezoidal (e.g., with a base wider than a top) and arched.

[0012] Disposed on the fin 130 in the embodiment of the structure of FIG. 1 is a gate stack. In one embodiment, the gate stack includes a gate dielectric layer, such as silicon dioxide or a dielectric material having a dielectric constant greater than silicon dioxide (a high-k dielectric material). Disposed on the gate dielectric layer, in one embodiment, is a gate 125, such as a metal. The gate stack may include spacers 150 of dielectric material on opposite sides thereof. Representative materials for spacers 150 are low-k materials such as silicon nitride (SiN) or silicon carbonitride (SiCN). FIG. 1 shows spacers 150 adjacent to the sidewalls of the gate stack and on the fin 130. Formed on or in the fin 130 on opposite sides of the gate stack are junction regions (source 140A and drain 140B).

[0013] In one embodiment, to form the three-dimensional transistor structure, a gate dielectric material is formed on the fin 130, such as by blanket deposition followed by blanket deposition of a sacrificial or dummy gate material. A masking material is introduced over the structure and patterned to protect the gate stack material (gate stack with sacrificial or dummy gate material) over the designated channel region. An etching process is then used to remove the gate stack material in undesired areas and pattern the gate stack over the designated channel region. Spacers 150 are then formed. One technique for forming spacers 150 is to deposit a film over the structure, protect the film in the desired areas, and then etch to pattern the film into the desired spacer dimensions.

[0014] After forming a gate stack comprising sacrificial or dummy gate material on fin 130 and spacers 150, junction regions (source and drain) are formed on or in fin 130. The source and drain are formed in fin 130 on opposite sides of the gate stack (sacrificial gate electrode on the gate dielectric layer). In the embodiment shown in FIG. 1 , source 140A and drain 140B are formed as a cladding layer on a portion of fin 130 by epitaxially growing source and drain material. Representative materials for source 140A and drain 140B include, but are not limited to, silicon, silicon germanium, or Group III-V or Group IV-V compound semiconductor materials. Source 140A and drain 140B can alternatively be formed by removing portions of the fin material and epitaxially growing source and drain material in designated junction regions where the fin material was removed.

[0015] After forming the source 140A and drain 140B, in one embodiment, the sacrificial or dummy gate is removed and replaced with a gate electrode material. In one embodiment, a dielectric material is deposited over the structure before removing the sacrificial or dummy gate stack. In one embodiment, the dielectric material is silicon dioxide or a low-k dielectric material, which is deposited as a blanket and then polished to expose the sacrificial or dummy gate 125. The sacrificial or dummy gate and gate dielectric layer are then removed, for example, by an etching process.

[0016] After removing the sacrificial or dummy gate and the gate dielectric layer, a gate stack is formed in the gate electrode region. The gate stack is introduced (e.g., deposited) onto the structure including the gate dielectric layer and the gate electrode. In one embodiment, the gate electrode 125 of the gate electrode stack is composed of a metal gate and the gate dielectric layer is composed of a material having a dielectric constant greater than that of silicon dioxide (a high-k material). For example, in one embodiment, the gate dielectric layer 127 (see FIG. 3C ) is composed of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In one embodiment, the gate electrode 125 is composed of a metal layer, such as, but not limited to, a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. After forming the gate stack, additional dielectric material such as silicon dioxide or a low-k dielectric material is deposited over the three-dimensional transistor device (e.g., over the ILD0) to seal or embed the device structure within the dielectric material. FIG1 shows dielectric material 155A sealing the three-dimensional transistor device (e.g., as the ILD0).

[0017] FIG. 2 shows the structure of FIG. 1 after forming openings or perforations through the dielectric material to expose source 140A and drain 140B. In one embodiment, opening 145A surrounding the source region and opening 145B surrounding the drain region are formed by a lithographic process, such as by masking an area of ​​the top surface of the dielectric material (as seen) to define the area for the openings and etching the openings or perforations through dielectric material 155A with an etchant selective to the dielectric material relative to the material of source 140A and drain 140B. As shown in FIG. 2 , in one embodiment, the etched area is large enough to form openings 145A and 145B in a manner that exposes the top surfaces of source 140A and drain 140B, as well as opposing side surfaces of the source and drain, respectively. The etch, in one embodiment, is an anisotropic etch that is performed to a depth exceeding the depth of the respective source and drain electrodes. Because the source 140A and drain 140B are formed as a capping layer on the top and sidewall surfaces of the fin 130 in this embodiment, the source and drain serve as masks as the etch proceeds through the dielectric material 155A beyond the source 140A and drain 140B to leave dielectric material directly adjacent to and on the opposing sidewalls of the fin 130 beneath the source 140A and drain 140B, respectively. In one embodiment, the etch proceeds through the dielectric material 155A to a depth approaching the base of the fin 130. In addition to the opening 145A in the source region and the opening 145B in the drain region, FIG. 2 shows a through-hole or opening 128 formed through the dielectric material 155A to the gate electrode 125. Opening 128 can be formed by a similar masking and etching process as openings 145A and 145B and, in this embodiment, exposes a portion of the top of the gate electrode 125.

[0018] Figures 3A-3C show cross-sectional side views through Figure 2. More specifically, Figure 3A shows a cross-sectional side view taken along line AA' of Figure 2, which is a cross-section through fin 130; Figure 3B shows a cross-sectional view taken along line BB', which is a cross-section through source 140A; and Figure 3C shows a cross-sectional view taken along line CC', which is a cross-section through gate electrode 125. The same orientation of the cross-sectional views (AC) will be presented throughout this description. Figure 3B shows an opening or through-hole 145A that exposes the top surface and opposite side surfaces of source 140A and extends to a depth close to the base of fin 130, while Figure 3C shows an opening for gate electrode 125.

[0019] FIG. 4 shows the structure of FIG. 1 after forming contacts and interconnects for the three-dimensional transistor device structure. In this embodiment, electrical connections are made with a first interconnect or metal layer to source 140A, drain 140B, and gate electrode 125. Typically, to form respective electrical contacts to source 140A, drain 140B, and gate electrode 125, a contact material, such as tungsten, is introduced (e.g., deposited) into openings 128, 145A, and 145B and the openings are filled to form contact 165A to source 140A, contact 165B to drain 140B, and contact 175 to gate electrode 125. The surface (top surface, as seen) of dielectric material 155 may then be seeded with a conductive seed material and then patterned with a masking material to define openings for interconnect paths with the respective openings exposing contacts 165A, 165B, and 175. Conductive material, such as copper, is then introduced by electroplating to form interconnect 160A connected to contact 165A to source 140A, interconnect 160B connected to contact 165B, and interconnect 170 connected to contact 175 to gate electrode 125. The masking material and unwanted seed material can then be removed. After forming the interconnect as the initial metal layer, a dielectric material, such as silicon dioxide or a low-k dielectric material, can be deposited over and around the interconnect as the ILD1 layer. Additional interconnect layers can then be formed according to conventional processes.

[0020] 5A-5C illustrate cross-sectional side views through the structure of FIG. 4 . Specifically, FIG. 5A illustrates a cross-sectional view through fin 130 along line AA'; FIG. 5B illustrates a cross-sectional view through drain 140B along line BB'; and FIG. 5C illustrates a cross-sectional side view through gate electrode 125 along line CC'. Referring to FIG. 5B , contact 165A is shown connected to the top surface of source 140A (as viewed) and having protrusions 1651A and 1652A that contact opposing sidewalls of source 140A and extend beyond source 140A toward the base of fin 130.

[0021] Figures 6A-6C show the structure of Figures 5A-5C after introducing (e.g., depositing) a dielectric material onto the interconnect on the device side of the structure, inverting or flipping the structure, and connecting it to a carrier. Figures 6A-6C respectively show cross-sections through the fin 130, drain 140B, and gate electrode 125, as described above with respect to Figures 3A-3C and 5A-5C. Referring to Figures 6A-6C, in this embodiment, a dielectric material 155B, such as silicon dioxide or a low-k dielectric material, is deposited as the ILD1 layer. The structure 100 is then flipped and connected to a carrier 180 on the device side (device side down). Carrier 180 is, for example, a semiconductor wafer. The structure 100 can be connected to the carrier 180 using an adhesive or other bonding technique between the dielectric material 155B and the carrier 180.

[0022] Figures 7A-7C show the structure of Figures 6A-6C after substrate 110 has been removed or thinned to expose the second side, or backside, of fin 130. In one embodiment, substrate 110 may be removed by a thinning process, such as mechanical grinding or an etching process. Figures 7A-7C show fin 130 exposed from the second side, or backside, of the structure. After exposing fin 130, the fin may optionally be recessed. Figures 7A-7C also show the structure after recessing fin 130. In one embodiment, to recess fin 130, an etching process may be utilized using an etchant that is selective for removing fin material relative to dielectric material 155A. Alternatively, a masking material may be patterned on the surface (exposed backside surface) of dielectric material 155 through openings that expose fin 130. Fin 130 material may be removed to recess fin 130, for example, by an etching process, and then the masking material may be removed.

[0023] Figures 8A-8C show the structure of Figures 7A-7C after depositing a dielectric material on the backside of fin 130. Figures 8A-8C show dielectric material 181, such as silicon dioxide or a low-k dielectric material, deposited by, for example, a blanket deposition process. Figures 9A-9C show the structure of Figures 8A-8C after patterning dielectric material 181 to form contact openings in the source and drain regions. Dielectric material 181 can be patterned, for example, by forming a masking material on the surface of dielectric material 181 with openings or perforations opposite, for example, source and drain regions on opposite sides of fin 130. Figure 9A shows opening 182A through dielectric material 181 on the backside of fin 130 corresponding to the source region (source 140A) of the fin, and opening 182B through dielectric material 181 corresponding to the drain region (drain 140B) of the fin. FIG. 9B shows that the opening (eg, opening 182A) has a diameter greater than the width of the fin 130 and exposes the distal ends of the protrusions 1651A and 1652A of the contact 165A.

[0024] Figures 10A-10C show the structure of Figures 9A-9C after filling the through-hole openings in dielectric material 181 with a conductive contact material, such as tungsten. Figure 10A shows contact 190A associated with source 140A and contact 190B associated with drain 140B. Figure 10B shows protrusions 1651A and 1652A contacting metal 190A, connected to contact 165A. Figure 10B shows connections to source 140A (via the contact material) from opposite sides of the structure (the first or device side and the back or second side, respectively). Interconnects to contacts 190A and 190B can now be formed, for example, using the techniques described above for the device-side interconnects (see Figures 4 and 5A-5C and accompanying text). 10A-10C show interconnect 195A connected to contact 190A and to source 140A, as part of a first backside interconnect or metal layer, for example. 10A-10C also show the structure after dielectric material 155C, such as silicon dioxide or a low-k dielectric material, is deposited over the interconnect or metal layer.

[0025] In the embodiment of the structure described above with reference to Figures 1-10C , backside metal contacts are shown encircling opposite sides of the fin in the source and drain regions, respectively. In another embodiment, metal contacts may be formed along only one side of the fin in the source and drain regions, respectively. Figure 11 shows various examples of cross-sections through the source region of a three-dimensional transistor device having contacts extending from a first side of the device layer to a second side of the device layer on only one side of the fin in the source region. The same element numbers are used as in Figure 10B . The process used to form the structure shown in Figure 11 would be similar to that shown in Figures 1-10C , with only one opening being formed, for example, by a lithographic process in the dielectric material, to expose the junction (source 140A) (see Figure 2 and accompanying text). Furthermore, the contact metal 190A can have a smaller width, as it would not necessarily extend across the width of the fin, for example.

[0026] FIG. 12 shows a schematic cross-sectional side view of one embodiment of an assembly including an integrated circuit chip or die connected to a packaging substrate. Assembly 200 includes a die 210, which can be formed as described above with reference to FIGs. 1-11. Die 210 includes a device layer or tier 215 comprising a plurality of devices (e.g., transistor devices). Device tier 215 includes a first side 2150A representing the first side of the tier and a second side or backside 2150B opposite first side 2150A. The transistor devices include, for example, one or more power transistors and logic circuits. Connected to device tier 215 of die 210 on the first side is interconnect 220, which, in one embodiment, includes, but is not limited to, a plurality of conductive metal lines connecting from first side 2150A to the devices in device tier 215. Referring to FIGs. 1-11, interconnects 160A, 160B, and 170 (see FIG. 4) represent the first layer of interconnects 220 above device tier 215. Disposed above interconnect 220 is a carrier substrate 240, similar to carrier substrate 180 described above with reference to Figures 6A-11. The device connected to die 210 through the second side 2100B of the die is, in this embodiment, interconnect 230, which may be, for example, a power interconnect (VDD, VDD gate, and VSS), a logic interconnect, or both. Interconnect 230 on the second or back side 2100B includes one or more layers or rows of metallization. Referring to Figures 10A-11, interconnect 195A represents the first layer of interconnect 230 below device level 215. Figure 12 also shows that one of this layer of metallization is connected to contacts (e.g., C4 bumps) 250, which are operable to connect die 210 to packaging substrate 290. Figure 12 further illustrates the VDD and VSS connections to die 210 through packaging substrate 290.

[0027] FIG13 is a flow chart of a process for forming wraparound contacts for the source and drain of a three-dimensional transistor device connected to backside metallization. Referring to FIG11 , process 300 begins by forming a three-dimensional transistor device on a base substrate, the device including a fin extending from the base substrate and a source and drain formed in or on the fin (block 310). From a first side, or device side, of the structure, deep through-holes or openings are formed around the source and drain regions of the device (block 315). The through-holes or openings are filled with contact material to form wraparound contacts, and device-side metallization is established (block 320). After establishing the metallization, the device is flipped and bonded device-side down to a carrier (block 325). The base substrate is then removed to expose the fin (block 330), and the fin is optionally recessed (block 335). Dielectric material is then introduced through the through-holes or openings surrounding the wraparound contacts and patterned on the backside of the device (block 340). The backside through-holes or openings are filled with contact material to create backside contacts to the wraparound contacts (block 345). Backside metallization is then optionally built up (block 350).

[0028] The above embodiments are described with reference to three-dimensional transistor devices (eg, multi-gate devices). In another embodiment, the description presented herein can be applied to other devices, such as planar devices or nanowire devices.

[0029] FIG14 illustrates an interposer 400, including one or more embodiments. Interposer 400 is an interposer substrate used to bridge a first substrate 402 to a second substrate 404. First substrate 402 may be, for example, an integrated circuit die. Second substrate 404 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of interposer 400 is to expand connections to a wider pitch or reroute connections to different connections. For example, interposer 400 may couple an integrated circuit die to a ball grid array (BGA) 406, which may then be coupled to the second substrate 404. In some embodiments, the first and second substrates 402 / 404 are attached to opposite sides of interposer 400. In other embodiments, the first and second substrates 402 / 404 are attached to the same side of interposer 400. In still other embodiments, three or more substrates are interconnected via interposer 400.

[0030] The interposer 400 may be formed from epoxy, glass-reinforced epoxy, ceramic materials, or polymer materials such as polyimide. In other embodiments, the interposer may be formed from alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials.

[0031] The interposer 400 may include metal interconnects 408 and vias 410, including but not limited to through-silicon vias (TSVs) 412. The interposer 400 may further include embedded devices 414, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 400.

[0032] According to one embodiment, the apparatus or process disclosed herein may be used in the manufacture of the interposer 400 .

[0033] FIG15 illustrates a computing device 500 according to one embodiment. The computing device 500 may include numerous components. In one embodiment, these components are attached to one or more motherboards. In alternative embodiments, these components are fabricated onto a single system-on-chip (SoC) die rather than a motherboard. The components in the computing device 500 include, but are not limited to, an integrated circuit die 502 and at least one communication chip 508. In some embodiments, the communication chip 508 is fabricated as part of the integrated circuit die 502. The integrated circuit die 502 may include a CPU 504 and on-die memory 506, typically used as cache memory, which may be provided by technologies such as embedded DRAM (eDRAM) or spin transfer torque memory (STTM or STTM-RAM).

[0034] The computing device 500 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within the SoC die. These other components include, but are not limited to, volatile memory 510 (e.g., DRAM), non-volatile memory 512 (e.g., ROM or flash memory), a graphics processing unit 514 (GPU), a digital signal processor 516, an encryption processor 542 (a dedicated processor that executes encryption algorithms in hardware), a chipset 520, an antenna 522, a display or touchscreen display 524, a touchscreen controller 526, a battery 528 or other power source, a power amplifier (not shown), a global positioning system (GPS) device 544, a compass 530, a motion co-processor or sensor 532 (which may include an accelerometer, a gyroscope, and a compass), a speaker 534, a camera 536, a user input device 538 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 540 (such as a hard drive, a compact disc (CD), a digital multimedia disc (DVD), etc.).

[0035] The communication chip 508 enables wireless communication for transferring data to and from the computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through non-solid media using modulated electromagnetic radiation. The term does not imply that the devices do not contain any wires, although in some embodiments they may not. The communication chip 508 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols designed with 3G, 4G, 5G, and beyond. The computing device 500 may include multiple communication chips 508. For example, the first communication chip 508 may be dedicated to short-range wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 508 may be dedicated to long-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0036] The processor 504 of the computing device 500 includes one or more devices, such as transistors or metal interconnects, formed with wraparound contacts and optional backside metallization according to the embodiments described above. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory.

[0037] The communication chip 508 may also include one or more devices, such as transistors or metal interconnects, formed by wraparound contacts and optional backside metallization according to the embodiments described above.

[0038] In other embodiments, another component housed within the computing device 500 may include one or more devices, such as transistors or metal interconnects, formed by wraparound contacts and optional backside metallization according to the embodiments described above.

[0039] In various embodiments, the computing device 500 may be a laptop, a mini-notebook, a notebook computer, an ultra-laptop, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In other embodiments, the computing device 500 may be any other electronic device that processes data. Examples

[0040] Example 1 is an apparatus comprising: a circuit structure including a first side and an opposing second side, the first side including a device layer including a plurality of devices; a conductive contact coupled to one of the plurality of devices on the first side; and a conductive interconnect disposed on the second side of the structure and coupled to the conductive contact.

[0041] In Example 2, the device of the apparatus of Example 1 includes a body comprising a first sidewall and an opposite second sidewall, wherein the conductive contact is disposed on each of the first sidewall and the second sidewall.

[0042] In Example 3, the contact of the apparatus of Example 2 includes a first portion disposed on the first side wall of the device and a second portion disposed on the second side wall, wherein each of the first portion and the second portion extends individually from the device in the direction of the second side of the structure.

[0043] In Example 4, the contact of the apparatus of any one of Examples 1-3 includes a device-side contact, the apparatus further including a back-side contact coupled to each of the first portion and the second portion of the device-side contact, and wherein the interconnect is connected to the back-side contact.

[0044] In Example 5, the interconnect of the apparatus of any one of Examples 1-4 is a first interconnect, and the apparatus further includes a second conductive interconnect coupled to the device from the first side of the structure.

[0045] In Example 5, one of the multiple devices of the apparatus of any one of Examples 1-5 includes a non-planar transistor device including a source and a drain, the source and the drain including a body including a first sidewall and a relative second sidewall, wherein the contact is coupled to one of the source and the drain and such coupling is arranged on each of the first sidewall and the second sidewall of the body.

[0046] Example 7 is a method comprising: forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming a conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

[0047] In Example 8, one of the source and the drain of the method of Example 7 includes a body including a first sidewall and an opposite second sidewall, wherein forming the contact includes setting such a contact on each of the first sidewall and the second sidewall of the body.

[0048] In Example 9, the method of any one of Examples 7-8, wherein the first sidewall and the second sidewall are separated by a thickness dimension of the body and forming the joint includes bridging the thickness dimension.

[0049] In Example 10, the contact of the method of any one of Examples 7-9 includes a device-side contact, and the method further includes forming a back-side contact coupled to each of the first portion and the second portion of the device-side contact.

[0050] In Example 11, the interconnect of the method of any one of Examples 7-10 includes coupling the interconnect to the backside contact.

[0051] In Example 12, the method of any one of Examples 7-11, wherein forming the transistor device includes forming a fin on a substrate, a source and a drain separated by the channel in the fin, and a gate electrode on the channel of the fin; and after forming the transistor device, embedding opposite side portions of the fin in a dielectric material, and before forming the contact, the method includes forming an opening in the dielectric material adjacent to the opposite side portions of the fin, and forming the contact includes forming the contact in the opening.

[0052] Example 13 is a method comprising: forming a non-planar transistor device including a fin on a substrate and a source and a drain separated by a channel in the fin and a gate electrode on the channel of the fin defining a first side of the device; forming a conductive contact to the transistor device from the first side; bonding the substrate to a carrier with the transistor device facing the carrier; removing the substrate to expose a second side of the device opposite the first side; and forming an interconnect coupled to the contact from the second side of the device.

[0053] In Example 14, forming the contact to the transistor device of the method of Example 13 includes forming the contact to one of the source and the drain.

[0054] In Example 15, forming the contact of the method of Example 14 includes disposing the contact adjacent to each of the first sidewall and the second sidewall of the fin.

[0055] In Example 16, the method of any one of Examples 13-15, wherein the first sidewall and the second sidewall are separated by a thickness dimension of the fin and forming the contact includes bridging the thickness dimension.

[0056] In Example 17, the contact of the method of any one of Examples 13-16 includes a device-side contact having a first portion adjacent to the first sidewall of the fin and a second portion adjacent to the second sidewall of the fin, and the method further includes forming a back-side contact coupled to each of the first portion and the second portion of the device-side contact.

[0057] In Example 18, the method of any one of Examples 13-17, wherein forming the interconnect includes coupling the interconnect to the backside contact.

[0058] In Example 19, after forming the transistor device, the method of any one of Examples 13-18 includes embedding opposite side portions of the fin in a dielectric material, and before forming the contact, the method includes forming an opening in the dielectric material adjacent to the opposite side portions of the fin and forming the contact includes forming the contact in the opening.

[0059] In Example 20, the method of any of Examples 13-19 includes forming an interconnect to the transistor device from the first side of the device.

[0060] The above description of the illustrated embodiments, including those described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific embodiments of the invention and examples for use therein are described herein for illustrative purposes, various equivalent modifications are possible within the scope, as those skilled in the relevant art will recognize.

[0061] Such modifications may be made in accordance with the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and claims. Rather, the scope of the present invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

1. An integrated circuit structure comprising: a semiconductor body including a source or drain region; a first contact structure above the top of the source or drain region, along a first sidewall of the source or drain region, and along a second sidewall of the source or drain region; a second contact structure below and in contact with the first contact structure, the second contact structure extending below the bottom of the source or drain region of the semiconductor body, wherein the second contact structure and the first contact structure together completely surround the top, the first sidewall, the second sidewall, and the bottom of the source or drain region of the semiconductor body from a cross-sectional view; a dielectric layer between the first contact structure and a portion of the first sidewall of the source or drain region of the semiconductor body, and between the first contact structure and a portion of the second sidewall of the source or drain region of the semiconductor body; and epitaxial material partially along the first and second sidewalls of the source or drain region of the semiconductor body.

2. The integrated circuit structure of claim 1, wherein the dielectric layer is further between the bottom of the source or drain region and the second contact structure.

3. The integrated circuit structure of claim 1, wherein the first contact structure is spaced apart from the top of the semiconductor body.

4. The integrated circuit structure of claim 3, wherein the epitaxial material is further located between the top of the semiconductor body and the first contact structure.

5. The integrated circuit structure of claim 1, wherein the semiconductor body is a fin.

6. The integrated circuit structure of claim 1 further includes: a gate structure laterally adjacent to the first contact structure.

7. The integrated circuit structure of claim 6, wherein the gate structure is on top of the semiconductor body.

8. The integrated circuit structure of claim 7 further includes: a second source or drain region on one side of the gate structure relative to the source or drain region.

9. The integrated circuit structure of claim 6 further includes: a second source or drain region on one side of the gate structure relative to the source or drain region.

10. A computing device comprising: a board; and an assembly coupled to the board, the assembly including an integrated circuit structure comprising: a semiconductor body including a source or drain region; a first contact structure above the top of the source or drain region, along a first sidewall of the source or drain region, and along a second sidewall of the source or drain region; a second contact structure below and in contact with the first contact structure, the second contact structure extending below the bottom of the source or drain region of the semiconductor body, wherein the second contact structure and the first contact structure together completely surround the top, the first sidewall, the second sidewall, and the bottom of the source or drain region of the semiconductor body from a cross-sectional view; A dielectric layer between the first contact structure and a portion of the first sidewall of the source or drain region of the semiconductor body, and between the first contact structure and a portion of the second sidewall of the source or drain region of the semiconductor body; and epitaxial material partially along the first and second sidewalls of the source or drain region of the semiconductor body.

11. The computing device of claim 10 further includes: memory coupled to the board.

12. The computing device of claim 10 further includes: a communication chip coupled to the board.

13. The computing device of claim 10 further includes: a battery coupled to the board.

14. The computing device of claim 10 further includes: a camera coupled to the board.

15. The computing device of claim 10 further includes: a speaker coupled to the board.

16. The computing device of claim 10 further includes: a GPS coupled to the board.

17. The computing device of claim 10 further includes: a motion sensor coupled to the board.

18. The computing device of claim 10, wherein the component is a packaged integrated circuit die.

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