Power conversion device and electrical power conversion circuit

Abstract

An electronic circuit is disclosed. The electronic circuit includes: a transistor having a gate terminal, a source terminal, and a drain terminal; and a gate driver circuit including: a pull-down transistor coupled to the gate terminal; and an input terminal configured to receive an input signal and generate a corresponding output signal at an output terminal coupled to the gate terminal, wherein the gate driver circuit is configured to store energy extracted from the input signal and use the stored energy to change a conductivity state of the pull-down transistor. In one embodiment, the transistor comprises gallium nitride (GaN). In another embodiment, the pull-down transistor comprises GaN.

Description

Technical Field

[0001] The described embodiments generally relate to power conversion devices, and more particularly, embodiments of the present invention relate to integrated power conversion devices utilizing gallium nitride (GaN) circuits. Prior Art

[0002] Electronic devices such as computers, servers, and televisions use one or more power conversion circuits to convert one form of electrical energy to another. Some power conversion circuits use a circuit topology called a half-bridge converter to convert a high DC voltage to a lower DC voltage. Because many electronic devices are sensitive to the size and efficiency of power conversion circuits, new power converters can provide relatively higher efficiency and smaller size for these new electronic devices. Summary of the Invention

[0003] In some embodiments, an electronic circuit is disclosed. The electronic circuit includes: a transistor having a gate terminal, a source terminal, and a drain terminal; and a gate driver circuit including: a pull-down transistor coupled to the gate terminal; and an input terminal configured to receive an input signal and generate a corresponding output signal at an output terminal coupled to the gate terminal, wherein the gate driver circuit is configured to store energy extracted from the input signal and use the stored energy to change a conductive state of the pull-down transistor.

[0004] In some embodiments, the transistor comprises gallium nitride (GaN).

[0005] In some embodiments, the pull-down transistor comprises GaN.

[0006] In some embodiments, the gate driver circuit comprises silicon.

[0007] In some embodiments, the gate driver circuit uses the stored energy to transition the pull-down transistor from an on state to an off state.

[0008] In some embodiments, the gate driver circuit and the transistor are disposed in a single electronic package.

[0009] In some embodiments, the unitary electronic package includes a power input contact, a power output contact, and an input signal contact.

[0010] In some embodiments, the input signal is a pulse width modulation (PWM) signal comprising a series of on and off commands.

[0011] In some embodiments, the gate driver circuit is configured to change the conductive state of the pull-down transistor from an off state to an on state during an off command of the PWM signal.

[0012] In some embodiments, the electronic circuit includes a unitary electronic package having a first external contact, a second external contact, and a third external contact.

[0013] In some embodiments, the transistor and the gate driver circuit are housed in a TO-247 package.

[0014] In some embodiments, the unitary electronic package is a TO-no-lead (TOLL) package.

[0015] In some embodiments, the gate driver circuit includes an energy harvesting circuit coupled to the gate terminal, wherein the energy harvesting circuit is configured to store energy harvested from the input signal and use the stored energy to operate the gate driver circuit when the PWM signal is in an off command.

[0016] In some embodiments, a circuit is disclosed. The circuit includes: a first transistor having a first gate terminal, a first source terminal, and a first drain terminal; and A current control circuit is configured to receive an input signal and, in response, transmit a corresponding output signal to the first gate terminal, wherein the current control circuit includes: a first path having a first impedance element coupled in series with a first unidirectional current conductor, the first unidirectional current conductor being oriented to allow current to flow to the first gate terminal; and a second path having a second impedance element coupled in series with a second unidirectional current conductor, the second unidirectional current conductor being oriented to allow current to flow from the first gate terminal.

[0017] In some embodiments, the circuit further includes a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, wherein the second drain terminal is coupled to the first gate terminal, wherein the second transistor is configured to clamp a voltage at the first gate terminal to a preset voltage value.

[0018] In some embodiments, the circuit further includes a third transistor having a third gate terminal, a third source terminal, and a third drain terminal, wherein the third source terminal is coupled to the first gate terminal, and the third drain terminal is coupled to the current control circuit.

[0019] In some embodiments, a circuit is disclosed. The circuit includes: a first transistor having a first gate terminal, a first source terminal, and a first drain terminal; a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, the second drain terminal being coupled to the first gate terminal; a first control circuit coupled to the second gate terminal and configured to change a conductive state of the second transistor from an off state to an on state in response to a voltage at the first gate terminal being lower than a first threshold voltage; A third transistor has a third gate terminal, a third source terminal, and a third drain terminal; and a second control circuit coupled to the third gate terminal and configured to change a conductive state of the third transistor from an off state to an on state in response to the voltage at the first gate terminal being higher than a second threshold value.

[0020] In some embodiments, the second transistor is configured to clamp the voltage at the first gate terminal to a first predetermined value.

[0021] In some embodiments, the third transistor is configured to clamp the voltage at the first gate terminal to a second predetermined value.

[0022] In some embodiments, the circuit further includes a current control circuit configured to receive an input signal and, in response, transmit a corresponding output signal to the first gate terminal, wherein the current control circuit includes: a first path having a first impedance element coupled in series with a first unidirectional current conductor, the first unidirectional current conductor being oriented to allow current to flow to the first gate terminal; and a second path having a second impedance element coupled in series with a second unidirectional current conductor, the second unidirectional current conductor being oriented to allow current to flow from the first gate terminal. Simple diagram description

[0023] FIG1 illustrates an integrated GaN power device and a silicon device in the same package according to one embodiment of the present disclosure;

[0024] FIG2 illustrates a schematic diagram of a gate driver circuit having energy harvesting, integrated pull-up and pull-down transistors, and voltage clamping features according to one embodiment of the present disclosure;

[0025] FIG3 shows a graph of the quiescent current at the input terminal of the gate driver circuit shown in FIG2 and a graph of the gate voltage of the GaN power transistor shown in FIG2;

[0026] FIG4A illustrates a schematic diagram of a circuit having a saturation current protection feature according to one embodiment of the present disclosure;

[0027] FIG4B illustrates a graph showing the voltage of each node within the circuit of FIG4A over time;

[0028] Figure 5 illustrates a schematic diagram of a circuit having a saturation current protection feature according to one embodiment of the present disclosure;

[0029] Figure 6 illustrates a schematic diagram of a circuit having a saturation current protection feature according to one embodiment of the present disclosure;

[0030] FIG7A illustrates a schematic diagram of a circuit having a turn-on dv / dt control feature according to one embodiment of the present disclosure;

[0031] FIG7B illustrates a graph showing the rate of change of the drain-to-source voltage over time during the on-period of a GaN power transistor;

[0032] FIG7C shows the rate of change of the drain-to-source voltage over time according to the resistance value of the external resistor in the circuit of FIG7A;

[0033] FIG8 illustrates a schematic diagram of a gate driver having a dV / dt control circuit and a gate clamp feature according to one embodiment of the present disclosure;

[0034] Figure 9 illustrates a schematic diagram of a circuit having a disconnect dI / dt control feature according to one embodiment of the present disclosure;

[0035] FIG10 illustrates a schematic diagram of a gate driver circuit with hysteresis according to one embodiment of the present disclosure;

[0036] Figure 11 illustrates the voltages at various nodes within the gate circuit of Figure 10;

[0037] Figure 12 illustrates a schematic diagram of a voltage regulator according to one embodiment of the present disclosure;

[0038] FIG13 illustrates an integrated GaN power device in a TO-247 package according to one embodiment of the present disclosure; and

[0039] Figure 14A illustrates an integrated GaN power device according to one embodiment of the present disclosure. Figure 14B illustrates an integrated GaN power device in a four-terminal TO-247 package according to one embodiment of the present disclosure. Figure 14C illustrates an integrated GaN power device in a TO-no-leads (TOLL) package according to one embodiment of the present disclosure. Implementation Method

[0040] Cross-reference to related applications

[0041] This application claims priority to U.S. Provisional Patent Application No. 63 / 202,973, “Integrated Power Device with Energy Harvesting Gate Driver,” filed on July 1, 2021, which is hereby incorporated by reference in its entirety for all purposes.

[0042] The circuits and related techniques disclosed herein generally relate to gallium nitride (GaN) power conversion devices. More specifically, the devices, circuits, and related techniques disclosed herein relate to GaN integrated circuits in which a gate driver integrated circuit (IC) can be used to extract energy from an input pulse-width modulated (PWM) signal to power the gate driver IC, thereby eliminating the need for a power supply for the gate driver IC. In some embodiments, the gate driver IC can be integrated with a GaN power transistor in a package to form an integrated GaN power device, which can be a pin-for-pin compatible replacement for a discrete silicon power MOSFET and its driver circuitry. In various embodiments, the gate driver IC can store energy extracted from the PWM signal and continue to operate and drive the GaN power transistor even when the PWM signal is in a low state, as further explained in FIG1 .

[0043] In some embodiments, the gate driver IC may include various protection circuits to keep the GaN power transistor within its safe operating region, as summarized here and described in more detail below. More specifically, in some embodiments, the IC may include a pull-down transistor for pulling down the gate voltage of the GaN power transistor. The pull-down transistor may be integrated into the IC or integrated on the same die as the GaN transistor. The IC may drive the gate of the pull-down transistor, as further explained in Figure 2.

[0044] In various embodiments, the IC may include a pull-up transistor. The pull-up transistor enables the PWM signal to drive the gate of the GaN power transistor to a high state. In some embodiments, the IC may include a clamping circuit to protect the GaN power transistor and the IC's internal circuitry. The clamping circuit can enable a relatively high operating voltage for PWM, such as 10 to 30 V, while allowing the gate of the GaN transistor to remain within its safe operating region, such as below 6.0 V. As will be understood by those of ordinary skill in the art having the benefit of this disclosure, the operating voltage can be set to any suitable value. The operation of the pull-up transistor and clamping circuit is described in more detail in FIG. 2 .

[0045] In some embodiments, the IC may include a saturation current protection circuit. The saturation current protection circuit senses the voltage at the drain of the GaN power transistor and triggers the protection circuit to prevent the GaN transistor from entering or remaining in its saturation region. As those skilled in the art will appreciate, a GaN transistor may operate normally in its linear operating region. However, if the GaN transistor enters its saturation operating region, the drain current may increase as the corresponding drain voltage increases, which is undesirable in power conversion applications. In some embodiments, the saturation protection circuit may use a depletion mode (D-mode) GaN transistor to sense the drain voltage of the GaN transistor and shut down the GaN transistor when saturation is detected. The saturation protection circuit is discussed in detail in Figures 4 through 6.

[0046] In various embodiments, the IC may include a turn-on dV / dt control circuit by utilizing an external resistor in series with the PWM signal. The dV / dt control circuit is discussed in detail in Figures 7A to 7C and Figure 8. In various embodiments, the IC may include a turn-off dV / dt control circuit by utilizing the package bond wire inductance. By using the turn-off dV / dt control circuit, the gate of the GaN transistor can be maintained in its safe operating region, where the stress voltage on the gate of the GaN transistor can be kept to a relatively minimum. The turn-off dV / dt control circuit is described in more detail in Figure 9.

[0047] In some embodiments, the IC may include a gate drive voltage generation circuit with hysteresis to control the gate voltage of the GaN transistor to reduce power consumption and increase operating speed. The gate drive voltage generation circuit with hysteresis is described in more detail in Figures 10 and 11.

[0048] As will be understood by those of ordinary skill in the art having the benefit of this disclosure, any portion and / or any combination of the features described herein may be integrated into an IC, may be integrated into a GaN transistor, or such features may be partially integrated into an IC and partially integrated into a GaN transistor. In various embodiments, integrated GaN power devices can operate at relatively higher frequencies than the silicon power MOSFETs they replace. Furthermore, the ICs may be formed from silicon, silicon carbide, GaN, or any other suitable semiconductor material. In various embodiments, the integrated power devices may be used in high current and / or high voltage power conversion applications such as, but not limited to, AC-to-DC converters, as well as applications such as solar power conversion, automotive, and battery charging.

[0049] Several illustrative embodiments will now be described with reference to the accompanying drawings, which form a part of these embodiments. The following description provides examples only and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the following description of the embodiments will provide those skilled in the art with an instructive description for implementing one or more embodiments. It should be understood that various changes may be made to the function and configuration of the components without departing from the spirit and scope of the present disclosure. In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent that the various embodiments can be practiced without these specific details. The drawings and description are not intended to be limiting. The words "example" or "exemplary" are used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" or "example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Integrated GaN power package

[0050] FIG1 illustrates an integrated GaN power device 100 according to one embodiment of the present disclosure. As shown in FIG1 , the integrated GaN power device 100 may include a GaN power transistor 114 and a gate driver integrated circuit (IC) 112 within a semiconductor package 110. By integrating the GaN power transistor 114 and the gate driver IC into a single semiconductor package 110, most package parasitics are eliminated, allowing the integrated GaN power device 100 to be used in high-current and high-power applications. The integrated GaN power device 100 may include a top plate 118. The drain of the GaN power transistor 114 may be coupled to the top plate 118 via a plurality of bond wires 120, wherein the top plate 118 is coupled to a plurality of pins 102 to form the drain of the integrated GaN power device 100. The integrated GaN power device 100 may further include a die pad 116.

[0051] The source of the GaN power transistor 114 can be coupled to a die pad 116 via a plurality of bond wires 122. The die pad 116 can be coupled to a plurality of pins 104 to form the source of the integrated GaN power device 100. The ground terminal of the IC 112 can be coupled to the pin 106 via a bond wire 126 to form a low-parasitic (Kelvin) source connection for the IC. The input terminal of the IC can be connected to an input pin 108 via a bond wire 124 to form an input for a drive signal to the integrated GaN power device 100. In some embodiments, the input pin 108 can be coupled to a pulse-width modulated (PWM) signal to drive the IC 112. The IC can be coupled to the GaN power transistor 114 via bond wires 128. In many embodiments, the IC can be coupled to the GaN power transistor 114 via a clip (e.g., a copper clip). In some embodiments, the IC can be coupled to the GaN power transistor 114 via a bump. In various embodiments, IC 112 can drive GaN power transistor 114 and can include various features for driving the GaN power transistor and maintaining it within its safe operating region. In the illustrated embodiment, integrated GaN power device 100 can be used to replace silicon power MOSFETs in various applications. Those skilled in the art will appreciate that gate driver IC 112 can be used to drive GaN high electron mobility transistors (HEMTs) and other power transistors, such as (but not limited to) isolated gate bipolar transistors (IGBTs) and silicon MOSFETs.

[0052] In various embodiments, gate driver IC 112 can operate without a power supply (V dd ). This feature eliminates the need for an additional V dd pin in package 110 and allows pin-to-pin compatibility of integrated GaN power device 100, making it interchangeable with discrete silicon power MOSFETs or other packaged semiconductor devices. In some embodiments, energy for IC 112 operation can be drawn from the input PWM signal when the PWM signal is high and the IC can store energy in its internal components. When the PWM signal is low, the IC can continue to function using this stored energy. Furthermore, even when the energy stored in the IC has dissipated, the IC can continue to actively pull down the gate of GaN power transistor 114 to prevent involuntary turn-on due to dv / dt events.

[0053] In the illustrated embodiment, input pin 108 of package 110 can draw a relatively small amount of current, similar to the gate of the discrete silicon power MOSFET it replaces. Similar to the gate of a silicon power MOSFET, the PWM signal can have two logic states: low and high. For example, in the low state, the PWM signal can be zero volts, while its high state value can be 10 to 30 V. IC 112 can drive the gate of GaN power transistor 114 at an appropriate voltage value, such as between 0 and 6 V, even if the PWM signal varies between 0 and 10-30 V. In this way, even if the PWM signal is higher than the safe operating voltage of the GaN transistor, IC 112 can maintain the gate of GaN power transistor 114 within its safe operating region and prevent damage to the GaN transistor's gate. As will be appreciated by those of ordinary skill in the art having the benefit of this disclosure, the value used for the operating voltage can be set to any suitable value suitable for a particular application.

[0054] In some embodiments, during power-up, IC 112 can be turned on and perform power-up functions to maintain GaN power transistor 114 within its safe operating region during power-up. IC 112 can drive the gate of GaN power transistor 114 while monitoring the status of GaN power transistor 114 by sensing various characteristics of the GaN transistor, such as, but not limited to, overcurrent, overvoltage, and overtemperature. To eliminate the need for a power pin, such as a Vdd pin, IC 112 can draw power from the input PWM signal and store energy in its internal capacitor 228. IC 112 can use this stored energy to function even when the PWM signal is low and GaN transistor 114 is off. During the PWM low state, IC 112 can continue to function and can actively hold the gate of GaN power transistor 114 low to prevent the gate from turning on due to a dv / dt event, which could damage the GaN transistor.

[0055] In some embodiments, the integrated GaN power device 100 can have little or no leakage current into its input terminals during standby mode. In various embodiments, the IC 112 and GaN power transistor 114 can be integrated using a semiconductor package such as, but not limited to, a dual flat no-lead (DFN) or TO-247 to form a pin-for-pin replacement for discrete silicon power MOSFETs, silicon carbide (SiC) FETs, or other power devices without requiring modifications to the printed circuit board (PCB) layout. As those skilled in the art will appreciate, in some applications, it can be difficult to use GaN power transistors in transistor outline (TO-type) power packages, such as three-terminal or four-terminal TO-247 or TOLL packages, because the relatively high parasitic inductance of the package can cause excessive ringing and oscillation in high-current applications. In the illustrated embodiment, by integrating the gate driver IC 112 along with the GaN power transistor 114 into a TO package, the GaN power transistor 114 can be used in TO-type packages such as, but not limited to, three-terminal TO-247, four-terminal TO-247, and TOLL packages. The various features of the gate driver IC (such as, but not limited to, dv / dt control and dI / dt control) enable the use of the GaN power transistor in the TO package. Furthermore, the integrated GaN power device 100 can be used as a pin-for-pin replacement for discrete power MOSFETs, silicon carbide (SiC) FETs, or other power devices without requiring modifications to the printed circuit board (PCB) layout. As will be appreciated by those of ordinary skill in the art having the benefit of this disclosure, other suitable semiconductor packages can be used for integrating the GaN power transistor 114 with the gate driver IC 112, depending on the specific application. Energy harvesting circuit, integrated pull-up and pull-down transistor circuit, and voltage clamp circuit

[0056] FIG2 illustrates a schematic diagram of a circuit 200 with energy harvesting, integrated pull-up and pull-down transistors, and voltage clamping features according to an embodiment of the present disclosure. In some embodiments, circuit 200 may be used in integrated GaN power device 100. As shown in FIG2 , circuit 200 may include a GaN power transistor 202 having a gate 208, a drain 204, and a source 206. In some embodiments, GaN power transistor 202 is similar to GaN power transistor 114. Drain 204 may be coupled to pin 277, and source 206 may be coupled to pin 279. In some embodiments, drain 204 and source 206 may not be coupled to pins; instead, they may be coupled to other circuit nodes monolithically integrated with GaN power transistor 202. Circuit 200 may further include an input terminal pin 257 configured to receive a signal 278. In some embodiments, signal 278 may be a pulse-width modulated (PWM) signal. Input terminal pin 257 can be connected to a pull-up transistor 210 having a collector 254, a base 216, and an emitter 214. In various embodiments, pull-up transistor 210 can be a bipolar NPN transistor, while in other embodiments, it can be a P-MOSFET. In some embodiments, pull-up transistor 210 can be an N-MOSFET. In various embodiments, pull-up transistor 210 can be formed in a compound semiconductor substrate or any other suitable substrate. In some embodiments, pull-up transistor 210 can be integrated into gate driver IC 112. In various embodiments, pull-up transistor 210 can be a GaN-based transistor and integrated into the same die as GaN power transistor 202.

[0057] Emitter electrode 214 can be connected to gate 208 of GaN power transistor 202. In some embodiments, GaN power transistor 202, along with circuit 200, can be configured for use in a low-side configuration. In various embodiments, GaN power transistor 202, along with circuit 200, can be configured for use in a half-bridge configuration. In some embodiments, GaN power transistor 202, along with circuit 200, can be configured for use in a high-side configuration. When signal 278 is high, pull-up transistor 210 can turn on, thereby allowing current to flow into gate 208, thereby charging the capacitance of gate 208. This can cause GaN power transistor 202 to turn on. In various embodiments, pull-up transistor 210 can be a bipolar NPN transistor, while in other embodiments, pull-up transistor 210 can be a P-MOSFET. In some embodiments, transistor 210 can be an N-MOSFET. In various embodiments, transistor 210 can be formed in a compound semiconductor substrate or any other suitable substrate. The pull-up transistor 210 may be integrated within the gate driver IC 112 , or it may be a GaN-based transistor and integrated into the same die as the GaN power transistor 202 .

[0058] Signal 278 can provide power to the base 216 of pull-up transistor 210 via resistor 252. When signal 278 goes high, pull-up transistor 210 can charge gate 208 by providing current, pulling the voltage of gate 208 of GaN power transistor 202 high. Circuit 200 can include substrate terminal 248 that can be connected to substrate 280 of IC 112 die. In various embodiments, substrate 280 can be connected to ground. Circuit 200 can include pull-down transistor 230 having a gate terminal 236, a source terminal 234, and a drain terminal 232. Drain terminal 232 of pull-down transistor 230 can be connected to gate 208 of GaN power transistor 202, and source terminal 234 of pull-down transistor 230 can be connected to source 206 of GaN power transistor 202 and substrate 248. The pull-down transistor is configured to pull down the voltage of the gate 208 of the GaN power transistor 202 when the PWM signal is low. The gate terminal 236 of the pull-down transistor 230 can be connected to the logic circuit 289 and driven by the signal Vptg2 generated by the logic circuit 289. When the PWM signal goes low, the signal Vptg2 can go high, which turns on the pull-down transistor 230, causing the drain terminal 232 to go low and pull down the gate 208 of the GaN power transistor 202. The pull-down transistor 230 can be formed on the same die as the gate driver circuit, or it can be GaN-based and formed and integrated on the same die as the GaN power transistor 202. The pull-down transistor 230 can be a relatively large transistor to provide a robust pull-down of the gate 208 of the GaN power transistor 202.

[0059] In some embodiments, circuit 200 may include a clamping circuit 295. Clamping circuit 295 can clamp the gate 208 of GaN power transistor 202, keeping the gate within its safe operating region. Clamping circuit 295 allows the PWM signal to have a wide range of operating voltages, such as 10 to 30 V, while keeping the gate 208 of GaN power transistor 202 within its safe operating region, such as below 6.0 V. As will be appreciated by those of ordinary skill in the art having the benefit of this disclosure, the operating voltage can be set to any suitable value. Clamping circuit 295 may include a Zener diode 250 and two diode-connected NPN transistors 262 and 272.

[0060] Emitter 266 of transistor 262 can be connected to Zener diode 250. Collector 268 can be connected to the base of transistor 262 and emitter 264 of transistor 272. Transistor 272 can have collector 274 connected to its base 276, where collector 274 is also connected to base 216 of pull-up transistor 210. Zener diode 250 can generate a voltage (Vz) at its cathode 233. The value of Vz can be, for example, 5.2 V. Diode-connected transistors 262 and 272 can each generate a voltage drop of, for example, 0.7 V across their collector-to-source terminals. Therefore, the voltage at base 216 of transistor 210 can be Vz + 2Vbe. Those skilled in the art will appreciate that the order in which these three devices are connected can be different, resulting in a voltage of Vz + 2Vbe. The voltage at the gate 208 of the GaN power transistor 202 can be lower than the voltage at the base 216 by one V be. Therefore, the voltage at the gate 208 of the GaN power transistor 202 can be V z + V be. This voltage can have a value of, for example, 5.9 V, thereby clamping the gate 208 to a voltage below 6.0 V, thereby preventing the gate 208 from exceeding its safe operating voltage.

[0061] Circuit 200 may include a clamping circuit 295. Clamping circuit 295 can clamp the gate 208 of GaN power transistor 202, keeping gate 208 within its safe operating region. Clamping circuit 295 allows the PWM signal to have a wide range of operating voltages, such as 10 to 30 V, while keeping gate 208 of GaN power transistor 202 within its safe operating region, such as below 6.0 V. As will be appreciated by those of ordinary skill in the art having the benefit of this disclosure, the PWM operating voltage can be set to any suitable value. Clamping circuit 295 may include a Zener diode 250 and two diode-connected NPN transistors 262 and 272. Transistor 262 has an emitter 266 connectable to Zener diode 250 and a collector 268 connectable to the base of transistor 262 and the emitter 264 of transistor 272.

[0062] Transistor 272 may have a collector 274 that may be connected to the base 216 of pull-up transistor 210. The Zener diode may generate a voltage Vz at its cathode 233, which may be, for example, 5.2 V. Diode-connected transistors 262 and 272 may each generate a voltage drop of, for example, 0.7 V across their collector-to-source terminals. Therefore, the voltage at base 216 may be Vz + 2Vbe. The voltage at gate 208 of GaN power transistor 202 may be lower than the voltage at base 216 of transistor 210 by one Vbe. Therefore, the voltage at gate 208 of GaN power transistor 202 may be Vz + Vbe. This voltage may be, for example, 5.9 V. Therefore, clamp circuit 295 may clamp gate 208 to a voltage below 5.9 V and prevent gate 208 from exceeding its safe operating voltage. As will be understood by those of ordinary skill in the art having the benefit of this disclosure, the output voltage of the clamping circuit can be set to any suitable value. In some embodiments, transistor 262 can be a diode-connected NPN bipolar transistor. Diode-connected transistor 262 can mitigate temperature variations in V z . In various embodiments, transistor 272 can mitigate manufacturing process and temperature variations in the characteristics of transistor 210 . Those skilled in the art will appreciate that the connection order of transistors 262 and 272 can be different while mitigating both temperature and manufacturing process variations.

[0063] Circuit 200 may include energy capture and storage circuit 229. Storage circuit 229 may include transistor 218 connected in series with energy storage capacitor 228. In some embodiments, transistor 218 may be configured as a diode-connected transistor. In various embodiments, a diode may be used in place of transistor 218. Transistor 218 may have a collector terminal 220, an emitter terminal 222, and a base terminal 226. Collector terminal 220 may be connected to base terminal 226. Emitter terminal 222 may be connected to capacitor 228. When the PWM signal goes high, transistor 210 may turn on, thereby turning on transistor 218. Capacitor 228 may charge and store energy from the PWM signal. Therefore, a voltage equal to Vz can be generated at the emitter terminal 222 of transistor 218 because, when the voltage at the emitter terminal 214 of transistor 210 is Vz + Vbe, the voltage at the emitter terminal 222 of transistor 218 can be lower than the voltage at the emitter terminal 214 of transistor 210 by one Vbe. The voltage at the emitter terminal 222 of transistor 218 can be, for example, 5.2 V. This voltage can be used to power circuits within IC 112 even when the PWM signal goes low. In some embodiments, the present disclosure includes methods for generating a voltage at the gate of GaN power transistor 202 and storing the regulated voltage in a storage element, such as capacitor 228.

[0064] Circuit 200 may include transistor 240, which can be used to disconnect the charging of gate 208 of GaN power transistor 202 when PWM goes low. The drain 242 of transistor 240 can be connected to the base 216 of pull-up transistor 210, and the source 244 of transistor 240 can be connected to substrate 248. Gate 246 of transistor 240 can be configured to receive signal Vptg2. When signal 278 goes low, signal Vptg2246 can go high and turn on both transistors 230 and 240. Pull-down transistor 230 can pull down the gate of GaN power transistor 202, and transistor 240 can pull down the base 216 of pull-up transistor 210, turning it off. By disconnecting pull-up transistor 210, charging of gate 208 of GaN power transistor 202 can be stopped.

[0065] Figure 3 shows a graph 300 of quiescent current at input terminal pin 257 of circuit 200 in Figure 2 and a graph 310 showing the gate voltage of GaN power transistor 202 in circuit 200 in Figure 2 . Graph 308 showing quiescent current and graph 310 showing gate voltage are plotted as a function of PWM voltage 306 . As shown in Figure 3 , as PWM voltage 306 increases, the gate voltage of the GaN power transistor increases linearly as the gate charges. The gate voltage increases to approximately 6.0 V and is clamped at this voltage due to clamping circuit 295 clamping gate 208 of GaN power transistor 202. Furthermore, graph 308 shows that no quiescent current flows into the PWM terminal before the gate is clamped. No current flows before clamping circuit 295 is activated. When gate 208 is clamped, the quiescent current increases linearly. In some embodiments, this feature makes integrated GaN power device 100 compatible with discrete power applications because its standby gate current is zero. Saturation current protection circuit

[0066] FIG4A illustrates a schematic diagram of a circuit 400A having a saturation current protection feature according to one embodiment of the present disclosure. As shown in FIG4A , circuit 400A may include a GaN power transistor 440 having a gate 412, a drain 422, and a source 428. Drain 422 may be connected to a load. Circuit 400A can be used to detect when GaN power transistor 440 enters its saturation operating region. When the transistor's drain current increases while its drain-to-source voltage remains relatively constant, it may be operating in the saturation region.

[0067] As shown in FIG4A , the source 428 of GaN power transistor 440 can be connected to ground node 430. Circuit 400A can monitor the drain voltage of the GaN power transistor using GaN transistor 442. In some embodiments, transistor 442 can be a depletion-mode GaN transistor. Although GaN power transistor 440 can be a high-voltage transistor with an operating voltage of, for example, 400 V, circuit 400A can be a low-voltage circuit for monitoring GaN power transistor 440 and preventing it from operating in the saturation region. In the illustrated embodiment, the voltage at the drain 422 of GaN power transistor 440 can be monitored, and when the voltage exceeds a threshold value (e.g., 8 V), circuit 400A can disconnect GaN power transistor 440 to protect it from damage, thereby preventing damage to the power converter. More specifically, in some embodiments, circuit 400A may utilize a depletion mode (D-mode) GaN transistor 442, wherein the drain 422 of GaN power transistor 440 is connected to the drain 421 of transistor 442. The gate 426 of transistor 442 may be connected to ground node 430. The source 424 of transistor 442 may be connected to a resistor divider 419.

[0068] Circuit 400A may include a comparator 406 and a logic circuit 408. In some embodiments, the resistor divider 419, the comparator 406, and the logic circuit 408 may be formed using low-voltage silicon technology. In various embodiments, the resistor divider 419, the comparator 406, and the logic circuit 408 may be formed using GaN technology and integrated on the same die as the GaN power transistor 440. In some embodiments, the resistor divider 419 may include two resistors 402 and 404 connected in series. The output 416 of the resistor divider may be connected to a first input 499 of the comparator 406, while the second input 414 of the comparator 406 may be connected to a reference voltage (Vref) 415. The reference voltage 415 may have a value of 2.5 V, for example. The output 418 of the comparator may be connected to the logic circuit 408. The voltage at the drain 422 of the GaN power transistor 440 may vary, for example, from 0 to 400 V. The source 424 of the D-mode GaN transistor 442 may be clamped at its clamping voltage, eg, 15V.

[0069] The source 424 of the D-mode GaN transistor 442 follows the drain voltage of the GaN power transistor 440 until it reaches its pinch-off voltage. Thereafter, the source 424 of the D-mode GaN transistor 442 is clamped at the pinch-off voltage, for example, 15 V. In some embodiments, the source voltage of the D-mode GaN transistor 442 follows its drain voltage until the source voltage reaches the transistor's pinch-off voltage. At this point, the source voltage is clamped to the pinch-off voltage and remains constant at that voltage. In this way, the D-mode GaN transistor 442 can connect its source 424 to the resistor divider 419, while the drain 421 of the D-mode GaN transistor 442 can operate at a high voltage, for example, up to 400 V. When the voltage at the source 424 of the D-mode GaN transistor 442 exceeds a predetermined value, for example, 8 V, it may cause the GaN power transistor 440 to shut down.

[0070] Resistor divider 419 can provide output 416, which tracks its input at node 423, but at a lower voltage level. The output voltage of resistor divider 419 can be compared to reference voltage 415, for example, 2.5 V, which is the threshold of comparator 406. When the voltage at comparator input 499 exceeds Vref, comparator 406 can switch, and its output 418 voltage can change from a low state to a high state. Output 418 of comparator 406 can be connected to logic circuit 408. When comparator output 418 changes to a high state, output 420 of logic circuit 408 opens the gate of GaN power transistor 440, turning off GaN power transistor 440. Those skilled in the art will appreciate that transistor 442 can be a D-mode GaN transistor, which can be integrated on the same die as GaN power transistor 440. In some embodiments, transistor 442 can be an enhancement-mode GaN transistor. In various embodiments, transistor 442 may be a silicon transistor.

[0071] Figure 4B illustrates graph 400B, which shows the voltages of nodes within circuit 400A over time. Graph 422a shows the drain voltage of GaN power transistor 440, which can vary from 0 volts to 400 V. Graph 424a shows the source voltage of D-mode GaN transistor 442 (graph 422a) tracking the drain voltage of GaN power transistor 440. As shown in graph 424a, the source voltage varies from 0 V to 15 V, with the source of D-mode GaN transistor 442 clamped at 15 V. Graph 416a shows the voltage at output 416 of resistor divider 419. Graph 415a shows the value of Vref at 2.5 V. Finally, graph 418a shows the output voltage of comparator 406, where the comparator switches from a low state to a high state when 416a (the output of the resistor divider) crosses 415a (Vref). As will be appreciated by those skilled in the art, the voltages shown in graph 400B are merely examples and other embodiments may have different operating characteristics.

[0072] FIG5 illustrates a schematic diagram of a circuit 500 including a saturation current protection feature according to one embodiment of the present disclosure. Circuit 500 is similar to circuit 400A, except that the gate 526 of transistor 542 is connected to the gate 512 of GaN power transistor 540. This enables the use of a low-pinchback (e.g., 5 V) D-mode GaN transistor to sense the drain voltage at drain 522 of GaN power transistor 540. To monitor the drain voltage of GaN power transistor 540 using a D-mode GaN transistor 542 with a low pinchback voltage, dynamic biasing of gate 526 can be used to allow proper operation of the D-mode GaN transistor. Dynamic biasing can increase the gate voltage of D-mode GaN transistor 542 and provide a variable, rather than fixed, gate-to-source voltage for the D-mode GaN transistor.

[0073] Circuit 500 can be used to detect when GaN power transistor 440 enters its saturation operating region. Source 528 of GaN power transistor 540 can be connected to ground node 530. Circuit 500 can monitor the drain voltage of the GaN power transistor using transistor 542. Although GaN power transistor 540 can be a high-voltage transistor with an operating voltage of, for example, 400 V, circuit 500 can utilize a low-voltage circuit to monitor the GaN power transistor and prevent it from operating in its saturation region. In some embodiments, this can be accomplished by monitoring the voltage at drain 522 of GaN power transistor 540. When the voltage exceeds a threshold value, such as 8 V, circuit 500 can disconnect the GaN power transistor to protect it from damage. More specifically, circuit 500 can use a D-mode GaN transistor 542, where drain 522 of GaN power transistor 540 is connected to drain 521 of transistor 542. Circuit 500 may include a comparator 506 and a logic circuit 508 .

[0074] In some embodiments, the resistor divider 519, comparator 506, and logic circuit 508 can be formed using low-voltage silicon technology. In various embodiments, the resistor divider 519, comparator 506, and logic circuit 508 can be formed using GaN technology and integrated on the same die as the GaN power transistor 540. The resistor divider 519 can include two resistors 502 and 504 connected in series. The output 516 of the resistor divider can be connected to a first input of the comparator 506, while the second input 514 of the comparator 506 can be connected to a reference voltage (Vref) 515. The reference voltage 515 can have a value of, for example, 2.5 V. The output 518 of the comparator can be connected to the logic circuit 508. The voltage at the drain 522 of the GaN power transistor 540 can vary, for example, from 0 to 400 V. The source 524 of the transistor 542 is clamped at its clamping voltage, for example, 15 V. The source 524 of transistor 542 follows the drain voltage of GaN power transistor 540 until it reaches its pinch-off voltage. Thereafter, the source 524 of transistor 542 is clamped at the pinch-off voltage, for example, 15 V. Transistor 542 has the characteristic that its source voltage follows its drain voltage until the source voltage reaches the transistor's pinch-off voltage. At this point, the source voltage is clamped to the pinch-off voltage and remains constant at that voltage. In this way, D-mode GaN transistor 542 can connect its source 524 to a low-voltage resistor divider 519, while the drain 521 of D-mode GaN transistor 542 can operate at a high voltage, for example, up to 400 V. When the voltage at the source 524 of transistor 542 exceeds a predetermined value, for example, 8 V, it may cause the GaN power transistor 540 to shut down.

[0075] Resistor divider 519 can provide an output at 516 that tracks its input at node 523, but at a lower voltage level. The output voltage of resistor divider 519 can be compared to reference voltage 515, such as 2.5 V, which is the threshold of comparator 506. When the voltage at comparator input 599 exceeds Vref, comparator 506 can switch its output voltage at 518 from a low state to a high state. Output 518 of comparator 506 can be connected to logic circuit 508. When output 518 goes high, output 520 of logic circuit 508 opens the gate of GaN power transistor 540 and turns off GaN power transistor 540. Those skilled in the art will appreciate that transistor 542 can be a D-mode GaN transistor, which can be integrated on the same die as GaN power transistor 540. In some embodiments, transistor 542 can be an enhancement-mode GaN transistor. In various embodiments, transistor 542 may be a silicon transistor.

[0076] FIG6 illustrates a schematic diagram of a circuit 600 having a saturation current protection feature according to one embodiment of the present disclosure. Circuit 600 is similar to circuit 400A, except that the gate 626 of transistor 642 is connected to the output of logic circuit 608 and is independently controlled by logic circuit 608. This enables the use of a low-pinchback (e.g., 5 V) D-mode GaN transistor to sense the drain voltage at drain 622 of GaN power transistor 640. To monitor the drain voltage of GaN power transistor 640 using a D-mode GaN transistor 642 with a low pinchback voltage, an independent bias voltage for gate 626 can be used to allow proper operation of the D-mode GaN transistor. Dynamic biasing can increase the gate voltage of D-mode GaN transistor 642 and provide for a variable, rather than fixed, gate-to-source voltage of the D-mode GaN transistor.

[0077] Circuit 600 can be used to detect when a GaN power transistor 640 enters its saturation operating region. The source 628 of GaN power transistor 640 can be connected to a ground node 630. Circuit 600 can monitor the drain voltage of the GaN power transistor using transistor 642. Although GaN power transistor 640 can be a high-voltage transistor with an operating voltage of, for example, 400 V, circuit 600 can utilize a low-voltage circuit to monitor the GaN power transistor and prevent it from operating in its saturation region. This can be done by monitoring the voltage at the drain 622 of GaN power transistor 640. When the voltage exceeds a threshold value of, for example, 8 V, circuit 600 can disconnect the GaN power transistor to protect it from damage. More specifically, circuit 600 can use a D-mode GaN transistor 642, where the drain 622 of GaN power transistor 640 is connected to the drain 621 of transistor 642.

[0078] Circuit 600 may include a comparator 606 and a logic circuit 608. In some embodiments, the resistor divider 619, comparator 606, and logic circuit 608 may be formed using low-voltage silicon technology. In various embodiments, the resistor divider 619, comparator 606, and logic circuit 608 may be formed using GaN technology and integrated on the same die as the GaN power transistor 640. The resistor divider 619 may include two resistors 602 and 604 connected in series. The output 616 of the resistor divider may be connected to a first input of the comparator 606, while the second input 614 of the comparator 606 may be connected to a reference voltage (Vref) 615. The reference voltage 615 may have a value of 2.5 V, for example. The output 618 of the comparator may be connected to the logic circuit 608.

[0079] The voltage at the drain 622 of the GaN power transistor 640 can vary, for example, from 0 to 400 V. The source 624 of the transistor 642 is clamped at its pinch voltage, for example, 15 V. The source 624 of the transistor 642 follows the drain voltage of the GaN power transistor 640 until it reaches its pinch voltage. Thereafter, the source 624 of the transistor 642 is clamped at the pinch voltage, for example, 15 V. The transistor 642 has the characteristic that its source voltage follows its drain voltage until the source voltage reaches the transistor's pinch voltage. At this point, the source voltage is clamped to the pinch voltage and remains constant at that voltage. In this way, the D-mode GaN transistor 642 can have its source 624 connected to the resistor divider 619, while the drain 621 of the D-mode GaN transistor 642 can operate at a high voltage, for example, up to 400 V. When the voltage at the source 624 of the transistor 642 exceeds a predetermined value, such as 8 V, it may cause the GaN power transistor 640 to turn off.

[0080] Resistor divider 619 can provide an output at 616 that tracks its input at node 623, but at a lower voltage level. The output voltage of resistor divider 619 can be compared to reference voltage 615, such as 2.5 V, which is the threshold of comparator 606. When the voltage at comparator input 699 exceeds Vref, comparator 606 can switch output 618 from a low state to a high state. Output 618 of comparator 606 can be connected to logic circuit 608. When output 618 goes high, output 620 of logic circuit 608 opens gate 612 of GaN power transistor 640, turning off GaN power transistor 640. Those skilled in the art will appreciate that transistor 642 can be a D-mode GaN transistor, which can be integrated on the same die as GaN power transistor 640. In some embodiments, transistor 642 can be an enhancement-mode GaN transistor. In various embodiments, transistor 642 may be a silicon transistor. Turn on dv / dt control

[0081] FIG7A illustrates a schematic diagram of a circuit 700A having a turn-on dV / dt control feature according to one embodiment of the present disclosure. Circuit 700A can be used to mitigate the relatively high parasitic inductance of electronic packages such as, but not limited to, TO-247 or TOLL packages. Circuit 700A illustrates a variation of circuit 200. Circuit 700A illustrates GaN power transistor 202, driver IC 710, and turn-on dV / dt control circuitry. Circuit 700A may include an impedance element 704. In some embodiments, circuit 200 may be coupled to impedance element 704. The impedance element may be external to integrated GaN power device 100. In various embodiments, impedance element 704 may include one or more passive components. In some embodiments, impedance element 704 may be a resistive element, while in other embodiments, impedance element 704 may include a resistive element and a capacitive element, wherein the capacitive element is coupled in parallel with the resistive element. In various embodiments, impedance element 704 may include a network of resistive and capacitive elements. Impedance element 704 can be coupled to input terminal pin 257. Impedance element 704 can be configured to receive signal 278. Impedance element 704 can be used to control the rate of change of voltage over time (dV / dt) of GaN power transistor 202. As discussed above in FIG. 1 , the integrated GaN power device 100 can be used as a pin-to-pin replacement for discrete silicon power MOSFETs, so the ability to control the dV / dt at the drain 204 of the GaN power transistor 202 can be beneficial. Without a dV / dt control circuit, parasitic dV / dt can cause ringing and oscillation at the drain 204, which can couple to the gate 208 and cause the GaN power transistor 202 to erroneously turn on.

[0082] Turn-on dV / dt control of the GaN power transistor 202 can be achieved by using an impedance element 704. Impedance element 704 can be used to slow the relatively rapid rate of change of the voltage at input terminal pin 257 over time. Gate drive node 730 can be connected to the gate 208 of the GaN power transistor 202. Capacitors 712 and 718, as well as inductor 716, are package parasitics. The substrate can be grounded at node 706 and connected to the source 206 of the GaN power transistor 202. In some embodiments, impedance element 704 can be integrated into the gate driver IC. In various embodiments, the current flowing through input terminal pin 257 to the gate of the GaN power transistor 202 can be limited by limiting the current of the pull-up transistor 210 to control the turn-on dV / dt. This can be achieved by reducing the gate drive of the pull-up transistor 210.

[0083] Figure 7B illustrates a graph 700B showing the PWM voltage 740 over time 748 and the rate of change of drain-to-source (V ds ) 742 over time when the GaN power transistor 202 is turned on. As can be seen in Figure 7B , as the resistance of the impedance element 704 increases, the slope of the drain turn-on falling edge decreases, indicating a reduction in dv / dt. Circuit 200 enables this feature because when signal 278 goes high, the current charging the gate 208 of the GaN power transistor 202 passes through the impedance element 704 in series with the pull-up transistor 210. In this way, the dv / dt at the drain 204 can be controlled, and electromagnetic interference (EMI) from the power conversion can be reduced. Figure 7C illustrates a graph of dv / dt 770 as a function of the resistance 778 of the impedance element 704 of circuit 700A. Graphs 772, 774, and 776 show dv / dt as a function of resistance 778 for PWM high values ​​of 8 V, 10, and 12 V, respectively. As the resistance value increases from, for example, a few ohms to a few thousand ohms, the dv / dt value may decrease from, for example, 100 V / ns to 10 V / ns.

[0084] FIG8 illustrates a schematic diagram of a circuit 800 including dv / dt control circuitry and gate clamping features according to one embodiment of the present disclosure. Circuit 800 shows gate driver and control circuitry 883 coupled to a GaN-based circuit 889. Circuit 800 can be used to mitigate ringing and oscillation caused by the relatively high parasitic inductance of electronic packages, such as, but not limited to, TO-247 or TOLL packages, as may be used as described in FIG1 . GaN-based circuit 889 can include a GaN power transistor 202 having a gate 208, a drain 204, and a source 206. GaN-based circuit 889 can further include a pull-down transistor 822 having a drain 824, a gate 828, and a source 826. Drain 824 can be connected to gate 208, while source 826 can be connected to ground node 840. In some embodiments, GaN-based circuit 889 can be used in a high-side configuration, where source 826 can be connected to the switching node (Vsw) of a half-bridge. The gate driver and control circuit 883 may include a pull-up transistor 814 having a gate 816, a drain 818, and a source 820. Gate 208 may be coupled to source 820. Pull-up transistor 814 may include an internal diode 819. Drain 818 may be coupled to input terminal pin 855. In some embodiments, gate driver and control circuit 883 may be formed on a silicon-based die, while GaN-based circuit 889 may be formed on a GaN-based die. In various embodiments, gate driver and control circuit 883 may be monolithically formed on the same die as GaN-based circuit 889. In some embodiments, while gate driver and control circuit 883 is formed on a separate die from GaN-based circuit 883, the pull-up transistor may be formed on the same die as GaN-based circuit 889. In various embodiments, input terminal pin 855 may be connected to external components.

[0085] Circuit 800 may further include a current control circuit. The current control circuit may include an impedance element 804, a unidirectional current conductor 806, an impedance element 808, and a unidirectional current conductor 810. The impedance element may include one or more passive components. In some embodiments, the impedance element may be a resistive element, while in other embodiments, the impedance element may include a resistive element and a capacitive element, wherein the capacitive element is coupled in parallel with the resistive element. In various embodiments, the impedance element may include a network of resistive and capacitive elements. The unidirectional current conductor may include, but is not limited to, a diode. Impedance element 804 may be coupled to node 802. Node 802 may be configured to receive signal 278. In some embodiments, impedance element 804, unidirectional current conductor 806, impedance element 808, and unidirectional current conductor 810 may be external to the integrated GaN power device 100 of FIG. 1 . In various embodiments, impedance element 804, unidirectional current conductor 806, impedance element 808, and unidirectional current conductor 810 can be external or internal to integrated GaN power device 100. Source 820 can be connected to gate 208. Pull-up transistor 814 can be a bipolar transistor or a MOSFET. In some embodiments, pull-up transistor 814 can be an N-MOSFET, while in other embodiments, pull-up transistor 814 can be a P-MOSFET.

[0086] Gate driver and control circuitry 883 may include logic circuitry and control circuitry 812 coupled to gate 828. Control and logic circuitry 812 may be configured to control the conductivity of pull-down transistor 822. In some embodiments, pull-down transistor 822 may be GaN-based and formed on the same die as GaN power transistor 202. In various embodiments, pull-down transistor 822 may be formed on a separate die. In some embodiments, pull-down transistor 822 may be formed in silicon or other suitable semiconductor substrates. Circuit 800 may further include clamping circuit 853. In some embodiments, circuit 800 may not include clamping circuit 853. Circuit 800 may further include control circuitry 869 configured to control the conductive state of gate 816. In some embodiments, circuit 800 may not include control circuit gate 816, and instead, gate 816 may be connected to input terminal pin 855 via an impedance element.

[0087] When signal 278 goes high, pull-up transistor 814 can turn on. Consequently, current can flow through impedance element 804, unidirectional current conductor 806, and pull-up transistor 814 to gate 208. This allows the capacitance of gate 208 to charge, causing GaN power transistor 202 to become conductive. By setting the value of impedance element 804, the user can control the turn-on dV / dt of GaN power transistor 202. This prevents ringing and oscillation, keeping GaN power transistor 202 within its safe operating area (SOA). Pull-up transistor 814 acts as a clamp to keep GaN power transistor 202 within its SOA. Clamp circuit 853 sets the voltage at gate 816 so that a significant portion of the input signal voltage is dropped across drain 818 to source 820. For example, the rated voltage of a GaN power transistor may be 7 V. When input signal 278 is, for example, 10 to 20 V, the disclosed dV / dt control circuit can maintain the GaN power transistor within its SOA. As will be appreciated by those of ordinary skill in the art having the benefit of this disclosure, the disclosed turn-on dV / dt control circuit can control dV / dt for other voltage values ​​at the input signal (e.g., 1 to 50 V). Furthermore, as will be appreciated by those of ordinary skill in the art, the disclosed turn-on dV / dt control circuit can utilize an external impedance element to control dV / dt. In various embodiments, the impedance element can include one or more passive components. In some embodiments, the impedance element can be a resistive element, while in other embodiments, the impedance element can include a resistive element and a capacitive element, wherein the capacitive element is coupled in parallel with the resistive element. In various embodiments, the impedance element can include a network of resistive and capacitive elements. In some embodiments, gate 816 can be controlled by other logic circuitry rather than clamp circuit 853. In various embodiments, clamp circuit 853 can be similar to clamp circuit 295.

[0088] When signal 278 goes low, the charge on gate 208 can discharge via internal diode 819, impedance element 808, and unidirectional current conductor 810. This discharges the charge on gate 208, causing the voltage at gate 208 to decrease, thereby rendering GaN power transistor 202 non-conductive. By setting the value of impedance element 808, the user can control the turn-off dV / dt of GaN power transistor 202. This prevents ringing and oscillation, thereby maintaining the GaN power transistor in a non-conductive state. Furthermore, logic and control circuit 812 can sense the voltage at gate 208. When the voltage drops below a threshold, logic and control circuit 812 can turn on pull-down transistor 822 after a relatively short period of time. This maintains gate 208 in a low state and prevents the GaN power transistor 202 from being accidentally turned on. In some embodiments, circuit 800 can be used in a high-side configuration. In various embodiments, the circuit 800 can be used in a half-bridge configuration. In some embodiments, the circuit 800 can be used in a low-side configuration. Disconnect dI / dt control

[0089] FIG9 illustrates a schematic diagram of a circuit 900 with an off-dI / dt control feature according to one embodiment of the present disclosure. Circuit 900 can be used to mitigate the relatively high parasitic inductance of a TO-247 or TOLL package. Circuit 900 may include a GaN power transistor 926 having a source 928, a gate 924, and a drain 922. In some embodiments, the GaN power transistor may be connected within its package via bond wires connecting the GaN transistor die to its package. The bond wires may have an associated inductance. Circuit 900 shows a bond wire inductance 920 having an inductance value L. For example, the bond wire inductance may be generated by a flip-chip bond between the source 928 of the GaN power transistor 926 and the package pad. Element 918 represents the package-to-printed circuit board inductance. The bond wire inductance L 920 can be used to sense the rate of change (dI / dt) of current in the source of the GaN power transistor 926 over time. When the GaN power transistor turns off, the current through the source of the GaN power device decreases. This can cause the voltage across inductor 920 (given by LxdI / dt) to change rapidly. The voltage across inductor 920 is sensed by resistors 914 and 916. Resistor 914 is connected to the cathode 919 of diode 912, and resistor 916 is connected to the anode 917 of diode 912.

[0090] The sensed voltage is fed back to the source 910 of the pull-down transistor 904. The drain 902 of the transistor 904 can be connected to the gate 924 of the GaN power transistor 926. In some embodiments, the pull-down transistor 904 can be a silicon transistor, while in other embodiments, it can be a GaN transistor integrated on the same die as the GaN power transistor 926. When the voltage across the inductor 920 increases, the voltage at the source 910 of the pull-down transistor 904 can increase because the voltage across the inductor 920 is fed back to the source 910 with a positive polarity. When the voltage at the source 910 of the pull-down transistor 904 increases, the gate-to-source voltage (Vgs) can decrease, which can result in less drive for the pull-down transistor 904. This, in turn, can reduce the turn-off speed of the GaN power transistor 926. The greater the voltage developed across inductor 920, the less drive pull-down transistor 904 can have, which in turn can slow the turn-off of GaN power transistor 926. Those skilled in the art will appreciate that transistor 904, resistors 914 and 916, and diode 912 can be formed in GaN and integrated within the same die as GaN power transistor 926, or can be formed in silicon, or some components can be formed in GaN while others are formed in silicon.

[0091] In some embodiments, feedback from the voltage across inductor 920 can be used to modulate the voltage at gate 906 of pull-down transistor 904, thereby reducing the pull-down drive and slowing down the turn-off of GaN power transistor 926. Source 910 of transistor 904 can be connected to source 928 of GaN power transistor 926, while modulating the voltage at gate 906 of pull-down transistor 904 to adjust the drive capability of pull-down transistor 904. In various embodiments, the inductance L of inductor 920 can vary due to manufacturing variations. Circuit 900 can compensate for variations in the value of inductor L. For example, if the value of inductor L decreases, the signal generated across inductor 920 also decreases. However, this signal will be sufficient to provide feedback to pull-down transistor 904 because the L x dI / dt value of the GaN power transistor also decreases.

[0092] In some embodiments, off-dI / dt control can control voltage spikes across the driver and across the drain-source of power transistor 926. Off-dI / dt control mitigates these spikes regardless of the value of inductor L. For example, if the value of inductor L is reduced, the off-dI / dt control system can mitigate higher dI / dt. Off-dI / dt control can mitigate voltage spikes as long as L x dI / dt closes the feedback loop comprising resistor 916, diode 912, and resistor 914. In various embodiments, diode 912 can provide feedback of a positive voltage across bond wire inductor 920 (i.e., node 930 is positive relative to node 932). In this way, the off-dI / dt control system prevents voltage ringing from feeding back into the system, which could cause high-frequency oscillations. Those skilled in the art will appreciate that when bond wire inductance 920 is available, the described turn-off dI / dt control system and circuit can be used in any power conversion circuit that includes power transistors, including but not limited to GaN and / or silicon power transistors. Gate driver circuit with hysteresis

[0093] FIG10 illustrates a schematic diagram of a gate driver circuit 1000 with hysteresis according to one embodiment of the present disclosure. Circuit 1000 can be used within circuit 200 to provide gate drive with hysteresis, which can be used to drive GaN power transistor 202. Circuit 1000 can include a GaN power transistor 1024 having a source 1030, a gate 1026, and a drain 1028. Circuit 1000 can include a rail 1020 configured to receive a PWM signal 1011. When PWM signal 1011 is high, it can turn on transistor 1010, which can begin charging gate 1026 of GaN power transistor 1024. Source 1012 of transistor 1010 can be connected to rail 1020, which is connected to input PWM signal 1011. Zener diode 1018 can be connected to gate 1014 of transistor 1010 to clamp the voltage at gate 1014 of transistor 1010. The gate of GaN power transistor 1024 can be connected to feedback and hysteresis circuit 1050. The feedback and hysteresis circuit can include a resistor divider formed by resistors 1052, 1054, and 1056, and transistor 1070. Comparator 1094 can have its first input 1096 connected to output 1049 of the resistor divider formed by resistors 1052, 1054, and 1056. Comparator 1094 can monitor the voltage at the gate of GaN power transistor 1024 via the resistor divider. When the gate of GaN power transistor 1024 is low, the drain 1016 of transistor 1010 is low, so transistor 1010 can turn on and charge the gate of GaN power transistor 1024. The voltage at the gate 1026 of the GaN power transistor goes high as it charges.

[0094] Comparator 1094 can detect the high state of the gate of GaN power transistor 1024 by comparing the voltage at its first input 1096 with a reference voltage V ref at node 1077. When the voltage at first input 1096 goes high, comparator 1094 switches, and its output 1098 goes high. Output 1098 can then turn on transistor 1005 via buffer 1015. Transistor 1005 can be connected to gate 1006 of PMOS transistor 1004 via resistor 1092. When transistor 1005 is turned on, the voltage at gate 1006 of PMOS transistor 1004 goes low, turning on PMOS transistor 1004. Source 1002 of PMOS transistor 1004 can be connected to rail 1020, and drain 1008 can be connected to gate 1014 of transistor 1010. Zener diode 1022 can be connected to gate 1006 of PMOS transistor 1004 to clamp its gate voltage and prevent damage to the gate. When PMOS transistor 1004 is turned on, it can turn off transistor 1010. Thus, the gate of the GaN power transistor can remain in a high state. If the voltage at the gate of the GaN power transistor drops due to leakage through parasitic elements, comparator 1094 can be turned back on due to hysteresis, turning transistor 1010 back on and charging the gate of the GaN power transistor.

[0095] By utilizing pull-up transistor 1010, circuit 1000 enables the use of PWM signals with a wide voltage range (e.g., from 5 V to 30 V). When pull-up transistor 1010 is incorporated into circuit 1000, its gate 1014 can be controlled by utilizing feedback and hysteresis circuit 1050. Circuit 1000 may include buffer 1019, which can control gate 1080 of transistor 1086 and gate 1076 of transistor 1070. When the gate of GaN power transistor 1024 is high, the inverted output 1017 of comparator 1094 is high. Inverted output 1017 drives gate 1080 of transistor 1086 via buffer 1019, turning transistor 1086 off. This allows the voltage at drain 1082, connected to resistor 1090, to move upward toward the voltage at rail 1020, thereby turning transistor 1010 off. At the same time, transistor 1005 can turn on, causing transistor 1004 to turn off. Transistors 1032, 1060, and 1042, combined with Zener diode 1040, form a clamping circuit for gate 1026 of GaN power transistor 1024, preventing the gate voltage from exceeding its safe operating area. Circuit 1000 enables driving the gate of GaN power transistor 1024 with a relatively low PWM voltage, while also enabling driving the gate of GaN power transistor 1024 with a relatively high PWM voltage.

[0096] FIG11 illustrates a graph 1100 showing the voltages at various nodes within circuit 1000. Graph 1102 shows the PWM signal going high. Graph 1104 shows the comparator input voltage at first input 1096 going high. Graph 1106 shows the comparator output 1098 voltage going high. Graph 1108 shows the voltage at the gate of GaN power transistor 1024 going high.

[0097] In various embodiments, hysteresis can be implemented, for example, within comparator 1094 itself. The comparator can have hysteresis, or the comparator can use two reference voltages at different levels. In some embodiments, a gate driver circuit with hysteresis can control the transistors of pull-up transistor 1010 in various ways. In some embodiments, a gate driver circuit with hysteresis can function without a gate clamp circuit comprising transistors 1032, 1060, and 1042. A gate driver circuit with hysteresis can function with or without a clamp circuit. In various embodiments, a gate driver circuit with hysteresis can be used in many gate driver applications. Furthermore, a gate driver circuit with hysteresis can be used as a voltage regulator, as illustrated in FIG12.

[0098] FIG12 illustrates a schematic diagram of a voltage regulator 1200 according to one embodiment of the present disclosure. Voltage regulator 1200 regulates the gate voltage of transistor 1010 of circuit 1000. Drain 1016 can be connected to capacitor 1220 and load 1218. Resistors 1208 and 1210 can form a resistor divider configured to provide a feedback signal. The feedback signal can be generated at node 1206, which is fed to the input of comparator 1204. Comparator 1204 can have hysteresis. Comparator 1204 can compare the voltage at node 1206 with a reference voltage Vref and provide the voltage at node 1227 to controller circuit 1202. Controller circuit 1202 can regulate the gate voltage of transistor 1010.

[0099] FIG13 illustrates an integrated GaN power device 1300 according to one embodiment of the present disclosure. As shown in FIG13 , the integrated GaN power device 1300 can utilize a TO-247 package to integrate a gate driver IC 112 and an integrated GaN power transistor 114. The integrated GaN power device 1300 can include a source terminal 1302, a drain terminal 1304, and a PWM terminal 1306. The integrated GaN power device 1300 can be a compatible replacement for a power MOSFET and its driver circuitry in a TO-247 package.

[0100] FIG14A illustrates an integrated GaN power device 1400A according to one embodiment of the present disclosure. As shown in FIG14A , the integrated GaN power device 1400A may utilize a TO-247 or TO-no-lead (TOLL) package to integrate the gate driver IC 112 and the GaN power transistor 114. In the illustrated embodiment, the integrated GaN power device 1400A may include a source terminal 1404, a drain terminal 1402, a PWM terminal 1408, and a Kelvin source 1406. In some embodiments, the integrated GaN power device 1400A may not include a Kelvin source and may utilize a three-terminal TO-247 package or a three-terminal TOLL package. In various embodiments, the integrated GaN power device 1400A may be a compatible replacement for a power MOSFET and its driver circuitry in a three-terminal or four-terminal TO-247 package. In many embodiments, the integrated GaN power device 1400A may be a compatible replacement for a power MOSFET and its driver circuitry in a three-terminal or four-terminal TOLL package. Figure 14B illustrates an integrated GaN power device 1400B in a four-terminal TO-247 package according to an embodiment of the present disclosure. Figure 14C illustrates an integrated GaN power device 1400C in a TOLL package according to an embodiment of the present disclosure.

[0101] While the integrated power device with energy harvesting gate driver is described and illustrated herein with respect to a specific configuration of a GaN integrated power device, embodiments of the present disclosure are suitable for use with other configurations of GaN and non-GaN devices. For example, any semiconductor device can be used with embodiments of the present disclosure. In some instances, embodiments of the present disclosure are particularly well-suited for use with silicon and other compound semiconductor devices.

[0102] For simplicity, various internal components such as details of the substrate, various lead frames, and other components of the integrated GaN power device 100 (see FIG. 1 ) are not shown.

[0103] In the foregoing specification, the embodiments of the present disclosure have been described with reference to numerous specific details that may vary from implementation to implementation. The specification and drawings are therefore to be regarded as illustrative rather than restrictive. The sole and exclusive indicator of the scope of the present disclosure, and what the applicants intend to be the scope of the present disclosure, is the literal and equivalent scope of the set of claims published in this application, in the specific form in which such claims are published, including any subsequent corrections. The specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of the embodiments of the present disclosure.

[0104] Additionally, spatially relative terms such as "bottom" or "top" may be used to describe an element and / or feature in relationship to another element and / or feature, for example, as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as the "bottom" surface could be oriented "above" other elements or features. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0105] As used herein, the terms "and," "or," and "one / or" can include multiple meanings, each of which is intended to depend at least in part on the context in which such terms are used. Generally, "or," when used in conjunction with a list such as A, B, or C, is intended to mean both A, B, and C, where used inclusively, and A, B, or C, where used exclusive. Furthermore, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in the singular, or to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example, and claimed subject matter is not limited to this example. Furthermore, if the term "at least one of" is used in conjunction with a list such as A, B, or C, it can be interpreted to mean any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, and so forth.

[0106] References throughout this specification to "one example," "an example," "some examples," or "illustrative implementations" mean that a particular feature, structure, or characteristic described in connection with a feature and / or example can be included in at least one feature and / or example of the claimed subject matter. Thus, the appearances of the phrases "in one example," "an example," "in some examples," or "in some implementations," or other similar phrases, in various places throughout this specification are not necessarily all referring to the same feature, example, and / or limitation. Furthermore, particular features, structures, or characteristics may be combined in one or more examples and / or features.

[0107] In the preceding detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will appreciate that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatuses that would be known to those skilled in the art have not been described in detail in order to avoid obscuring the claimed subject matter. Therefore, it is intended that the claimed subject matter not be limited to the specific examples disclosed, but that the claimed subject matter may encompass all aspects within the scope of the appended claims and their equivalents.

[0108] 100: Integrated GaN power devices 102: Pin 104: Pin 106: Pin 108: Input pin 110:Semiconductor packaging 112: Gate driver integrated circuit 114:GaN power transistors 116: Grain pad 118: Top plate 120:Joint wire 122:Joint line 124:Joint line 126:Joint line 128:Joint line 200: Circuit 202:GaN power transistors 204: Drain 206: Source 208: Gate 210: Pull-up transistor 214: Emitter electrode 216: Base 218: Transistor 220: Collector terminal 222: Emitter terminal 226: Base terminal 228: Internal capacitor / energy storage capacitor 229: Storage Circuit 230: Pull-down transistor 232:Drain terminal 233: cathode 234: Source terminal 236: Gate terminal 240: Transistor 242: Jiji 244: Source 246: Gate / Signal 248:Baseboard terminal / baseboard 250: Zener diode 252: Resistor 254: Collector 257: Input terminal pin 262:NPN transistor 264: Emitter 266: Emitter 272:NPN transistor 274: Collector 276: Base 277: Pin 278:Signal 279: Pin 280:Substrate 289:Logic Circuit 295: Clamping Circuit 300: Curve Graph 306:PWM voltage 310: Graph 400A:Circuit 400B: Curve Graph 402: Resistor 404: Resistor 406: Comparator 408:Logic Circuit 412: Gate 414: Second input 415: Reference voltage 415A: Graph 416: Output 416A: Graph 418: Output 418A: Graph 419:Resistor voltage divider 420: Output 421: Jiji 422: Drain 422A: Graph 423: Node 424: Source 424A: Graph 426: Gate 428: Source 430: Ground node 440:GaN power transistor 442:GaN transistor 499: First input 500: Circuit 502: Resistor 504: Resistor 506: Comparator 508:Logic Circuit 512: Gate 514: Second input 515: Reference voltage 516: Output 518: Output 519:Resistor voltage divider 520: Output 521: Jiji 522: Drain 523: Node 524: Source 526: Gate 528: Source 530: Ground node 540:GaN power transistor 542: Transistor 599: Input 600: Circuit 602: Resistor 604: Resistor 606: Comparator 608: Logic Circuit 612: Gate 614: Second input 615: Reference voltage 616: Output 618: Output 619:Resistor voltage divider 620: Output 621: Jiji 622: Drain 623: Node 624: Source 626: Gate 628: Source 630: Ground node 640:GaN power transistor 642: Transistor 699: Input 700A:Circuit 700B: Curve Graph 704: Impedance element 706: Node 710: Driver IC 712:Capacitor 716: Inductor 718:Capacitor 730: Gate driver node 740:PWM voltage 742: Drain to Source (V ds) 748: Time 770:dv / dt 772: Curve Graph 774: Graph 776: Curve Graph 778:Resistance 800: Circuit 802: Node 804: Impedance element 806: One-way current conductor 808: Impedance element 810: One-way current conductor 812: Logic Circuit and Control Circuit / Control and Logic Circuit 814: Pull-up transistor 816: Gate 818: Jiji 819: Internal diode 820: Source 822: Pull-down transistor 824: Jiji 826: Source 828: Gate 840: Ground node 853: Clamping Circuit 855: Input terminal pin 869: Control circuit 883: Gate driver and control circuit 889:GaN-based circuits 902: Drain 904: Pull-down transistor 906: Gate 910: Source 912: Diode 914: Resistor 916: Resistor 917: Anode 918: Component 919: cathode 920: Inductor 922: Drain 924: Gate 926:GaN power transistors 928: Source 930: Node 932: Node 1000: Gate driver circuit 1002: Source 1004:PMOS transistor 1005: Transistor 1006: Gate 1008: Drain 1010: Transistor 1011: PWM signal 1012: Source 1014: Gate 1015: Buffer 1016: Drain 1017: Inverted output 1018: Zener diode 1020: Track 1024:GaN power transistor 1026: Gate 1028: Drain 1030: Source 1032: Transistor 1040: Zener diode 1042: Transistor 1049: Output 1050: Feedback and hysteresis circuit 1052: Resistor 1054: Resistor 1056: Resistor 1060: Transistor 1070: Transistor 1076: Gate 1077: Node 1080: Gate 1082: Drain 1086: Transistor 1090: Resistor 1092: Resistor 1094: Comparator 1096: First input 1098: Output 1100: Graph 1102: Graph 1104: Graph 1106: Graph 1108: Graph 1200: Voltage regulator 1202: Controller circuit 1204: Comparator 1206: Node 1208: Resistors 1210: Resistor 1218: Load 1220:Capacitor 1227: Node 1300: Integrated GaN power devices 1302: Source terminal 1304: Drain terminal 1306: PWM terminal 1400A: Integrated GaN power device 1400B: Integrated GaN power device 1400C: Integrated GaN Power Device 1402: Drain terminal 1404: Source terminal 1406: Kelvin Source 1408: PWM terminal

Claims

1. A power conversion device, comprising: A package base; a GaN-based semiconductor device attached to the package base, the GaN-based semiconductor device comprising: a first transistor having a first gate terminal, a first source terminal, and a first drain terminal; and a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, wherein the second drain terminal is coupled to the first gate terminal; and a silicon-based semiconductor device attached to the package base, the silicon-based semiconductor device comprising a control circuit that is configured to turn on the second transistor when the first transistor transitions from an on state to an off state and a voltage at the first gate terminal is lower than a predetermined threshold voltage; An electrically insulating encapsulant that at least partially encapsulates the package base, the GaN-based semiconductor device, and the silicon-based semiconductor device; and a current control circuit arranged to receive an input signal and, in response, transmit a corresponding output signal to the first gate terminal.

2. The power conversion device of claim 1, wherein the control circuit is arranged to sense the voltage at the first gate terminal in order to determine when the voltage at the first gate terminal is lower than the predetermined threshold voltage.

3. The power conversion device of claim 1, wherein when the second transistor is turned on, the voltage at the first gate terminal is clamped to a preset voltage.

4. The power conversion device of claim 1, wherein the current control circuit comprises: a first path having a first impedance element coupled in series with a first unidirectional current conductor, the first unidirectional current conductor being oriented to allow current to flow to the first gate terminal; and a second path having a second impedance element coupled in series with a second unidirectional current conductor, the second unidirectional current conductor being oriented to allow current to flow from the first gate terminal.

5. The power conversion device of claim 1, wherein the control circuit further includes a third transistor having a third gate terminal, a third source terminal and a third drain terminal, wherein the third source terminal is coupled to the first gate terminal and the third drain terminal is coupled to the current control circuit.

6. An electric power conversion circuit, the electric power conversion circuit comprising: A first transistor having a first gate terminal, a first source terminal and a first drain terminal; and a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, wherein the second drain terminal is coupled to the first gate terminal; a control circuit configured to turn on the second transistor when the first transistor changes from an on state to an off state and a voltage at the first gate terminal is lower than a predetermined threshold voltage; and a current control circuit configured to receive an input signal and, upon response, transmit a corresponding output signal to the first gate terminal.

7. The power conversion circuit of claim 6, wherein the control circuit is arranged to sense the voltage at the first gate terminal in order to turn on the second transistor.

8. The power conversion circuit of claim 6, wherein when the second transistor is turned on, the voltage at the first gate terminal is clamped to a preset voltage.

9. The power conversion circuit of claim 6, wherein the first transistor and the second transistor system are disposed on a GaN-based die.

10. The power conversion circuit of claim 9, wherein the control circuit is mounted on a silicon-based die.

11. The power conversion circuit of claim 10, wherein the GaN-based die and the silicon-based die system are co-packaged in a single electronic package.

12. The power conversion circuit of claim 6, wherein the current control circuit comprises: a first path having a first impedance element coupled in series with a first unidirectional current conductor, the first unidirectional current conductor being oriented to allow current to flow to the first gate terminal; and a second path having a second impedance element coupled in series with a second unidirectional current conductor, the second unidirectional current conductor being oriented to allow current to flow from the first gate terminal.

13. The power conversion circuit of claim 12, wherein the control circuit further includes a third transistor having a third gate terminal, a third source terminal and a third drain terminal, wherein the third source terminal is coupled to the first gate terminal and the third drain terminal is coupled to the current control circuit.

14. An electric power conversion circuit, the electric power conversion circuit comprising: A transistor comprising a gate terminal, a source terminal, and a drain terminal; A gate driver circuit includes: a pull-down transistor coupled to the gate terminal; an input terminal configured to receive an input signal and generate a corresponding output signal at an output terminal coupled to the gate terminal; wherein the gate driver circuit stores energy directly extracted from the input signal and uses the stored energy to change the conductivity state of the pull-down transistor.

15. The power conversion circuit of claim 14, wherein the gate driver circuit uses the stored energy to operate an over-temperature protection circuit.

16. The power conversion circuit of claim 14, wherein the gate driver circuit further includes an over-temperature protection circuit.

17. The power conversion circuit of claim 16, wherein the gate driver circuit uses the stored energy to further operate the over-temperature protection circuit.

18. The power conversion circuit of claim 14, wherein the transistor system is disposed on a GaN-based die, and the gate driver circuit is disposed on a silicon-based die, and wherein the GaN-based die and the silicon-based die are co-packaged in a single electronic package.

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