Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same are provided. The method includes: forming a first work function metal layer around a first nanostructure in a fin disposed above a substrate; at least partially oxidizing the first work function metal layer, wherein the first work function metal layer between the first nanostructure and an adjacent second nanostructure in a stack of fins is less oxidized; removing the oxidized portion of the first work function metal layer from around the first nanostructure; and forming a second work function metal layer around the first nanostructure, wherein the first work function metal layer and the second work function metal layer fill a void between the first nanostructure and the adjacent second nanostructure.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for forming the same, and particularly to a gap filling scheme for high aspect ratio wafer-to-wafer spacing on a nanosheet structure. [Previous Technology]

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication method of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the multiple material layers to form circuit components and units on the semiconductor substrate.

[0003] The semiconductor industry continues to reduce minimum structural dimensions to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, or the like) to integrate more components into a given area. However, as the minimum structural dimensions shrink, additional problems arise that need to be addressed. [Summary of the Invention]

[0004] One embodiment relates to a method of forming a semiconductor device, comprising: forming a multilayer stacked structure over a substrate, the multilayer stacked structure including a plurality of layers alternating between a first semiconductor material and a second semiconductor material; patterning the multilayer stacked structure into a fin, the fin including and alternating between a plurality of first nanostructures of the first semiconductor material and at least two second nanostructures of the second semiconductor material in a first region of the substrate; removing the first nanostructures from the multilayer stacked structure in the first region of the substrate; forming a first work function metal layer around each of the at least two second nanostructures; partially oxidizing the first work function metal layer, wherein an unoxidized portion remains in the region between the at least two second nanostructures; removing the oxidized portion of the first work function metal layer; and forming a second work function metal layer around each of the at least two second nanostructures, wherein the second work function metal layer and the first work function metal layer fill the space between the at least two second nanostructures.

[0005] Another embodiment relates to a method of manufacturing a semiconductor device, comprising: forming a first work function metal layer around a first nanostructure in a fin disposed above a substrate; at least partially oxidizing the first work function metal layer, wherein the first work function metal layer between the first nanostructure and an adjacent second nanostructure in the stack of the fins is less oxidized; removing the oxidized portion of the first work function metal layer from around the first nanostructure; and forming a second work function metal layer around the first nanostructure, wherein the first work function metal layer and the second work function metal layer fill a void between the first nanostructure and the adjacent second nanostructure.

[0006] Yet another embodiment relates to a semiconductor device, comprising: a first nanostructure and a second nanostructure in a stack above a substrate fin; a gate dielectric layer surrounding the first nanostructure and the second nanostructure; a first work function metal layer filling a portion of a space between the first nanostructure and the second nanostructure and disposed on each of the first nanostructure and the second nanostructure; a second work function metal layer filling at least a portion of the remaining portion of the space between the first nanostructure and the second nanostructure not filled by the first work function metal layer; an epitaxial source / drain region on an adjacent side of the stack; and a gate electrode including the first work function metal layer and the second work function metal layer.

Implementation Method

[0008] The following disclosure provides many different embodiments or examples for implementing different components of this disclosure. Specific examples of components and configurations are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to be limiting. For example, the following description mentioning that a first component is formed on or above a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, the embodiments of the invention may repeat the numbers and / or letters of element symbols in various examples; this repetition is for simplification and clarity and does not specify a relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, spatial relative terms such as "below," "under," "lower than," "above," "above," and similar terms may be used herein to help describe the relationship between one element or component shown in the figure and another element(s). These spatial relative terms are used to cover different orientations of the device in use or operation, other than those depicted in the figures. The device may be rotated (rotated 90 degrees or otherwise), and the spatial relative descriptions used herein may be interpreted accordingly.

[0010] Embodiments of the present invention relate to semiconductor devices, specifically methods for enhancing performance and reducing defects, particularly in the case of nanostructure field-effect transistors (nano-FETs). As the semiconductor industry relentlessly increases the density of electronic components, managing and improving the performance of these dense structures becomes increasingly complex. This disclosure addresses these challenges by utilizing disposable oxide interposers (DOI) processes.

[0011] In some embodiments, the disclosed semiconductor device includes a substrate having a plurality of nanostructures formed thereon, the nanostructures serving as channel regions for nanostructured field-effect transistors. The aforementioned disposable oxide intermediate process includes using oxide materials such as silicon dioxide (SiO2), silicon oxynitride (SiON), and aluminum oxide (Al2O3) to replace silicon germanium (SiGe) as a dummy material in the manufacturing process. The advantage of such substitution is that it reduces silicon-germanium intermixing and mitigates germanium diffusion through the oxygen / silicon interface. As a result, the nanostructures retain greater height and undergo less metal gate extrusion, thereby improving device performance and reliability.

[0012] Furthermore, in the aforementioned polishable oxide intermediate process, the nanostructures retain a more closely spaced shape and have openings between the nanostructures. The disclosed method further utilizes gradient oxidation and selective etching to transform the re-entrant openings between the sheets into a V-shape. In a gate all around (GAA), the work function metal becomes easier to fill the sheet-to-sheet gaps, and the gaps between the work function metals of the internal sheets become smaller.

[0013] Compared to conventional technologies, the disclosed semiconductor device and method offer several advantages. By reducing germanium diffusion and avoiding metal gate extrusion defects, the disclosed method enables the fabrication of nanostructured field-effect transistors with superior electrical properties, such as lower resistance and higher drive current. Furthermore, the larger channel height achieved through the aforementioned polishable oxide dielectric process helps reduce channel resistance, further enhancing the performance of the semiconductor device. Additionally, by using the aforementioned polishable oxide dielectric process with improved work function metal formation technology, punch-through during etching can be reduced, damage to the fin tops can be avoided, and overall coverage of the metal capping film can be provided.

[0014] In summary, the disclosed semiconductor devices and methods represent substantial progress in the field of nanostructured field-effect transistor fabrication. By solving technical problems related to Si / Ge intermixing and metal gate extrusion, the disclosed techniques provide a pathway to manufacture semiconductor devices with excellent performance and fewer defects.

[0015] The following embodiments are described in the context of a grain including a nanostructured field-effect transistor. However, various embodiments may be applied to grains containing other types of transistors (for example, stacked transistors or the like) to replace or combine with nanostructured field-effect transistors.

[0016] Figure 1 is a three-dimensional diagram illustrating an example of a nanostructured field-effect transistor according to some embodiments. Specific structures in Figure 1 have been simplified and / or omitted for ease of illustration. The nanostructured field-effect transistor includes a plurality of second nanostructures 54 (e.g., nanosheets, nanowires, or the like) located above a substrate 50 (e.g., a fin 66 on a semiconductor substrate, wherein the second nanostructures 54 serve as channel regions for the nanostructured field-effect transistor (as described in more detail below, also forming a plurality of first nanostructures 52 (see Figure 3), but the first nanostructures 52 are removed in an intermediate process step of forming the nanostructured field-effect transistor illustrated in Figure 1). The second nanostructures 54 may include p-type nanostructures, n-type nanostructures, or combinations thereof. A plurality of shallow trench isolation (STI) regions 68 (Also considered as a shallow trench isolation structure or STI region) It is placed between adjacent fins 66, and the fins 66 may protrude from and be higher than the shallow trench isolation regions 68 between adjacent shallow trench isolation regions 68. Furthermore, although the shallow trench isolation regions 68 shown are separate from the substrate 50, the term "substrate" as used herein may refer to the semiconductor substrate itself or a combination of a semiconductor substrate and an isolation region. Additionally, although the bottom of the fins 66 in the figures is a single continuous material with the substrate 50, the bottom of the fins 66 and / or the substrate 50 may comprise a single material or multiple materials. In this description, the fins 66 may be considered as portions extending between adjacent shallow trench isolation regions 68.

[0017] A plurality of gate dielectric layers 100 are located above the top surface of the fins 66 and along the top surface, sidewalls, and bottom surface of the second nanostructure 54. A plurality of gate electrodes 102 are located above the gate dielectric layers 100. A plurality of epitaxial source / drain regions 92 are located on the fins 66 on both sides of the gate dielectric layers 100 and the gate electrodes 102. The epitaxial source / drain regions 92 may be considered as sources or drains individually or together, depending on their purpose.

[0018] Figure 1 also shows reference cross-sections used in subsequent figures. Cross-section A-A' is along the longitudinal axis of the gate electrode 102, and its direction is, for example, perpendicular to the current direction between the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. Cross-section B-B' is perpendicular to cross-section A-A' and parallel to the longitudinal axis of the fin 66 of the aforementioned nanostructured field-effect transistor, and its direction is, for example, the current direction between the epitaxial source / drain regions 92 of the aforementioned nanostructured field-effect transistor. Cross-section C-C' is parallel to cross-section A-A' and extends through the epitaxial source / drain regions of the aforementioned nanostructured field-effect transistor. Subsequent figures will be based on these reference cross-sections for illustrative purposes.

[0019] Some embodiments described herein are illustrated in the context of nanostructured field-effect transistors formed using a gate-last process. In other embodiments, a gate-first process may be employed. Furthermore, some embodiments are intended to apply this concept to planar devices (e.g., planar field-effect transistors) or fin field-effect transistors (FinFETs).

[0020] Figures 2 to 4, 5A, 5B, 6A, 6B, 7A, 7B, 7C, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 10D, 11A, 11B, 11C, 11D, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B, 19C, 20A, 20B, 20C, 21A, 21B and 21C are cross-sectional views illustrating intermediate steps in the fabrication of nanostructured field-effect transistors according to some embodiments. Figures 2 to 4, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 19A, 20A, and 21A are drawn in section A-A' shown in Figure 1. Figures 5B, 6B, 7B, 8B, 9B, 10B, 10C, 10D, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, and 21B are drawn in section B-B' shown in Figure 1. Figures 7C, 11C, 11D, 19C, 20C, and 21C are drawn in section C-C' shown in Figure 1.

[0021] In Figure 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (for example, doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer may be provided on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide), or combinations thereof.

[0022] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an n-type metal-oxide-semiconductor (e.g., an n-type nanostructured field-effect transistor); while the p-type region 50P can be used to form a p-type device, such as a p-type metal-oxide-semiconductor (e.g., a p-type nanostructured field-effect transistor). The n-type region 50N and the p-type region 50P are physically separated (as shown in the figure, physically separated by the separator 20), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be placed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are illustrated, any number of n-type regions 50N and p-type regions 50P can be provided. Unless otherwise stated, the process steps illustrated in the following figures can be performed in either the n-type region 50N or the p-type region 50P.

[0023] Further, as shown in Figure 2, a multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes a plurality of layers alternating between first semiconductor layers 51A to 51C (which can be collectively considered as first semiconductor layer 51) and second semiconductor layers 53A to 53C (which can be collectively considered as second semiconductor layer 53). For illustrative purposes and as detailed below, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 will be patterned to form channel regions of nanostructured field-effect transistors in both the n-type region 50N and the p-type region 50P. Nevertheless, in some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form channel regions of nanostructured field-effect transistors in both the n-type region 50N and the p-type region 50P. For example, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (for example: silicon or another semiconductor material) and may be formed simultaneously.

[0024] In other embodiments, in the p-type region 50P, the first semiconductor layer 51 can be removed and the second semiconductor layer 53 can be patterned to form a channel region of a nanostructured field-effect transistor; while in the n-type region 50N, the second semiconductor layer 53 can be removed and the first semiconductor layer 51 can be patterned to form a channel region of a nanostructured field-effect transistor. In still other embodiments, in the n-type region 50N, the first semiconductor layer 51 can be removed and the second semiconductor layer 53 can be patterned to form a channel region of a nanostructured field-effect transistor; while in the p-type region 50P, the second semiconductor layer 53 can be removed and the first semiconductor layer 51 can be patterned to form a channel region of a nanostructured field-effect transistor. In such embodiments, the channel regions of the n-type region 50N and the p-type region 50P may have different material compositions. The first semiconductor layer 51 and the second semiconductor layer 53 can be selectively removed from each n-type region 50N and p-type region 50P via additional masking and etching steps. For example, the channel region of the n-type region 50N can be a silicon channel region, while the channel region of the p-type region 50P can be a silicon-germanium channel region.

[0025] The illustrated multilayer stack 64 includes three first semiconductor layers 51 and three second semiconductor layers 53, and is for illustrative purposes only. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition, atomic layer deposition, vapor phase epitaxy, molecular beam epitaxy, or similar processes.

[0026] In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material, such as silicon germanium or the like, while the second semiconductor layer 53 may be formed of a second semiconductor material, such as silicon, silicon carbide, or the like. The first semiconductor material and the second semiconductor material may be materials with high etch selectivity relative to each other. In this way, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby patterning the second semiconductor layer 53 to form the channel region of the nanostructured field-effect transistor.

[0027] Referring now to Figure 3, according to some embodiments, a plurality of fins 66 are formed on a substrate 50, and a plurality of nanostructures 55 are formed on a multilayer stack 64 (shown in Figure 2). In some embodiments, the nanostructures 55 and fins 66 can be formed on the multilayer stack 64 (shown in Figure 2) and the substrate 50 respectively by etching trenches 58 in the multilayer stack 64 (shown in Figure 2) and the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar processes, or combinations thereof. The etching can be anisotropic. During the etching process, a hard mask (not shown) can be used to define the pattern of the fins 66 and the nanostructures 55. The hard mask can include any suitable insulating material, such as oxides, nitrides, oxynitrides, or the like. In some embodiments (not shown separately), the hard mask described above may be a multilayer structure. One or more acceptable processes, such as thermal oxidation, physical vapor deposition, chemical vapor deposition, atomic layer deposition, a combination of the above, or similar methods, may be used to form the hard mask above the nanostructure 55.

[0028] The fin 66 and the nanostructure 55 can be patterned by any suitable method. For example, one or more optical lithography processes, including dual patterning or multiple patterning processes, can be used to pattern the fin 66 and the nanostructure 55. Generally, dual patterning or multiple patterning processes combine optical lithography and self-alignment processes to allow the resulting pattern to have a pitch (e.g.) smaller than that achievable using a single, direct optical lithography process. For example, a sacrificial layer can be formed over a substrate and patterned using an optical lithography process. Then, a self-alignment process can be used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 66 and the nanostructure 55.

[0029] A nanostructure 55 is formed by etching a multilayer stack 64 (shown in Figure 2). First nanostructures 52A to 52C (collectively considered as first nanostructure 52) can be further defined from the first semiconductor layer 51, and second nanostructures 54A to 54C (collectively considered as second nanostructure 54) can be defined from the second semiconductor layer 53. The first nanostructure 52 and the second nanostructure 54 can be further considered as nanostructure 55.

[0030] The fins 66 shown in Figure 3 have substantially the same width, which is for illustrative purposes only. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or less than the width of the fins 66 in the p-type region 50P; or vice versa. Furthermore, although the fins 66 and nanostructures 55 shown in Figure 3 each have the same width, in other embodiments the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of each fin 66 and / or nanostructure 55 continuously increases in the direction toward the substrate 50. In such embodiments, the nanostructures 55 may each have different widths and be trapezoidal.

[0031] In Figure 4, a plurality of shallow trench isolation regions 68 are formed adjacent to the fins 66. The shallow trench isolation regions 68 can be formed by depositing an insulating material on the substrate 50, the fins 66, and the nanostructure 55, and between adjacent fins 66 to fill the trenches 58. The insulating material can be an oxide, nitride, or similar compound, such as silicon oxide, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), similar methods, or combinations thereof. Other insulating materials formed by any acceptable process can also be used. In the illustrated embodiment, the insulating material is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material shown in the illustration is a single layer, some embodiments may employ multilayer insulating materials. For example, in some embodiments, a liner (not shown separately) may first be formed along the surfaces of the substrate 50, fins 66, and nanostructures 55. A filler material, such as that described above, may then be formed on top of the liner.

[0032] Then, a removal process is performed on the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), etch-back, a combination thereof, or a similar process. The planarization process exposes the nanostructure 55 so that the nanostructure 55 after the planarization process is completed is flush with the upper surface of the insulating material.

[0033] The insulating material is then recessed to form shallow trench isolation regions 68. The insulating material is recessed so that the upper part of the fin 66 protrudes from between adjacent shallow trench isolation regions 68. Furthermore, the top surface of the shallow trench isolation region 68 can be a flat surface, a convex surface, a recessed surface (such as dishing), or a combination thereof, as shown in the figure. The top surface of the shallow trench isolation region 68 can be made flat, convex, and / or recessed by suitable etching. An acceptable etching process can be used to recess the shallow trench isolation region 68, such as an etching process selective to the material of the insulating material (for example, etching at a rate greater than etching at a rate between the fin 66 and the nanostructure 55). For example, an oxide removal method can be used, which may use, for example, diluted hydrofluoric acid (dHF acid).

[0034] Also in Figure 4, suitable wells (not shown separately) can be formed in the fins 66 and / or nanostructures 55. In embodiments with different well morphologies, photoresist or other masks (not shown separately) can be used to achieve different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed above the fins 66 and nanostructures 55 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using spin coating technology and can be patterned using acceptable optical lithography techniques. Once the photoresist is patterned, n-type impurities are implanted in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The aforementioned n-type impurities may be phosphorus, arsenic, antimony, or similar substances, and their concentration implanted in the aforementioned region may be from approximately 10¹³ atoms / cm³ to approximately 10¹⁴ atoms / cm³. After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0035] Before or after the implantation of the p-type region 50P, a photoresist or other mask (not shown separately) may be formed over the fins 66 and nanostructures 55 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable optical lithography technique. Once the photoresist is patterned, p-type impurities may be implanted in the n-type region 50N, and the photoresist may act as a mask to substantially prevent the implantation of p-type impurities into the p-type region 50P. The p-type impurities may be boron, boron fluoride, indium, or the like, and their concentration implanted in the region may be from about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. The photoresist may be removed after implantation, for example by an acceptable ashing process.

[0036] After implanting the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, in-situ doping can be performed during the growth process of the epitaxial fin material, which can omit implantation, but in-situ doping and implantation doping can be used in combination.

[0037] In Figures 5A and 5B, a dummy gate 76 is formed along and above the sidewalls of the nanostructure 55 and the fin 66. To form the dummy gate 76, a dummy dielectric layer is first formed on the fin 66 and / or the nanostructure 55. The dummy dielectric layer may be silicon oxide, silicon nitride, a combination thereof, or similar materials, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer is formed above the dummy dielectric layer, and a masking layer is formed above the dummy gate layer. The dummy gate layer may be deposited above the dummy dielectric layer, and then planarized by methods such as chemical mechanical polishing. The masking layer may be deposited above the dummy gate layer. The aforementioned dummy gate layer can be a conductive or non-conductive material, and can be selected from the group including amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium, metal nitrides, metal silicates, metal oxides, and metals. The deposition of the aforementioned dummy gate layer can be performed by physical vapor deposition, chemical vapor deposition, sputtering deposition, or other techniques used for depositing the selected materials. The aforementioned dummy gate layer can be made of other materials that exhibit high etch selectivity relative to the etching of the isolation region. For example, the aforementioned masking layer may include, for example, silicon nitride, silicon oxynitride, or the like.

[0038] Subsequently, acceptable optical lithography and etching techniques can be used to pattern the mask layer to form mask 78. The pattern of mask 78 can then be transferred to the dummy gate layer and the dummy dielectric layer to form dummy gate 76 and dummy gate dielectric layer 70, respectively. Dummy gate 76 covers individual channel regions of fin 66. The pattern of mask 78 can be used to physically separate adjacent dummy gates 76 from each other. The length direction of the dummy gate 76 can also be substantially perpendicular to the length direction of the individual fin 66. It is worth noting that the illustrated dummy gate dielectric layer 70 only covers fin 66 and nanostructure 55 and is for illustrative purposes only. In some embodiments, dummy gate dielectric layer 70 can be deposited to cover shallow trench isolation region 68, such that dummy gate dielectric layer 70 extends between dummy gate 76 and shallow trench isolation region 68.

[0039] In Figures 6A and 6B, a plurality of gate spacers 81 are formed above the nanostructure 55 and the shallow trench isolation region 68, and on the exposed sidewalls of the mask 78 (if present), the dummy gate 76, and the dummy gate dielectric layer 70. The gate spacers 81 can be formed by conformally forming one or more dielectric materials, followed by etching of the dielectric materials. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like, which can be formed by a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar methods. Other insulating materials formed by any acceptable process may be used. Any acceptable etching process, such as dry etching, wet etching, similar processes, or combinations thereof, can be performed to pattern the dielectric materials. The etching may be anisotropic. The etched dielectric material is partially retained on the sidewalls of the dummy gate 76, thus forming a gate spacer 81. As detailed below, the etched dielectric material may also be partially retained on the sidewalls of the fin 66 (semiconductor fin) and / or the nanostructure 55, thus forming a fin spacer 83 (see Figure 7C). After etching, the fin spacer 83 and / or the gate spacer 81 may have straight sidewalls (as shown) or may have curved sidewalls (not shown separately).

[0040] Furthermore, the placement of lightly doped source / drain (LDD) regions (not shown separately) can be performed. The placement of the lightly doped source / drain regions can be performed before forming the gate spacer 81. In embodiments of different device types, similar to the placement used in the aforementioned well, a mask, such as a photoresist, can be formed over the n-type region 50N, exposing the p-type region 50P. A suitable type (e.g., p-type) of impurity can be placed into the fins 66 (semiconductor fins) and nanostructures 55 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over the p-type region 50P, exposing the n-type region 50N. A suitable type (e.g., n-type) of impurity can be placed into the fins 66 and nanostructures 55 exposed in the n-type region 50N. The mask can then be removed. The aforementioned n-type impurities can be any of the aforementioned n-type impurities, and the aforementioned p-type impurities can be any of the aforementioned p-type impurities. The impurity concentration in the lightly doped source / drain regions can be from 10¹⁵ atoms / cm³ to 10¹⁹ atoms / cm³. Annealing can be used to repair implantation damage and activate implanted impurities.

[0041] It is worth noting that the above disclosure describes a general process for forming spacers and lightly doped source / drain regions. Other processes and sequences may also be used. For example, fewer or additional spacers may be used, different step sequences may be used, additional spacers may be formed and removed, and / or similar adjustments may be made. Furthermore, different structures and steps may be used to form the above-mentioned n-type device and the above-mentioned p-type device.

[0042] In Figures 7A to 7C, according to some embodiments, a plurality of first recesses 86 are formed in the fin 66, nanostructure 55, and substrate 50. A plurality of epitaxial source / drain regions will subsequently be formed in the first recesses 86. The first recesses 86 may extend through the first nanostructure 52 and the second nanostructure 54 into the substrate 50. As shown in Figure 7C, the top surface of the shallow trench isolation region 68 may be flush with the bottom surface of the first recesses 86. In other embodiments, the fin 66 may be etched such that the bottom surface of the first recesses 86 is higher or lower than the top surface of the shallow trench isolation region 68. The first recesses 86 may be formed by etching the fin 66, nanostructure 55, and substrate 50 using an anisotropic etching process such as reactive ion etching, neutral beam etching, or similar etching. In the etching process described above for forming the first recess 86, the gate spacer 81, fin spacer 83, and mask 78 can mask portions of the fin 66, nanostructure 55, and substrate 50. A single etching process or multiple etching processes can be used to etch each layer of the nanostructure 55 and / or the fin 66. After the first recess 86 reaches the desired depth, a time-controlled etching process can be used to stop the etching of the first recess 86.

[0043] In Figures 8A to 9B, the first nanostructure 52 is replaced with a sacrificial material segment 72 (also considered as a disposable oxide interposer (DOI)). Replacing the first nanostructure 52 may include using a suitable etching process, such as an isotropic etching process, to etch away the first nanostructure 52 via a first recess 86, as shown in Figures 8A and 8B. The etching process described above may be selective in the material of the first nanostructure 52 and may remove the first nanostructure 52 without significantly removing the second nanostructure 54 or the fin 66 (semiconductor fin). In an embodiment where the first nanostructure 52 comprises, for example, silicon germanium and the second nanostructure 54 comprises, for example, silicon or silicon carbide, a dry etching process using tetramethylammonium hydroxide, ammonium hydroxide, or the like may be used to remove the first nanostructure 52.

[0044] Subsequently, a sacrificial material layer 71 is deposited in the space formed by the first recess 86 and the removal of the first nanostructure 52. The deposition of the sacrificial material layer 71 can be performed by a conformal deposition process, such as chemical vapor deposition, atomic layer deposition, or similar methods. The sacrificial material layer 71 may include an insulating material such as silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), or similar materials, and its etch selectivity differs from that of the second nanostructure 54.

[0045] In Figures 9A and 9B, the sacrificial material layer 71 may then be etched to form the sacrificial material segment 72. The etching may be isotropic or anisotropic. For example, the etching of the sacrificial material layer may be performed by a wet etching process using diluted hydrofluoric acid or the like as an etchant. In some embodiments, the etching is performed until the sidewalls of the sacrificial material segment 72 are more recessed than the sidewalls of the second nanostructure 54. Although the sidewalls of the sacrificial material segment 72 shown in Figure 9B are flat, these sidewalls may be concave or convex (see, for example, Figure 10C).

[0046] Replacing the first nanostructure 52 with a sacrificial material segment 72 can provide several advantages. For example, in subsequent source / drain formation steps, one or more high-temperature processes can be performed to activate the dopants in the aforementioned source / drain regions. When the material of the first nanostructure 52 (e.g., silicon-germanium) is exposed to high temperatures, germanium may mix between the first nanostructure 52 and the second nanostructure 54, increasing interface roughness. These manufacturing defects can degrade the performance of the resulting transistor device. For example, when germanium diffuses into the second nanostructure 54, germanium residues may remain in the channel regions of the resulting transistor device, negatively impacting the performance of the channel regions. By replacing the first nanostructure 52 with an insulating material prior to high-temperature processes (e.g., source / drain annealing), manufacturing defects can be reduced and device performance improved (e.g., increased drive current, reduced capacitance, and improved short-channel effect).

[0047] In Figures 10A and 10B, a plurality of inner spacers 90 are formed in a first recess 86 on the sidewall of the sacrificial material section 72. The inner spacers 90 can serve as isolation components between the subsequently formed source / drain regions and a gate structure. As detailed below, a plurality of source / drain regions can be formed in the first recess 86, and the sacrificial material section 72 will be replaced with the corresponding gate structure. The inner spacers 90 can also be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes, such as etching processes used to form the gate structure.

[0048] The inner spacer 90 can be formed by depositing an inner spacer layer (not shown separately) over the structures shown in Figures 10A and 10B. The deposition of the inner spacer layer can be performed using a conformal deposition process such as chemical vapor deposition, atomic layer deposition, or a similar process. The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, but any suitable material may be used, such as a low dielectric constant (low k) material with a dielectric constant lower than about 3.5. The inner spacer layer can then be anisotropically etched to form the inner spacer 90. The etching of the inner spacer layer can be performed using anisotropic etching processes such as reactive ion etching, neutral beam etching, or a similar process.

[0049] Although the outer sidewall of the inner spacer 90 is flush with the sidewall of the second nanostructure 54 as shown, the outer sidewall of the inner spacer 90 may extend beyond or be recessed from the sidewall of the second nanostructure 54 (see Figure 10C). Furthermore, although the outer sidewall of the inner spacer 90 is straight as shown in Figure 10B, the outer sidewall of the inner spacer 90 may be concave or convex. In one embodiment shown in Figure 10C, the sidewall of the sacrificial material segment 72 is concave, the outer sidewall of the inner spacer 90 is concave, and the inner spacer 90 is recessed from the sidewall of the second nanostructure 54. Other configurations are also possible. For example, in one embodiment shown in Figure 10D, the sidewall of the sacrificial material segment 72 is concave, the outer sidewall of the inner spacer 90 is straight, and the inner spacer 90 is flush with the sidewall of the second nanostructure 54.

[0050] In Figures 11A to 11D, epitaxial source / drain regions 92 are formed in the first recess 86. In some embodiments, the epitaxial source / drain regions 92 may apply stress to the second nanostructure 54 in the n-type region 50N and / or apply stress to the first nanostructure 52 in the p-type region 50P, thereby improving performance. As shown in Figure 11B, the epitaxial source / drain regions 92 are formed in the first recess 86 such that dummy gates 76 are each located between individual adjacent pairs of epitaxial source / drain regions 92. In some embodiments, gate spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, while inner spacers 90 are used to provide a suitable lateral distance between the epitaxial source / drain regions 92 and the sacrificial material segment 72, so that the epitaxial source / drain regions 92 do not short-circuit outward with the gate subsequently formed by the resulting nanostructure field-effect transistor.

[0051] The formation of the epitaxial source / drain region 92 in the n-type region 50N, such as an n-type metal-oxide-semiconductor region, can be achieved by masking the p-type region 50P, such as a p-type metal-oxide-semiconductor region. The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 within the n-type region 50N. The epitaxial source / drain region 92 may comprise any acceptable material suitable for an n-type nanostructure field-effect transistor. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 in the n-type region 50N may comprise a material that applies tensile stress to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like.

[0052] The formation of the epitaxial source / drain region 92 in the p-type region 50P, such as a p-type metal-oxide-semiconductor region, can be achieved by masking the n-type region 50N, such as an n-type metal-oxide-semiconductor region. The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 within the p-type region 50P. The epitaxial source / drain region 92 may comprise any acceptable material suitable for a p-type nanostructure field-effect transistor. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 in the p-type region 50P may comprise a material that applies compressive stress to the second nanostructure 54, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like.

[0053] Dopants can be implanted into the epitaxial source / drain region 92, the second nanostructure 54, and / or the substrate 50 to form the source / drain region, which is similar to the aforementioned process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the aforementioned source / drain region can be between about 1 x 10¹⁹ atoms / cm³ and about 1 x 10²¹ atoms / cm³. The n-type and / or p-type impurities used for the source / drain region can be any of the aforementioned impurities. In some embodiments, the epitaxial source / drain region 92 can be in-situ doped during the growth process.

[0054] The epitaxial process used to form epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P results in the upper surface of the epitaxial source / drain regions 92 having facets that laterally extend outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions of the same nanostructure field-effect transistor to merge, as shown in Figure 11C. In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as shown in Figure 11D. In the embodiments shown in Figures 11C and 11D, fin spacers 83 may be formed on the top surface of the shallow trench isolation region 68 to block epitaxial growth. In some other embodiments, fin spacers 83 may cover part of the sidewalls of the nanostructure 55 to further block epitaxial growth. In some other embodiments, the fin spacers 83 may be omitted, and the epitaxial growth region may extend to the surface of the shallow trench isolation region 68.

[0055] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used in the epitaxial source / drain region 92. The first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may each be formed of different semiconductor materials and may each be doped with different dopant concentrations. In some embodiments, the dopant concentration of the first semiconductor material layer 92A may be less than the dopant concentration of the second semiconductor material layer 92B and may be greater than the dopant concentration of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0056] In Figures 12A and 12B, a first interlayer dielectric layer 96 is deposited over the structures shown in Figures 11A and 11B, respectively. The first interlayer dielectric layer 96 may be formed of a dielectric material, and its deposition may be performed by any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. The dielectric material may include phospholipid glass, borosilicate glass, borosilicate glass, undoped silicate glass, or the like. Other insulating materials formed by any acceptable process may also be used. In some embodiments, a contact etch stop layer 94 is disposed between the first interlayer dielectric layer 96 and the epitaxial source / drain region 92, the mask 78, and the gate spacer 81. The contact etch stop layer 94 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having an etch rate different from the etch rate of the material of the first interlayer dielectric layer 96 thereon.

[0057] After depositing the first interlayer dielectric layer 96, a planarization process, such as chemical mechanical polishing, can be performed to make the top surface of the first interlayer dielectric layer 96 flush with the top surface of the dummy gate 76 (as shown) or the mask 78. The planarization process can also remove the mask 78 on the dummy gate 76, and portions of the gate spacer 81 along the sidewalls of the mask 78. After the planarization process, within process variations, the dummy gate 76, the gate spacer 81, and the top surface of the first interlayer dielectric layer 96 can be flush. In summary, the top surface of the dummy gate 76 is exposed via the first interlayer dielectric layer 96. In some embodiments, the mask 78 can be retained, in which case the planarization process flushes the top surface of the first interlayer dielectric layer 96 with the top surfaces of the mask 78 and the gate spacer 81.

[0058] In Figures 13A and 13B, the dummy gate 76 and the mask 78 (if present) are removed by one or more etching steps, thus forming a second recess 98. A portion of the dummy gate dielectric layer 70 may also be removed from the second recess 98. In some embodiments, the dummy gate 76 and the dummy gate dielectric layer 70 may be removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases to selectively etch the dummy gate 76 at a rate greater than the rate at which the first interlayer dielectric layer 96 or the gate spacer 81 is etched. Each of the second recesses 98 exposes a portion of the nanostructure 55 and / or is located on a portion of the nanostructure 55, which serves as a channel region in the subsequently completed nanostructure field-effect transistor. The portion of the nanostructure 55 serving as a channel region is positioned between adjacent pairs of epitaxial source / drain regions 92. During the removal process, when etching the dummy gate 76, the dummy gate dielectric layer 70 can serve as an etching stop layer. Then, after removing the dummy gate 76, the dummy gate dielectric layer 70 can be removed.

[0059] In Figures 14A and 14B, the sacrificial material segment 72 is removed to extend the second recess 98. Removing the sacrificial material segment 72 may include performing an isotropic etching process, such as wet etching using an etchant selective to the material of the sacrificial material segment 72, or a similar method, so that the second nanostructure 54 remains relatively unetched relative to the sacrificial material segment 72. The sacrificial material segment 72 may be completely removed, or a residue of the sacrificial material segment 72 may be left on the sidewalls of the inner spacers in the second recess 98 (see, for example, Figure 18D).

[0060] In some embodiments, the shallow trench isolation region 68 may be etched when the sacrificial material segment 72 is removed, but the total loss in the shallow trench isolation region 68 may be reduced by controlling the etching parameters (e.g., time) during the removal of the sacrificial material segment 72. In other embodiments, the shallow trench isolation region 68 may include a hard mask (not shown separately) on its top surface to protect the underlying shallow trench isolation region 68 from etching during patterning and removal of the sacrificial material segment 72. In such embodiments, the hard mask may include, for example, a nitride.

[0061] In Figures 15A to 15B, a gate dielectric layer 100 is formed according to some embodiments. The gate dielectric layer 100 is compliantly deposited in the second recess 98. The gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls, and bottom surface of the second nanostructure 54. In some embodiments, the gate dielectric layer 100 may also be deposited on the top surface of the first interlayer dielectric layer 96, the contact etch stop layer 94, the gate spacer 81, and the shallow trench isolation region 68. In such embodiments, excess gate dielectric layer on the top surface of the first interlayer dielectric layer 96, the contact etch stop layer 94, and the gate spacer 81 may be removed via a planarization process before or after the formation of the gate electrode 102 (described below).

[0062] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high dielectric constant material, and in these embodiments, the dielectric constant of the gate dielectric layer 100 is greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The method of forming the gate dielectric layer 100 may include molecular-beam deposition (MBD), atomic layer deposition, plasma-assisted chemical vapor deposition, or similar methods.

[0063] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by separate processes, such that the gate dielectric layer 100 in each region can be made of different materials and / or have different numbers of layers. When using separate processes, various masking steps can be used to mask and expose appropriate areas. In some embodiments, the height of the void between the second nanostructures (sometimes referred to as the space (Sn) between the second nanostructures) is 5 to 10 nanometers.

[0064] In Figures 16A to 18B, a multilayer gate electrode 102 is formed according to some embodiments.

[0065] Figures 16A and 16B illustrate the deposition of a first work function metal layer 102A of a gate electrode according to some embodiments. The first work function metal layer 102A is deposited above the gate dielectric layer 100 and above the exposed tops of the first interlayer dielectric layer 96, the gate spacer 81, and the contact etch stop layer 94. The first work function metal layer 102A may include a metal containing a metallic material such as titanium nitride, titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tungsten carbonitride (WCN), molybdenum nitride (MoN), aluminum-doped titanium carbide (TiAlC), or having an oxide form exhibiting high etch selectivity relative to the unoxidized form and / or other work function metals containing the gate dielectric layer 100 and the second nanostructure 54 (or the first nanostructure 52, in embodiments where the second nanostructure 54 is removed). The deposition of the first work function metal layer 102A may be performed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, or similar processes. In some embodiments, the first work function metal layer 102A may be between 1.0 nanometers and 3.5 nanometers thick.

[0066] The first work function metal layer 102A may include a p-type work function metal (PWFM) or an n-type work function metal (NWFM) to adjust the work function metal of a device to a desired amount given to the application of the device to be formed, and may be deposited using an acceptable deposition process. A masking layer may be patterned over the substrate 50 to prevent the first work function metal layer 102A from being deposited in a specific region. For example, if the first work function metal layer 102A is a p-type work function metal, the masking layer may be formed and patterned to cover the n-type region 50N to prevent the first work function metal layer 102A of the p-type work function metal from being deposited in the n-type region 50N. Any acceptable method may be used to form and pattern the masking layer. In some embodiments, the masking layer may be the same mask described above for forming the gate dielectric layer 100. Figure 16C shows an enlarged view of the portion partially framed in Figure 16A, providing a better illustration of the initial application of the first work function metal layer 102A.

[0067] As shown in Figure 16D, according to some embodiments, the first work function metal layer 102A can then undergo a gradual heating oxidation process to transform a portion of the first work function metal layer 102A into a surface oxide layer 103. For example, in the case where the first work function metal layer 102A is titanium nitride (TiN), the above oxidation process results in the formation of a surface oxide layer 103 of titanium oxide (TiO₂), while nitrogen is released as a byproduct. The above oxidation process is generally an outside-in process, wherein the surface layer of the first work function metal layer 102A oxidizes first when exposed to an oxygen-rich environment, causing the oxidized metal surface oxide layer 103 to gradually transition to the originally deposited work function metal and the covered second nanostructure 54 closer to the inner surface of the first work function metal layer 102A. The dashed line between the first work function metal layer 102A and the surface oxide layer 103 in Figure 16D represents that the oxidation is gradual and there may not be a clear boundary between these layers.

[0068] Due to the stacking and proximity of the second nanostructures 54 (according to the embodiments shown in Figures 14A to 21C, where the first nanostructure 52 is a removed nanostructure), the oxidation process described above can be controlled to preferentially oxidize the first work function metal layer 102A on the outer portion of the stack of the second nanostructures 54 (for example: the top and sides of the stack of the second nanostructures 54), thereby substantially converting the outer portion of the first work function metal layer 102A into a surface oxide layer 103. However, due to the confined space between the second nanostructures 54 and the fins 66 of the substrate at the bottom of the second nanostructures 54, the first work function metal layer 102A located in these regions will oxidize at a slower rate, resulting in thicker unoxidized portions of the first work function metal layer 102A in these regions as schematically shown in Figure 16D (and a thinner surface oxide layer 103 closer to the center of the pore between the vertically adjacent second nanostructures 54).

[0069] For example, as shown in Figure 16D, where the first work function metal layer 102A is deposited as a titanium nitride (TiN) layer, the oxidation process described above can be controlled to substantially allow most of the surface of the first work function metal layer 102A not located in the voids between the second nanostructures 54 to be oxidized to produce a surface oxide layer 103 of titanium oxide (TiO₂). However, a large portion of the first work function metal layer 102A located between the second nanostructures 54 may remain, for example, as titanium nitride (TiN). In the embodiment shown in Figure 16C, transforming the first work function metal layer 102A into a surface oxide layer 103 may result in a roughly elongated shape for the remaining unoxidized portion of the first work function metal layer 102A in the voids between the second nanostructures 54. However, it is anticipated that the remaining first work function metal layer 102A will have other shapes, which may include protruding or recessed shapes at the entrances of the voids between the second nanostructures 54, for example, as shown in Figure 16D. The gradient oxidation of the first work function metal layer 102A can be selected from any suitable heating and plasma treatment. In some embodiments, the oxidation process of the first work function metal layer 102A can be performed using a temperature in the range of 25°C to 650°C and a pressure in the range of 1 to 200 torr.

[0070] In Figures 17A and 17B, according to some embodiments, the first work function metal layer 102A undergoes a selective etching process. The oxidized portion of the first work function metal layer 102A (facing the substrate metal) can be removed using highly selective etching, creating a V-shaped sheet-to-sheet opening profile between the second nanostructures 54. This is shown more clearly in Figure 17, which is an enlarged view of the portion partially framed in Figure 17A. While the embodiment shown in Figure 17C displays a coarse linear inclination of the remaining first work function metal layer 102A, other shapes are also expected to cause the apertures between the second nanostructures 54 to gradually narrow towards the centerline. For example, as shown in Figure 17D, the remaining first work function metal layer 102A may have a protruding or recessed shape at the entrance to the apertures between the second nanostructures 54.

[0071] In some embodiments, the selective etching described above can be performed using tungsten chloride (WCl5), tungsten fluoride (WF6), or some other metal halide gases. In some embodiments, the etching can be performed in a temperature range between 200°C and 600°C. In some embodiments, the first work function metal layer 102A can be completely removed from the outer portion of the stack of second nanostructures 54, leaving the first work function metal layer 102A only in the region between the second nanostructures 54 and in the region between the bottom second nanostructure 54A and the fin 66 of the substrate.

[0072] In some embodiments, the unoxidized base metal layer of the first work function metal layer 102A may be retained and cover each second nanostructure 54. In such cases where a portion of the first work function metal layer 102A is left around the outer portion of the second nanostructure 54 after the aforementioned oxidation and etching processes, the unoxidized portion of the first work function metal layer 102A can serve as an etching stop for the removal of the surface oxide layer 103 using the aforementioned selective etching process. In some embodiments, the first work function metal layer 102A may be between 0.5 nm and 3 nm thick between adjacent second nanostructures 54, and between 0 nm and 1 nm thick outside the channel portion. In some embodiments, the minimum distance (Dmin, see Figure 17C) between the first work function metal layers 102A on adjacent second nanostructures 54 may be between 0.0 nm and 9.0 nm.

[0073] Figures 18A and 18B show a second work function metal layer 102B according to some embodiments. The second work function metal layer 102B is deposited above the first work function metal layer 102A and the gate dielectric layer 100 to completely or partially fill the gate electrode 102 (a structure including both the first work function metal layer 102A and the second work function metal layer 102B). In some embodiments, the gate electrode 102 may further include a filler metal together with the second work function metal layer 102B. In some embodiments, the second work function metal layer 102B or the aforementioned filler metal may also be deposited above the exposed top of the first interlayer dielectric layer 96, the gate spacer 81, and the contact etch stop layer 94, and removed from the top of the aforementioned structure via a planarization process described later. The second work function metal layer 102B may include a metallic material, such as titanium nitride, titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tungsten carbonitride (WCN), molybdenum nitride (MoN), aluminum-doped titanium carbide (TiAlC), or other work function metals. In some embodiments, the second work function metal layer 102B has a minimum thickness between 1 nanometer and 5 nanometers in the region of the stacked channel of the second nanostructure 54. In some embodiments, the second work function metal layer 102B may be selected for specific threshold voltage regulation characteristics.

[0074] For simplicity, the formation of gate electrodes 102 in the n-type region 50N and p-type region 50P has been shown in the foregoing and figures as occurring simultaneously. However, due to the differences in the operation and materials used in the n-type and p-type semiconductors, it is desirable to apply different deposition processes to the n-type region 50N and p-type region 50P respectively. For example, a first work function metal layer 102A can be formed in both the n-type region 50N and p-type region 50P, while a second work function metal layer 102B can only be formed in, for example, the n-type region 50N. In some embodiments, the first work function metal layer 102A and the second work function metal layer 102B can be formed from the same material across multiple regions and region morphologies (for example: n-type region 50N and p-type region 50P). However, it is desirable to have embodiments consistent with this disclosure in which the gate electrode 102 in each region can be formed by different processes, so that the gate electrode 102 in the n-type region 50N can be a different material and / or have a different number of layers compared to the p-type region 50P. In addition to the first work function metal layer 102A and the second work function metal layer 102B, the gate electrode 102 may include other layers, such as one or more adhesive layers, one or more conditioning layers deposited prior to the first work function metal layer 102A, filler metal, or the like. Various masking steps can also be used when using different processes to mask and expose suitable areas, consistent with the previously disclosed uses.

[0075] By utilizing the aforementioned deposition, oxidation, etching, and filling techniques, the interlayer filling efficiency of the work function metal in a fully wound gate structure is improved, and the gaps between interfaces are reduced. Furthermore, high selectivity for selective etching of the oxide layer can be achieved, resulting in reduced impact of the oxidation and etching processes on other layers. Breakdown reduction is also achieved, fin top damage is suppressed, and it helps maintain complete coverage of the metal capping layer.

[0076] After filling the second recess 98, a planarization process, such as chemical mechanical polishing, can be performed to remove excess material from the gate dielectric layer 100 and gate electrode 102 above the upper surface of the first interlayer dielectric layer 96. The remaining material from the gate electrode 102 and gate dielectric layer 100 thus forms a replacement gate structure for the formed nanostructured field-effect transistor. The gate electrode 102 (including at least a first work function metal layer 102A and / or a second work function metal layer 102B) and the gate dielectric layer 100 can be considered together as a "gate structure".

[0077] Figures 18C and 18D (respectively) show detailed views of various components in Figures 18A and 18B, including epitaxial source / drain regions 92, gate dielectric layer 100, gate electrode 102 (including at least a first work function metal layer 102A and / or a second work function metal layer 102B), second nanostructure 54, and inner spacer 90. In some embodiments, as shown in Figure 18D, residues of sacrificial material 72 may remain on the inner spacer 90, for example, between the inner spacer 90 and the gate dielectric layer 100 / gate electrode 102. For example, the sacrificial material segment 72 may not be completely removed, and the gate dielectric layer 100 may be formed on the remaining sacrificial material segment 72. Since the sacrificial material segment 72 is an insulating material (for example, silicon oxide), the remaining residue may not significantly affect the electrical performance of the formed device.

[0078] In Figures 19A to 19C, the gate structure (including the gate dielectric layer 100 and its corresponding gate electrode 102) is recessed to form a recess directly above the gate structure and between opposing portions of the gate spacer 81. A gate shield 104 comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, may be filled into the recess, followed by a planarization process to remove excess portions of the dielectric material extending above the first interlayer dielectric layer 96. A subsequently formed gate contact (e.g., gate contact 114 illustrated below with reference to Figures 21A to 21C) passes through the gate shield 104 to contact the top surface of the recessed gate 102.

[0079] As shown in Figures 19A to 19C, a second interlayer dielectric layer 106 is deposited above the first interlayer dielectric layer 96 and above the gate shield 104. In some embodiments, the second interlayer dielectric layer 106 is a flowable film formed by flowable chemical vapor deposition. In some embodiments, the second interlayer dielectric layer 106 is formed of a dielectric material such as phospholipid glass, borosilicate glass, borosilicate glass, undoped silicate glass, or the like, and its deposition can be by any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or similar methods.

[0080] In Figures 20A to 20C, the second interlayer dielectric layer 106, the first interlayer dielectric layer 96, the contact etch stop layer 94, and the gate mask 104 are etched to form a third recess 108, exposing the epitaxial source / drain region 92 and / or the surface of the aforementioned gate structure. The third recess 108 can be formed by an anisotropic etching process, such as reactive ion etching, neutral beam etching, or a similar process. In some embodiments, a first etching process can be used to etch through the second interlayer dielectric layer 106 and the first interlayer dielectric layer 96, a second etching process can be used to etch through the gate mask 104, and then a third etching process can be used to etch through the contact etch stop layer 94 to etch out the third recess 108. A mask, such as a photoresist, can be formed and patterned over the second interlayer dielectric layer 106 to shield a portion of the second interlayer dielectric layer 106 from the aforementioned first and second etching processes. In some embodiments, the etching process described above may over-etch, therefore the third recess 108 extends into the epitaxial source / drain region 92 and / or the gate structure, and the bottom of the third recess 108 may be flush with (for example: at the same level or at the same distance from the substrate) or lower than (for example: closer to the substrate) the epitaxial source / drain region 92 and / or the gate structure. Although Figure 20B illustrates the third recess 108 as exposing the epitaxial source / drain region 92 and the gate structure in the same cross-section, in various embodiments the epitaxial source / drain region 92 and the gate structure may be exposed in different cross-sections, thereby reducing the risk of short circuits with subsequently formed contacts.

[0081] After forming the third recess 108, a plurality of silicide regions 110 can be formed above the epitaxial source / drain region 92. In some embodiments, the silicide regions 110 are formed by first depositing a metal (not shown) that can react with the semiconductor material of the underlying epitaxial source / drain region 92 (for example, reacting with silicon, silicon-germanium, or germanium) to form silicide or germanide regions. For example, metals that can be used include nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The aforementioned metals can be deposited above the exposed portion of the epitaxial source / drain region 92. The silicide regions 110 can then be formed using a heat annealing process. The unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicate region 110 is considered a silicate region, it can also be a germanide region or a silicon-germanide region (for example, a region containing both silicate and germanide). In one embodiment, the silicate region 110 includes titanium silicate having a thickness in the range of about 2 nm to about 10 nm.

[0082] Next, in Figures 21A to 21C, contacts 112 and 114 (which can also be considered as contact plugs) are formed in the third recess 108. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to a conductive component below (for example, the gate electrode 102 and / or the silicate region 110 in the illustrated embodiment). Contact 114 is electrically coupled to the gate electrode 102 and can be considered as a gate contact, while contact 112 is electrically coupled to the silicate region 110 and can be considered as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material from the surface of the second interlayer dielectric layer 106.

[0083] By utilizing the aforementioned technology, the interlayer filling efficiency of the work function metal in a fully wound gate structure is improved, and the gaps between interfaces are reduced. Furthermore, high selectivity for selective etching of the oxide layer can be achieved, resulting in reduced impact of the oxidation and etching processes on other layers. Breakdown reduction is also achieved, fin top damage is suppressed, and it helps maintain complete coverage of the metal capping layer. Therefore, smaller and thinner components can be realized, resulting in increased miniaturization, improved efficiency, reduced energy consumption, and reduced energy loss and heat generation.

[0084] In a first embodiment, a method is provided, the method comprising: forming a multilayer stacked structure over a substrate, the multilayer stacked structure including a plurality of layers alternating between a first semiconductor material and a second semiconductor material; patterning the multilayer stacked structure as a fin, the fin including and alternating between a plurality of first nanostructures of the first semiconductor material and at least two second nanostructures of the second semiconductor material in a first region of the substrate; removing the first nanostructures from the multilayer stacked structure in the first region of the substrate; forming a first work function metal layer around each of the at least two second nanostructures; partially oxidizing the first work function metal layer, wherein an unoxidized portion remains in the region between the at least two second nanostructures; removing the oxidized portion of the first work function metal layer; and forming a second work function metal layer around each of the at least two second nanostructures, wherein the second work function metal layer and the first work function metal layer fill the space between the at least two second nanostructures.

[0085] In some embodiments, the method further includes, before forming the first work function metal layer and after removing the first nanostructure, forming a sacrificial material between the layers of the first region and the second semiconductor material; forming a plurality of source / drain regions adjacent to the at least two second nanostructures in the first region and the sacrificial material; and removing the sacrificial material between the at least two second nanostructures. In some embodiments, the sacrificial material is selected from the group consisting of silicon oxide, silicon oxynitride, and aluminum oxide. In some embodiments, the method further includes forming a plurality of inner spacers on the sidewalls of the sacrificial material before forming the source / drain regions, wherein the dielectric constant of the inner spacers is less than 3.5. In some embodiments, the inner spacers include silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the local oxidation of the first work function metal layer includes heating oxidation in the range of 25°C to 650°C. In some embodiments, removing the oxide portion of the first work function metal layer includes selective etching using a gas comprising a metal halide gas in the range of 25°C to 650°C. In some embodiments, before the first work function metal layer is locally oxidized, the first work function metal layer has a thickness between 1.0 nm and 3.5 nm. In some embodiments, after removing the oxide portion of the first work function metal layer, the first work function metal layer has a thickness between 0.5 nm and 3.0 nm in the region between the at least two second nanostructures, the first work function metal layer thinning towards the outer side of the region between the at least two second nanostructures and thickening towards the center of the region between the at least two second nanostructures, forming a V-shaped profile between the at least two second nanostructures.

[0086] In a second embodiment, a method is provided, the method comprising: forming a first work function metal layer around a first nanostructure in a fin disposed above a substrate; at least partially oxidizing the first work function metal layer, wherein the first work function metal layer between the first nanostructure and an adjacent second nanostructure in the stack of the fins is less oxidized; removing the oxidized portion of the first work function metal layer from around the first nanostructure; and forming a second work function metal layer around the first nanostructure, wherein the first work function metal layer and the second work function metal layer fill a void between the first nanostructure and the adjacent second nanostructure.

[0087] In some embodiments, the first work function metal layer is between 1.0 nm and 3.5 nm thick before oxidation, and the first work function metal layer does not completely fill the voids between the first nanostructure and the adjacent second nanostructure. In some embodiments, after removing the oxidized portion of the first work function metal layer, the first work function metal layer on the first nanostructure has a thickness between 0.5 nm and 3.0 nm in the voids between the first nanostructure and the adjacent second nanostructure. The first work function metal layer thins as it approaches the sidewall of the fin and thickens as it approaches the centerline of the fin, forming a V-shaped profile at the opposing entrances of the voids between the first nanostructure and the adjacent second nanostructure. In some embodiments, the first work function metal layer comprises at least one of titanium nitride, titanium silicon nitride, titanium aluminum nitride, tungsten carbonitride, molybdenum nitride, and aluminum-doped titanium carbide; and the first work function metal layer is at least partially oxidized, including thermal oxidation in the range of 25°C to 650°C. In some embodiments, removing the oxidized portion of the first work function metal layer from around the first nanostructure comprises selective etching using a metal halide gas in the range of 200°C to 600°C. In some embodiments, before forming the first work function metal layer around the first nanostructure, the method further comprises removing a polishable oxide intermediary between the first nanostructure and the adjacent second nanostructure to form the aforementioned void between the first nanostructure and the adjacent second nanostructure; and forming a gate dielectric layer around the first nanostructure and the adjacent second nanostructure. In some embodiments, the gate dielectric layer is between 2.0 nanometers and 10.0 nanometers thick. In some embodiments, the aforementioned disposable oxide medium is formed from a material selected from the group consisting of silicon oxide, silicon oxynitride, and aluminum oxide.

[0088] In a third embodiment, a semiconductor device is provided, the device comprising: a first nanostructure and a second nanostructure in a stack above a substrate fin; a gate dielectric layer surrounding the first nanostructure and the second nanostructure; a first work function metal layer filling a portion of a space between the first nanostructure and the second nanostructure and disposed on each of the first nanostructure and the second nanostructure; a second work function metal layer filling at least a portion of the remaining portion of the space between the first nanostructure and the second nanostructure not filled by the first work function metal layer; an epitaxial source / drain region on an adjacent side of the stack; and a gate electrode including the first work function metal layer and the second work function metal layer.

[0089] In some embodiments of the above-described semiconductor device, the first work function metal layer forms a V-shaped entrance into the space between the first nanostructure and the second nanostructure, wherein the distance between the first work function metal layer on the first nanostructure and the first work function metal layer on the second nanostructure widens as it approaches the sidewall of the stack and narrows to a minimum distance towards a centerline of the stack. In some embodiments of the above-described semiconductor device, the first work function metal layer comprises a material selected from the group consisting of titanium nitride, titanium silicon nitride, titanium aluminum nitride, tungsten carbonitride, molybdenum nitride, and aluminum-doped titanium carbide.

[0090] The foregoing outlines features of many embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the inventive spirit and scope of the embodiments of the present invention. [Simplified Explanation of the Diagram]

[0007] The contents disclosed herein can be better understood by reading the following detailed description in conjunction with the accompanying drawings. It should be emphasized that, according to industry standard operating procedures, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily enlarged or reduced for clear discussion. Figure 1 is a three-dimensional diagram illustrating an example of a nanostructure field-effect transistor (nano-FET) according to some embodiments. Figures 2, 3, 4, 5A, 5B, 6A, 6B, 7A, 7B, 7C, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 10D, 11A, 11B, 11C, 11D, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, and 16B are various diagrams illustrating intermediate steps in the manufacture of nanostructure field-effect transistors according to some embodiments. Figure 16C is a partial detailed diagram of Figure 16A before the oxidation of a first work function metal layer, according to some embodiments. Figure 16D is a partial detailed diagram of Figure 16A after the oxidation of the first work function metal layer, according to some embodiments. Figure 16E is a partial detailed diagram of possible alternative embodiments of the oxidized first work function metal layer, according to some embodiments. Figures 17A and 17B are diagrams of various intermediate steps in fabricating nanostructured field-effect transistors, according to some embodiments. Figure 17C is a partial detailed diagram of Figure 17A, according to some embodiments. Figure 17D is a partial detailed diagram of possible alternative embodiments of the first work function metal layer after the removal of the surface oxide layer, according to some embodiments. Figures 18A and 18B are diagrams of various intermediate steps in fabricating nanostructured field-effect transistors, according to some embodiments. Figures 18C and 18D are partial detailed diagrams of Figures 18A and 18B, respectively, according to some embodiments. Figures 19A, 19B, 19C, 20A, 20B, 20C, 21A, 21B, and 21C are diagrams illustrating various intermediate steps in the fabrication of nanostructured field-effect transistors, according to some embodiments.

Claims

1. A method for forming a semiconductor device, comprising: A multilayer stacked structure is formed on a substrate, the multilayer stacked structure including a plurality of alternating layers of a first semiconductor material and a second semiconductor material; the multilayer stacked structure is patterned as a fin, the fin including and alternating a plurality of first nanostructures of the first semiconductor material and at least two second nanostructures of the second semiconductor material in a first region of the substrate; the first nanostructures in the first region of the substrate are removed from the multilayer stacked structure; a first work function metal layer is formed around each of the at least two second nanostructures; the first work function metal layer is locally oxidized, wherein an unoxidized portion remains in the region between the at least two second nanostructures; the oxidized portion of the first work function metal layer is removed; and a second work function metal layer is formed around each of the at least two second nanostructures, wherein the second work function metal layer and the first work function metal layer fill the space between the at least two second nanostructures.

2. The method of forming a semiconductor device as described in claim 1, further comprising, before forming the first work function metal layer and after removing the first nanostructures: A sacrificial material is formed in the first region and between the layers of the second semiconductor material; Forming a plurality of source / drain regions adjacent to the at least two second nanostructures and the sacrificial material in the first region; and removing the sacrificial material between the at least two second nanostructures.

3. The method of forming a semiconductor device as described in claim 2 further includes: Before forming these source / drain regions, a plurality of inner spacers are formed on the sidewalls of the sacrificial material, wherein the dielectric constant of these inner spacers is less than 3.

5.

4. A method for forming a semiconductor device as claimed in any one of claims 1 to 3, wherein after removing the oxide portion of the first work function metal layer, the first work function metal layer has a thickness between 0.5 nanometers and 3.0 nanometers in the region between the at least two second nanostructures, the first work function metal layer thins as it approaches the outer side of the region between the at least two second nanostructures, and the first work function metal layer thickens as it approaches the center of the region between the at least two second nanostructures, forming a V-shaped profile between the at least two second nanostructures.

5. A method for forming a semiconductor device, comprising: A first work function metal layer is formed around a first nanostructure in a fin placed above a substrate; The first work function metal layer is at least partially oxidized, wherein the first work function metal layer between the first nanostructures and an adjacent second nanostructure in the stack of fins is less oxidized; the oxidized portion of the first work function metal layer is removed from around the first nanostructure; and a second work function metal layer is formed around the first nanostructures, wherein the first work function metal layer and the second work function metal layer fill a void between the first nanostructure and the adjacent second nanostructure.

6. The method of forming a semiconductor device as claimed in claim 5, wherein after removing the oxidized portion of the first work function metal layer, a V-shaped profile is formed at the opposing entrance of the aperture between the first nanostructure and the adjacent second nanostructure in the aperture between the first nanostructure and the adjacent second nanostructure, wherein the first work function metal layer on the first nanostructure has a thickness between 0.5 nanometers and 3.0 nanometers, the first work function metal layer thins as it approaches the sidewall of the fin, and the first work function metal layer thickens as it approaches the centerline of the fin.

7. A method for forming a semiconductor device as claimed in claim 5, wherein removing the oxidized portion of the first work function metal layer from around the first nanostructure includes: Selective etching is performed using metal halide gases in the range of 200°C to 600°C.

8. A semiconductor device, comprising: A first nanostructure and a second nanostructure are in a stack above a substrate fin; A gate dielectric layer surrounding the first nanostructure and the second nanostructure; a first work function metal layer filling a portion of a space between the first nanostructure and the second nanostructure and disposed on each of the first nanostructure and the second nanostructure; a second work function metal layer filling at least a portion of the remaining portion of the space between the first nanostructure and the second nanostructure that is not filled by the first work function metal layer; an epitaxial source / drain region on an adjacent side of the stack; and a gate electrode including the first work function metal layer and the second work function metal layer.

9. The semiconductor device of claim 8, wherein the first work function metal layer forms a V-shaped entrance to the space between the first nanostructure and the second nanostructure, wherein the distance between the first work function metal layer on the first nanostructure and the first work function metal layer on the second nanostructure widens as it approaches the sidewall of the stack and narrows to a minimum distance toward a centerline of the stack.

10. The semiconductor device as claimed in claim 8 or 9, wherein the first work function metal layer comprises a material selected from the group consisting of titanium nitride, titanium silicon nitride, titanium aluminum nitride, tungsten carbonitride, molybdenum nitride, and aluminum-doped titanium carbide.

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