Die-level parametric prediction boosting method and system for improving prediction accuracy by incorporating physical location parametric data

TWI937625BActive Publication Date: 2026-09-01MEDIATEK INC
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Patent Information

Application Number
TW113145800
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Priority Date
2024-11-14
Filing Date
2024-11-27
Publication Date
2026-09-01
Estimated Expiration
2044-11-26

AI Technical Summary

Technical Problem

Existing methods for identifying anomalous integrated circuits (ICs) struggle with inaccurate parameter predictions due to varying electrical characteristics among ICs, lacking sufficient incorporation of additional information about the ICs themselves.

Method used

A method and system that combines physical location parameter data with electrical parameter features using a training model, such as a neural network, to generate accurate grain-level predictions by inputting data from a wafer image, enhancing prediction accuracy through deep learning or machine learning processes.

Benefits of technology

Improves prediction accuracy by leveraging physical location parameters alongside electrical features, enabling more precise identification of anomalous ICs and simplifying subsequent testing procedures.

✦ Generated by Eureka AI based on patent content.

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Patent Text Reader

Abstract

A method for improving grain-level parameter prediction includes obtaining a wafer image containing a plurality of grains, selecting one grain from the plurality of grains, inputting the physical location parameter data and a plurality of electrical parameter features of the grain into a training model, and generating prediction data of the grain by the training model based on the physical location parameter data and the plurality of electrical parameter features.
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Description

Technical Field

[0001] This invention relates to semiconductor technology, and in particular to a method and system for improving grain-level parameter prediction. Prior Technology

[0002] With the rapid development of technology, various chips and integrated circuits (ICs) are widely used in our daily lives. Therefore, various electronic applications require high-quality ICs with low operational risks. In the silicon testing process, to provide high-quality ICs with low operational risks, abnormal ICs are identified and flagged by analyzing measured test data.

[0003] However, in traditional methods for identifying anomalous ICs, some anomalous ICs can be identified based on their measurement and test data. It should be understood that different ICs have different electrical parameter characteristics. Because these electrical parameter characteristics vary among ICs, generating accurate predictions based on these characteristics is difficult without incorporating additional information about the ICs themselves.

[0004] Therefore, developing a parameter prediction system that can improve prediction accuracy is an important design problem. Summary of the Invention

[0005] In one embodiment of the present invention, a method for improving grain-level parameter prediction is disclosed. This method includes acquiring a wafer image comprising a plurality of grains, selecting one grain from the plurality of grains, inputting physical location parameter data and a plurality of electrical parameter features of the grain into a training model, and generating prediction data for the grain from the training model based on the physical location parameter data and the plurality of electrical parameter features.

[0006] In another embodiment of the present invention, a grain-level parameter prediction and improvement system is disclosed. This system includes a large-scale production data source and a training model. The training model is connected to the large-scale production data source. After obtaining a wafer image comprising a plurality of grains from the large-scale production data source, a grain is selected from the plurality of grains. The physical location parameters of the grain and a plurality of electrical parameter features of the grain are input into the training model. The training model generates prediction data for the grain based on the physical location parameters and the plurality of electrical parameter features.

[0007] These and other objectives of the present invention will undoubtedly become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments depicted in various figures and diagrams. Simple Explanation of the Diagram

[0008] Figure 1 is a block diagram of a grain-level parameter prediction and enhancement system according to an embodiment of the present invention. Figure 2 is an inset of the physical features of the wafer diagram of the grain-level parameter prediction enhancement system in Figure 1. Figure 3 is a flowchart of the grain-level parameter prediction and improvement method executed by the grain-level parameter prediction and improvement system in Figure 1. Implementation

[0009] Figure 1 is a block diagram of a grain-level parameter prediction and enhancement system 100 according to an embodiment of the present invention. The grain-level parameter prediction and enhancement system 100 includes a mass production data source 10 and a training model 11. The training model 11 is connected to the mass production data source 10. The mass production data source 10 can be at least one stage node of a wafer test line. For example, the mass production data source 10 can be a wafer probe (CP) stage node or a final test (FT) stage node. The CP stage node or the FT stage node can provide mass production data. In another embodiment, the mass production data source 10 can be both a CP stage node and an FT stage node of a wafer test line. The CP stage node and the FT stage node can jointly provide mass production data. The training model 11 can emulate a neural network architecture. Therefore, the training model 11 can perform processes related to deep learning or machine learning. In the grain-level parameter prediction and enhancement system 100, after obtaining a wafer map containing a plurality of grains from the mass production data source 10, a grain is selected from the plurality of grains. The wafer map can be predefined based on the mass production data obtained from the mass production data source 10. Then, the physical location parameter data D2 of the grain and the complex electrical parameter features D1 are input into the training model 11. Finally, the training model 11 can generate (or infer) the predicted data D3 of the grain based on the physical location parameter data D2 and the complex electrical parameter features D1. The details of the grain-level parameter prediction improvement method are shown below.

[0010] In the grain-level parameter prediction enhancement system 100, the training model 11 can obtain a plurality of electrical parameter features of the grain based on a large amount of production data. Specifically, the plurality of electrical parameter features of the grain may include wafer speed, wafer power leakage, or wafer minimum voltage measured by sensors or detectors embedded in the grain. For example, N electrical parameter features of the i-th grain on the wafer map can be input into the training model 11. The N electrical parameter features of the i-th grain on the wafer map (as shown in D1 in Figure 1) can be represented as Table T1. Table T1 Index n=1 Electrical parameter characteristics-1(i) Index n=2 Electrical parameter characteristics - 2(i) ⋮ ⋮ Index n=N Electrical parameter characteristics - N(i)

[0011] N is a positive integer. Therefore, when M dies are selected, N×M electrical parameter features can be input into the training model 11 to infer the predicted data D3. Here, the distribution of the M dies on the wafer map can be arbitrary. M is a positive integer. In the grain-level parameter prediction enhancement system 100, the predicted data D3 of the dies can include an on / off current, a threshold voltage, or channel information of a metal-oxide-semiconductor field-effect transistor (MOSFET). Any hardware or technical modifications are within the scope of this invention.

[0012] As previously described, training model 11 can embody a neural network architecture. Therefore, training model 11 should be fully trained before inferring prediction data D3. In one embodiment, grain training data can be obtained from CP stage nodes or FT stage nodes. Training model 11 may include pre-trained electrical feature information for each grain in the wafer diagram. Then, after obtaining the grain training data, training model 11 is built based on the grain training data. Gradient validation data can then be used to determine whether training model 11 has been fully trained. When training model 11 is not fully trained, it is retrained or continuously trained based on the grain training data. When training model 11 is fully trained, it is output as the final training model to generate prediction data D3. In this embodiment, training model 11 can be implemented using any neural network architecture, such as a convolutional neural network (CNN) or a recurrent neural network (RNN).

[0013] Figure 2 is a schematic diagram of the physical characteristics of the wafer map 12 of the grain-level parameter prediction enhancement system 100. The wafer map 12 can be viewed as a discrete map of grains with approximately circular boundaries. The wafer center O is marked as the center of the circular wafer map 12. A grain DA is selected from a plurality of grains in the wafer map 12. The coordinates of the center of grain DA are represented as (X, Y). The distance from the center of grain DA to the wafer center O is represented as d. In this embodiment, the physical location parameter data D2 of grain DA may include the coordinates (X, Y) of the center of grain DA on the wafer map 12, and the distance d from the center of grain DA to the wafer center O. As previously described, the training model 11 may include information on the pre-trained electrical characteristics of each grain in the wafer map 12. Therefore, when the physical location parameter data D2 of grain DA is input to the training model 11, the physical location parameter data D2 can be used to assist the training model 11 in inferring accurate prediction data D3. However, any technical modifications are within the scope of this invention. For example, in another embodiment, the information of the wafer center O is pre-configured in the training model 11. Therefore, when the coordinates (X, Y) of the center of die DA are input into the training model 11, the distance from the center of die DA to the wafer center O can be derived as √((Xa)^2 - (Xb)^2). Here, the coordinates of the wafer center O are represented as (a, b). In another embodiment, the physical location parameter data D2 of die DA can further include the electrical variations of dies adjacent to die DA. In other words, the features of “adjacent” dies can be used to enhance the prediction accuracy of the inferred prediction data D3, since the physical or electrical distributions of die DA and “adjacent” dies are similar. After the training model 11 infers the prediction data D3, the prediction data D3 can be used to simplify subsequent testing procedures. Furthermore, after the training model 11 infers the prediction data D3, the neural network can use the training model 11 to identify anomalous dies among a plurality of dies based on the prediction data.

[0014] Figure 3 is a flowchart of the grain-level parameter prediction and improvement method, performed by the grain-level parameter prediction and improvement system 100. The grain-level parameter prediction and improvement method includes steps S301 to S304. Any technical or hardware modifications are within the scope of this invention. Steps S301 to S304 are shown below.

[0015] Step S301: Obtain a wafer image 12, which includes a plurality of grains.

[0016] Step S302: Select a grain DA from the plurality of grains.

[0017] Step S303: Input the physical location parameter data D2 of the grain DA and the complex electrical parameter features D1 of the grain DA into the training model 11.

[0018] Step S304: The training model 11 generates prediction data D3 for the grain DA based on the physical location parameter data D2 and the multiple electrical parameter features D1.

[0019] The details of steps S301 to S304 have been previously described and are therefore omitted here. In the grain-level parameter prediction enhancement system 100, the physical location parameter data D2 of the grain DA, together with a plurality of electrical parameter features D1, is used to enhance the prediction accuracy of the training model 11 inferring prediction data D3. In particular, the physical location parameter data D2 may include the coordinates (X, Y) of the center of the grain DA and the distance d from the center of the grain DA to the wafer center O. Therefore, the additional amount of data and additional computation required to enhance the prediction accuracy of the inferred prediction data D3 can be minimized.

[0020] In summary, this invention discloses a grain-level parameter prediction enhancement method and a grain-level parameter prediction enhancement system. The grain-level parameter prediction enhancement system can combine physical location parameter data with multiple electrical parameter features to infer prediction data. Although using electrical parameter features when inferring prediction data may complicate achieving high prediction accuracy, physical location parameter data can help train the model to make highly accurate predictions.

[0021] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while retaining the illustrative nature of the invention. Therefore, the foregoing disclosure should be interpreted only within the scope of the appended claims. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0022] 10: Abundant sources of production materials 11: Training the model 12: Wafer Diagram 100: Grain-level parameter prediction and enhancement system D1: Electrical Parameter Characteristics D2: Physical location parameter data D3: Forecast Data DA: Grain d: distance O: Wafer Center S301: Steps S302: Steps S303: Steps S304: Steps (X,Y): Coordinates

Claims

1. A method for improving grain-level parameter prediction, comprising: Obtain a wafer map comprising a plurality of dies; select one die from the plurality of dies; select a plurality of neighboring dies from the wafer map that are adjacent to the die and that the neighboring dies have a similar physical or electrical distribution to the die; input the physical location parameters of the die and a plurality of electrical parameters of the die into a training model, wherein the physical location parameters of the die include the center coordinates of the die on the wafer map, the distance from the center of the die to the center of the wafer, and the electrical variations of the die with respect to the neighboring dies; and generate prediction data for the die from the training model based on the physical location parameters and the plurality of electrical parameters.

2. The method as described in claim 1, further comprising: Obtain large amounts of production data from multiple dies at the wafer probe (CP) stage node and / or final test (FT) stage node; The wafer diagram is defined based on a large amount of production data.

3. The method as described in claim 2, further comprising: Grains that acquire multiple electrical parameter characteristics based on a large amount of production data; The plurality of electrical parameter characteristics of the die include wafer speed, wafer power leakage, or wafer minimum voltage as measured by sensors or detectors embedded in the die.

4. The method of claim 1, wherein the die of the predicted data includes an on / off current, a threshold voltage, or channel information of a metal-oxide-semiconductor field-effect transistor (MOSFET).

5. The method as described in claim 1, further comprising: Obtain grain training data; And a training model is built based on the grain training data; wherein the training model includes the pre-trained electrical feature information of each grain in the wafer diagram.

6. The method as described in claim 5, further comprising: When the training model is not fully trained, the training model is retrained based on the grain training data.

7. The method as described in claim 5, further comprising: When the training model is fully trained, the output training model is used as the final training model to generate prediction data.

8. The method as described in claim 1, further comprising: Identify at least one anomalous grain among a plurality of grains based on the predicted data.

9. A grain-level parameter prediction and enhancement system, comprising: A large source of means of production; And a training model is connected to a large number of production data sources; wherein, after obtaining a wafer map including a plurality of dies from the large number of production data sources, a die is selected from the plurality of dies, and a plurality of neighboring dies adjacent to the die are selected from the wafer map, and these neighboring dies are similar to the die in a physical or electrical distribution; the physical location parameters of the die and a plurality of electrical parameter features of the die are input into the training model, and the training model generates prediction data of the die based on the physical location parameters and the plurality of electrical parameter features, and the physical location parameters of the die include the center coordinates of the die on the wafer map, the distance from the center of the die to the center of the wafer, and the electrical changes of the die with the neighboring dies.

10. The system of claim 9, wherein the wafer map is defined based on mass production data obtained from a mass production data source, and the mass production data source includes a wafer probe (CP) stage node and / or a final test (FT) stage node.

11. The system of claim 10, wherein the training model acquires a plurality of electrical parameter features of the die based on a large amount of production data, and the plurality of electrical parameter features of the die includes wafer speed, wafer power leakage, or wafer minimum voltage as measured by a sensor or detector embedded in the die.

12. The system of claim 9, wherein the die of the predicted data includes an on / off current, a threshold voltage, or channel information of a metal-oxide-semiconductor field-effect transistor (MOSFET).

13. The system of claim 9, wherein after acquiring the grain training data, a training model is built based on the grain training data, and the training model includes pre-trained electrical feature information of each grain in the wafer diagram.

14. The system as described in claim 13, wherein when the training model is not fully trained, the training model is retrained based on the training data.

15. The system of claim 13, wherein when the training model has been fully trained, the training model is output as the final training model to generate prediction data.

16. The system of claim 9, wherein the training model identifies at least one anomalous grain based on prediction data.

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