Semiconductor structure and fabrication method thereof

Abstract

A semiconductor structure includes a semiconductor substrate; a source structure disposed in the semiconductor substrate, the source structure including a source drift region and a heavily doped source region disposed within the source drift region; a groove disposed in the semiconductor substrate and spaced apart from the source structure; a drain structure disposed at the bottom of the groove, the drain structure including a drain drift region, a heavily doped drain region disposed within the drain drift region and a carbon doped surface layer located on the heavily doped drain region; and a gate structure disposed on the semiconductor substrate and located between the source structure and the drain structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an electrostatic discharge (ESD) protection element and its manufacturing method. Prior Technology

[0002] Electrostatic discharge (ESD) protection components are used to protect the internal circuitry on semiconductor wafers. These ESD protection components are connected to each wafer input / output (I / O) and power pad. When electrostatic discharge from outside the wafer enters the wafer pads, the ESD protection components and circuitry absorb the resulting high current, protecting the internal wafer circuitry from damage. ESD protection components are typically located near the wafer pads to which they are connected.

[0003] However, ESD protection components can be affected by CoSi spikes, a phenomenon where CoSi peaks form and grow under electrical stress. The formation of CoSi spikes creates localized conductive paths, leading to increased leakage current, reduced component performance, and decreased reliability. Furthermore, as stress concentration points, CoSi spikes can cause dielectric material degradation and lower the breakdown voltage of ESD protection components. This makes the components more susceptible to damage from ESD events. Summary of the Invention

[0004] The main objective of this invention is to provide an improved semiconductor ESD device structure and its fabrication method to overcome the shortcomings or disadvantages of existing technologies.

[0005] The present invention provides a semiconductor structure comprising: a semiconductor substrate having a first conductivity type; a source structure disposed in the semiconductor substrate, wherein the source structure includes a source drift region having a second conductivity type and a heavily doped source region having the second conductivity type disposed within the source drift region; a groove disposed in the semiconductor substrate and spaced apart from the source structure; a drain structure disposed at the bottom of the groove, wherein the drain structure includes a drain drift region having the second conductivity type, a heavily doped drain region having the second conductivity type disposed within the drain drift region, and a carbon doped surface layer located on the heavily doped drain region; and a gate structure disposed on the semiconductor substrate and located between the source structure and the drain structure.

[0006] According to an embodiment of the present invention, the gate structure includes a gate electrode, a first sidewall located on a first sidewall of the gate electrode, a second sidewall located on a second sidewall of the gate electrode, and a gate dielectric layer located between the gate electrode and the semiconductor substrate.

[0007] According to an embodiment of the present invention, viewed from above, the source drift region completely overlaps the first sidewall and partially overlaps the gate electrode.

[0008] According to an embodiment of the present invention, when viewed from above, the drain drift region does not overlap the second sidewall and the gate electrode.

[0009] According to an embodiment of the present invention, the groove includes a sidewall disposed next to the outer surface of the first sidewall.

[0010] According to an embodiment of the present invention, the corner between the sidewall of the groove and the bottom of the groove is a rounded corner.

[0011] According to an embodiment of the present invention, the depth of the groove below a main surface of the semiconductor substrate is between 1,000 angstroms and 2,500 angstroms.

[0012] According to an embodiment of the present invention, the semiconductor structure further includes: a first silicon metal layer disposed on the heavily doped source region; a second silicon metal layer disposed on the heavily doped drain region, wherein the end of the second silicon metal layer maintains a predetermined distance from the sidewall of the groove; and a third silicon metal layer disposed on the top of the gate electrode near the source structure.

[0013] According to an embodiment of the present invention, the first siliconized metal layer, the second siliconized metal layer, and the third siliconized metal layer comprise cobalt silicon.

[0014] According to an embodiment of the present invention, the first conductivity type is P-type and the second conductivity type is N-type.

[0015] Another aspect of the present invention provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate having a first conductivity type; forming a source structure in the semiconductor substrate, wherein the source structure includes a source drift region having a second conductivity type and a heavily doped source region having the second conductivity type disposed within the source drift region; forming a groove in the semiconductor substrate, such that the groove is spaced apart from the source structure; forming a drain structure at the bottom of the groove, wherein the drain structure includes a drain drift region having the second conductivity type, a heavily doped drain region having the second conductivity type disposed within the drain drift region, and a carbon doped surface layer located on the heavily doped drain region; and forming a gate structure on the semiconductor substrate and between the source structure and the drain structure.

[0016] According to an embodiment of the present invention, the gate structure includes a gate electrode, a first sidewall located on a first sidewall of the gate electrode, a second sidewall located on a second sidewall of the gate electrode, and a gate dielectric layer located between the gate electrode and the semiconductor substrate.

[0017] According to an embodiment of the present invention, viewed from above, the source drift region completely overlaps the first sidewall and partially overlaps the gate electrode.

[0018] According to an embodiment of the present invention, when viewed from above, the drain drift region does not overlap the second sidewall and the gate electrode.

[0019] According to an embodiment of the present invention, the groove includes a sidewall disposed next to the outer surface of the first sidewall.

[0020] According to an embodiment of the present invention, the corner between the sidewall of the groove and the bottom of the groove is a rounded corner.

[0021] According to an embodiment of the present invention, the depth of the groove below a main surface of the semiconductor substrate is between 1,000 angstroms and 2,500 angstroms.

[0022] According to an embodiment of the present invention, the method further includes: forming a first siliconized metal layer on the heavily doped source region; forming a second siliconized metal layer on the heavily doped drain region, wherein the end of the second siliconized metal layer maintains a predetermined distance from the sidewall of the groove; and forming a third siliconized metal layer on the top of the gate electrode near the source structure.

[0023] According to an embodiment of the present invention, the first siliconized metal layer, the second siliconized metal layer, and the third siliconized metal layer comprise cobalt silicon.

[0024] According to an embodiment of the present invention, the first conductivity type is P-type and the second conductivity type is N-type. Simple Explanation of the Diagram

[0025] Figure 1 is a partial layout diagram of a semiconductor structure according to an embodiment of the present invention. Figures 2 through 8 are schematic cross-sectional views along the tangent line I-I' in Figure 1, illustrating a method for fabricating a semiconductor structure. Figure 9 shows a cross-sectional view of a partial semiconductor structure of the present invention. Implementation

[0026] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and are depicted in a manner that describes specific examples in which the embodiments can be implemented. The embodiments described below are described in sufficient detail to enable those skilled in the art to implement them.

[0027] Of course, other embodiments may also be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the detailed description below should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0028] Please refer to Figures 1 to 8, wherein Figure 1 is a partial layout diagram of a semiconductor structure according to an embodiment of the present invention, and Figures 2 to 8 are schematic cross-sectional views along the tangent line I-I' in Figure 1, illustrating a method for fabricating a semiconductor structure.

[0029] As shown in Figure 1, the semiconductor structure 1 of the present invention can be applied to, but is not limited to, electrostatic discharge (ESD) protection elements, which are fabricated on a semiconductor substrate 100, wherein the semiconductor substrate 100 is, for example, a silicon substrate or other semiconductor substrate. It should be understood that Figure 1 only shows a partially enlarged view of the ESD protection element illustratively for simplification. According to an embodiment of the present invention, the semiconductor structure 1 includes an active region 101, a trench insulating region ST surrounding the active region 101, a plurality of gate structures P extending along a first direction D1, and doped regions DR located on both sides of the gate structures P, wherein the doped regions DR can be, for example, N+ doped regions, serving as the drain or source of the ESD protection element.

[0030] According to an embodiment of the present invention, the semiconductor substrate 100 may have a first conductivity type, such as P-type, but is not limited thereto. According to an embodiment of the present invention, a plurality of gate structures P are arranged parallel to each other at a predetermined spacing in a second direction D2. According to an embodiment of the present invention, the semiconductor structure 1 may further include an annular heavily doped region 102 located around the trench insulating region ST, such as a P+ doped region, but is not limited thereto.

[0031] As shown in Figure 2, firstly, an input / output P-type well (I / OP well) 101p can be formed in the semiconductor substrate 100, and a deep N-type well 101n can be formed below the input / output P-type well 101p. Adjacent gate structures P1 and P2 are formed on the semiconductor substrate 100. For example, gate structure P1 includes a gate electrode GE1, a gate dielectric layer GD1 located between the gate electrode GE1 and the semiconductor substrate 100, and a sidewall sub-SP1 located on the opposite sidewall of the gate electrode GE1. Gate structure P2 includes, for example, a gate electrode GE2, a gate dielectric layer GD2 located between the gate electrode GE2 and the semiconductor substrate 100, and a sidewall sub-SP2 located on the opposite sidewall of the gate electrode GE2.

[0032] According to embodiments of the present invention, for example, gate electrodes GE1 and GE2 may contain polycrystalline silicon, but are not limited thereto. According to embodiments of the present invention, for example, gate dielectric layers GD1 and GD2 may contain silicon oxide, but are not limited thereto. According to embodiments of the present invention, for example, sidewalls SP1 and SP2 may contain silicon nitride, silicon oxide, or silicon oxynitride, but are not limited thereto.

[0033] According to an embodiment of the present invention, a drain region 202 is located between gate electrode GE1 and gate electrode GE2. On the other side of gate electrode GE1, opposite to drain region 202, is source region 201. On the other side of gate electrode GE2, opposite to drain region 202, is another source region 203. According to an embodiment of the present invention, the width of drain region 202 may be greater than the widths of source regions 201 and 203.

[0034] According to an embodiment of the present invention, a source drift region DF1 having a second conductivity type is formed in the source region 201, a drain drift region DF2 having a second conductivity type is formed in the drain region 202, and a source drift region DF3 having a second conductivity type is formed in the source region 203, wherein the drain drift region DF2, the source drift region DF1, and the source drift region DF3 are, for example, N-type drift regions.

[0035] According to an embodiment of the present invention, viewed from above, the source drift region DF1 completely overlaps with the sidewalls SP1 and partially overlaps with the gate electrode GE1, and the source drift region DF2 completely overlaps with the sidewalls SP2 and partially overlaps with the gate electrode GE2. According to an embodiment of the present invention, viewed from above, the drain drift region DF2 does not overlap with the sidewalls SP1 and SP2 and the gate electrodes GE1 and GE2.

[0036] As shown in Figure 3, a photoresist pattern PR is then formed on the semiconductor substrate 100, having an opening PO1 with a width of w1 and an opening PO2 with a width of w2, respectively exposing portions of the drain region 202 adjacent to the gate structure P1 and portions of the drain region 202 adjacent to the gate structure P2. According to an embodiment of the invention, a predetermined distance w0 is maintained between the openings PO1 and PO2. According to an embodiment of the invention, the sum of the widths w1, w2, and the predetermined distance w0 is approximately equal to the width of the drain region 202. According to an embodiment of the invention, the opening PO1 may expose a portion of the sidewall SP1, while the opening PO2 may expose a portion of the sidewall SP2.

[0037] As shown in Figure 4, the carbon ion implantation process IMP1 is then performed. Through openings PO1 and PO2 in the photoresist pattern PR, carbon atoms are implanted into the P-type well 101p within the drain region 202, forming carbon-doped regions CR1 and CR2. According to embodiments of the present invention, for example, the implantation dose of the carbon ion implantation process IMP1 is approximately 1E14 / cm², and the implantation depth is approximately 1200 Å to 2700 Å, but is not limited thereto. The carbon-doped regions CR1 and CR2 can avoid the formation of CoSi spiking and dopant diffusion.

[0038] As shown in Figure 5, an etching process, such as anisotropic dry etching, is then performed. Using the photoresist pattern PR shown in Figure 4 as an etching mask, recesses RT1 and RT2 are formed in the P-type well 101p via openings PO1 and PO2, respectively. According to an embodiment of the invention, for example, the depth d of recesses RT1 and RT2 below the main surface 100a of the semiconductor substrate 100 can be between 1000 angstroms and 2500 angstroms. According to an embodiment of the invention, the depth d of recesses RT1 and RT2 is less than the implantation depth of carbon-doped regions CR1 and CR2. According to an embodiment of the invention, at this time, carbon-doped surface layers CS1 and CS2 are still retained at the bottom SB1 and SB2 of recesses RT1 and RT2, respectively.

[0039] As shown in Figure 6, the next step is a photoresist stripping process and a cleaning process to remove the photoresist pattern PR. According to an embodiment of the present invention, the aforementioned cleaning process can be performed using a diluted hydrofluoric acid solution and an SPM solution. For example, the SPM solution can be a mixture of sulfuric acid solution and hydrogen peroxide aqueous solution in a ratio of 3:1. According to an embodiment of the present invention, after the above cleaning process, the corners R between the sidewalls SW1 and SW2 of the grooves RT1 and RT2 and their bottoms SB1 and SB2 are rounded, as shown in the enlarged view. This rounding reduces the peak electric field intensity and prevents the formation of CoSi peaks.

[0040] As shown in Figure 7, an ion implantation process is then performed to form a P+ doped region PD1 within the annular heavily doped region 102. Heavy doped source regions NR1 and NR3 are then formed in source drift regions DF1 and DF3, respectively, and a heavily doped drain region NR2 is formed in drain drift region DF2. According to an embodiment of the present invention, the heavily doped source regions NR1 and NR3, and the heavily doped drain region NR2, are, for example, N+ doped regions. According to an embodiment of the present invention, the heavily doped drain region NR2 includes a heavily doped drain region NR2a located at the bottom SB1 of the recess RT1, a heavily doped drain region NR2b located at the bottom SB2 of the recess RT2, and a heavily doped drain region NR2c located in the island-shaped region IS between the recess RT1 and the recess RT2.

[0041] According to an embodiment of the present invention, the heavily doped drain region NR2a located at the bottom SB1 of groove RT1 and the heavily doped drain region NR2b located at the bottom SB2 of groove RT2 have substantially the same junction depth, while the junction depth of the heavily doped drain region NR2c can be less than the junction depths of the heavily doped drain regions NR2a and NR2b. Subsequently, a rapid thermal processing (RTP) process can be performed to activate the dopants implanted in the semiconductor substrate 100. At this time, a source structure SS is formed in the semiconductor substrate 100 and a drain structure DS is formed at the bottom of grooves RT1 and RT2.

[0042] As shown in Figure 8, a silicon metal barrier layer 302 is then formed on the semiconductor substrate 100, which covers the top surface of the gate electrode GE1 and the gate electrode GE2 near the drain structure DS, the outer surface of the sidewalls SP1 and SP2 near the drain structure DS, the sidewalls SW1 and SW2 of the grooves RT1 and RT2, and the top surface of the heavily doped drain regions NR2a and NR2b.

[0043] A self-aligned metal silicide process is then performed to form metal silicide layers SAC1-SAC5, for example, cobalt silicide (CoSi), on the surface of the semiconductor substrate 100 not covered by the metal silicide barrier layer 302. Metal silicide layers SAC1 and SAC3 are formed on the surfaces of the heavily doped source regions NR1 and NR3, respectively. Metal silicide layer SAC2 is formed on the surface of the heavily doped drain region NR2c in the island region IS between recesses RT1 and RT2. Metal silicide layer SAC4 is formed on the surface of the P+ doped region PD1 within the annular heavily doped region 102. Metal silicide layer SAC5 is formed on the top of the gate electrodes GE1 and GE2 near the source structure SS. According to an embodiment of the present invention, the end of metal silicide layer SAC2 maintains a predetermined distance from the sidewalls SW1 and SW2 of recesses RT1 and RT2.

[0044] Next, a chemical vapor deposition process is performed to deposit a dielectric layer 310, such as a silicon oxide layer, but not limited to it, on the semiconductor substrate 100. Then, a metallization process is performed to form contact plugs CT1-CT4 in the dielectric layer 310. Contact plugs CT1 and CT3 contact the silicon metal layers SAC1 and SAC3 on the heavily doped source regions NR1 and NR3, respectively. Contact plug CT2 contacts the silicon metal layer SAC2 on the heavily doped drain region NR2c. Contact plug CT3 contacts the silicon metal layer SAC4 on the P+ doped region PD1.

[0045] Please refer to Figure 9, which is a cross-sectional view of a partial semiconductor structure according to an embodiment of the present invention, wherein the same regions, materials, or layers are still represented by the same symbols. As shown in Figure 9, the semiconductor structure 1 includes a semiconductor substrate 100 having a first conductivity type, for example, P-type. An input / output P-type well 101p may be formed in the semiconductor substrate 100, and a deep N-type well 101n may be formed below the input / output P-type well 101p. A spaced-apart source structure SS and a drain structure DS are disposed in the semiconductor substrate 100. According to an embodiment of the present invention, the source structure SS includes a source drift region DF1 and a heavily doped source region NR1 disposed within the source drift region DF1. The source drift region DF1 and the heavily doped source region NR1 have a second conductivity type, for example, N-type.

[0046] According to an embodiment of the present invention, a groove RT1 is provided in a semiconductor substrate 100, and the groove RT1 is spaced apart from the source structure SS. According to an embodiment of the present invention, a drain structure DS is partially disposed at the bottom of the groove RT1, wherein the drain structure DS includes a drain drift region DF2, a heavily doped drain region NR2a disposed in the drain drift region DF2, and a carbon doped surface layer CS1 located on the heavily doped drain region NR2a.

[0047] According to an embodiment of the present invention, a gate structure P1 is provided on a semiconductor substrate 100, wherein the gate structure P1 is located between the source structure SS and the drain structure DS.

[0048] According to an embodiment of the present invention, the gate structure P1 includes a gate electrode GE1, a sidewall sub-SP1 located on the opposite sidewall of the gate electrode GE1, and a gate dielectric layer GD1 located between the gate electrode GE1 and the semiconductor substrate 100.

[0049] According to an embodiment of the present invention, viewed from above, the source drift region DF1 completely overlaps the source-side sidewall SP1 and partially overlaps the gate electrode GE1. According to an embodiment of the present invention, viewed from above, the drain drift region DF2 does not overlap the drain-side sidewall SP1 and the gate electrode GE1.

[0050] According to an embodiment of the present invention, the groove RT1 includes a sidewall SW1 disposed next to the outer surface of the sidewall SP1. According to an embodiment of the present invention, the corner R between the sidewall SW1 and the bottom of the groove RT1 is a rounded corner. According to an embodiment of the present invention, the depth of the groove RT1 below the main surface 100a of the semiconductor substrate 100 is between 1000 angstroms and 2500 angstroms.

[0051] According to an embodiment of the present invention, the semiconductor structure 1 further includes a silicon metal layer SAC1 disposed on the heavily doped source region NR1, and a silicon metal layer SAC2 disposed on the heavily doped drain region NR2c, wherein the end of the silicon metal layer SAC2 maintains a predetermined distance from the sidewall SW1 of the recess RT1. The semiconductor structure 1 further includes a silicon metal layer SAC5 disposed on the top of the gate electrode GE1 near the source structure SS. According to an embodiment of the present invention, for example, the silicon metal layers SAC1, SAC2, and SAC5 comprise cobalt silicon. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0052] 1: Semiconductor Structure 100: Semiconductor substrate 100a: Main surface 101: Active Region 101p: Input / output P-type well 101n: Deep N-type well 102: Ring-shaped heavily doped region 201, 203: Source Region 202: Duji Zone 302: Siliconized metal barrier layer 310: Dielectric layer CR1, CR2: Carbon-doped regions CS1, CS2: Carbon-doped surface layers CT1-CT4: Contact plugs DF1, DF3: Source pole drift region DF2: Drain drift region IMP1: Carbon Ion Implantation Process IS: Island area GE1, GE2: Gate electrodes GD1, GD2: Gate dielectric layer NR1, NR3: Heavily doped source pole regions NR2, NR2a, NR2b, NR2b: Heavily doped drain regions SAC1-SAC5: Siliconized metal layers SB1, SB2: Bottom SP1, SP2: Sidewall ST: Insulated area of ​​trench SW1, SW2: Sidewalls P, P1, P2: Gate structure PD1: P+ doped region PR: Photoresist pattern PO1, PO2: Open R: Corner RT1, RT2: Grooves SS: Source structure DS: Drain structure d: depth DR: Doped region D1: First Direction D2: Second Direction w0: Pre-determined distance w1, w2: Width

Claims

1. A semiconductor structure comprising: a semiconductor substrate having a first conductivity type; and a source structure disposed in the semiconductor substrate, wherein, The source structure includes a source drift region having a second conductivity type and a heavily doped source region having the second conductivity type disposed within the source drift region; a groove disposed in the semiconductor substrate and spaced apart from the source structure; a drain structure disposed at the bottom of the groove, wherein the drain structure includes a drain drift region having the second conductivity type, a heavily doped drain region having the second conductivity type disposed within the drain drift region, and a carbon doped surface layer located on the heavily doped drain region; and a gate structure disposed on the semiconductor substrate and located between the source structure and the drain structure.

2. The semiconductor structure as described in claim 1, wherein, The gate structure includes a gate electrode, a first sidewall located on a first sidewall of the gate electrode, a second sidewall located on a second sidewall of the gate electrode, and a gate dielectric layer located between the gate electrode and the semiconductor substrate.

3. The semiconductor structure as described in claim 2, wherein, Viewed from above, the source drift region completely overlaps the first sidewall and partially overlaps the gate electrode.

4. The semiconductor structure as described in claim 2, wherein, Viewed from above, the drain drift region does not overlap with the second sidewall and the gate electrode.

5. The semiconductor structure as described in claim 2, wherein, The groove includes a sidewall disposed next to the outer surface of the first sidewall.

6. The semiconductor structure as described in claim 5, wherein, The corner between the sidewall and the bottom of the groove is a rounded corner.

7. The semiconductor structure as claimed in claim 1, wherein, The groove is between 1,000 and 2,500 angstroms deep below a main surface of the semiconductor substrate.

8. The semiconductor structure as described in claim 5, wherein, It further includes: a first siliconized metal layer disposed on the heavily doped source region; a second siliconized metal layer disposed on the heavily doped drain region, wherein the end of the second siliconized metal layer maintains a predetermined distance from the sidewall of the groove; and a third siliconized metal layer disposed on the top of the gate electrode near the source structure.

9. The semiconductor structure as described in claim 8, wherein, The first, second, and third siliconized metal layers contain cobalt silicon.

10. The semiconductor structure as claimed in claim 1, wherein, The first conductivity type is P-type, and the second conductivity type is N-type.

11. A method of forming a semiconductor structure, comprising: providing a semiconductor substrate having a first conductivity type; forming a source structure in the semiconductor substrate, wherein, The source structure includes a source drift region having a second conductivity type and a heavily doped source region having the second conductivity type disposed within the source drift region; a groove is formed in the semiconductor substrate, such that the groove is spaced apart from the source structure; a drain structure is formed at the bottom of the groove, wherein the drain structure includes a drain drift region having the second conductivity type, a heavily doped drain region having the second conductivity type disposed within the drain drift region, and a carbon doped surface layer located on the heavily doped drain region; and a gate structure is formed on the semiconductor substrate and between the source structure and the drain structure.

12. The method as described in claim 11, wherein, The gate structure includes a gate electrode, a first sidewall located on a first sidewall of the gate electrode, a second sidewall located on a second sidewall of the gate electrode, and a gate dielectric layer located between the gate electrode and the semiconductor substrate.

13. The method as described in claim 12, wherein, Viewed from above, the source drift region completely overlaps the first sidewall and partially overlaps the gate electrode.

14. The method as described in claim 12, wherein, Viewed from above, the drain drift region does not overlap with the second sidewall and the gate electrode.

15. The method as described in claim 12, wherein, The groove includes a sidewall disposed next to the outer surface of the first sidewall.

16. The method as described in claim 15, wherein, The corner between the sidewall and the bottom of the groove is a rounded corner.

17. The method as described in claim 11, wherein, The groove is between 1,000 and 2,500 angstroms deep below a main surface of the semiconductor substrate.

18. The method as described in claim 15, wherein, It further includes: forming a first siliconized metal layer on the heavily doped source region; forming a second siliconized metal layer on the heavily doped drain region, wherein the end of the second siliconized metal layer maintains a predetermined distance from the sidewall of the groove; and forming a third siliconized metal layer on the top of the gate electrode near the source structure.

19. The method as described in claim 18, wherein, The first, second, and third siliconized metal layers contain cobalt silicon.

20. The method as described in claim 11, wherein, The first conductivity type is P-type, and the second conductivity type is N-type.

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