Memory apparatus, memory system and method for memory structure

Abstract

A device includes one or more control circuits configured to be connected to a non-volatile memory cell structure, the non-volatile memory cell structure including non-volatile memory cells each having a programmable resistive element. The one or more control circuits are configured to receive an address corresponding to a location in the non-volatile memory cell structure and to set a variable resistor according to the location. The variable resistor is connected in series with a selected non-volatile memory cell located at that location. The one or more control circuits are further configured to drive a memory access current through the selected non-volatile memory cell and the variable resistor connected in series.

Description

Technical Field

[0001] This invention relates to a variable resistor for current control in a non-volatile memory array. Prior Technology

[0002] Memory systems are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery pack).

[0003] One example of non-volatile memory is magnetoresistive random access memory (MRAM), which uses magnetization to represent stored data, unlike some other memory technologies that use electron charges to store data. Typically, MRAM comprises a large number of magnetic memory cells formed on a semiconductor substrate, each memory cell representing at least one bit of data. A bit of data is written to the memory cell by changing the magnetization direction of the magnetic elements within the memory cell, and a bit is read by measuring the resistance of the memory cell (low resistance generally represents a "0" bit and high resistance generally represents a "1" bit). As used herein, the magnetization direction is the direction of the magnetic moment orientation.

[0004] While MRAM is a promising technology, various phenomena can cause errors in the data stored in MRAM. Error Correction Code (ECC) can be used to correct such errors. Correcting errors using ECC can require significant resources and time. In some cases, the data may contain too many errors to be corrected using a given ECC scheme. Such data may be considered uncorrectable or "UE" by ECC. For example, without proper management, uneven current (e.g., uneven write current used to write to or program memory cells) can lead to serious errors. Summary of the Invention

[0005] A device includes one or more control circuits configured to be connected to a non-volatile memory cell structure, the non-volatile memory cell structure including non-volatile memory cells each having a programmable resistive element. The one or more control circuits are configured to receive an address corresponding to a location in the non-volatile memory cell structure and to set a variable resistor according to the location. The variable resistor is connected in series with a selected non-volatile memory cell located at that location. The one or more control circuits are further configured to drive a memory access current through the selected non-volatile memory cell and the variable resistor connected in series. Simple Explanation of the Diagram

[0006] Components with similar numbers are referenced to common components in different diagrams. [Figure 1] is a block diagram of an embodiment of a memory system connected to a host computer. [Figure 2] is a block diagram of one embodiment of the front-end processor circuit. In some embodiments, the front-end processor circuit is part of the controller. [Figure 3] is a block diagram of one embodiment of the back-end processor circuit. In some embodiments, the back-end processor circuit is part of the controller. [Figure 4] is a block diagram of an embodiment of memory packaging. [Figure 5] is a block diagram of one embodiment of a memory chip. [Figure 6A] and [Figure 6B] illustrate an example of a control circuit on a control chip coupled to a memory structure on a memory chip. [Figure 7A] An embodiment of a memory array forming a cross-point architecture is depicted in oblique view. [Figure 7B] and [Figure 7C] respectively present the side view and top view of the intersection structure in Figure 7A. [Figure 7D] An embodiment of a second-order memory array forming a crosspoint architecture is depicted in oblique view. [Figure 8] illustrates an embodiment of the structure of an MRAM memory cell. [Figure 9] illustrates in more detail an embodiment of an MRAM memory cell design when implemented as a cross-point array. [Figure 10A] and [Figure 10B] illustrate the writing of MRAM memory cells using a spin torque transfer (STT) mechanism. [Figure 11A] and [Figure 11B] illustrate an embodiment incorporating a threshold switching selector into an MRAM memory array with a crosspoint architecture. [Figure 12] shows an example of a memory structure comprising non-volatile memory cells connected by zigzag lines and bit lines of varying lengths. Figures 13A and 13B show an example of a non-volatile memory cell connected by word lines and bit lines of varying lengths. [Figures 14A] to [Figures 14B] are schematic diagrams showing examples of access current in a non-volatile memory cell. Figures 15A through 15D show schematic diagrams illustrating examples of access current through a non-volatile memory cell connected in series with a variable resistor. [Figure 16] shows an example of a variable resistor. Figures 17A and 17B show examples of control circuits for controlling variable resistors. [Figure 18] shows an example of a method that includes setting a plurality of variable resistors. [Figure 19] shows an example of a method including determining and recording series resistance. Implementation

[0007] In a memory array with a cross-point type architecture, a first set of conductive lines (e.g., word lines or WL) travels across the surface of a substrate, and a second set of conductive lines (e.g., bit lines or BL) travels above the substrate in a direction perpendicular to the first set of conductive lines. The memory cell is located at the cross-point junction of the two sets of conductive lines. Embodiments of the memory cell may include programmable resistive elements (such as MRAM elements) that can be connected in series with selector switches in such a cross-point memory structure.

[0008] In some memory structures, including cross-point MRAM memory structures, the word line resistance and bit line resistance connected in series with memory cells may not be consistent for all memory cells. For example, depending on the location of the memory cells in the memory structure, memory cells may be connected by longer lines (e.g., WL and / or BL) that result in higher series resistance, or by shorter lines that result in lower series resistance. This non-uniformity in the series resistance of the lines of different memory cells can lead to non-uniformity in memory access (e.g., data write operations), which can introduce errors into the stored data. Various forms of this technology provide technical solutions to the technical problems associated with non-uniform current when accessing different memory cells in a memory structure (e.g., because memory cells at different locations have different line lengths, resulting in different resistances connected in series with the cell being accessed).

[0009] According to various embodiments of this technology, a variable resistor can be connected in series with a selected memory cell (and in series with the corresponding selected WL and BL), and the resistance of the variable resistor can be set to a value that depends on the location of the selected memory cell and / or other factors. For example, for memory cells located at locations resulting in high series resistance (e.g., due to long WL and / or BL), the variable resistor can be set to a low value, while for memory cells located at locations resulting in low series resistance (e.g., due to short WL and / or BL), the variable resistor can be set to a high value. In this way, the variable resistor can be used to compensate for the different WL and BL resistances associated with different locations in the memory structure (e.g., for all memory cells, the total series resistance of WL, BL, and the variable resistor can remain substantially equal). The series-connected variable resistor can also be controlled according to temperature and / or other factors.

[0010] Figure 1 is a block diagram of one embodiment of a memory system 100 connected to host 120. The memory system 100 may implement the techniques for managing error rates presented herein. Many different types of memory systems may be used with the techniques presented herein. Example memory systems include solid-state drives ("SSDs"), memory cards (including dual in-line memory modules (DIMMs) for DRAM replacement), and embedded memory devices; however, other types of memory systems may also be used.

[0011] The memory system 100 of Figure 1 includes a controller 102, non-volatile memory 104 for storing data, and local memory (e.g., DRAM / ReRAM / MRAM) 106. The controller 102 includes a front-end processor (FEP) circuitry 110 and one or more back-end processor (BEP) circuitry 112. In one embodiment, the FEP circuitry 110 is implemented on an application-specific integrated circuit (ASIC). In one embodiment, each BEP circuitry 112 is implemented on a separate ASIC. In other embodiments, a unified controller ASIC can combine both front-end and back-end functions. Implementing the ASICs for each of the BEP circuitry 112 and the FEP circuitry 110 on the same semiconductor allows the controller 102 to be fabricated as a system-on-a-chip (SoC). Both the FEP circuitry 110 and the BEP circuitry 112 include their own processors. In one embodiment, FEP circuit 110 and BEP circuit 112 operate in a master-slave configuration, where FEP circuit 110 is the master circuit and each BEP circuit 112 is a slave circuit. For example, FEP circuit 110 implements a Flash Translation Layer (FTL) or performs memory management (e.g., garbage collection, wear leveling, etc.), logic-to-physical address translation, communication with the host, DRAM (local volatile memory) management, and a Media Management Layer (MLL) for the overall operation of SSDs (or other non-volatile storage systems). When requested by FEP circuit 110, BEP circuit 112 manages memory operations within the memory package / die. For example, BEP circuit 112 can perform read, erase, and programming operations. Additionally, BEP circuit 112 can perform buffer management, set specific voltage levels requested by FEP circuit 110, perform error correction (ECC), and control the dual-state thixotropic interface to the memory package. In one embodiment, each BEP circuit 112 is responsible for its own memory package group.

[0012] In one embodiment, the non-volatile memory 104 comprises a plurality of memory packages. Each memory package includes one or more memory chips. Therefore, the controller 102 is connected to one or more non-volatile memory chips. In one embodiment, each memory chip in the memory package 104 utilizes inverse NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory package may include other types of memory, such as storage class memory (SCM) based on resistive random access memory (such as ReRAM, MRAM, FeRAM, or RRAM) or phase change memory (PCM). In other embodiments, a BEP or FEP may be included on the memory chip.

[0013] Controller 102 communicates with host 120 via an interface 130 implementing protocols such as, for example, Fast NVM (NVM Express, NVMe) or Compute Express Link (CXL) via PCI Express (PCIe) or using a JEDEC standard Double Data Rate or Low Power Double Data Rate (DDR or LPDDR) interface (such as DDR5 or LPDDR5). To work with memory system 100, host 120 includes host processor 122, host memory 124, and a PCIe interface 126 connected along bus 128. Host memory 124 is the host's physical memory and may be DRAM, SRAM, MRAM, non-volatile memory, or another type of storage. Host 120 is external to and separate from memory system 100. In one embodiment, memory system 100 is embedded within host 120.

[0014] Figure 2 is a block diagram of one embodiment of the FEP circuit 110. Figure 2 shows a PCIe interface 150 communicating with a host 120 and a host processor 152 communicating with the PCIe interface. The host processor 152 may be any type of processor known in the art suitable for this embodiment. The host processor 152 communicates with a network-on-chip (NOC) 154. The NOC is a communication subsystem on integrated circuits, typically between cores in a SoC. The NOC can span synchronous and asynchronous clock domains or use time-independent asynchronous logic. NOC technology applies network theory and methods to on-chip communication and brings significant improvements beyond conventional bus and crossbar interconnects. Compared to other designs, NOC improves the scalability of SoCs and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Because all links in the NOC can operate simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to grow, the NOC offers enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). Connected to and communicating with the NOC 154 are the memory processor 156, SRAM 160, and DRAM controller 162. The DRAM controller 162 is used to operate and communicate with the DRAM (e.g., DRAM 106). The SRAM 160 is local RAM memory used by the memory processor 156. The memory processor 156 is used to run the FEP circuitry and perform various memory operations. Furthermore, communicating with the NOC are two PCIe interfaces 164 and 166. In the embodiment of FIG2, the SSD controller will include two BEP circuits 112; therefore, there are two PCIe interfaces 164 / 166. Each PCIe interface communicates with one of the BEP circuits 112. In other embodiments, there may be more or fewer than two BEP circuits 112; therefore, there may be more than two PCIe interfaces.

[0015] FEP circuit 110 may also include a flash memory translation layer (FTL), or more generally, a media management layer (MML) 158 that performs memory management (e.g., garbage collection, wear leveling, load balancing, etc.), logic-to-physical address translation, communication with the host, DRAM (local volatile memory) management, and overall operation management of SSDs or other non-volatile storage systems. The media management layer MML 158 can be integrated into the memory management portion that handles memory errors and interfaces with the host. Specifically, the MML may be a module within FEP circuit 110 and may be responsible for the essence of memory management. Specifically, MML 158 may include an algorithm in the memory device firmware that translates writes from the host into writes to the memory structure at the die (e.g., 502 / 602 in Figures 5 and 6 below). MML 158 may be necessary for the following reasons: 1) the memory may have limited tolerance; 2) the memory structure can only be written to multiple pages; and / or 3) the memory structure may not be written to unless it is completely erased. MML 158 understands these potential limitations of the memory structure that the host may not be able to see. Therefore, MML 158 attempts to translate writes from the host into writes to the memory structure.

[0016] Figure 3 is a block diagram of one embodiment of the BEP circuit 112. Figure 3 shows a PCIe interface 200 for communicating with the FEP circuit 110 (e.g., with one of the PCIe interfaces 164 and 166 of Figure 2). The PCIe interface 200 communicates with two NOCs 202 and 204. In one embodiment, the two NOCs can be combined into one large NOC. Each NOC (202 / 204) is connected to the SRAM (230 / 260), buffer (232 / 262), processor (220 / 250), and connected to the data path controller (222 / 252) via an XOR engine (224 / 254) and an ECC engine (226 / 256). As known in the art, the ECC engine 226 / 256 is used to perform error correction. The XOR engine 224 / 254 is used to XOR data so that the data can be combined and stored in a way that allows recovery in the event of a programmed error. Data path controller 222 is connected to an interface module for communicating with the memory package via four channels. Therefore, top NOC 202 is associated with interface 228 for the four channels communicating with the memory package, and bottom NOC 204 is associated with interface 258 for four additional channels communicating with the memory package. Each interface 228 / 258 includes four dual-state thixotropic mode interfaces (TM interfaces), four buffers, and four schedulers. One scheduler, buffer, and TM interface are provided for each channel. The processor can be any standard processor known in the art. Data path controller 222 / 252 can be a processor, FPGA, microprocessor, or other type of controller. XOR engines 224 / 254 and ECC engines 226 / 256 are dedicated hardware circuitry referred to as hardware accelerators. In other embodiments, XOR engines 224 / 254 and ECC engines 226 / 256 can be implemented in software. The scheduler, buffer, and TM interface are hardware circuitry.

[0017] Figure 4 is a block diagram of one embodiment of a memory package 104 including a plurality of memory chips 292 connected to a memory bus (data line and chip enable line) 294. The memory bus 294 is connected to a dual-state thixotropic interface 296 for communicating with a TM interface (see, for example, Figure 3) of a BEP circuit 112. In some embodiments, the memory package may include a small controller connected to the memory bus and the TM interface. The memory package may have one or more memory chips. In one embodiment, each memory package includes eight or 16 memory chips; however, other numbers of memory chips may also be implemented. In another embodiment, the dual-state thixotropic interface is replaced by DDR or LPDDR of the JEDEC standard, with or without variations (such as relaxed time-sets or smaller page sizes). The techniques described herein are not limited to any particular number of memory chips.

[0018] Figure 5 is a block diagram depicting an example of a memory system 500 that can implement the techniques described herein. The memory system 500 includes a memory array 502 that may include any of the memory cells described below. The array terminal lines of the memory array 502 include word lines(s) organized in columns and bit lines(s) organized in rows. However, other orientations may also be implemented. The memory system 500 includes a column control circuitry system 520, the outputs 508 of which are connected to the individual word lines of the memory array 502. The column control circuitry system 520 receives a group of M column address signals and one or more various control signals from system control logic circuitry 560, and generally includes circuitry for both read and write operations, such as a column decoder 522, an array terminal driver 524 (e.g., a word line driver), and a block selection circuitry system 526. The memory system 500 also includes a row control circuitry system 510, whose inputs / outputs 506 are connected to individual bit lines of the memory array 502. Although only a single block is displayed for the memory array 502, the memory die may include multiple arrays or "tiles" that can be accessed individually. The row control circuitry system 510 receives a group of N row address signals and one or more various control signals from the system control logic 560, and generally may include circuitry such as a row decoder 512, an array terminal receiver or driver 514 (e.g., a bit line driver), a block selection circuitry system 516, a read / write circuitry system, and I / O multiplexer circuitry.

[0019] System control logic 560 receives data and commands from the host and provides output data and status to the host. In other embodiments, system control logic 560 receives data and commands from a separate controller circuit and provides output data to that controller circuit, which communicates with the host. In some embodiments, system control logic 560 may include a state machine that provides grain-level control for memory operation. In one embodiment, the state machine may be software-programmable. In other embodiments, the state machine is implemented entirely in hardware (e.g., circuitry) without using software. In another embodiment, the state machine is replaced by a microcontroller, which may be on the memory chip or off-chip. System control logic 560 may also include a power control module that controls the power and voltage supplied to the columns and rows of memory array 502 during memory operation and may include charge pump and regulator circuitry for generating regulated voltages. System control logic 560 may include one or more state machines, registers, and other control logic for controlling the operation of memory system 500. Figure 5 illustrates such a temporary register at 561, which can be used, for example, to record data such as settings, which can be used when accessing (e.g., reading or writing) memory cells of memory array 502. System control logic 560 includes temperature measurement circuitry 563, which may have a temperature converter and can generate a temperature measurement value from the temperature sensed by the converter (e.g., from a measurement of current, voltage, resistance, or other measurement or a combination of measurements). The temperature measurement value obtained by temperature measurement circuitry 563 can be sent to system control logic 560 and / or other components of memory system 500, which can use the temperature measurement value (e.g., to adjust certain parameters according to temperature).

[0020] In some embodiments, all components of the memory system 500 (including system control logic 560) may be formed as part of a single die. In other embodiments, some or all of the system control logic 560 may be formed on different dies.

[0021] For the purposes of this document, the phrase "one or more control circuits" may include a controller, state machine, microcontroller, and / or other control circuit system as represented by system control logic 560, and / or other similar circuits for controlling non-volatile memory.

[0022] In one embodiment, memory structure 502 comprises a three-dimensional memory array of non-volatile memory cells, wherein multiple memory layers are formed on a single substrate (such as a wafer). The memory structure may comprise any type of non-volatile memory, such non-volatile memory systems being monolithically formed in one or more solid layers of memory cells having active regions disposed above a silicon (or other type) substrate. In one example, the non-volatile memory cells comprise vertical NAND word strings with charge trapping.

[0023] In another embodiment, memory structure 502 includes a two-dimensional memory array of non-volatile memory cells. In one instance, the non-volatile memory cells are NAND flash memory cells with floating gates. Other types of memory cells (e.g., NOR type flash memory) may also be used.

[0024] The exact type of memory array architecture or memory cell included in memory structure 502 is not limited to the examples described above. Many different types of memory array architectures or memory technologies can be used to form memory structure 326. No specific non-volatile memory technology is required for the purposes of the new claimed embodiments presented herein. Other examples of suitable technologies for the memory cells of memory structure 502 include ReRAM (Resistive Random Access Memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase-change memory (e.g., PCM), and the like. Examples of suitable technologies for the memory cell architecture of memory structure 502 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit-line arrays, and the like.

[0025] One example of a ReRAM crosspoint memory includes a reversible resistance-switching element configured in a crosspoint array accessed via X and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallized cell. The conductive bridge memory element can be used as a state-change element based on the physical relocation of ions within a solid electrolyte. In some cases, the conductive bridge memory element may include two solid metal electrodes (one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper)) having a solid electrolyte film between the two electrodes. As temperature increases, ion mobility also increases, resulting in a decrease in the programmability threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory element has a wide range of programmability thresholds over a temperature range.

[0026] Another example is magnetoresistive random access memory (MRAM), which uses magnetic storage elements to store data. The element is formed from two ferromagnetic layers separated by a thin insulating layer, each of which can remain magnetized. One of the two layers is set as a permanent magnet of a specific polarity; the magnetization of the other layer can be changed to match the magnetization of an external field storing the memory. The memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below it. An induced magnetic field is generated when current passes through them. MRAM-based memory embodiments will be discussed in more detail below.

[0027] Phase change memory (PCM) utilizes the unique behavior of sulfide glasses. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve a non-thermal phase transition by simply changing the coordination state of germanium atoms using programmable current pulses. It should be noted that the use of "pulse" in this document does not require a square pulse, but rather includes (continuous or discontinuous) vibrations or bursts of sound, current, voltage, light, or other waves. These memory elements (or bits) within individual selectable memory cells may include further series elements of selectors (such as bidirectional limit switches or metal-insulator substrates).

[0028] Those skilled in the art will recognize that the techniques described herein are not limited to a single specific memory structure, memory construction, or material composition, but encompass a wide range of related memory structures within the spirit and scope of the techniques described herein and understood by those skilled in the art.

[0029] The components in Figure 5 can be divided into two parts: the structure of the memory cell structure 502 and the peripheral circuitry system including all other components. An important characteristic of memory circuitry is its capacity, which can be increased by increasing the area of ​​the memory die delivered to the memory system 500 of the memory cell structure 502; however, this reduces the area of ​​the memory die available for the peripheral circuitry system. This can place significant limitations on these peripheral components. For example, the need to fit the sense amplifier circuitry within the available area can be a significant limitation on the sense amplifier design architecture. Regarding the system control logic 560, the reduced area availability can limit the available functionality that can be implemented on the chip. Therefore, the fundamental trade-off in the design of the memory die for the memory system 500 is the amount of area dedicated to the memory cell structure 502 and the amount of area dedicated to the peripheral circuitry system.

[0030] Another reason for the inconsistency between memory structure 502 and its peripheral circuitry is the processing involved in forming these regions, as these regions often involve different processing techniques and trade-offs between different techniques on a single die. For example, when memory structure 502 is a NAND flash memory, it is an NMOS structure, while the peripheral circuitry is typically CMOS-based. For instance, components in system control logic 560 (such as sense amplifier circuitry, charge pumps, logic elements in the state machine, and other peripheral circuitry) typically employ PMOS devices. The processing operations used to manufacture CMOS dies will differ in many ways from those optimized for NMOS flash NAND memory or other memory cell technologies.

[0031] To mitigate these limitations, the embodiments described below can separate the elements of FIG5 onto separately formed dies that are subsequently bonded together. More specifically, the memory structure 502 can be formed on a single die, and some or all of the peripheral circuitry elements, including one or more control circuits, can be formed on separate dies. For example, the memory die can be formed solely from memory elements (such as flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or arrays of memory cells of other memory types). Some or all of the peripheral circuitry (even including elements such as decoders and sense amplifiers) can then be moved to separate dies. This allows each memory die to be individually optimized according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without concern for the CMOS elements now moved to separate peripheral circuitry dies that can be optimized for CMOS processing. This allows for more space to be used for peripheral components, which can now be combined with the additional ability that was previously limited by the margin of maintaining identical chips in the memory cell array. Two chips can then be bonded together in a bonded multi-chip memory circuit, where an array on one chip is connected to peripheral components on the other memory circuit. While the following focuses on a bonded memory circuit with one memory chip and one peripheral circuit system chip, other embodiments may use more chips, such as two memory chips and one peripheral circuit system chip.

[0032] Figures 6A and 6B show alternative configurations of the arrangement in Figure 5, which can be implemented using wafer-to-wafer bonding to provide bonded die pairs for the integrated memory assembly 600. Figure 6A shows an example of a peripheral circuitry system (including control circuitry) coupled to the peripheral circuitry of the memory structure 602 formed in memory die 601 or formed in control die 611. As with 502 in Figure 5, memory die 601 may include multiple independently accessible arrays or "tiles". Common components are labeled similarly to those in Figure 5 (e.g., 502 is now 602, 510 is now 610, and so on). System control logic 659, column control circuitry system 620, and row control circuitry system 610 (which may be formed by CMOS programming) are visible in control die 611. Additional components (such as functionality from controller 102) may also be moved to control die 611. System control logic 659, column control circuitry 620, and row control circuitry 610 can be formed using a common program (e.g., a CMOS program), so that adding components and functionality more commonly found on memory controller 102 may require few or no additional programming steps (i.e., the same programming steps used to manufacture controller 102 can also be used to manufacture system control logic 659, column control circuitry 620, and row control circuitry 610). Therefore, while moving such circuitry from a memory die such as memory system 500 can reduce the number of steps required to manufacture that die, adding such circuitry to a die such as control die 611 may require no additional programming steps.

[0033] Figure 6A shows a row control circuitry system 610 on a control die 611 coupled to a memory structure 602 on a memory die 601 via an electrical path 606. For example, electrical path 606 can provide electrical connections between the row decoder 612, the driver circuitry system 614, and the block select 616, and the bit lines of the memory structure 602. The electrical path can extend from the row control circuitry system 610 in the control die 611 through corresponding pads on the control die 611 bonded to the memory die 601, these corresponding pads connecting to the bit lines of the memory structure 602. Each bit line of the memory structure 602 can have a corresponding electrical path connected to the row control circuitry system 610 in electrical path 606 (including a pair of bonded pads). Similarly, a column control circuitry system 620, including a column decoder 622, an array driver 624, and a block select 626, is coupled to the memory structure 602 via an electrical path 608. Each electrical path 608 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 611 and the memory die 601.

[0034] Figure 6B is a block diagram showing further details of the configuration of one embodiment of the integrated memory assembly 600 formed by bonded dies. The memory die 601 contains a memory structure 602 of memory cells. The memory die 601 may have additional arrays (e.g., multiple modules, each including an array). A representative bit line (BL) and a representative word line (WL) 666 are depicted for the memory structure 602. Each memory structure 602 may have thousands or tens of thousands of such bit lines. In one embodiment, the array represents a group of interconnected memory cells sharing a common set of unbroken word lines and unbroken bit lines.

[0035] The control die 611 includes a plurality of bit line drivers 650. In some embodiments, each bit line driver 650 is connected to one bit line or may be connected to multiple bit lines. The control die 611 includes a plurality of word line drivers 660(1) to 660(n). The word line drivers 660 are configured to provide voltage to word lines. In this example, there are "n" word lines per array or per plane. In one embodiment, if the memory operation is programmed or read, one word line within a selected block is selected for memory operation. In one embodiment, if the memory operation is erased, all word lines within a selected block are selected for erase. The word line drivers 660 provide voltage to the word lines in the memory die 601. As discussed above in relation to FIG. 6A, the control die 611 may also include charge pumps, voltage generators, and the like, not shown in FIG. 6B, which may be used to provide voltage for the word line drivers 660 and / or the bit line drivers 650.

[0036] The memory die 601 has a plurality of bonding pads 670a, 670b on a first primary surface 682 of the memory die 601. There may be "n" bonding pads 670a to receive voltages from corresponding "n" word line drivers 660(1) to 660(n). Each bit line associated with the memory structure 602 may have one bonding pad 670b. Component symbol 670 will generally be used to refer to the bonding pads on the primary surface 682.

[0037] The control die 611 has a plurality of bonding pads 674a, 674b on a first primary surface 684 of the control die 611. There may be "n" bonding pads 674a to deliver voltage from the corresponding "n" word line drivers 660(1) to 660(n) to the memory die 601. Each bit line associated with the memory structure 602 may have a bonding pad 674b. Component symbol 674 will generally be used to refer to the bonding pad on the primary surface 682. It should be noted that there may be bonding pad pairs 670a / 674a and bonding pad pairs 670b / 674b. In some embodiments, bonding pads 670 and / or 674 are flip-chip bonding pads.

[0038] Compared to Figure 5, the on-chip control circuit of Figure 6A can be more generalized than the capabilities typically found in memory controller 102 and some CPU capabilities, but also includes addition functions, which are application-specific features, within its logic elements.

[0039] In the following text, the system control logic 560 / 660, row control circuitry 510 / 610, column control circuitry 520 / 620, and / or controller 102 (or equivalent functional circuitry), combined with all or a subset of other circuitry depicted on the control die 611 in FIG. 5 or FIG. 6A and similar elements in FIG. 5, can be considered as part of one or more control circuitry that performs the functions described herein. Control circuitry may consist solely of hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of control circuitry. Control circuitry may include processors, FGAs, ASICs, integrated circuits, or other types of circuitry.

[0040] In the following discussion, the memory arrays 502 / 602 of Figures 5 and 6A will be discussed primarily within the context of crosspoint architecture, although much of this discussion can be applied more generally. The following discussion will focus primarily on embodiments based on crosspoint architecture using MRAM memory cells, although many of the arguments can be applied more generally to non-volatile memory cells.

[0041] Figure 7A depicts an embodiment of a memory array forming a crosspoint architecture in a perspective view. The memory arrays 502 / 602 of Figure 7A are examples of embodiments of memory array 502 in Figure 5 or memory array 602 in Figure 6A, wherein a memory die may include multiple such array structures. Bit lines BL1 to BL5 are arranged in a first direction (e.g., "bit line direction") relative to the substrate below the die (not shown) (and are indicated as rows entering the drawing), and word lines WL1 to WL5 are arranged in a second direction perpendicular to the first direction (e.g., "word line direction") (and span the drawing). Figure 7A is an example of a horizontal crosspoint structure, wherein both word lines WL1 to WL5 and BL1 to BL5 travel in a horizontal direction relative to the substrate, and memory cells (both indicated by 701) are oriented such that current flows through the memory cells (such as shown as I cells) in a vertical direction. In memory arrays with additional memory cell layers, such as those related to Figure 7D discussed below, there will be corresponding layers of additional bit lines and word lines.

[0042] As depicted in Figure 7A, memory arrays 502 / 602 include a plurality of memory cells 701. Memory cells 701 may include rewritable memory cells, such as those implemented using ReRAM, MRAM, PCM, FeRAM, or other materials with programmable resistors. Current in the memory cells of the first memory stage is shown as flowing upwards, as indicated by the arrow I cell, but current can flow in either direction, as discussed in more detail below.

[0043] Figures 7B and 7C present the side and top views, respectively, of the intersection structure in Figure 7A. The side view of Figure 7B shows a bottom conductor (or word line) WL1 and top conductors (or bit lines) BL1 to BLn. The intersections between the top and bottom conductors are MRAM memory cells; however, PCM, FeRAM, ReRAM, or other technologies can be used. Figure 7C is a top view illustrating the intersection structure of M bottom conductors WL1 to WLM and N top conductors BL1 to BLN. In a binary embodiment, the MRAM cell at each intersection can be programmed to one of two resistance states: high and low. Further details of embodiments of MRAM memory cell designs and techniques for programming such cells are given below.

[0044] Figure 7A illustrates an embodiment of a single layer / story with word lines and bit lines, where MRAM or other memory cells are located at the intersection of two sets of conductive lines. To increase the storage density of memory chips, multiple layers / stories of such memory cells and conductive lines can be formed. A two-layer / 2-story example is illustrated in Figure 7D.

[0045] Figure 7D depicts an embodiment of a portion of a two-tier (two-layer) memory array forming a crossover architecture in an oblique view. As shown in Figure 7A, Figure 7D shows the first layer (layer / story) 718 of memory cell 701 at the crossover point of word lines WL 1,1 to WL 1,4 and bit lines BL 1 to BL 5 of array 502 / 602. A second layer (layer / story) 720 of the memory cell is formed above bit lines BL 1 to BL 5 and between these bit lines and a second set of word lines WL 2,1 to WL 2,4. Although Figure 7D shows two layers (layers / story) 718 and 720 of the memory cell, the structure can extend upwards through additional alternating layers of word lines and bit lines. Depending on the embodiment, the word lines and bit lines of the array in Figure 7D can be biased for read or programmable operations, allowing current in each layer to flow from the word line layer to the bit line layer or other surrounding paths. The two layers can be structured to allow current to flow in the same direction in each layer for a given operation, for example, from bit line to word line for a read, or to allow current to flow in opposite directions, for example, from word line to bit line for a read of layer 1 and from bit line to word line for a read of layer 2.

[0046] The use of a cross-point architecture allows for arrays with a small footprint, and several such arrays can be formed on a single die. The memory cells formed at each cross-point can be resistive memory cells, where data values ​​are encoded into different resistance levels. Depending on the embodiment, the memory cells can be binary values ​​having a low-resistance state or a high-resistance state, or can be multi-level cells (MLCs) with additional resistance between the low-resistance and high-resistance states. The cross-point array described herein can be used as memory die 292 of FIG4, replacing local memory 106, or both.

[0047] Figure 8 illustrates one embodiment of the structure of an MRAM memory cell. The voltage applied across the memory cell between corresponding word lines and bit lines is represented as voltage source Vapp813. The memory cell includes a bottom electrode 801, a pair of magnetic layers (reference layer 803 and free layer 807) separated by a separating or tunneling layer of magnesium oxide (MgO) 805 (in this example), and a top electrode 811 separated from the free layer 807 by a spacer 809. The state of the memory cell is based on the relative orientation of the magnetization of the reference layer 803 and the free layer 807: if the two layers are magnetized in the same direction, the memory cell will be in a parallel (P) low resistance state (LRS); and if they have opposite orientations, the memory cell will be in an anti-parallel (AP) high resistance state (HRS). MLC embodiments will include additional intermediate states. The orientation of the reference layer 803 is fixed, and in the example of Figure 15, it is oriented upwards. Reference layer 803 is also called a fixed layer or pinned layer.

[0048] Data is written to MRAM memory cells by programming the free layer 807 to have the same or opposite orientation. The reference layer 803 is formed such that it retains its orientation when the free layer 807 is programmed. The reference layer 803 can have a more complex design, including a synthetic antiferromagnetic layer and additional reference layers. For simplicity, these additional layers are omitted in the diagrams and discussion, which focus only on the fixed magnetic layer of the tunneling magnetoresistance in the main responsible cell.

[0049] Figure 9 illustrates in more detail an embodiment of an MRAM memory cell design implemented as a cross-point array. When placed in a cross-point array, the top and bottom electrodes of the MRAM memory cell are connected to two layers of adjacent conductor layers of the array, such as the top and bottom conductors of a second-order or double-layer array. In the embodiment shown here, the bottom electrode is the word line 901 of the memory cell, and the top electrode is the bit line 911 of the memory cell; however, in some embodiments, this can be reversed by reversing the orientation of the memory element. Between the word line 901 and the bit line 911 are a reference layer 903 and a free layer 907, which are again separated by a MgO barrier 905. In the embodiment shown in Figure 9, an MgO cap 908 is also formed on top of the free layer 907, and a conductive spacer 909 is formed between the bit line 911 and the MgO cap 908. The reference layer 903 is separated from the word line 901 by another conductive spacer 902. Pads 921 and 923 are attached to either side of the memory cell structure. These pads may be part of the same structure, but are shown as separate parts in the cross section of FIG9. Some of the filler materials 925 and 927 used to fill the originally empty areas of the intersection structure are shown on either side of pads 921 and 923.

[0050] Regarding the free layer 907, embodiments include a CoFe or CoFeB alloy with a thickness of about 1 to 2 nm, wherein an Ir layer may be intercalated in the free layer adjacent to the MgO barrier 905, and the free layer 907 may be doped with Ta, W, or Mo. Embodiments of the reference layer 903 may include a bilayer of CoFeB and CoPt multilayers coupled to Ir or Ru spacers 902. An MgO cap 908 is optional but may be used to increase the anisotropy of the free layer 907. The conductive spacers may be conductive metals such as Ta, W, Ru, CN, TiN, and TaN, etc.

[0051] To sense the state of data stored in MRAM, a voltage, represented by Vapp, is applied across the memory cell to determine its resistance state. To read an MRAM memory cell, the voltage difference Vapp can be applied in either direction; however, MRAM memory cells are directional, and therefore, in some cases, reading in one direction takes precedence over reading in another. For example, the optimal current amplitude for writing bits to AP (high resistance state, HRS) can be 50% or more larger than the current amplitude for writing to P (low resistance state), so a lower bit error rate (read interference) is less likely when reading from AP (2AP). Some of these cases and the resulting read directionality are discussed below. The directionality of the bias voltage is particularly relevant to some embodiments of MRAM memory cell programming, as further discussed with reference to Figures 10A and 10B.

[0052] The following discussion will primarily focus on MRAM memory cells with vertical spin-transfer torque (STT), where the free layers 807 / 907 in Figures 8 and 9 contain switchable magnetization directions perpendicular to the plane of the free layers. Spin-transfer torque ("STT") is the effect of modifying the orientation of the magnetic layer in the magnetic tunneling interface using spin-polarized current. Charge carriers (such as electrons) have a known property of spin, which is a small amount of angular momentum inherent to the carrier. Current is typically non-polarized (e.g., composed of 50% high-spin electrons and 50% low-spin electrons). Spin-polarized current is the current of more electrons with either spin (e.g., mostly high-spin electrons or mostly low-spin electrons). Spin-polarized current is generated by passing current through a thick magnetic layer (reference layer). If this spin-polarized current is directed into a second magnetic layer (free layer), angular momentum is transferred to this second magnetic layer, changing the magnetization direction of the second magnetic layer. This is called spin-transfer torque. Figures 10A and 10B illustrate the use of spin-transfer torque to program or write MRAM memory. Spin-transfer torque magnetic random access memory (STT MRAM) offers advantages over MRAM variations (such as bi-state thixotropic MRAM) in terms of lower power consumption and better scalability. Compared to other MRAM implementations, STT switching technology requires relatively low power, effectively eliminates the problem of adjacent bit interference, and has more favorable scaling for higher memory cell densities (reducing MRAM cell size). The latter is also advantageous for STT MRAM, where the magnetization systems of the free layer and reference layer are perpendicular to the film plane rather than in-plane oriented.

[0053] Since the STT phenomenon is more easily described in terms of electronic behavior, the discussion in Figures 10A and 10B, and others, is given in terms of electron current, where the direction of the writing current is defined as the direction of electron flow. Therefore, referring to the terminology in Figures 10A and 10B, writing current refers to electron current. Because electrons are negatively charged, the electron current will be in the opposite direction to the conventionally defined current, causing the electron current to flow from a lower voltage level to a higher voltage level, rather than the conventional current flow from a higher voltage level to a lower voltage level.

[0054] Figures 10A and 10B illustrate writing to an MRAM memory cell using the STT mechanism. These figures depict a simplified schematic representation of an example of STT-switched MRAM memory cell 1000, where the magnetization of both the reference layer and the free layer is in the vertical direction. The memory cell 1000 includes a magnetic tunnel junction (MTJ) 1002, which comprises an upper ferromagnetic layer 1010, a lower ferromagnetic layer 1012, and a tunnel barrier (TB) 1014 serving as an insulating layer between the two ferromagnetic layers. In this example, the upper ferromagnetic layer 1010 is the free layer FL, and its magnetization direction is switchable. The lower ferromagnetic layer 1012 is the reference (or fixed) layer RL, and its magnetization direction is not switchable. When the magnetization in the free layer 1010 is parallel to the magnetization in the reference layer RL 1012, the resistance across the memory cell 1000 is relatively low. When the magnetization in the free layer FL 1010 is antiparallel to the magnetization in the reference layer RL 1012, the resistance across the memory cell 1000 is relatively high. Data ("0" or "1") in the memory cell 1000 is read by measuring the resistance of the memory cell 1000. In this regard, electrical conductors 1006 / 1008 attached to the memory cell 1000 are used to read MRAM data. By design, both the parallel and antiparallel configurations remain stable in the quiescent state and / or during read operations (with sufficiently low read current).

[0055] For both the reference layer RL 1012 and the free layer FL 1010, the magnetization direction is in the vertical direction (that is, perpendicular to the plane defined by the free layer and perpendicular to the plane defined by the reference layer). Figures 10A and 10B show the magnetization direction of the reference layer RL 1012 as upward and the magnetization direction of the free layer FL 1010, which is also perpendicular to the plane, as being switchable between upward and downward.

[0056] In one embodiment, the tunneling barrier 1014 is made of magnesium oxide (MgO); however, other materials may also be used. The free layer 1010 is a ferromagnetic metal capable of changing / switching its magnetization direction. Multiple layers based on transition metals (such as Co, Fe, and their alloys) can be used to form the free layer 1010. In one embodiment, the free layer 1010 comprises an alloy of cobalt, iron, and boron. The reference layer 1012 can be made of many different types of materials, including (but not limited to) multiple layers of cobalt and platinum and / or an alloy of cobalt and iron.

[0057] To "set" the MRAM memory cell bit values ​​(i.e., select the free layer magnetization direction), an electron write current 1050 is applied from conductor 1008 to conductor 1006, as depicted in Figure 10A. Due to the negative charge of electrons, the top conductor 1006 is placed at a higher voltage level than the bottom conductor 1008 to generate the electron write current 1050. Because the reference layer 1012 is a ferromagnetic metal, electrons in the electron write current 1050 become spin-polarized as they pass through the reference layer 1012. When spin-polarized electrons tunnel across the tunneling barrier 1014, the conservation of angular momentum results in a spin-transfer torque being applied to both the free layer 1010 and the reference layer 1012, but this torque (by design) is insufficient to affect the magnetization direction of the reference layer 1012. Conversely, if the initial magnetization orientation of free layer 1010 is antiparallel (AP) to reference layer 1012, this spin-transfer torque (by design) is sufficient to switch the magnetization orientation in free layer 1010 to be parallel (P) to the magnetization orientation of reference layer 1012, a process known as anti-parallel-to-parallel (AP2P) writing. Parallel magnetization then remains stable before or after the electronic writing current is turned off.

[0058] Conversely, if the magnetization of free layer 1010 and reference layer 1012 is initially parallel, the magnetization direction of free layer 1010 can be switched to become antiparallel to reference layer 1012 by applying an electron write current in the opposite direction to the above case. For example, electron write current 1052 is applied from conductor 1006 to conductor 1008, as depicted in FIG10B, by setting a higher voltage level on lower conductor 1008. This writes free layer 1010 from the P state to the AP state, called parallel-to-antiparallel (P2AP) writing. Therefore, by the same STT physics, the magnetization direction of free layer 1010 can be definitively set to either of two stable orientations by the deliberate choice of the direction (polarity) of the electron write current.

[0059] Data ("0" or "1") in memory cell 1000 can be read by measuring the resistance of memory cell 1000. Low resistance generally represents a "0" bit and high resistance generally represents a "1" bit, although alternation sometimes occurs. A read current can be applied across memory cells (e.g., across magnetic tunneling junction 1002) by applying an electronic read current flowing from conductor 1008 to conductor 1006 as shown at 1050 in FIG. 10A ("AP2P direction"); alternatively, an electronic read current can be applied from conductor 1006 to conductor 1008 as shown at 1052 in FIG. 10B ("P2AP direction"). During a read operation, if the electronic write current is too high, this can interfere with the data stored in the memory cell and change its state. For example, if the electronic read current uses the P2AP direction of FIG. 10B, a current or voltage level that is too high can switch any memory cell in the low-resistance P state to the high-resistance AP state. Therefore, although MRAM memory cells can be read in either direction, the directional nature of write operations can make one read direction superior to another, such as the P2AP direction in various embodiments, because more current is required to write bits in that direction.

[0060] Although the discussion in Figures 10A and 10B takes place in the context of electronic currents used for reading and writing currents, unless otherwise specified, the subsequent discussion will take place in the context of conventional currents.

[0061] Whether reading from or writing to the selected memory cells in the array structures of Figures 7A through 7D, the bit lines and word lines corresponding to the selected memory cells are biased to apply a voltage across the selected memory cells, causing an electron flow as illustrated in Figures 10A or 10B. This also applies a voltage across the non-selected memory cells of the array, which can induce current in the non-selected memory cells. While this wasted power consumption can be mitigated to some extent by designing the memory cells to have relatively high resistance levels for both high and low resistance states, this still results in increased current and power consumption and places additional design constraints on the design of the memory cells and the array.

[0062] One approach to address this unwanted current leakage is to place a selector element in series with each MRAM or other resistive (e.g., ReRAM, PCM, and FeRAM) memory cell. For example, the selector transistor can be placed in series with each resistive memory cell element in Figures 7A through 7D, such that memory cell 701 is now a combination of a selector and a programmable resistor. However, the use of transistors requires the introduction of additional control lines to enable the corresponding transistor via the selected memory cell. Furthermore, transistors often cannot scale in the same way as resistive memory elements, making the use of transistor-based selectors a limiting factor when memory arrays are moved to smaller sizes.

[0063] An alternative to the selector element is a threshold switching selector device connected in series with a programmable resistive element. When the threshold switching selector is biased to a voltage lower than its threshold voltage, it has high resistance (in the off or non-conducting state); when biased to a voltage higher than its threshold voltage, it has low resistance (in the on or conducting state). The threshold switching selector remains on until its current falls below a holding current, or its voltage falls below a holding voltage. When this occurs, the threshold switching selector returns to the off state. Therefore, to program memory cells at the crossover point, a voltage or current sufficient to turn on the associated threshold switching selector is applied to set or reset the memory cell; and to read the memory cell, the threshold switching selector must similarly be activated by turning on before the resistive state of the memory cell can be determined. One example of a threshold switching selector is the bidirectional threshold switching material of a bidirectional threshold switch (OTS).

[0064] Figures 11A and 11B illustrate an embodiment incorporating a threshold switching selector into an MRAM memory array with a crosspoint architecture. The examples in Figures 11A and 11B show two MRAM cells in a two-layer (2-layer) crosspoint array, as shown in Figure 7D, but in a side view. Figures 11A and 11B show the first lower conductive line of word line 1 1100, the first upper conductive line of word line 2 1120, and the second intermediate conductor of bit line 1110. In these figures, for ease of representation, all such lines are shown as if traveling across the page from left to right. A more accurate representation of these lines in the crosspoint array is shown in the oblique view of Figure 7D, where the word line (or first conductive line or conductor) travels in a direction parallel to the surface of the underlying substrate, and the bit line (or second conductive line or conductor) travels in a second direction, primarily orthogonal to the first direction and parallel to the surface of the substrate. MRAM memory cells are also represented in a simplified form, showing only the reference layer, free layer, and intermediate tunneling barrier. However, in actual implementations, additional structures related to Figure 9 described above are generally included.

[0065] An MRAM device 1102, comprising a free layer 1101, a tunneling barrier 1103, and a reference layer 1105, is formed on a threshold switching selector 1109. This series combination of the MRAM device 1102 and the threshold switching selector 1109 forms a layer 0 cell between bit line 1110 and word line 11100. When the threshold switching selector 1109 is turned on, the series combination of the MRAM device 1102 and the threshold switching selector 1109 operates as described above as relating to Figures 10A and 10B, except for some voltage drop across the threshold switching selector 1109. Although the threshold switching selector 1109 initially needs to be turned on by applying a voltage higher than its threshold voltage Vth, the bias current or voltage then needs to be maintained high enough to be higher than the holding current or holding voltage of the threshold switching selector 1109 to keep it on during subsequent read or write operations.

[0066] In Layer 1, an MRAM device 1112, comprising a free layer 1111, a tunneling barrier 1113, and a reference layer 1115, is formed on a threshold switching selector 1119. The series connection of the MRAM device 1112 and the threshold switching selector 1119 forms a Layer 1 cell between bit line 1110 and word line 2 1120. The Layer 1 cell operates as a Layer 0 cell, except that the lower conductor now corresponds to bit line 1110 and the upper conductor now corresponds to word line 2 1120.

[0067] In the embodiment of FIG11A, the threshold switching selectors 1109 / 1119 are formed below the MRAM devices 1102 / 1112, but in alternative embodiments, the threshold switching selectors may be formed above one or two layers of MRAM devices. As discussed with respect to FIG10A and FIG10B, the MRAM memory cells are directional. In FIG11A, MRAM devices 1102 and 1112 have the same orientation, wherein the free layer 1101 / 1111 is above the reference layer 1105 / 1115 (relative to a substrate not shown). Since each of these two layers, and subsequent layers in embodiments with more layers, can be formed according to the same manufacturing sequence, forming such layers with the same structure between conductive lines can have several advantages, particularly regarding process advantages.

[0068] Figure 11B illustrates an alternative embodiment configured similarly to the embodiment of Figure 11A, except that in the Layer 1 cell, the positions of the reference layer and the free layer are reversed. More specifically, as shown in Figure 11A, between word line 1 1150 and bit line 1160, the Layer 0 cell includes an MRAM structure 1152 having a free layer 1151 formed above a tunneling barrier 1153, which is rotatably formed above the reference layer 1155, wherein the MRAM structure 1152 is formed above the threshold switching selector 1159. The upper layer (Layer 1) of the embodiment of Figure 11B again has an MRAM device 1162 formed above the threshold switching selector 1169 between bit line 1160 and word line 2 1170, but relative to Figure 11A, with the MRAM device 1162 reversed, the reference layer 1161 is now formed above the tunneling barrier 1163 and the free layer 1165 is now below the tunneling barrier 1163.

[0069] While the embodiment of Figure 11B requires different programming sequences for layer formation, it can have advantages in some embodiments. Specifically, the directionality of the MRAM structure makes the embodiment of Figure 11B attractive because when writing or reading in the same direction (relative to the reference layer and the free layer), the bit lines are biased equally to both the lower and upper layers, and the two word lines will be biased equally. For example, if the memory cells of layer 1 and layer 2 are sensed in the P2AP direction (relative to the reference layer and the free layer), bit line 1160 will be biased in such a P2AP direction, and with word lines 1 1150 and 2 1170 both biased to higher voltage levels, bit line 1160 will be biased low (e.g., 0V) to both the upper and lower cells. Similarly, regarding write operations, for a write to a high-resistance AP state, with both word line 1 1150 and word line 2 1170 biased to a higher voltage level, bit line 1160 is biased low (e.g., 0V) to both the upper and lower cells; and for a write to a low-resistance P state, with both word line 1 1150 and word line 2 1170 biased to a low voltage level, bit line 1160 is biased to a high voltage level. Conversely, in the embodiment of FIG11A, the bit lines and word lines would need to have their bias levels reversed for any operation performed at a higher level relative to the lower level.

[0070] Reading data from or writing data to an MRAM memory cell involves passing current through the memory cell. In embodiments where a threshold switching selector is placed in series with the MRAM device, the threshold switching selector needs to be turned on by applying a sufficient voltage across the series combination of the threshold switching selector and the MRAM device before current can pass through the MRAM device.

[0071] Figure 12 illustrates an example of a memory structure 602 having multiple corresponding word line drivers 660 and multiple bit line drivers 650 (the word line drivers 660 and bit line drivers 650 may be on a memory die having the memory structure 602 or on a separate die connected to the memory die containing the memory structure 602). Two bit lines (BL0 and BLn) and two word lines (WL0 and WLn) are shown together with a first memory cell 1670 and a second memory cell 1672 (additional lines and memory cells are omitted for clarity). The first memory cell 1670 (the nearby memory cell) is relatively close to both the multiple word line drivers 660 and the multiple bit line drivers 650. The first memory cell 1670 is connected to (a plurality of) bit line drivers 650 via BLn (which has an effective bit line length BLmin) and to (a plurality of) word line drivers 660 via WL0 (which has an effective word line length WLmin). This provides a combined electrical distance (combined effective word line and bit line lengths) BLmin + WLmin. The second memory cell 1672 (a remote memory cell) is relatively remote from both (a plurality of) word line drivers 660 and (a plurality of) bit line drivers 650. The second memory cell 1672 is connected to (a plurality of) bit line drivers 650 via BL0 (which has an effective bit line length BLmax) and to (a plurality of) word line drivers 660 via WLn (which has an effective word line length WLmax). This provides a combined electrical distance (combined effective word line and bit line lengths) BLmax + WLmax.

[0072] The resistance of electrical conductors such as word lines or bit lines (which can be considered substantially uniform in cross-section) depends on the length of the conductor and can increase linearly with length (e.g., the resistance per unit length can be considered uniform, so the total resistance is proportional to the length). Due to different electrical distances and their associated resistances, memory access operations (e.g., write operations including set and / or reset operations) for the first memory cell 1670 and the second memory cell 1672 can have different results. For example, non-uniform resistance of word lines and bit lines can lead to non-uniform series resistance and non-uniform memory access current (e.g., write current for set and / or reset), which can result in non-uniform programming and a higher error rate compared to a more uniform memory access current.

[0073] First memory cell 1670 and second memory cell 1672 represent either end of a possible range of electrical distances from the memory cells of memory structure 602 to the bit lines and word line drivers (e.g., in memory structure 602, BLmin and BLmax may be the minimum and maximum bit line distances, respectively, while WLmin and WLmax may be the minimum and maximum word line distances, respectively). Other memory cells may have electrical distances at some point within this range, corresponding word line and bit line distances and resistances between the word line and bit line distances and resistances of the first memory cell 1670 and the second memory cell 1672, which may result in a series resistance between the series resistances of the first memory cell 1670 and the second memory cell 1672. The word line and bit line resistances associated with accessing different memory cells can be predicted based on the individual locations of the cells in the memory structure (e.g., based on individual distances to the word line and bit line drivers).

[0074] Although Figure 12 shows examples of WL and BL drivers connected to the ends of word lines and bit lines respectively, this technique is not limited to any particular configuration of lines and individual driver circuits.

[0075] Figures 13A and 13B illustrate an example of a portion of a cross-point MRAM structure 1330, wherein the connection of the lines is formed at or near its midpoint. For example, Figure 13A shows a selected memory cell 1332 connected between selected word line 1334 and selected bit line 1336. Figure 13A shows a WL driver 660 connected at the midpoint of selected WL 1334 and a BL driver 650 connected at the midpoint of selected BL 1336. Because the selected memory cell 1332 is located near the midpoint of selected WL 1334 and selected BL 1336, at or near the connection of the respective WL and BL drivers, the series resistance of selected WL 1334 and selected BL 1336 can be very small (e.g., zero or close to zero) when accessing the selected memory cell 1332. Typically, the conductive lines between the driver and the word lines or bit lines (e.g., conductive lines 1338 and 1339) have a relatively large cross-sectional area (e.g., thicker and / or wider than WL or BL), resulting in a lower resistance than the BL and WL resistances. In some cases, such resistance can be ignored, while in others, it can be considered part of the WL and BL resistances, respectively.

[0076] Figure 13B shows another selected memory cell 1342 connected between selected word line 1344 and selected bit line 1346. Figure 13B shows a WL driver 660 connected at the midpoint of selected WL 1344 and a BL driver 650 connected at the midpoint of selected BL 1346. Because the selected memory cell 1342 is located relatively far from the midpoint of selected WL 1344 and selected BL 1346, away from the connections to the individual WL and BL drivers, the series resistance (RWL) of selected WL 1344 and the series resistance (RBL) of selected BL 1346 are significant when accessing the selected memory cell 1342.

[0077] Although Figures 12-13B show two configurations (end connection and midpoint connection) for connecting driver circuitry to word lines and bit lines, other configurations are possible and the technique is not limited to any particular configuration. Typically, accessing memory cells at different locations within a memory structure may include allowing current to flow through electrical conductors connected in series with selected memory cells (e.g., via selected word lines and bit lines) that have different resistances (e.g., depending on their distance from the individual driver circuitry). Such different resistances can affect memory access operations, including write operations (e.g., MRAM reset operations).

[0078] Figures 14A and 14B illustrate the current flowing through two selected memory cells during a write (reset) operation. Figure 14A shows selected memory cell 1450 in layer 0 (e.g., layer 0 cells in Figures 11A and 11B) and Figure 14B shows selected memory cell 1452 in layer 1 (e.g., layer 1 cells in Figures 11A and 11B). In Figure 14A, WL driver 660 provides voltage VPP and BL driver 650 provides voltage VNN to allow the reset current Ireset to flow through the selected WL (shown as R WL), selected memory cell 1450, and selected BL (shown as R BL). In Figure 14B, BL driver 650 provides voltage VPP and WL driver 660 provides voltage VNN to allow the reset current Ireset to flow through the selected BL (shown as R BL), selected memory cell 1452, and selected WL (shown as R WL). In both examples, the word line resistance, RWL, bit line resistance, and RBL are schematically shown as variable resistors connected in series with the selected memory cell (e.g., connected in series between the WL driver and the BL driver). Figures 14A and 14B can be considered general schematics of any selected memory cell in individual layers, where the resistance of the variable resistors RWL and RBL depends on the location of the selected memory cell, as illustrated in the examples of Figures 12 and 13B. The layer in which a particular memory cell is located can affect the series resistance because, for example, current can flow in different directions and different lines can be used (e.g., in Figure 11A, layer 0 is accessed through word line 1, while layer 1 is accessed through word line 2). Additional factors (e.g., layers and locations in addition to the WL and BL directions) can also affect the series resistance when accessing different memory cells (e.g., differences in memory structure due to program variations, differences due to environmental factors such as temperature, and / or other differences).

[0079] According to various embodiments of this technology, one or more variable resistors can be connected in series with selected non-volatile memory cells and can be set according to the location of the selected non-volatile memory cells (e.g., according to the layer and location along the WL and BL directions). For example, when receiving an address corresponding to one location in the non-volatile memory cell structure (e.g., from the host, memory controller, or otherwise received in a memory access command such as a write command), the variable resistor(s) can be set to appropriate resistance values ​​depending on the location, based on a previously established relationship. The variable resistor(s) can be used to balance the effects of different layer, word line and / or bit line resistances, and / or other factors, such that the total series resistance of the selected word line, the selected bit line, and the variable resistors is substantially equal for all memory cells at all locations in the non-volatile memory cell structure. For example, when the WL and / or BL resistances are relatively low (e.g., memory cell 1670 or 1332), the variable resistor(s) can be set to have relatively high resistances. When the WL and / or BL resistances are relatively high (e.g., memory cell 1672 or 1342), the variable resistor(s) can be set to have relatively low resistances. In this context, "substantially equal" can mean that the total series resistance of the selected word line, selected bit line, and variable resistor(s) of all memory cells is within a certain range (e.g., an average of + / - 1%, 2%, 5%, or 10%), where an appropriate range can be selected based on the influence of different series resistances in a given memory structure.

[0080] Figures 15A and 15B illustrate examples of variable resistors connected in series with selected non-volatile memory cells in story 0 and story 1, respectively (for example, Figures 15A and 15B are schematic diagrams corresponding to Figures 14A and 14B, with variable resistors added).

[0081] Figure 15A shows a variable resistor 1570 with resistance RVAR connected in series with the selected memory cell 1450, and in series with the selected word line and bit line, respectively, having resistances RWL and RBL. Since the series resistances RWL and RBL vary depending on the location of the selected memory cell 1450, the variable resistor 1570 can be set to a resistance value that tends to maintain a constant total series resistance (e.g., such that RWL + RBL + RVAR = constant), and it can also tend to ensure substantially equal memory access currents from one location to another (e.g., Ireset). For example, if the values ​​of RWL + RBL + RVAR are within + / - 1%, 2%, 5%, or 10% of the average resistance value, then Ireset is expected to remain within the corresponding range of + / - 1%, 2%, 5%, or 10% of the average current value. Appropriate ranges can be selected based on the effects of different series resistances and currents in a given memory structure.

[0082] Similarly, in Figure 15B, the variable resistor 1572 can be set to a resistance value based on the location of the selected memory cell 1452, which may tend to maintain a constant total series resistance and a constant Ireset resistance. For example, control circuitry on the same die as the memory structure or on another die can set the variable resistor to a location-dependent resistance value, such that for locations corresponding to higher combined word line resistance and bit line resistance, the resistance value is lower, and for locations with lower combined word line resistance and bit line resistance, the resistance value is set to higher. The resistance value can be set to lower for locations corresponding to higher combined word line resistance and bit line resistance, and can be set to higher for locations with lower combined word line resistance and bit line resistance. The positions corresponding to the higher combined word line resistance and bit line resistance can be located in one or more corner regions of the non-volatile memory structure (e.g., as shown in Figures 12 and 13B), and the positions corresponding to the lower combined word line resistance and bit line resistance can be located in another corner region (e.g., as shown in Figure 12) or the central region (e.g., as shown in Figure 13A) of the non-volatile memory structure.

[0083] Although Figures 15A and 15B show various examples of implementing this technique using a single variable resistor, in other examples, two or more variable resistors may be used. Figures 15C and 15D show examples of using two variable resistors in layer 0 and layer 1, respectively.

[0084] Figure 15C shows an example including a first variable resistor 1570 with resistance R VAR1 and a second variable resistor 1571 with resistance R VAR2, which are connected in series with a selected memory cell 1450 and corresponding selected WL and BL. The combined resistance of the first resistor 1570 and the second resistor 1571 can be controlled according to the location of the selected memory cell 1450 and / or other factors to provide a substantially uniform total series resistance. For example, since the series resistances R WL and R BL vary according to the location of the selected memory cell 1450, the first variable resistor 1570 and the second variable resistor 1571 can be set to resistance values ​​that tend to keep the total series resistance constant (e.g., such that R WL + R BL + R VAR1 + R VAR2 = constant), which can also tend to ensure substantially equal memory access currents (e.g., Ireset) from one location to another. In one example, each variable resistor is individually controlled to compensate for the variable resistance of the corresponding line (e.g., BL or WL), such that, for example, R WL + R VAR1 = constant and R BL + R VAR2 = constant.

[0085] Figure 15D shows an example including a first variable resistor 1572 with resistance RVAR1 and a second variable resistor 1573 with resistance RVAR2, which are connected in series with the selected memory cell 1452 and the corresponding selected WL and BL in layer 1. The combined resistance of the first resistor 1572 and the second resistor 1573 can be controlled according to the position of the selected memory cell 1452 and / or other factors to provide a substantially uniform total series resistance. For example, since the series resistances RWL and RBL vary according to the position of the selected memory cell 1452, the first variable resistor 1572 and the second variable resistor 1573 can be set to resistance values ​​that tend to keep the total series resistance constant (e.g., such that RWL + RBL + RVAR1 + RVAR2 = constant), which can also tend to ensure substantially equal memory access currents (e.g., Ireset) from one position to another. The number and location of the variable resistors shown in these examples are for illustrative purposes, and it should be understood that any number of variable resistors connected to any suitable one or more locations can be used to add variable resistance.

[0086] Appropriate series resistors can be implemented in different ways. For example, memory cells in a memory structure can be partitioned based on their distance from or connection to the driver circuitry and the associated series resistance of individual word lines and bit lines (e.g., memory cell 1332 may be in a first region, while memory cell 1342 may be in a second region). The number of such regions can be selected based on the range of the WL and BL resistors and the desired degree of current uniformity for a given memory structure. The number of regions can range from two to the number of memory cells. In memory structures with layers (or stories) of different configurations, different layers can receive different resistances (e.g., different RVA values), allowing appropriate series resistors to be selected based on the location specified by the regions and layers.

[0087] In some instances, the setting of a variable resistor can be obtained by testing the memory die to optimize the resistance value. For example, the resistance value of layer 1 can differ from that of layer 2, except for differences based on the location of word line and bit line resistances. Other factors can also affect memory access operations and can be addressed using variable resistors. For example, temperature and / or other environmental factors can affect memory access operations. In some instances, one or more variable resistors can be used to compensate for temperature-related effects (e.g., the resistance value can be selected based on temperature and / or location). When the resistance value is obtained, it can be stored in a record (e.g., a lookup table or other structure stored in the memory die) for subsequent use when accessing the memory cell structure.

[0088] In one instance, the access current, which in this case is the write current (reset current), can be approximated by the following equation: Where: V supply = total supply voltage across the path (e.g., VPP + VNN); Vselector = voltage drop across the ON selector; R VAR = the resistance of (multiple) variable resistors (e.g., the R VAR of variable resistor 1570 or a combination of R VAR1 and R VAR2 of variable resistors 1570 and 1571); R MRAM = Voltage drop across the MRAM, which depends on the state of the MRAM; RBL = Voltage drop across the BL conductor; RWL = voltage drop across the conductor WL; and R CMOS = Voltage drop across all CMOS elements in the path.

[0089] By adjusting the value of R VAR, consistency of Iwrite can be achieved for different locations with different R BL and R WL (for example, Iwrite at all locations can be maintained within a predetermined range).

[0090] Variable resistors (e.g., variable resistors 1570 and / or 1572) used for series connection with memory cells can be implemented in any suitable manner. Figure 16 shows an example implementation of variable resistor 1570 comprising N switchable resistors connected in parallel (e.g., between a driver circuit such as WL driver 660 or BL driver 650 and a word line or bit line of a non-volatile memory cell structure). The resistance RVAR of variable resistor 1570 depends on which resistors are activated by closing individual switches. The resistances R1 to RRN of each switchable resistor can be configured to provide a wide range of possible resistance values. For example, R1 can be a relatively small resistance, R2 can be 2xR1, R3 can be 4xR1, R4 can be 8xR1, etc., where RRN = 2NxR1. The desired resistance can be obtained by activating only the selected resistors.

[0091] Figure 17A shows an example of a control circuit that can be used to control the resistance of a variable resistor (e.g., variable resistor 1570) in any of the foregoing examples. The variable resistor 1570 is shown as having a plurality of switchable resistors formed by a CMOS device (e.g., the size of the CMOS device can be selected to produce appropriate resistances R1 to RN). Digital media control circuitry 1780 receives address 1782 (e.g., in a write command or other memory access command from a memory controller).

[0092] The digital media control circuitry 1780 may also receive an additional input 1784. For example, the additional input 1784 may include temperature or other information about conditions that may affect memory access operations. In one example, the temperature is obtained from on-chip temperature measurement circuitry (e.g., temperature measurement circuits 563 and 663) and received by the digital media control circuitry 1780 as an additional input 1784. The digital media control circuitry 1780 may use address 1782 to generate location information in an appropriate format. For example, the location information may be generated in the form of regions (e.g., where memory cells in a memory structure are partitioned according to their location along the WL and BL directions and the associated series resistances of WL and BL) and layers (e.g., where the memory structure consists of layers (story or layer) with different characteristics (e.g., illustrated in Figures 11A to 11B)).

[0093] Digital media control circuitry 1780 sends data 1786 to library controller 1788, where data 1786 may include location information (e.g., region and layer) along with any other information (e.g., temperature). Library controller 1788 can use data 1786 to determine the appropriate series resistor (e.g., the value of R VAR). For example, library controller 1788 may check the received location and / or other data in data 1786 to find the corresponding entry in record 1790. Record 1790 may be a lookup table or other such structure with entries linking the region and / or temperature to resistor settings. Record 1790 may be stored in registers 561, 661, or other such structures. Resistor settings 1792 from record 1790 (e.g., in trimmed bits or other forms) are sent to module logic 1794. Module logic 1794 generates a signal to enable / disable the selected switchable resistor 1570 according to resistor setting 1792 (e.g., closing a switch to enable the corresponding resistor to achieve the desired value of R VAR).

[0094] Figure 17B shows an example of a control circuit that can be used to control the resistance of two variable resistors (e.g., variable resistors 1570 and 1571 of Figure 15C). Variable resistors 1570 and 1571 are each shown as having a plurality of switchable resistors formed by a CMOS device (e.g., the size of the CMOS device can be selected to produce appropriate resistances R1 to RN). Digital media control circuitry 1780, library controller 1788, and recording 1790 can operate as previously described. Module logic 1794 generates signals to enable / disable the selected switchable resistors of variable resistors 1570 and 1571 according to resistor setting 1792 (e.g., closing a switch to enable the corresponding resistors to achieve the desired values ​​of R VAR1 and R VAR2).

[0095] The components shown in Figures 17A and 17B can be considered as an example of a component that sets a variable resistor (e.g., variable resistor 1570) to a resistance value selected according to the location of the non-volatile memory cell in the non-volatile memory cell structure to be accessed, and accesses the non-volatile memory cell by passing current through the variable resistor connected in series with the non-volatile memory cell (e.g., in conjunction with read and / or write circuitry such as column control circuitry 520 and row control circuitry 510 and / or system control logic 560).

[0096] Although the examples in Figures 17A and 17B show specific components in a particular configuration, the present invention can be implemented using different components in different configurations. For example, the control circuitry system (including digital media control circuitry 1780, library controller 1788, recording 1790, module logic 1794, and variable resistor 1570) used to implement the present invention can be located on a memory die (e.g., on a die with the same memory structure connected to the variable resistor 1570) or on another die (e.g., a control die) or a combination thereof (e.g., some on-chip circuitry and some off-chip circuitry).

[0097] Figure 18 shows an example of a method according to various embodiments of the present technology. The method includes receiving a plurality of addresses 1810 corresponding to locations in a cross-point magnetoresistive random access memory (MRAM) structure (e.g., receiving addresses in a memory access command such as a write command), setting a plurality of variable resistors connected in series with selected non-volatile memory cells at the locations, each variable resistor being set to a respective resistance value 1812 depending on the location of the selected non-volatile memory cell to which it is connected (e.g., setting the RVAR of variable resistor 1570 according to the location), and driving memory access current through the selected non-volatile memory cell and variable resistor 1814 (e.g., driving Ireset as shown in Figures 15A to 15B to write data).

[0098] Figure 19 illustrates an example of a method that can be used to configure a data storage system. The method includes mapping non-volatile memory cells of a memory structure to a plurality of regions 1920 (e.g., from "near" cells with low WL and BL resistances to "far" cells with high WL and BL resistances) based on WL and BL resistances, and for each region, determining an appropriate additional series resistance to achieve a uniform total series resistance 1922 (e.g., determining an appropriate value for R VAR to achieve more uniform current when accessing memory cells in different regions). The method further includes recording the additional series resistance 1924 of each region (e.g., in record 1790), and when accessing such memory cells, controlling a variable resistor 1926 connected in series with the memory cell in each region based on the recorded additional series resistance of that region (e.g., controlling the R VAR of variable resistor 1570 based on data from record 1790).

[0099] The method shown in Figure 19 can be performed as a single operation across a wide range of memory structures. For example, appropriate additional series resistances can be determined by calculation or experimentation and can be loaded and used in all similar memory dies. Alternatively, appropriate additional series resistances can be obtained on a die-by-die, plane-by-plane, block-by-block, or other basis and can be customized accordingly so that different dies use different resistances and / or different portions of the memory structure within a die use different resistances. In some cases, some or all of the steps of the procedure in Figure 19 can be performed multiple times on a given memory structure or a portion thereof. For example, after a period of use, step 1922 can be performed to obtain new additional series resistances, which can be recorded and subsequently used to access memory cells. Such operations can be triggered by elapsed time, usage (e.g., write-erase cycle counts), error rates (e.g., detected by ECC decoding), or other triggering events.

[0100] According to a first configuration sample, a device includes one or more control circuits configured to be connected to a non-volatile memory cell structure, the non-volatile memory cell structure including non-volatile memory cells each having a programmable resistive element. The one or more control circuits are configured to receive an address corresponding to a location in the non-volatile memory cell structure and to set a variable resistor according to the location. The variable resistor is connected in series with a selected non-volatile memory cell located at that location. The one or more control circuits are further configured to drive a memory access current through the selected non-volatile memory cell and the variable resistor connected in series.

[0101] In one or more of the above-described devices, the one or more control circuits are connected to a memory controller and configured to receive the address from the memory controller in a command from the memory controller.

[0102] In one or more of the above-described devices, the command is a write command used to write data to the location in the non-volatile memory, and the memory access current is a write current.

[0103] In one or more of the above-described devices, the control circuits are configured to set the variable resistor to a resistance value that depends on the location, such that for a location corresponding to a higher combined word line resistance and bit line resistance, the resistance value is a lower resistance value, and for a location having a lower combined word line resistance and bit line resistance, the resistance value is set to a higher resistance value.

[0104] In one or more of the above-described devices, the higher combined word line resistance and bit line resistance connected in series with the lower resistance value are substantially equal to the lower combined word line resistance and bit line resistance connected in series with the higher resistance value.

[0105] In one or more of the above-described devices, the positions corresponding to the higher combined word line resistance and bit line resistance are located in one or more corner regions of the non-volatile memory cell structure, and the positions corresponding to the lower combined word line resistance and bit line resistance are located in the central region of one of the non-volatile memory cell structures.

[0106] In one or more of the above-described devices, the variable resistor includes a plurality of switchable resistors connected in parallel between a driver circuit and a word line or bit line of the non-volatile memory cell structure.

[0107] In one or more of the above-mentioned devices, the non-volatile memory cell structure includes a plurality of word lines extending along a word line direction, a plurality of bit lines extending along a bit line direction perpendicular to the word line direction, and a plurality of non-volatile memory cells extending vertically, each non-volatile memory cell being connected between word lines.

[0108] In one or more of the above-described devices, each non-volatile memory cell includes a selector connected in series with the programmable resistive element.

[0109] According to another configuration, a method includes receiving a plurality of addresses corresponding to locations in a crosspoint magnetoresistive random access memory (MRAM) structure; setting a plurality of variable resistors connected in series with selected non-volatile memory cells at the locations, each variable resistor being set to a resistance value depending on a location of one of the selected non-volatile memory cells connected thereto; and driving memory access current through the selected non-volatile memory cells and the variable resistors.

[0110] In one or more of the above methods, each variable resistor is set to a value depending on the location of the selected non-volatile memory cell to which it is connected, such that for each selected non-volatile memory cell, the series resistance of each word line, bit line, and variable resistor is substantially equal.

[0111] In one or more of the above methods, driving the memory access current includes driving substantially equal memory access currents through each of the selected non-volatile memory cells.

[0112] In one or more of the above methods, setting the plurality of variable resistors includes enabling only the selected resistor among the plurality of resistors connected in parallel for each variable resistor.

[0113] In one or more of the above methods, setting the plurality of variable resistors includes checking each address by referring to a record indicating the corresponding resistor to be selected.

[0114] In one or more of the above methods, the method further includes measuring the temperature at or near the intersection MRAM structure; and setting the plurality of variable resistors to their respective resistance values ​​based on the location and the temperature.

[0115] In one or more of the above methods, the method further includes testing a die including the MRAM structure to determine the individual resistance values ​​at the locations; and storing the individual resistance values ​​of the die in the die.

[0116] In one or more of the above methods, the method further includes, after storing the individual resistance values, performing memory access operations using the individual resistance values ​​during a first time period; subsequently, repeatedly testing the die to determine new individual resistance values ​​at the locations; storing the new individual resistance values ​​in the die; and subsequently using the new individual resistance values ​​during a second time period.

[0117] In another configuration, a system includes a non-volatile memory cell structure comprising non-volatile memory cells each having a programmable resistive element; and components for: setting a variable resistor to a resistance value selected according to a location of the non-volatile memory cell in the non-volatile memory cell structure to be accessed, and accessing the non-volatile memory cell by passing a current through the variable resistor connected in series with the non-volatile memory cell.

[0118] In one or more of the above-described systems, the system further includes a temperature measurement circuit connected to the component for setting the variable resistor to provide a temperature measurement to the component for selecting the resistance value.

[0119] In one or more of the above systems, the non-volatile memory cell structure is located on a memory die, and the component for setting the variable resistor is located on a control die bonded to the memory die.

[0120] For the purposes of this document, references to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" in this specification may be used to describe different or the same embodiments.

[0121] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is referred to as a connection or coupling to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intermediary element. When an element is referred to as being directly connected to another element, there is no intermediary element between the element and the other element. If two devices are directly or indirectly connected such that they can transmit electronic signals between them, the devices are "in communication".

[0122] For the purposes of this document, the term "based on" can be interpreted as "based at least in part on".

[0123] For the purposes of this document, without additional context, the use of numerical terms (such as "first" object, "second" object, and "third" object) may not imply the order of objects, but may instead be used for identification purposes to distinguish different objects.

[0124] For the purposes of this document, the term "set" as used to refer to an "ensemble" of one or more objects.

[0125] The above embodiments have been provided for purposes of illustration and description. They are not intended to be exhaustive or limited to the precise forms disclosed. In view of the foregoing teachings, many modifications and variations are possible. The described embodiments have been selected to best explain the principles and practical application of the proposed technology, thereby enabling those skilled in the art to best utilize it in various embodiments and to contemplate various modifications suitable for that particular purpose. It is intended that this scope be defined by the appended claims.

[0126] 100: Memory System 102: Controller; Memory Controller 104: Non-volatile memory; memory packaging 106: Local Memory; DRAM 110: Front-end processor circuit; FEP circuit 112: Back-end processor circuit; BEP circuit 120: Host 122: Host Processor 124: Host Memory 126: PCIe Interface 128: Busbar 130: Interface 150: PCIe Interface 152: Host Processor 154: Chip Network; NOC 156: Memory Processor 158: Media Management; Media Management MML; MML 160:SRAM 162: DRAM controller 164: PCIe Interface 166: PCIe Interface 200: PCIe Interface 202:NOC; Top NOC 204:NOC; Bottom NOC 220: Processor 222: Data Path Controller 224: XOR Engine 226: ECC Engine 228: Interface 230:SRAM 232: Buffer 250: Processor 252: Data Path Controller 254: XOR Engine 256: ECC Engine 258: Interface 260:SRAM 262: Buffer 292: Memory chip 294: Memory Bus 296: Dual-state thixotropic mode interface 326: Memory Structure 500: Memory System 502: Memory array; memory structure; array 506: Input / Output 508: Output 510: Line control circuit system 512: Line Decoder 514: Array terminal receiver or driver 516: Block Selection Circuit System 520: Train control circuit system 522: Column Decoder 524: Array Termination Driver 526: Block Selection Circuit System 560: System control logic circuit; system control logic 561: Temporary Register 563: Temperature Measurement Circuit 600: Integrated Memory Assembly 601: Memory chip 602: Memory structure; memory array; array 606: Electrical Path 608: Electrical Path 610: Line control circuit system 611: Controlling grain size 612: Line Decoder 614: Driver Circuit System 616: Block Selection 620: Train control circuit system 622: Column Decoder 624: Array Driver 626: Block Selection 650: Bit line driver; BL driver 659: System Control Logic 660: Word line driver; WL driver 660(1)-660(n): word line driver; BL driver 661: Temporary Register 663: Temperature Measurement Circuit 666: Representative Bit Line (BL) and Representative Word Line (WL) 670: Bonding pad 670a, 670b: Bonding pads 674: Bonding pad 674a, 674b: Bonding pad 682: First principal surface; principal surface 684: First Principal Surface 701: Memory Unit 718: First Floor 720: Second Floor 801: Bottom Electrode 803: Reference Layer 805: Magnesium oxide (MgO) 807: Free Layer 809: Spacers 811: Top Electrode 813: Voltage source V app 901: Word Line 902: Conductive spacer 903: Reference Layer 905:MgO barrier 907: Free Layer 908: MgO cap 909: Conductive spacer 911: Bitline 921: Padding 923: Padding 925: Filler material 927: Filler material 1000: STT switching MRAM memory unit; memory unit 1002: Magnetic Tunneling Joint (MTJ) 1006: Electrical conductor; conductor; top conductor 1008: Electrical conductor; conductor; bottom conductor; lower conductor 1010: Upper ferromagnetic layer; Free layer FL; Free layer 1012: Lower ferromagnetic layer; Reference layer RL; Reference layer 1014: Tunneling Barrier (TB) 1050: Electron writing current 1052: Electron Writing Current 1100: Word Line 1 1101: Free Layer 1102: MRAM device 1103: Tunneling Barrier 1105: Reference Layer 1109: Perimeter Switching Selector 1110: Bit line 1111: Free Layer 1112: MRAM device 1113: Tunneling Barrier 1115: Reference Layer 1119: Limit Switching Selector 1120: Word Line 2 1150: Word Line 1 1151: Free Layer 1152: MRAM Structure 1153: Tunneling Barrier 1155: Reference Layer 1159: Perimeter Switching Selector 1160: Bit line 1161: Reference Layer 1162: MRAM device 1163: Tunneling Barrier 1165: Free Layer 1169: Limit Switching Selector 1170: Word Line 2 1330: Crosspoint MRAM Structure 1332: Selected memory unit 1334: Selected wordline; Selected WL 1336: Selected bit line; Selected BL 1338: Conductive wire 1339: Conductive wire 1342: Selected memory unit 1344: Selected wordline; Selected WL 1346: Selected bit line; Selected BL 1450: Selected memory unit 1452: Selected memory unit 1570: Variable resistor; First variable resistor; First resistor 1571: Variable resistor; second variable resistor; second resistor 1572: Variable resistor; First variable resistor; First resistor 1573: Variable resistor; second variable resistor; second resistor 1670: First memory unit 1672: Second memory unit 1780: Digital Media Control Circuit 1782: Address 1784: Additional Input 1786: Data 1788: Library Controller 1790: Record 1792: Resistor Setting 1794: Modular Logic 1810: Steps 1812: Steps 1814: Steps 1920: Steps 1922: Steps 1924: Steps 1926: Steps BL 1~BL N: Bit lines; top conductors WL 1~WL M: Word lines; bottom guide lines WL 1,1~WL 1,4: Word lines WL 2,1~WL 2,4: Second group of letter lines BLmin: Minimum bit line distance BLmax: Maximum bit line distance WLmin: Minimum word line spacing WLmax: Maximum letter spacing R WL, R BL: Series resistor; variable resistor; resistor VNN: Voltage VPP: Voltage Ireset: Reset current R VAR: Resistance R VAR1: Resistor R VAR2: Resistance R1 to RN: Switchable resistors Vth: Threshold voltage

Claims

1. A memory device comprising: one or more control circuits configured to be connected to a non-volatile memory cell structure, the non-volatile memory cell structure including non-volatile memory cells each having a programmable resistive element, the one or more control circuits configured to: receive an address corresponding to a location in the non-volatile memory cell structure; set a variable resistor according to the location, the variable resistor being connected in series with a selected non-volatile memory cell located at the location; and drive a memory access current through the selected non-volatile memory cell and the variable resistor connected in series.

2. The device of claim 1, wherein the one or more control circuits are connected to a memory controller and configured to receive the address from the memory controller in a command from the memory controller.

3. The device of claim 2, wherein the command is a write command for writing data to the location in the nonvolatile memory, and the memory access current is a write current.

4. The device of claim 1, wherein the one or more control circuits are configured to set the variable resistor to a resistance value depending on the location, such that for a location corresponding to a higher combined word line resistance and bit line resistance, the resistance value is a lower resistance value, and for a location having a lower combined word line resistance and bit line resistance, the resistance value is set to a higher resistance value.

5. The device of claim 4, wherein the higher combined word line resistance and bit line resistance connected in series with the lower resistance value are substantially equal to the lower combined word line resistance and bit line resistance connected in series with the higher resistance value.

6. The device of claim 5, wherein the locations corresponding to the higher combined word line resistance and bit line resistance are located in one or more corner regions of the non-volatile memory cell structure, and the locations corresponding to the lower combined word line resistance and bit line resistance are located in the central region of one of the non-volatile memory cell structures.

7. The device of claim 1, wherein the variable resistor comprises a plurality of switchable resistors connected in parallel between a driver circuit and a word line or bit line of the non-volatile memory cell structure.

8. The device of claim 1, wherein the non-volatile memory cell structure includes a plurality of word lines extending along a word line direction, a plurality of bit lines extending along a bit line direction perpendicular to the word line direction, and a plurality of non-volatile memory cells extending perpendicularly, each non-volatile memory cell being connected between word lines.

9. The device as claimed in claim 8, wherein each non-volatile memory cell includes a selector connected in series with the programmable resistive element.

10. A method for a memory structure, comprising: receiving a plurality of addresses corresponding to locations in a crosspoint magnetoresistive random access memory (MRAM) structure; configuring a plurality of variable resistors connected in series with selected non-volatile memory cells at the locations, each variable resistor being configured to a specific resistance value depending on a location of one of the selected non-volatile memory cells connected thereto; and driving memory access current through the selected non-volatile memory cells and the variable resistors, wherein each variable resistor is configured to a specific value depending on the location of the selected non-volatile memory cell connected thereto, such that for each selected non-volatile memory cell, the series resistance of each word line, bit line, and variable resistor is substantially equal.

11. The method of claim 10, wherein driving the memory access current includes driving substantially equal memory access currents through each of the selected nonvolatile memory cells.

12. The method of claim 10, wherein setting the plurality of variable resistors includes, for each variable resistor, enabling only the selected resistor among the plurality of resistors connected in parallel.

13. The method of claim 12, wherein setting the plurality of variable resistors includes checking each address by referring to a record indicating the corresponding resistor to be selected.

14. The method of claim 10, further comprising: measuring the temperature at or near the intersection MRAM structure; and setting the plurality of variable resistors to their respective resistance values ​​based on the location and the temperature.

15. The method of claim 10, further comprising: testing a die including the MRAM structure to determine individual resistance values ​​at the locations; and storing the individual resistance values ​​of the die in the die.

16. The method of claim 15, further comprising: after storing the individual resistance values, performing a memory access operation using the individual resistance values ​​during a first time period; subsequently, repeatedly testing the die to determine new individual resistance values ​​for the locations; storing the new individual resistance values ​​in the die; and subsequently using the new individual resistance values ​​during a second time period.

17. A memory system comprising: a non-volatile memory cell structure including non-volatile memory cells each having a programmable resistive element; and a component for: setting a variable resistor to a resistance value selected according to a location of the non-volatile memory cell in the non-volatile memory cell structure to be accessed, and accessing the non-volatile memory cell by passing a current through the variable resistor connected in series with the non-volatile memory cell, wherein the non-volatile memory cell structure is located on a memory die, and the component for setting the variable resistor is located on a control die bonded to the memory die.

18. The system of claim 17 further includes a temperature measuring circuit connected to the component for setting the variable resistor to provide a temperature measurement to the component for selecting the resistance value.

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